FSTD16211GX - Fairchild - Datasheet.Directory

June 2000

Revised April 2005

FSTD16211 24-Bit Bus Switch with Level Shifting

FSTD16211

24-Bit Bus Switch with Level Shifting

General Descript ion

The Fairchild Switch FSTD16211 provides 24-bits of high-

speed CMOS TTL-compatible bus switching. The low On

Resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

addition al ground boun ce noise. A diode to VCC has been

integrated into the circuit to allow for level shifting between

5V inputs and 3.3V outputs.

The device is organized as a 12-bit or 24-bit bus switch.

When OE1 is LOW, the switch is ON and Port 1A is con-

nected to Port 1B. When OE2 is LOW, Port 2A is connected

to Port 2B. When OE1/2 is HIGH, a high impedance state

exists between the A and B Ports.

Features

■4

switch connection between two ports

■Volta ge level shifting

■Minimal propagation delay through the switch

■Low lCC

■Zero bounce in flow-through mode

■Control inputs compatible with TTL level

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Order ing code “G” indicat es T r a ys.

Note 2: Devices also availab le in Tape and Reel. Specify by ap pending the suffix lette r “X” to the or dering co de.

Logic Diagram

Order Number Package Number Package Description

FSTD16211G

(Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

FSTD16211MTD

(Note 2) MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

FSTD16211

Connection Diagrams

Pin Assignment for TSS OP

Pin Assignment for FBG A

(Top Thru View)

Pin Descriptions

Pin Assignment for FBGA

Truth Table

Pin Name Description

OE1, OE2Bus Switch Enables

1A, 2A Bus A

1B, 2B Bus B

NC No Connect

123456

A1A21A1NC OE21B11B2

B1A41A31A7OE11B31B4

C1A61A5GND 1B71B51B6

D1A10 1A91A81B81B91B10

E1A12 1A11 2A12B11B11 1B12

F2A42A32A22B22B32B4

G2A62A5VCC GND 2B52B6

H2A82A72A92B92B72B8

J2A12 2A11 2A10 2B10 2B11 2B12

Inputs Inputs/Outputs

OE1OE21A, 1B 2A, 2B

LL1A

1B 2A

LH1A

1B Z

HLZ2A

HHZZ

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FSTD16211

Absolute Maximum Ratings(Note 3) Recommended Operating

Conditions (Note 6)

Note 3: The “Absolute Maximum Ratings” are those val ues beyond w hich

the saf ety of the device cannot be guarante ed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended O peratin g Con ditions ” table will defin e the condition s

for actu al device operation.

Note 4: VS is the voltage observed/applied at either A or B Ports across the

switch.

Note 5: The input and output negative voltage ratings may be exceeded if

the in put and output diode cu rrent ratings are observ ed.

Note 6: Unused cont rol input s must be he ld HIG H or L OW. They ma y not

float.

DC Electrical Characteristics

Note 7: Typical valu es are at VCC

5.0V an d T A



Note 8: Measured by t he v oltage dr op betwee n A and B pin s a t the indicat ed curre nt th rough the s w it c h. On Resistan c e is determin ed by the lower of th e

voltages o n t he t w o (A or B) pin s.

Supply Voltage (VCC)



0.5V to



7.0V

DC Switch Voltage (VS) (Note 4)



0.5V to



7.0V

DC Input Control Pin Voltage (VIN)(Note 5)



0.5V to



7.0V

DC Input Diode Current (lIK) VIN





50 mA

DC Output (IOUT) 128 mA

DC VCC/GND Current (ICC/IGND)





100 mA

Storage Temperature Range (TSTG)



C to



150

Power Su pply Ope rat i ng (V CC) 4.5V to 5.5V

Input Voltage (VIN) 0V to 5.5V

Output Voltage (VOUT) 0V to 5.5V

Input Rise and Fall Time (tr, tf)

Switch Control Input 0 ns/V to 5 ns/V

Switch I/O 0 ns/V to DC

Free Air Operating Temperature (TA)-40

C to



Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Typ

(Note 7) Max

VIK Clamp Diode Voltage 4.5



1.2 V IIN



18 mA

VIH HIGH Level Input V olt age 4.5–5.5 2.0 V

VIL LOW Level Input Voltage 4.5–5.5 0.8 V

VOH HIGH Level 4.5–5.5 See Figure 3 V

IIInput Leakage Current 5.5

1.0

VIN

5.5V

010

5.5V

IOZ OFF-STA T E Leakage Curr ent 5.5

1.0

A, B

VCC

RON Switch On Resistance 4.5 4 7

VIN

0V, IIN

64 mA

(Note 8) 4.5 4 7

VIN

0V, IIN

30 mA

4.5 35 50

VIN

2.4V, IIN

15 mA

ICC Quiescent Supply Current 5.5 1.5 mA OE1

OE2

GND

VIN

VCC or GND, IOUT

AOE

OE2

VCC

VIN

VCC or GND, IOUT

ICCT Increase in ICC per Control Input 5.5 2.5 mA One Control Input at 3.4V

Other Control Inputs at VCC or GND

www.fairchildsemi.com 4

FSTD16211

AC Electrical Characteristics

Note 9: This parameter is guara nt eed by des ign but is not test ed. The bus switch cont ributes no pr opagatio n delay othe r tha n t he R C delay of the typ ical On

Resis tance of the s w it c h and the 50pF load c apac itance, wh en driven by an ideal volt age sour c e (z ero output im pedance).

Cap acitance (Note 10)

Note 10: TA



C, f

1 MHz, C apacitance is ch aracterized but not te s te d.

AC Loading and Waveforms

Note: Input driven by 50

source terminated in 50

Note: CL includes load and stray capacitance

Note: Input PRR

1.0 MHz , tW

500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol Parameter



C to



Units Conditions

50pF, RU

500

Figure

VCC

4.5 – 5.5V Number

Min Max

tPHL, tPLH Propagation Delay Bus to Bus (Note 9) 0.25 ns VI

OPEN Figures

1, 2

tPZH, tPZL Output Enable Time 1.5 5.5 ns VI

7V for tPZL Figures

1, 2

OPEN for tPZH

tPHZ, tPLZ Output Disable Time 1.5 6.5 ns VI

7V for tPLZ Figures

1, 2

OPEN for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 3.5 pF VCC

5.0V

CI/O Input/Output Capacitance 5.5 pF VCC, OE

5.0V

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FSTD16211

Output Voltage HIGH vs. Supply Voltage

FIGURE 3.

www.fairchildsemi.com 6

FSTD16211

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

7 www.fairchildsemi.com

FSTD16211 24-Bit Bus Switch with Level Shifting

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD56

Technology Description

The Fairchild Switch family derives fr om and embodies Fairchild’s proven switch technology used fo r several years in its

74LVX3L384 (FST3384) bus switch product.

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.