1
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
MX25L3233F
3V, 32M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Hold Feature
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Auto Erase and Auto Program Algorithms
• Program Suspend/Resume & Erase Suspend/Resume
2
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Contents
1. FEATURES ........................................................................................................................................................ 5
2. GENERAL DESCRIPTION ............................................................................................................................... 6
3. PIN CONFIGURATION ...................................................................................................................................... 7
4. PIN DESCRIPTION ............................................................................................................................................ 7
5. BLOCK DIAGRAM ............................................................................................................................................. 8
6. DATA PROTECTION .......................................................................................................................................... 9
Table 1. Protected Area Sizes ..............................................................................................................10
Table 2. 4K-bit Secured OTP Denition ............................................................................................... 11
7. MEMORY ORGANIZATION ............................................................................................................................. 12
Table 3. Memory Organization .............................................................................................................12
8. DEVICE OPERATION ...................................................................................................................................... 13
9. HOLD FEATURE .............................................................................................................................................. 14
10. COMMAND DESCRIPTION ........................................................................................................................... 16
Table 4. Command Sets ....................................................................................................................... 16
10-1. Write Enable (WREN) ..........................................................................................................................19
10-2. Write Disable (WRDI) ........................................................................................................................... 20
10-3. Read Identication (RDID) ...................................................................................................................21
10-4. Read Status Register (RDSR) .............................................................................................................22
10-5. Read Conguration Register (RDCR) .................................................................................................. 23
Table 5. Status Register .......................................................................................................................24
Table 6. Conguration Register ............................................................................................................ 25
Table 7. Dummy Cycle and Frequency Table .......................................................................................25
10-6. Write Status Register (WRSR) ............................................................................................................. 26
Table 8. Protection Modes ....................................................................................................................27
10-7. Read Data Bytes (READ) ....................................................................................................................29
10-8. Read Data Bytes at Higher Speed (FAST_READ) ..............................................................................30
10-9. Dual Read Mode (DREAD) ..................................................................................................................31
10-10. 2 x I/O Read Mode (2READ) ...............................................................................................................32
10-11. Quad Read Mode (QREAD) ................................................................................................................33
10-12. 4 x I/O Read Mode (4READ) ...............................................................................................................34
10-13. Performance Enhance Mode ...............................................................................................................36
10-14. Burst Read ...........................................................................................................................................37
10-15. Sector Erase (SE) ................................................................................................................................38
10-16. Block Erase (BE) .................................................................................................................................39
10-17. Block Erase (BE32K) ...........................................................................................................................40
10-18. Chip Erase (CE) ................................................................................................................................... 41
10-19. Page Program (PP) .............................................................................................................................42
10-20. 4 x I/O Page Program (4PP) ................................................................................................................43
10-21. Deep Power-down (DP) .......................................................................................................................46
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES) .......................................47
10-23. Read Electronic Manufacturer ID & Device ID (REMS) ....................................................................... 49
Table 9. ID Denitions .........................................................................................................................50
10-24. Enter Secured OTP (ENSO) ................................................................................................................50
10-25. Exit Secured OTP (EXSO) ................................................................................................................... 50
10-26. Read Security Register (RDSCUR) .....................................................................................................51
Table 10. Security Register Denition ..................................................................................................52
10-27. Write Security Register (WRSCUR) .....................................................................................................53
3
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-28. Program Suspend and Erase Suspend ...............................................................................................54
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended ..................54
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL ...........................54
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required) ...................................... 55
10-29. Program Resume and Erase Resume ................................................................................................. 56
10-30. No Operation (NOP) ............................................................................................................................57
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ...............................................................57
10-32. Read SFDP Mode (RDSFDP) ..............................................................................................................58
Table 14. Signature and Parameter Identication Data Values ........................................................... 59
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables .........................................................60
Table 16. Parameter Table (1): Macronix Flash Parameter Tables ......................................................62
11. POWER-ON STATE ....................................................................................................................................... 64
12. Electrical Specications .............................................................................................................................. 65
12-1. Absolute Maximum Ratings .................................................................................................................65
12-2. Capacitance TA = 25°C, f = 1.0 MHz ...................................................................................................65
Table 17. DC Characteristics ................................................................................................................67
Table 18. AC Characteristics ................................................................................................................68
13. TIMING ANALYSIS ........................................................................................................................................ 70
14. OPERATING CONDITIONS ........................................................................................................................... 72
Table 19. Power-Up/Down Voltage and Timing .................................................................................... 74
14-1. Initial Delivery State .............................................................................................................................74
15. ERASE AND PROGRAMMING PERFORMANCE ........................................................................................ 75
16. DATA RETENTION ........................................................................................................................................ 75
17. LATCH-UP CHARACTERISTICS .................................................................................................................. 75
18. ORDERING INFORMATION .......................................................................................................................... 76
19. PART NAME DESCRIPTION ......................................................................................................................... 77
20. PACKAGE INFORMATION ............................................................................................................................ 78
20-1. 8-pin SOP (150mil) ..............................................................................................................................78
20-2. 8-pin SOP (200mil) ..............................................................................................................................79
20-3. 8-land USON (4x3mm) ........................................................................................................................80
20-4. 16-pin SOP (300mil) ............................................................................................................................81
20-5. 8-WSON (6x5mm) ...............................................................................................................................82
21. REVISION HISTORY ..................................................................................................................................... 83
4
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figures
Figure 1. Serial Modes Supported (for Normal Serial mode) .......................................................................................................13
Figure 2. Hold Condition Operation ............................................................................................................................................14
Figure 3. Write Enable (WREN) Sequence (Command 06h).......................................................................................................19
Figure 4. Write Disable (WRDI) Sequence (Command 04h) ......................................................................................................20
Figure 5. Read Identication (RDID) Sequence (Command 9Fh) ..............................................................................................21
Figure 6. Read Status Register (RDSR) Sequence (Command 05h) .........................................................................................22
Figure 7. Read Conguration Register (RDCR) Sequence .........................................................................................................23
Figure 8. Write Status Register (WRSR) Sequence (Command 01h) ........................................................................................26
Figure 9. WRSR ow ...................................................................................................................................................................28
Figure 10. Read Data Bytes (READ) Sequence (Command 03h) ..............................................................................................29
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh) ..........................................................................30
Figure 12. Dual Read Mode Sequence (Command 3Bh) ............................................................................................................31
Figure 13. 2 x I/O Read Mode Sequence (Command BBh) ........................................................................................................32
Figure 14. Quad Read Mode Sequence (Command 6Bh) ...........................................................................................................33
Figure 15. 4 x I/O Read Mode Sequence (Command EBh) ........................................................................................................34
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode) .................................................36
Figure 17. Burst Read ..................................................................................................................................................................37
Figure 18. Sector Erase (SE) Sequence (Command 20h) .........................................................................................................38
Figure 19. Block Erase (BE) Sequence (Command D8h) ..........................................................................................................39
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52h) ..........................................................................................40
Figure 21. Chip Erase (CE) Sequence (Command 60h or C7h) ................................................................................................41
Figure 22. Page Program (PP) Sequence (Command 02h) .......................................................................................................42
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38h) .........................................................................................43
Figure 24. Program/Erase Flow(1) with read array data ..............................................................................................................44
Figure 25. Program/Erase Flow(2) without read array data .........................................................................................................45
Figure 26. Deep Power-down (DP) Sequence (Command B9h) ................................................................................................46
Figure 27. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command ABh) ......................47
Figure 28. Release from Deep Power-down (RDP) Sequence ...................................................................................................48
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence .................................................................................49
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2Bh) ...............................................................................51
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2Fh) (SPI mode) ............................................................53
Figure 32. Suspend to Read Latency ..........................................................................................................................................55
Figure 33. Resume to Suspend Latency .....................................................................................................................................55
Figure 34. Suspend to Program Latency .....................................................................................................................................56
Figure 35. Resume to Read Latency ...........................................................................................................................................56
Figure 36. Software Reset Recovery ...........................................................................................................................................57
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence ............................................................................58
Figure 38. Maximum Negative Overshoot Waveform ..................................................................................................................65
Figure 39. Maximum Positive Overshoot Waveform ....................................................................................................................65
Figure 40. Input Test Waveforms and Measurement Level .........................................................................................................66
Figure 41. Output Loading ...........................................................................................................................................................66
Figure 42. SCLK TIMING DEFINITION .......................................................................................................................................66
Figure 43. Serial Input Timing ......................................................................................................................................................70
Figure 44. Output Timing .............................................................................................................................................................70
Figure 45. Hold Timing .................................................................................................................................................................71
Figure 46. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..........................................................................71
Figure 47. AC Timing at Device Power-Up ..................................................................................................................................72
Figure 48. Power-Down Sequence ..............................................................................................................................................73
Figure 49. Power-up Timing .........................................................................................................................................................73
Figure 50. Power Up/Down and Voltage Drop .............................................................................................................................74
5
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
32M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• 33,554,432 x 1 bit structure
or 16,777,216 x 2 bits (two I/O read mode) struc-
ture
or 8,388,608 x 4 bits (four I/O mode) structure
• 1024 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 128 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 64 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 to 3.6 volt for read, erase, and program op-
erations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.65 to 3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD:
133MHz with 8 dummy cycles
- 2READ:
104MHz with 4 dummy cycle,
133MHz with 8 dummy cycle
- 4READ:
104MHz with 6 dummy cycle,
133MHz with 10 dummy cycle
- Congurable dummy cycle number for 2READ
and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
KEY FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block Lock Protection
The BP0-BP3 and T/B status bits dene the site of the
area to be protected against program and erase instruc-
tions.
• Additional 4K bits secured OTP
- Features unique identier
- Factory locked identiable and customer lockable
• Auto Erase and Auto Program Algorithms
- Automatically erases and veries data at selected
sector
- Automatically programs and veries data at select-
ed page by an internal algorithm that automatically
times the program pulse width (Any page to be pro-
grammed should have page in the erased state rst.)
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identication
- JEDEC 1-byte Manufacturer ID and 2-byte Device
ID
- RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP)
mode
- All devices are RoHS Compliant and Halogen-
free
6
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
2. GENERAL DESCRIPTION
MX25L3233F is 32Mb bits Serial NOR Flash memory, which is congured as 4,194,304 x 8 internally. When it is
in four I/O mode, the structure becomes 8,388,608 bits x 4. When it is in two I/O mode, the structure becomes
16,777,216 bits x 2.
MX25L3233F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L3233F, MXSMIO® (Serial Multi I/O) ash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L3233F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
7
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
3. PIN CONFIGURATION 4. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0
Serial Data Input (for 1xI/O)/ Serial Data
Input & Output (for 2xI/O mode and 4xI/
O mode)
SO/SIO1
Serial Data Output (for 1xI/O)/Serial
Data Input & Output (for 2xI/O mode
and 4xI/O mode)
SCLK Clock Input
WP#/SIO2 Write protection Active Low or Serial
Data Input & Output (for 4xI/O mode)
HOLD#/
SIO3
To pause the device without deselecting
the device or Serial data Input/Output
for 4 x I/O mode
VCC + 3.0V Power Supply
GND Ground
NC No Connection
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
HOLD#/SIO3
SCLK
SI/SIO0
8
7
6
5
8-PIN SOP (150mil)/8-PIN SOP (200mil)
8-LAND USON (4x3mm)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
16-PIN SOP (300mil)
1
2
3
4
5
6
7
8
HOLD#/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
8-WSON (6x5mm)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
Note:
1. The pin of HOLD#/SIO3 or WP#/SIO2 will remain
internal pull up function while this pin is not
physically connected in system conguration.
However, the internal pull up function will be
disabled if the system has physical connection to
HOLD#/SIO3 or WP#/SIO2 pin.
8
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
5. BLOCK DIAGRAM
Address
Generator
Memory Array
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
* Depends on part number options.
9
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or pro-
gramming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specic command se-
quences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and complet-
ed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be
protected as read only. The protected area denition is shown as table of "Table 1. Protected Area Sizes", the
protected areas are more exible which may protect various areas by setting value of TB, BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0, TB) bits and
SRWD bit.
10
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 1. Protected Area Sizes
Protected Area Sizes (TB bit = 0)
Status bit Protect Level
BP3 BP2 BP1 BP0 32Mb
00000 (none)
00011 (1block, block 63rd)
00102 (2blocks, block 62nd-63rd)
00113 (4blocks, block 60th-63rd)
01004 (8blocks, block 56th-63rd)
01015 (16blocks, block 48th-63rd)
01106 (32blocks, block 32nd-63rd)
01117 (64blocks, protect all)
10008 (64blocks, protect all)
10019 (64blocks, protect all)
101010 (64blocks, protect all)
101111 (64blocks, protect all)
110012 (64blocks, protect all)
110113 (64blocks, protect all)
111014 (64blocks, protect all)
111115 (64blocks, protect all)
Protected Area Sizes (TB bit = 1)
Status bit Protect Level
BP3 BP2 BP1 BP0 32Mb
00000 (none)
00011 (1block, block 0th)
00102 (2blocks, block 0th-1st)
00113 (4blocks, block 0th-3rd)
01004 (8blocks, block 0th-7th)
01015 (16blocks, block 0th-15th)
01106 (32blocks, block 0th-31st)
01117 (64blocks, protect all)
10008 (64blocks, protect all)
10019 (64blocks, protect all)
101010 (64blocks, protect all)
101111 (64blocks, protect all)
110012 (64blocks, protect all)
110113 (64blocks, protect all)
111014 (64blocks, protect all)
111115 (64blocks, protect all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
11
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
II. Additional 4K-bit secured OTP for unique identier: to provide 4K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and
going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO com-
mand.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 10. Security Register Denition" for
security register bit denition and "Table 2. 4K-bit Secured OTP Denition" for address range denition.
Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured
OTP mode, array access is not allowed.
Table 2. 4K-bit Secured OTP Denition
Address range Size Standard Factory Lock Customer Lock
xxx000~xxx1FF 4096-bit Determined by Factory Determined by customer
12
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 3. Memory Organization
Block(32K-byte) Sector (4K-byte)
1023 3FF000h 3FFFFFh
…
1016 3F8000h 3F8FFFh
1015 3F7000h 3F7FFFh
…
1008 3F0000h 3F0FFFh
1007 3EF000h 3EFFFFh
…
1000 3E8000h 3E8FFFh
999 3E7000h 3E7FFFh
…
992 3E0000h 3E0FFFh
991 3DF000h 3DFFFFh
…
984 3D8000h 3D8FFFh
983 3D7000h 3D7FFFh
…
976 3D0000h 3D0FFFh
47 02F000h 02FFFFh
…
40 028000h 028FFFh
39 027000h 027FFFh
…
32 020000h 020FFFh
31 01F000h 01FFFFh
…
24 018000h 018FFFh
23 017000h 017FFFh
…
16 010000h 010FFFh
15 00F000h 00FFFFh
…
8008000h 008FFFh
7007000h 007FFFh
…
0000000h 000FFFh
124
123
122
Address Range
127
126
125
Block(64K-byte)
61
2
1
0
63
62
0
5
4
3
2
1
7. MEMORY ORGANIZATION
13
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode un-
til next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 4READ, QREAD,
2READ, DREAD, RDCR, RES, and REMS the shifted-in instruction sequence is followed by a data-out se-
quence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, BE32K, CE, PP, 4PP, Suspend, Resume, NOP, RSTEN, RST, ENSO, EXSO, WR-
SCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not
executed.
6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is ne-
glected and will not affect the current operation of Write Status Register, Program, Erase.
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while
not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial
mode is supported.
Figure 1. Serial Modes Supported (for Normal Serial mode)
SCLK
MSB
CPHA shift in shift out
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
14
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not
start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while
Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until
Serial Clock being low).
Figure 2. Hold Condition Operation
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5
Bit 5
Bit 7
Bit 7 Bit 6
Bit 6
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈
Valid Data Valid Data Valid DataDon’t care
High_Z High_Z
Don’t care
Bit 7 Bit 6 Bit 5 Bit 3Bit 4
Bit 7 Bit 6 Bit 4
Bit 5 Bit 3
HOLD#
CS#
SCLK
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
≈ ≈ ≈ ≈ ≈ ≈ ≈≈
15
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK)
and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#)
drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with
chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
16
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10. COMMAND DESCRIPTION
Table 4. Command Sets
Read Commands
I/O 112244
Command READ
(normal read)
FAST READ
(fast read
data)
2READ
(2 x I/O read
command)
DREAD
(1I / 2O read
command)
4READ
(4 x I/O read
command)
QREAD
(1I/4O read
command)
1st byte 03 (hex) 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex)
2nd byte A[23:16] A[23:16] A[23:16] A[23:16] A[23:16] A[23:16]
3rd byte A[15:8] A[15:8] A[15:8] A[15:8] A[15:8] A[15:8]
4th byte A[7:0] A[7:0] A[7:0] A[7:0] A[7:0] A[7:0]
5th byte Dummy(8) Dummy* Dummy(8) Dummy* Dummy(8)
Action
n bytes read
out until CS#
goes high
n bytes read
out until CS#
goes high
n bytes read
out by 2 x I/O
until CS# goes
high
n bytes read
out by Dual
Output until
CS# goes high
Quad I/O
read with
congurable
dummy cycles
Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Conguration Register.
Please refer to "Table 6. Conguration Register".
17
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Other Commands
Command WREN
(write enable)
WRDI
(write disable)
RDSR (read
status register)
RDCR (read
conguration
register)
WRSR
(write status/
conguration
register)
4PP (quad
page program)
SE
(sector erase)
1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 38 (hex) 20 (hex)
2nd byte Values A[23:16] A[23:16]
3rd byte Values A[15:8] A[15:8]
4th byte A[7:0] A[7:0]
Action
sets the (WEL)
write enable
latch bit
resets the
(WEL) write
enable latch
bit
to read out the
values of the
status register
to read out the
values of the
conguration
register
to write new
values of the
conguration/
status register
quad input to
program the
selected page
to erase the
selected
sector
Command
BE 32K
(block erase
32KB)
BE
(block erase
64KB)
CE
(chip erase)
PP
(page
program)
DP (Deep
power down)
RDP (Release
from deep
power down)
PGM/ERS
Suspend
(Suspends
Program/
Erase)
1st byte 52 (hex) D8 (hex) 60 or C7 (hex) 02 (hex) B9 (hex) AB (hex) 75/B0 (hex)
2nd byte A[23:16] A[23:16] A[23:16]
3rd byte A[15:8] A[15:8] A[15:8]
4th byte A[7:0] A[7:0] A[7:0]
Action
to erase the
selected 32KB
block
to erase the
selected 64KB
block
to erase whole
chip
to program the
selected page
enters deep
power down
mode
release from
deep power
down mode
program/erase
operation is
interrupted
by suspend
command
Command
PGM/ERS
Resume
(Resumes
Program/
Erase)
RDID
(read identic-
ation)
RES (read
electronic ID)
REMS (read
electronic
manufacturer
& device ID)
ENSO (enter
secured OTP)
1st byte 7A/30 (hex) 9F (hex) AB (hex) 90 (hex) B1 (hex)
2nd byte x x
3rd byte x x
4th byte x ADD
Action
to continue
performing the
suspended
program/erase
sequence
outputs
JEDEC
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
to read out
1-byte Device
ID
output the
Manufacturer
ID & Device ID
to enter the
4K-bit secured
OTP mode
18
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Command
(byte)
EXSO (exit
secured OTP)
RDSCUR
(read security
register)
WRSCUR
(write security
register)
RSTEN
(Reset Enable)
RST
(Reset
Memory)
RDSFDP SBL (Set Burst
Length)
1st byte C1 (hex) 2B (hex) 2F (hex) 66 (hex) 99 (hex) 5A (hex) C0/77 (hex)
2nd byte A[23:16]
3rd byte A[15:8] Value
4th byte A[7:0]
5th byte Dummy(8)
Action
to exit the
4K-bit secured
OTP mode
to read value
of security
register
to set the lock-
down bit as
"1" (once lock-
down, cannot
be update)
(Note 2)
n bytes read
out until CS#
goes high
to set Burst
length
Note 1: It is not recommended to adopt any other code not in the command denition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
Command
(byte)
NOP
(No
Operation)
1st byte 00 (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
19
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, BE32K, CE, and WRSR which are intended to change the device content, should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
The SIO[3:1] are don't care.
Figure 3. Write Enable (WREN) Sequence (Command 06h)
21 34567
High-Z
0
06h
Command
SCLK
SI
CS#
SO
20
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- WRDI command completion
- WRSR command completion
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
Figure 4. Write Disable (WRDI) Sequence (Command 04h)
21 34567
High-Z
0
04h
Command
SCLK
SI
CS#
SO
21
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 5. Read Identication (RDID) Sequence (Command 9Fh)
10-3. Read Identication (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Ma-
cronix Manufacturer ID and Device ID are listed as table of "Table 9. ID Denitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data
out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the
cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
21 3456789 10 11 12 13 14 15
Command
0
Manufacturer Identification
High-Z
MSB
15 14 13 3210
Device Identification
MSB
7 6 5 3 2 1 0
16 17 18 28 29 30 31
SCLK
SI
CS#
SO
9Fh
22
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even
in program/erase/write status register condition) and continuously. It is recommended to check the Write in Pro-
gress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care.
Figure 6. Read Status Register (RDSR) Sequence (Command 05h)
21 3456789 10 11 12 13 14 15
command
0
76543210
Status Register Out
High-Z
MSB
76543210
Status Register
Out
MSB
7
SCLK
SI
CS#
SO
05h
23
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-5. Read Conguration Register (RDCR)
The RDCR instruction is for reading Conguration Register Bits. The Read Conguration Register can be read
at any time (even in program/erase/write conguration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write conguration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conguration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 7. Read Conguration Register (RDCR) Sequence
21 3456789 10 11 12 13 14 15
command
0
76543210
Configuration register Out
High-Z
MSB
76543210
Configuration register Out
MSB
7
SCLK
SI
CS#
SO
15h
Mode 3
Mode 0
24
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Status Register
The denition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/
write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write
status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/
write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs
to be set to “1” before the device can accept program and erase instructions, otherwise the program and erase
instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes. To en-
sure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it is recom-
mended that WIP be conrmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is
applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protect-
ed area (as dened in "Table 1. Protected Area Sizes") of the device to against the program/erase instruction
without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the
Write Status Register (WRSR) instruction to be executed. Those bits dene the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
QE bit. The Quad Enable (QE) bit is a non-volatile bit with a factory default of “0”. When QE is “0”, Quad mode
commands are ignored; pins WP#/SIO2 and HOLD#/SIO3 function as WP# and HOLD#, respectively. When QE is “1”,
Quad mode is enabled and Quad mode commands are supported along with Single and Dual mode commands.
Pins WP#/SIO2 and HOLD#/SIO3 function as SIO2 and SIO3, respectively, and their alternate pin functions are
disabled. Enabling Quad mode also disables the HPM and HOLD features.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is oper-
ated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware pro-
tection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode,
the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block
Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".
Table 5. Status Register
Note 1: Please refer to the "Table 1. Protected Area Sizes".
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SRWD
(status
register write
protect)
QE
(Quad
Enable)
BP3
(level of
protected
block)
BP2
(level of
protected
block)
BP1
(level of
protected
block)
BP0
(level of
protected
block)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=status
register write
disabled
0=status
register write
enabled
1= Quad
Enable
0=not Quad
Enable
(note 1) (note 1) (note 1) (note 1)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit volatile bit volatile bit
25
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Conguration Register
The Conguration Register is able to change the default status of Flash memory. Flash memory will be congured
after the CR bit is set.
ODS bit
The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The
Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status
Register (WRSR) instruction to be executed.
TB bit
The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to congure the Block Protect area by BP
bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device.
To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
Table 6. Conguration Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Reserved
DC
(Dummy
Cycle)
Reserved Reserved
TB
(top/bottom
selected)
Reserved Reserved ODS
x
2READ/
4READ
Dummy
Cycle
x x
0=Top area
protect
1=Bottom
area protect
(Default=0)
x x
0, Output driver
strength=1
1, Output driver
strength=1/4
(Default=0)
xvolatile x x OTP x x volatile
Note: Refer to "Table 7. Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Conguration
Registers.
DC Numbers of Dummy
Cycles Freq. (MHz)
2READ 0 (default) 4 104
1 8 133
4READ 0 (default) 6 104
1 10 133
Table 7. Dummy Cycle and Frequency Table
26
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-6. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Conguration Register Bits. Be-
fore sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the
Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3,
BP2, BP1, BP0) bits to dene the protected area of memory (as shown in "Table 1. Protected Area Sizes"). The
WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD)
bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of
the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is en-
tered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Regis-
ter data on SI→ CS# goes high.
Figure 8. Write Status Register (WRSR) Sequence (Command 01h)
21 3456789 10 11 12 13 14 15
Status
Register In
Configuration
Register In
0
MSB
SCLK
SI
CS#
SO
01h
High-Z
command
Mode 3
Mode 0
16 17 18 19 20 21 22 23
765 4321 0 15 14 13 12 11 10 9 8
27
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-
able Latch (WEL) bit is reset.
Note: As dened by the values in the Block Protect (BP3, BP2, BP1, BP0, TB) bits of the Status Register, as
shown in "Table 1. Protected Area Sizes".
Mode Status register condition WP# and SRWD bit status Memory
Software protection
mode (SPM)
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area cannot
be programmed or erased.
Hardware protection
mode (HPM)
The SRWD, BP0-BP3, TB of
status register bits cannot be
changed
WP#=0, SRWD bit=1 The protected area cannot
be programmed or erased.
Table 8. Protection Modes
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode
(HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is dened by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is dened by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hard-
ware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3,
BP2, BP1, BP0, TB and hardware protected mode by the WP#/SIO2 to against data modication.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is
entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be en-
tered; only can use software protected mode via BP3, BP2, BP1, BP0, TB.
If the system goes into four I/O mode, the feature of HPM will be disabled.
28
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 9. WRSR ow
WREN command
WRSR command
Write status register data
RDSR command
WRSR successfully
Yes
Yes
WRSR fail
No
start
Verify OK?
WIP=0? No
RDSR command
Yes
WEL=1? No
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
29
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-7. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The rst address byte can be at any location. The ad-
dress is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest ad-
dress has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address
on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 10. Read Data Bytes (READ) Sequence (Command 03h)
SCLK
SI
CS#
SO
21 345678910 28 29 30 31 32 33 34 35 36 37 38
Data Out 1
24 ADD Cycles
0
MSB MSB
MSB
39
Data Out 2
03
High-Z
Command
D7
A23 A22 A21 A3 A2 A1 A0
D7D6 D5 D4 D3 D2 D1 D0
30
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-8. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The rst address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ opera-
tion can use CS# to high at any time during data out. (Please refer to "Figure 11. Read at Higher Speed (FAST_
READ) Sequence (Command 0Bh)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 11. Read at Higher Speed (FAST_READ) Sequence (Command 0Bh)
23
21 3456789 10 28 29 30 31
22 21 3210
High-Z
24 BIT ADDRESS
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Cycle
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
0Bh
Command
31
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-9. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The rst address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writ-
ing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
Figure 12. Dual Read Mode Sequence (Command 3Bh)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
930 31 32 39 40 41 43 44 4542
3B D4
D5
D2
D3
D7
D6 D6 D4
D0
D7 D5
D1
Command 24 ADD Cycle 8 dummy
cycle
A23 A22 A1 A0
… …
…
Data Out
1
Data Out
2
32
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-10. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK
at a maximum frequency fT. The rst address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writ-
ing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-
terleave on SIO1 & SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 13. 2 x I/O Read Mode Sequence (Command BBh)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9 18 19 20
BB(hex)
21 22 23 24 25 26 27 28 29
P0
P2
P1
P3
D4
D5
D2
D3
D7
D6 D6 D4
D0
D7 D5
D1
Command 12 ADD Cycle Configurable
Dummy cycles
A22 A20 A2 A0
A3 A1
A23 A21
…
…
…
Data Out
1
Data Out
2
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the rst two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
33
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-11. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The rst address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD in-
struction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
Figure 14. Quad Read Mode Sequence (Command 6Bh)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
29
930 31 32 33 38 39 40 41 42
6B
High Impedance
WP#/SIO2
High Impedance
HOLD#/SIO3
8 dummy cycles
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
A23 A22 A2 A1 A0
Command 24 ADD Cycles Data
Out 1
Data
Out 2
Data
Out 3
…
…
…
34
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-12. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The rst address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ in-
struction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ
instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address in-
terleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data out interleave on SIO3, SIO2, SIO1
& SIO0→ to end 4READ operation can use CS# to high at any time during data out. (Please refer to the gure
below)
Figure 15. 4 x I/O Read Mode Sequence (Command EBh)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9 1210 11 13 14
EBh address
bit20, bit16..bit0
address
bit21, bit17..bit1
P4 P0
P5 P1
P6 P2
P7 P3
data
bit4, bit0, bit4....
data
bit5 bit1, bit5....
15 16 17 18 19 20 21 22 23 n
High Impedance
WP#/SIO2 address
bit22, bit18..bit2 data
bit6 bit2, bit6....
High Impedance
HOLD#/SIO3 address
bit23, bit19..bit3 data
bit7 bit3, bit7....
8 Bit Instruction 6 Address cycles
Performance
enhance indicator
(Note 1 & 2)
Data Output
Configurable
Dummy cycles
(Note 3)
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Congurable Dummy Cycle is set by Conguration Register Bit. Please see "Dummy Cycle and Fre-
quency Table"
35
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→send
4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling
bit P[7:0]→4 dummy cycles →data out until CS# goes high → CS# goes low (The following 4READ instruction is
not allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 24-bit random ac-
cess address (Please refer to "Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI
Mode)" ).
In the performance-enhancing mode (Notes of "Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EBh) (SPI Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance mode. And after-
wards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
36
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-13. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note
"Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)")
Performance enhance mode is supported for 4READ mode.
“EBh” commands support enhance mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low
of the rst clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose rst two dummy cycles is not toggle then exit. Or issue
”FFh” data cycles to exit enhance mode.
Figure 16. 4 x I/O Read enhance performance Mode Sequence (Command EBh) (SPI Mode)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9 1210 11 13 14
EBh address
bit20, bit16..bit0
address
bit21, bit17..bit1
P4 P0
P5 P1
P6 P2
P7 P3
data
bit4, bit0, bit4....
data
bit5 bit1, bit5....
15 16
n+1 ........... ...... ........... ...........n+7 n+9 n+13
17 18 19 20 21 22 23 n
High Impedance
WP#/SIO2 address
bit22, bit18..bit2 data
bit6 bit2, bit6....
High Impedance
HOLD#/SIO3 address
bit23, bit19..bit3 data
bit7 bit3, bit7....
8 Bit Instruction 6 Address cycles
Performance
enhance
indicator (Note1)
Data Output
SCLK
SI/SIO0
SO/SIO1
CS#
address
bit20, bit16..bit0
address
bit21, bit17..bit1
P4 P0
P5 P1
P6 P2
P7 P3
data
bit4, bit0, bit4....
data
bit5 bit1, bit5....
WP#/SIO2 address
bit22, bit18..bit2 data
bit6 bit2, bit6....
HOLD#/SIO3 address
bit23, bit19..bit3 data
bit7 bit3, bit7....
6 Address cycles
Performance
enhance
indicator (Note1)
Data Output
Congurable
Dummy cycles
(Note 2)
Congurable
Dummy cycles
(Note 2)
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.
2. The Congurable Dummy Cycle is set by Conguration Register Bit. Please see "Dummy Cycle and
Frequency Table"
37
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-14. Burst Read
The Burst Read feature allows applications to ll a cache line with a xed length of data without using multiple
read commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting
the Burst Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes)
containing the initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the
8-byte-page-aligned boundary containing the initial read address.
To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE →
drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.
Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The 4READ read
command supports the wrap around feature after Burst Read is enabled. To change the wrap depth, resend the
Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read instruction
with Wrap Code 1xh. “EBh" supports wrap around feature after wrap around is enabled.
0
CS#
SCLK
SIO
77h D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 6 7 8 9 10 1112 13 14 155
Mode 3
Mode 0
Figure 17. Burst Read
Data Wrap Around Wrap Depth
00h Yes 8-byte
01h Yes 16-byte
02h Yes 32-byte
03h Yes 64-byte
1xh No X
38
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-15. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 3. Memory Organiza-
tion" ) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary
(the least signicant bit of the address has been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The SIO[3:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
sector is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 18. Sector Erase (SE) Sequence (Command 20h)
24 Bit Address
21 3456789 29 30 310
23 22 2 1 0
MSB
SCLK
CS#
SI
20h
Command
39
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-16. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 3. Mem-
ory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte
boundary (the least signicant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on
SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be reset.
Figure 19. Block Erase (BE) Sequence (Command D8h)
24 Bit Address
21 3456789 29 30 310
23 22 2 0
1
MSB
SCLK
CS#
SI
D8h
Command
40
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-17. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 3.
Memory Organization" ) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at
the byte boundary (the least signicant bit of address byte has been latched-in); otherwise, the instruction will be
rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte ad-
dress on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 20. Block Erase 32KB (BE32K) Sequence (Command 52h)
24 Bit Address
21 3456789 29 30 310
23 22 2 0
1
MSB
SCLK
CS#
SI
52h
Command
41
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-18. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) in-
struction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 21. Chip Erase (CE) Sequence (Command 60h or C7h)
21 345670
60h or C7h
SCLK
SI
CS#
Command
42
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-19. Page Program (PP)
The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the
device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)
bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256
data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction
requires that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] species
the starting address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of
the selected page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are
going to be programmed, A[7:0] should be set to 0.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the
tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care.
Figure 22. Page Program (PP) Sequence (Command 02h)
4241 43 44 45 46 47 48 49 50 52 53 54 5540
23
21 3456789 10 28 29 30 31 32 33 34 35
22 21 3210
36 37 38
24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
SCLK
CS#
SI
SCLK
CS#
SI
02h
Command
43
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-20. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set
to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0,
SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of lower
clock less than f4PP. For system with faster clock, the Quad page program cannot provide more performance,
because the required internal page program time is far more than the time data ows in. Therefore, we suggest
that while executing this command (especially during sending data), user can slow the clock speed down to f4PP
below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38h)
A20 A16 A12 A8 A4 A0
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
21 3456789
6 ADD cycles Data
Byte 1
Data
Byte 2
Data
Byte 256
0
SCLK
CS#
SI/SIO0
SO/SIO1
HOLD#/SIO3
WP#/SIO2
38
Command
10 11 12 13 14 15 16 17 524 525
…
…
…
…
…
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
44
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
The Program/Erase function instruction function ow is as follows:
Figure 24. Program/Erase Flow(1) with read array data
WREN command
Program/erase command
Write program data/address
(Write erase address)
RDSR command
Read array data
(same address of PGM/ERS)
Program/erase successfully
Yes
Yes
Program/erase fail
No
No
Start
Program/erase completed
Verify OK?
WIP=0?
Program/erase
another block?
Yes
No
RDSR command*
Yes
WEL=1? No
*
* Issue RDSR to check BP[3:0].
45
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 25. Program/Erase Flow(2) without read array data
46
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-21. Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Pow-
er-down mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS#
must go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); other-
wise the instruction will not be executed. SIO[3:1] are "don't care".
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-
down mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions
will be ignored except Release from Deep Power-down (RDP).
The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep
Power-down (RDP) instruction, power-cycle, or reset. Please refer to "Figure 28. Release from Deep Power-
down (RDP) Sequence".
Figure 26. Deep Power-down (DP) Sequence (Command B9h)
21 345670tDP
Deep Power-down Mode
Stand-by Mode
SCLK
CS#
SI
B9h
Command
47
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in
the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously
in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specied in "Table 18. AC Characteristics". Once in
the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 9.
ID Denitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to
be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current
program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previous-
ly in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously
in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high
at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 27. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command
ABh)
23
21 3456789 10 28 29 30 31 32 33 34 35
22 21 3210
36 37 38
765432 0
1
High-Z Electronic Signature Out
3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
SCLK
CS#
SI
SO
ABh
Command
48
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 28. Release from Deep Power-down (RDP) Sequence
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
High-Z
SCLK
CS#
SI
SO
ABh
Command
Mode 3
Mode 0
49
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-23. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID val-
ues are listed in "Table 9. ID Denitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by
two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the
device ID are shifted out on the falling edge of SCLK with the most signicant bit (MSB) rst. If the address byte
is 00h, the manufacturer ID will be output rst, followed by the device ID. If the address byte is 01h, then the de-
vice ID will be output rst, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs
can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Notes: (1) ADD=00H will output the manufacturer's ID rst and ADD=01H will output device ID rst.
Figure 29. Read Electronic Manufacturer & Device ID (REMS) Sequence
15 14 13 3 2 1 0
21 3456789 10
2 Dummy Bytes
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
Manufacturer ID
ADD (1)
MSB
76543210
Device ID
MSB MSB
7
47
765432 0
1
3531302928
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
90h
High-Z
Command
Mode 3
Mode 0
50
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-24. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While the device is in 4K-bit Se-
cured OTP mode, array access is not available. The additional 4K-bit Secured OTP is independent from main ar-
ray, and may be used to store unique serial number for system identier. After entering the Secured OTP mode,
follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot
be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
Please note that WRSR/WRSCUR/CE/BE/SE/BE32K commands are not acceptable during the access of secure
OTP region, once Security OTP is locked down, only read related commands are valid.
10-25. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are don't care.
Table 9. ID Denitions
Command Type MX25L3233F
RDID Manufacturer ID Memory Type Memory Density
C2 20 16
RES Electronic ID
15
REMS Manufacturer ID Device ID
C2 15
51
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-26. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is: CS# goes low→ sending RDSCUR instruction → Security Reg-
ister data out on SO→ CS# goes high.
The SIO[3:1] are don't care.
21 3456789 10 11 12 13 14 15
command
0
76543210
Security Register Out Security Register Out
High-Z
MSB
76543210
MSB
7
SCLK
SI
CS#
SO
2B
Figure 30. Read Security Register (RDSCUR) Sequence (Command 2Bh)
The denition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the Secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of ash memory. After the ash memory is suspended by Program Sus-
pend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users
may use ESB to identify the state of ash memory. After the ash memory is suspended by Erase Suspend com-
mand, ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
52
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the
failure indication of one or more program operations. This fail ag bit will be cleared automatically after the next
successful program operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase opera-
tion fails on a protected memory region or locked OTP region, this bit will also be set. This bit can be the failure
indication of one or more erase operations. This fail ag bit will be cleared automatically after the next successful
erase operation.
Table 10. Security Register Denition
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Reserved E_FAIL P_FAIL Reserved
ESB (Erase
Suspend
status)
PSB
(Program
Suspend
status)
LDSO
(lock-down 4K-
bit Secured
OTP)
Secured OTP
Indicator bit
(4K-bit
Secured OTP)
Reserved
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
Reserved
0=Erase
is not
suspended
1=Erase is
suspended
(default=0)
0=Program
is not
suspended
1=Program
is suspended
(default=0)
0 = not
lockdown
1 = lock-down
(cannot
program/erase
OTP)
0 = nonfactory
lock
1 = factory
lock
non-volatile
bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit
Reserved Read Only Read Only Read Only Read Only OTP Read Only
53
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-27. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the
WREN instruction is required before sending WRSCUR instruction. The WRSCUR instruction may change the
values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to
"1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The SIO[3:1] are don't care.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2Fh) (SPI mode)
21 345670
2F
SCLK
SI
CS#
Command
SO High-Z
54
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-28. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 11. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 11. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation Readable Region of Memory Array
Page Program All but the Page being programmed
Sector Erase (4KB) All but the 4KB Sector being erased
Block Erase (32KB) All but the 32KB Block being erased
Block Erase (64KB) All but the 64KB Block being erased
When the serial ash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 32. Suspend
to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after
which the device is ready to accept one of the commands listed in "Table 12. Acceptable Commands During Pro-
gram/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 18. AC Characteristics" for tPSL and
tESL timings. "Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands
for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be is-
sued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Sus-
pend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an
erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
Table 12. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name Command Code Suspend Type
Program Suspend Erase Suspend
READ 03h • •
FAST READ 0Bh • •
DREAD 3Bh • •
QREAD 6Bh • •
2READ BBh • •
4READ EBh • •
RDSFDP 5Ah • •
RDID 9Fh • •
REMS 90h • •
ENSO B1h • •
EXSO C1h • •
SBL C0h or 77h • •
WREN 06h •
RESUME 7Ah or 30h • •
PP 02h •
4PP 38h •
55
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 13. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name Command Code
Suspend Type
Program Suspend Erase Suspend
WRDI 04h • •
RDSR 05h • •
RDCR 15h • •
RDSCUR 2Bh • •
RES ABh • •
RSTEN 66h • •
RST 99h • •
NOP 00h • •
Figure 32. Suspend to Read Latency
CS#
tPSL / tESL
tPSL: Program Latency
tESL: Erase Latency
Suspend Command Read Command
Figure 33. Resume to Suspend Latency
CS#
tPRS / tERS
Resume Command Suspend
Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
56
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-28-1. Program Suspend
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction
must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to nish before the suspended erase can be resumed. The Status Register can be polled to determine the status
of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page
Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 34. Suspend to Program Latency
CS#
tPSL / tESL
tPSL: Program Latency
tESL: Erase Latency
Suspend Command
Program Command
10-29. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the serial ash receives the Resume instruction, the WEL and WIP bits are set to “1” and the
PSB or ESB is cleared to “0”. The program or erase operation will continue until nished ("Figure 35. Resume to
Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 33. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the serial ash is in “Performance Enhance Mode”.
Make sure the serial ash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 35. Resume to Read Latency
CS#
tSE/tBE/tBE32K/tPP
Resume Command Read Command
57
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-30. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect
any other command.
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed rst to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable
will be invalid.
If the Reset command is executed during program or erase operation, the operation will be disabled, the data un-
der processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a pro-
gram operation than from other operations.
Figure 36. Software Reset Recovery
CS#
Mode
66 99
Stand-by Mode
tRCR
tRCP
tRCE
58
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
10-32. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial ash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation
can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 37. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
23
21 3456789 10 28 29 30 31
22 21 3210
High-Z
24 BIT ADDRESS
0
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Cycle
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
SCLK
SI
CS#
SO
SCLK
SI
CS#
SO
5Ah
Command
59
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 14. Signature and Parameter Identication Data Values
Description Comment Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
SFDP Signature Fixed: 50444653h
00h 07:00 53h53h
01h 15:08 46h46h
02h 23:16 44h44h
03h 31:24 50h50h
S F D P M i n o r R e v i s i o n N u m b e r Start from 00h 04h 07:00 00h00h
SFDP Major Revision Number Start from 01h 05h 15:08 01h01h
Number of Parameter Headers This number is 0-based. Therefore,
0 indicates 1 parameter header. 06h 23:16 01h01h
Unused 07h 31:24 FFh FFh
ID number (JEDEC) 00h: it indicates a JEDEC specied
header. 08h 07:00 00h00h
Parameter Table Minor Revision
Number Start from 00h 09h 15:08 00h00h
Parameter Table Major Revision
Number Start from 01h 0Ah 23:16 01h01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table 0Bh 31:24 09h09h
Parameter Table Pointer (PTP) First address of JEDEC Flash
Parameter table
0Ch 07:00 30h30h
0Dh 15:08 00h00h
0Eh 23:16 00h00h
Unused 0Fh 31:24 FFh FFh
ID number
(Macronix manufacturer ID)
it indicates Macronix manufacturer
ID 10h 07:00 C2hC2h
Parameter Table Minor Revision
Number Start from 00h 11h 15:08 00h00h
Parameter Table Major Revision
Number Start from 01h 12h 23:16 01h01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table 13h 31:24 04h04h
Parameter Table Pointer (PTP) First address of Macronix Flash
Parameter table
14h 07:00 60h60h
15h 15:08 00h00h
16h 23:16 00h00h
Unused 17h 31:24 FFh FFh
SFDP Table (JESD216) below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G,
MX25L3233FMI-08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-
08Q, MX25L3233FMI-08Q and MX25L3233FZNI-08Q
60
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 15. Parameter Table (0): JEDEC Flash Parameter Tables
Description Comment Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
30h
01:00 01b
E5h
Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b
Write Enable Instruction Required
for Writing to Volatile Status
Registers
0: not required
1: required 00h to be written to the
status register
03 0b
Write Enable Opcode Select for
Writing to Volatile Status Registers
0: use 50h opcode,
1: use 06h opcode
Note: If target ash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04 0b
Unused Contains 111b and can never be
changed 07:05 111b
4KB Erase Opcode 31h 15:08 20h20h
(1-1-2) Fast Read (Note2) 0=not support 1=support
32h
16 1b
F1h
Address Bytes Number used in
addressing ash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved 18:17 00b
Double Transfer Rate (DTR)
Clocking 0=not support 1=support 19 0b
(1-2-2) Fast Read 0=not support 1=support 20 1b
(1-4-4) Fast Read 0=not support 1=support 21 1b
(1-1-4) Fast Read 0=not support 1=support 22 1b
Unused 23 1b
Unused 33h 31:24 FFh FFh
Flash Memory Density 37h:34h 31:00 01FF FFFFh
(1-4-4) Fast Read Number of Wait
states (Note3)
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 38h
04:00 0 0100b
44h
(1-4-4) Fast Read Number of
Mode Bits (Note4)
Mode Bits:
000b: Not supported; 010b: 2 bits 07:05 010b
(1-4-4) Fast Read Opcode 39h 15:08 EBh EBh
(1-1-4) Fast Read Number of Wait
states
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 3Ah
20:16 0 1000b
08h
(1-1-4) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits 23:21 000b
(1-1-4) Fast Read Opcode 3Bh 31:24 6Bh 6Bh
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI-
08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
61
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Description Comment Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
(1-1-2) Fast Read Number of Wait
states
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 3Ch
04:00 0 1000b
08h
(1-1-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits 07:05 000b
(1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh
(1-2-2) Fast Read Number of Wait
states
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 3Eh
20:16 0 0100b
04h
(1-2-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits 23:21 000b
(1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh
(2-2-2) Fast Read 0=not support 1=support
40h
00 0b
EEh
Unused 03:01 111b
(4-4-4) Fast Read 0=not support 1=support 04 0b
Unused 07:05 111b
Unused 43h:41h 31:08 FFh FFh
Unused 45h:44h 15:00 FFh FFh
(2-2-2) Fast Read Number of Wait
states
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 46h
20:16 0 0000b
00h
(2-2-2) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits 23:21 000b
(2-2-2) Fast Read Opcode 47h 31:24 FFh FFh
Unused 49h:48h 15:00 FFh FFh
(4-4-4) Fast Read Number of Wait
states
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8 4Ah
20:16 0 0000b
00h
(4-4-4) Fast Read Number of
Mode Bits
Mode Bits:
000b: Not supported; 010b: 2 bits 23:21 000b
(4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh
Sector Type 1 Size Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB 4Ch 07:00 0Ch0Ch
Sector Type 1 erase Opcode 4Dh 15:08 20h20h
Sector Type 2 Size Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB 4Eh 23:16 0Fh 0Fh
Sector Type 2 erase Opcode 4Fh 31:24 52h52h
Sector Type 3 Size Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB 50h 07:00 10h10h
Sector Type 3 erase Opcode 51h 15:08 D8hD8h
Sector Type 4 Size 00h: N/A, This sector type doesn't
exist 52h 23:16 00h00h
Sector Type 4 erase Opcode 53h 31:24 FFh FFh
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI-
08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
62
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 16. Parameter Table (1): Macronix Flash Parameter Tables
Description Comment Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Vcc Supply Maximum Voltage
2000h=2.000V
2700h=2.700V
3600h=3.600V
61h:60h 07:00
15:08
00h
36h
00h
36h
Vcc Supply Minimum Voltage
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
2350h=2.350V, 2650h=2.650V
2700h=2.700V
63h:62h 23:16
31:24
50h
26h
50h
26h
H/W Reset# pin 0=not support 1=support
65h:64h
00 0b
F99Eh
H/W Hold# pin 0=not support 1=support 01 1b
Deep Power Down Mode 0=not support 1=support 02 1b
S/W Reset 0=not support 1=support 03 1b
S/W Reset Opcode Reset Enable (66h) should be
issued before Reset Opcode 11:04 1001 1001b
(99h)
Program Suspend/Resume 0=not support 1=support 12 1b
Erase Suspend/Resume 0=not support 1=support 13 1b
Unused 14 1b
Wrap-Around Read mode 0=not support 1=support 15 1b
Wrap-Around Read mode Opcode 66h 23:16 77h77h
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
67h 31:24 64h64h
Individual block lock 0=not support 1=support
6Bh:68h
00 0b
CFFEh
Individual block lock bit
(Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 1b
Individual block lock Opcode 09:02 1111 1111b
(FFh)
Individual block lock Volatile
protect bit default protect status 0=protect 1=unprotect 10 1b
Secured OTP 0=not support 1=support 11 1b
Read Lock 0=not support 1=support 12 0b
Permanent Lock 0=not support 1=support 13 0b
Unused 15:14 11b
Unused 31:16 FFh FFh
Unused 6Fh:6Ch 31:00 FFh FFh
MX25L3233FM1I-08G-SFDP_2016-10-11,SF10
SFDP Table below is for MX25L3233FM1I-08G, MX25L3233FZBI-08G, MX25L3233FM2I-08G, MX25L3233FMI-
08G, MX25L3233FZNI-08G, MX25L3233FM1I-08Q, MX25L3233FZBI-08Q, MX25L3233FM2I-08Q,
MX25L3233FMI-08Q and MX25L3233FZNI-08Q
63
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Notes:
1: h/b is hexadecimal or binary.
2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode
(x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-
1), (2-2-2), and (4-4-4)
3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specied. (eg, read performance enhance toggling bits)
5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h
6: All unused and undened area data is blank FFh for SFDP Tables that are dened in Parameter
Identication Header. All other areas beyond dened SFDP Table are reserved by Macronix.
64
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
11. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following
levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data
change during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
65
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Vcc + 2.0V
Vcc
20ns 20ns
20ns
Vss
Vss-2.0V
20ns 20ns
20ns
12. Electrical Specications
12-1. Absolute Maximum Ratings
Symbol Parameter Min. Typ. Max. Unit Conditions
CIN Input Capacitance 6pF VIN = 0V
COUT Output Capacitance 8pF VOUT = 0V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see
the gures below.
Figure 38. Maximum Negative Overshoot Waveform
12-2. Capacitance TA = 25°C, f = 1.0 MHz
Figure 39. Maximum Positive Overshoot Waveform
RATING VALUE
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to 4.6V
Applied Output Voltage -0.5V to 4.6V
VCC to Ground Potential -0.5V to 4.6V
66
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm
+3.3V
CL=30/15pF Including jig capacitance
Figure 40. Input Test Waveforms and Measurement Level
Figure 41. Output Loading
AC
Measurement
Level
Input timing reference level Output timing reference level
0.8VCC 0.7VCC
0.3VCC
0.5VCC
0.2VCC
Note: Input pulse rise and fall time are <2.4ns
Figure 42. SCLK TIMING DEFINITION
VIH (Min.)
0.5VCC
VIL (Max.)
tCHCL
tCH
1/fSCLK
tCL
tCLCH
67
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 17. DC Characteristics
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and
speeds).
2. Typical value is calculated by simulation.
3. The value guaranteed by characterization, not 100% tested in production.
Temperature = -40°C to 85°C for Industrial grade
Symbol Parameter Notes Min. Typ. Max. Units Test Conditions
ILI Input Load Current 1 ± 2 uA VCC = VCC Max,
VIN = VCC or GND
ILO Output Leakage Current 1 ± 2 uA VCC = VCC Max,
VOUT = VCC or GND
ISB1 VCC Standby Current 1 10 50 uA VIN = VCC or GND,
CS# = VCC
ISB2 Deep Power-down Current 3 20 uA VIN = VCC or GND,
CS# = VCC
ICC1 VCC Read 1
2.5 5 mA
f=50MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
10 17 mA
fQ=133MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
ICC2 VCC Program Current (PP) 1 10 15 mA Program in Progress,
CS# = VCC
ICC3 VCC Write Status Register
(WRSR) Current 10 15 mA Program status register in
progress, CS#=VCC
ICC4 VCC Sector Erase
Current (SE) 1 10 15 mA Erase in Progress,
CS#=VCC
ICC5 VCC Chip Erase Current
(CE) 1 10 15 mA Erase in Progress,
CS#=VCC
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
68
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Table 18. AC Characteristics
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE32K, BE, CE, RES, WREN,
WRDI, RDID, RDSR, WRSR
D.C. 133 MHz
fTSCLK fT Clock Frequency for 2READ/DREAD instructions 133 MHz
fQ Clock Frequency for 4READ/QREAD instructions 133 MHz
f4PP Clock Frequency for 4PP (Quad page program) 133 MHz
fRSCLK fR Clock Frequency for READ instructions 50 MHz
tCH(1) tCLH Clock High Time Others (fSCLK) 45% x (1/fSCLK) ns
Normal Read (fRSCLK) 9 ns
tCL(1) tCLL Clock Low Time Others (fSCLK) 45% x (1/fSCLK) ns
Normal Read (fRSCLK) 9 ns
tCLCH(2) Clock Rise Time (peak to peak) 0.1 V/ns
tCHCL(2) Clock Fall Time (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 4ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 4 ns
tDVCH tDSU Data In Setup Time 2ns
tCHDX tDH Data In Hold Time 3ns
tCHSH CS# Active Hold Time (relative to SCLK) 4ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 4ns
tSHSL tCSH CS# Deselect Time
From Read to next Read 15 ns
From Write/Erase/Program
to Read Status Register 50 ns
tSHQZ(2) tDIS Output Disable Time 2.65V-3.6V 10 ns
3.0V-3.6V 8ns
tHLCH HOLD# Setup Time (relative to SCLK) 5 ns
tCHHH HOLD# Hold Time (relative to SCLK) 5 ns
tHHCH HOLD Setup Time (relative to SCLK) 5 ns
tCHHL HOLD Hold Time (relative to SCLK) 5 ns
tHHQX tLZ HOLD to Output Low-Z
Loading=30pF
2.65V-3.6V 10 ns
3.0V-3.6V 8ns
tHLQZ tHZ HOLD# to Output High-Z
Loading=30pF
2.65V-3.6V 10 ns
3.0V-3.6V 8ns
tCLQV tV Clock Low to Output Valid
VCC=2.65V-3.6V
Loading: 15pF 6ns
Loading: 30pF 8ns
tCLQX tHO Output Hold Time 1ns
tWHSL(3) Write Protect Setup Time 20 ns
tSHWL(3) Write Protect Hold Time 100 ns
tESL(4) Erase Suspend Latency 20 us
tPSL(4) Program Suspend Latency 20 us
tPRS(5) Latency between Program Resume and next Suspend 0.3 100 us
tERS(6) Latency between Erase Resume and next Suspend 0.3 200 us
Temperature = -40°C to 85°C for Industrial grade
69
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
5. For tPRS, minimum timing must be observed before issuing the next program suspend command.
However, a period equal to or longer than the typical timing is required in order for the program operation
to make progress.
6. For tERS, minimum timing must be observed before issuing the next erase suspend command.
However, a period equal to or longer than the typical timing is required in order for the erase operation to
make progress.
Symbol Alt. Parameter Min. Typ. Max. Unit
tRCR Recovery Time from Read 20 us
tRCP Recovery Time from Program 20 us
tRCE Recovery Time from Erase 12 ms
tDP CS# High to Deep Power-down Mode 10 us
tRES1 CS# High to Standby Mode without Electronic Signature
Read 100 us
tRES2 CS# High to Standby Mode with Electronic Signature Read 100 us
tW Write Status Register Cycle Time 40 ms
tBP Byte-Program 10 50 us
tPP Page Program Cycle Time 0.33 1.2 ms
tSE Sector Erase Cycle Time (4KB) 25 200 ms
tBE32K Block Erase Cycle Time (32KB) 0.14 0.6 s
tBE Block Erase Cycle Time (64KB) 0.25 1 s
tCE Chip Erase Cycle Time 10 30 s
tWSR Write Security Register Time 1 ms
70
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 43. Serial Input Timing
Figure 44. Output Timing
13. TIMING ANALYSIS
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
LSB
ADDR.LSB IN
tSHQZ
tCH
tCL
tCLQX
tCLQV
tCLQX
tCLQV
SCLK
SO
CS#
SI
71
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 45. Hold Timing
High-Z
01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tWHSL tSHWL
SCLK
SI
CS#
WP#
SO
Figure 46. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
SCLK
SO
CS#
HOLD#
72
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the gure, please refer
to "Table 18. AC Characteristics".
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 500000 us/V
14. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 47. AC Timing at Device Power-Up" and "Figure 48. Power-Down Sequence"
are for the supply voltages and the control signals at device power-up and power-down. If the timing in the g-
ures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 47. AC Timing at Device Power-Up
SCLK
SI
CS#
VCC
MSB IN
SO
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
tVR
VCC(min)
GND
73
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
Figure 48. Power-Down Sequence
CS#
SCLK
VCC
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
Figure 49. Power-up Timing
VCC
VCC(min)
Chip Selection is Not Allowed
tVSL
time
Device is fully accessible
VCC(max)
VWI
74
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
14-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
Figure 50. Power Up/Down and Voltage Drop
Table 19. Power-Up/Down Voltage and Timing
VCC
Time
VCC (max.)
VCC (min.)
V
tPWD
tVSL
Chip Select is not allowed
Full Device
Access
Allowed
PWD
(max.)
When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 50. Power Up/Down and Voltage Drop" and "Table 19. Power-
Up/Down Voltage and Timing" below for more details.
Note: These parameters are characterized only.
Symbol Parameter Min. Max. Unit
tVSL VCC(min.) to device operation 800 us
VWI Write Inhibit Voltage 1.5 2.5 V
VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.9 V
tPWD The minimum duration for ensuring initialization will occur 300 us
VCC VCC Power Supply 2.65 3.6 V
75
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
15. ERASE AND PROGRAMMING PERFORMANCE
16. DATA RETENTION
Min. Max.
Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax
Input Voltage with respect to GND on SO -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
17. LATCH-UP CHARACTERISTICS
Parameter Condition Min. Max. Unit
Data retention 55˚C 20 years
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.65V.
3. System-level overhead is the time required to execute the rst-bus-cycle sequence for the programming com-
mand.
Parameter Typ.(1) Max.(2) Unit
Write Status Register Cycle Time 40 ms
Sector Erase Time (4KB) 25 200 ms
Block Erase Time (64KB) 0.25 1 s
Block Erase Time (32KB) 0.14 0.6 s
Chip Erase Time 10 30 s
Byte Program Time (via page program command) 10 50 us
Page Program Time 0.33 1.2 ms
Erase/Program Cycle 100,000 cycles
76
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
18. ORDERING INFORMATION
Please contact our regional sales for the latest product selection and available form factors.
PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark
MX25L3233FM1I-08G 133 -40°C to 85°C 8-SOP
(150mil)
MX25L3233FM2I-08G 133 -40°C to 85°C 8-SOP
(200mil)
MX25L3233FZBI-08G 133 -40°C to 85°C 8-USON
(4x3mm)
MX25L3233FMI-08G 133 -40°C to 85°C 16-SOP
(300mil)
MX25L3233FZNI-08G 133 -40°C to 85°C 8-WSON
(6x5mm)
MX25L3233FM1I-08Q 133 -40°C to 85°C 8-SOP
(150mil)
MX25L3233FM2I-08Q 133 -40°C to 85°C 8-SOP
(200mil)
MX25L3233FZBI-08Q 133 -40°C to 85°C 8-USON
(4x3mm)
MX25L3233FZNI-08Q 133 -40°C to 85°C 8-WSON
(6x5mm)
77
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
19. PART NAME DESCRIPTION
MX 25 LM1 I
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M1: 150mil 8-SOP
M2: 200mil 8-SOP
ZB: 4x3mm 8-USON
M: 300mil 16-SOP
ZN: 6x5mm 8-WSON
DENSITY & MODE:
3233F: 32Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial NOR Flash
3233F 08 G
OPTION:
G/Q: RoHS Compliant & Halogen-free
Manufacturing Location
SPEED:
08: 133MHz
78
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
20. PACKAGE INFORMATION
20-1. 8-pin SOP (150mil)
79
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
20-2. 8-pin SOP (200mil)
80
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
20-3. 8-land USON (4x3mm)
81
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
20-4. 16-pin SOP (300mil)
82
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
20-5. 8-WSON (6x5mm)
83
MX25L3233F
P/N: PM2113 Rev. 1.6, March 10, 2017
21. REVISION HISTORY
Revision No. Description Page Date
0.01 1. Added 16-SOP(300mil) package information P5,7,76,77, OCT/03/2014
P81
2. Added parameters name for Suspend/Resume P55,56,68
3. Modied input pulse time for Test Waveforms gure P66
4. Modied Notes of AC Characteristics Table P68-69
5. Content Modication P13,34,57
6. Added Release from Deep Power-down (RDP) Sequence. P49
7. Added Read Electronic Manufacturer ID & Device ID (REMS). P50
8. Modied Power-Up/Down Voltage and Timing table P74
9. Added minimum voltage description in SFDP Table P62
10. Modied Package Outline of SOP 16L (300MIL) P81
11. Modied Hold gure and description P14,15
1.0 1. Removed "ADVANCED INFORMATION" All OCT/23/2014
2.
Added "Advanced Information" for 8-USON and 16-SOP part no.
P76
3. Added package 8-WSON (6x5mm) and P5,P7,76,77,82
Part number MX25L3233FZNI-08G (Advanced Information)
4. Revised AC value: tRCR (min) = 20us. P69
1.1 1. Updated the ordering information of MX25L3233FZBI-08G, P77 JAN/05/2015
MX25L3233FMI-08G, and MX25L3233FZNI-08G.
2. Modied BLOCK DIAGRAM. P8
3. Updated suspend/resume descriptions. P55-57
4. Modied tCH/tCL formula. P69
5. Modied "10-14. Burst Read" content. P38
1.2 1. Removed note 1 of PIN DESCRIPTION P7 MAR/11/2015
1.3 1. Updated part number list. P76-77 OCT/11/2016
2. Added a statement for product ordering information. P76
3. Updated the information of erase/program cycles. P72
4. Content modication. P1,5,18,24,
33,49,51
5. Modied Performance Enhance Mode Reset descriptions. P36-37
6. Modied Deep Power-down (DP) descriptions. P46
7. Updated tVR values. P72,74
1.4 1. Updated "19. PART NAME DESCRIPTION". P77 OCT/21/2016
1.5 1. Added the note for the internal pull up status of HOLD#/SIO3 P7 DEC/28/2016
and WP#/SIO2
2. Added "Figure 42. SCLK TIMING DEFINITION" P66
1.6 1. Content modication. P1,16-18 MAR/10/2017
P35,68,74
2. Modied the descriptions of "10-19. Page Program (PP)". P42
3. Modied the descriptions of "10-14. Burst Read". P37
Except for customized products which have been expressly identied in the applicable agreement, Macronix's prod-
ucts are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household
applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury,
or severe property damages. In the event Macronix products are used in contradicted to their target usage above,
the buyer shall take any and all actions to ensure said Macronix's product qualied for its actual use in accordance
with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released
from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2014-2017. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix
NBit, eLiteFlash, HybridNVM, HybridFlash, HybridXFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Book, Rich TV, OctaRAM, OctaBus, OctaFlash and
FitCAM. The names and brands of third party referred thereto (if any) are for identication purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
84
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specications without notice.
MX25L3233F