For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MX7841 contains eight 14-bit, voltage-output digi-
tal-to-analog converters (DACs). On-chip precision out-
put amplifiers provide the voltage outputs. The device
operates from ±15V supplies. Its bipolar output voltage
swing ranges from (VSS + 2.5V) to (VDD - 2.5V) and is
achieved with no external components. The MX7841
has three pairs of differential reference inputs; two of
these pairs are connected to two DACs each, and a
third pair is connected to four DACs. The references
are independently controlled, providing different full-
scale output voltages to the respective DACs.
The MX7841 features double-buffered interface logic
with a 14-bit parallel data bus. Each DAC has an input
latch and a DAC latch. Data in the DAC latch sets the
output voltage. The eight input latches are addressed
with three address lines. Data is loaded to the input
latch with a single write instruction. An asynchronous
load input (LDAC) transfers data from the input latch to
the DAC latch. The LDAC input controls all DACs;
therefore, all DACs can be updated simultaneously by
asserting LDAC.
An asynchronous CLR input sets the output of all eight
DACs to the respective DUTGND input of the op amp.
Note that CLR is a CMOS input, which is powered by
VDD. All other logic inputs are TTL/CMOS compatible.
The MX7841 is pin-for-pin compatible with AD7841.
Applications
Automatic Test Equipment (ATE)
Industrial Process Controls
Arbitrary Function Generators
Avionics Equipment
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
SONET Applications
Features
♦Full 14-Bit Performance Without Adjustments
♦Eight DACs in a Single Package
♦Buffered Voltage Outputs
♦Unipolar or Bipolar Voltage Swing of (VSS + 2.5V)
to (VDD - 2.5V)
♦31µs Output Settling Time
♦Low Power Consumption: 8mA (typ)
♦Small 44-Pin MQFP Package
♦Double-Buffered Digital Inputs
♦Asynchronous Load Updates All DACs
Simultaneously
♦Asynchronous CLR Forces All DACs to
DUTGND_ _ Potential
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
________________________________________________________________ Maxim Integrated Products 1
DUTGNDGH
OUTH
REFGH-
REFGH+
CLR
DB13
DB12
DB11
DB10
DB9
DB8
DUTGNDAB
OUTA
REFAB-
REFAB+
VDD
VSS
LDAC
A2
A1
A0
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WR
VCC
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OUTB
OUTC
DUTGNDCD
OUTD
REFCDEF-
REFCDEF+
VDD
OUTE
DUTGNDEF
OUTF
OUTG
MQFP
MX7841
TOP VIEW
19-2953; Rev 0; 7/03
PART
MX7841BS
MX7841AS -40°C to +85°C
-40°C to +85°C
TEMP RANGE PIN-
PACKAGE
44 MQFP
44 MQFP
Functional Diagram appears at end of data sheet.
Pin Configuration
Ordering Information
INL
(LSB)
±2
±4
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND ...........................................................-0.3V to +17V
VSS to GND ........................................................... -17V to +0.3V
VCC to GND ............................................................ -0.3V to +6V
A_, DB_, WR, CS, LDAC, CLR to GND .....+0.3V to (VCC + 0.3V)
REF_ _ _ _+, REF_ _ _ _-,
DUTGND_ _ .................................(VSS - 0.3V) to (VDD + 0.3V)
OUT_ ..........................................................................VDD to VSS
Maximum Current into REF_ _ _ _ _, DUTGND_ _ ...........±10mA
Maximum Current into Any Signal Pin ..............................±50mA
OUT_ Short-Circuit Duration to VDD, VSS, and GND ................1s
Continuous Power Dissipation (TA= +70°C)
44-Pin MQFP (derate 11.1mW/°C above +70°C).........870mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(Note 1)
MX7841BS
(Note 1)
(Note 1)
MX7841AS
Guaranteed monotonic
CONDITIONS
Ω0.5DC Output Impedance
pF50Capacitive Load to GND
kΩ5Resistive Load to GND
V
(VSS + 2.5) to
(VDD - 2.5)
Output Voltage Swing
V210
(REF_ _ _ _+) - (REF_ _ _ _-)
Range
V-5 0REF_ _ _ _- Input Range
V05REF_ _ _ _+ Input Range
µA±1Input Current
MΩ100Input Resistance
±2
Bits14NResolution
µV75 120DC Crosstalk
ppm
FSR/°C
0.5 10Gain Temperature Coefficient
LSB±2Gain Error
LSB
±4
INLRelative Accuracy
LSB±1DNLDifferential Nonlinearity
LSB±2 ±8Full-Scale Error
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL= 5kΩ,
CL= 50pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
LSB±2 ±8Zero-Scale Error
STATIC PERFORMANCE (ANALOG SECTION)
REFERENCE INPUTS
ANALOG OUTPUTS
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL= 5kΩ,
CL= 50pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
INTERFACE TIMING CHARACTERISTICS
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, Figure 2a,
TA= TMIN to TMAX, unless otherwise noted.)
CONDITIONS
kΩ60Input Impedance per DAC
µA±300Maximum Input Current per DAC
UNITSMIN TYP MAXSYMBOLPARAMETER
Digital inputs = 0V or VCC µA±1 ±10IIN
V-2 +2Input Range
Input Current
V4.75 5.25VCC
VCC Digital Power Supply
V13.5 16.5VDD
VDD Analog Power-Supply
Range
V-16.75 -13.5VSS
VSS Analog Power-Supply
Range
VSS = -15V ±5%
VDD = +15V ±5%
dB90
RL= ∞
dB
RL= ∞
90PSRR, ∆VOUT / ∆VDD
PSRR, ∆VOUT / ∆VSS
mA810ISS
mA810IDD
Positive Supply Current
Negative Supply Current
(Note 2) mA0.5ICC
Digital Supply Current
ns0t4
ns50t3
LDAC Pulse Width Low
CS Low to WR Low
CONDITIONS
ns50t1
CS Pulse Width Low
ns50t2
WR Pulse Width Low
UNITSMIN TYP MAXSYMBOLPARAMETER
ns15t8
ns0t7
Data Valid to WR Hold
Address Valid to WR Setup
ns0t5
CS High to WR High
ns20t6
Data Valid to WR Setup
ns0t9
Address Valid to WR Hold
(Note 1) pF10CIN
Input Capacitance
V2.4VIH
Input Voltage High
V0.8VIL
Input Voltage Low
DUTGND_ _ CHARACTERISTICS
POWER SUPPLIES
DIGITAL INPUTS
(Figure 2b) ns300t10
CLR Pulse-Activation Time
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
4 _______________________________________________________________________________________
Note 1: Guaranteed by design. Not production tested.
Note 2: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at GND or VCC potential.
Note 3: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at +0.8V or +2.4V.
Note 4: All digital inputs (DB0 to DB13) transition from GND to VCC with WR = VCC
DYNAMIC CHARACTERISTICS
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL= 5kΩ,
CL= 50pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 4)
(Note 3)
VREF+ = VREF- = 0
0.2
To ±0.5 LSB of full scale
0.1Digital Feedthrough
Digital Crosstalk
nV/√Hz
200
dB99Channel-to-Channel Isolation
CONDITIONS
Output Noise Spectral Density
230Digital-to-Analog Glitch Impulse
nV-s
nV-s
nV-s
nV-s
40DAC-to-DAC Crosstalk
µs31Output Settling Time
V/µs0.7Output Slew Rate
UNITSMIN TYP MAXSYMBOLPARAMETER
Typical Operating Characteristics
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA=
+25°C, unless otherwise noted.)
INL vs. CODE
MX7841 toc01
CODE
INL (LSB)
14336122888192 102404096 61442048
-0.400
-0.300
-0.200
-0.100
0
0.100
0.200
0.300
0.400
0.500
-0.500
0 16384
DNL vs. CODE
MX7841 toc02
CODE
DNL (LSB)
14336122888192 102404096 61442048
-0.400
-0.300
-0.200
-0.100
0
0.100
0.200
0.300
0.400
0.500
-0.500
0 16384
INL AND DNL ERROR
vs. TEMPERATURE
MX7841 toc03
TEMPERATURE (°C)
ERROR (LSB)
8060-20 020 40
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.4
-40
INL
DNL
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________ 5
1M 10M
-40
-35
-30
-25
-20
-10
-15
-5
0
5
1k 10k 100k
REFERENCE INPUT FREQUENCY RESPONSE
MX7841 toc07
FREQUENCY (Hz)
AMPLITUDE (dB)
REF_ _ _ _ _ = 200mVp-p
SETTLING TIME
vs. CAPACITIVE LOAD
MX7841 toc08
CAPACITIVE LOAD (pF)
SETTLING TIME (µs)
10,0001000100
10
20
30
40
50
60
70
80
90
100
0
10 100,000
LARGE-SIGNAL STEP RESPONSE
MX7841 toc09
10µs/div
LDAC
5V/div
OUT_
5V/div
POSITIVE SETTLING TIME
MX7841 toc10
10µs/div
OUT_
1mV/div
LDAC
5V/div
NEGATIVE SETTLING TIME
MX7841 toc11
10µs/div
OUT_
1mV/div
LDAC
5V/div
1000
100
10 100 1k 10k
NOISE VOLTAGE DENSITY
vs. FREQUENCY
MX7841 toc12
FREQUENCY (Hz)
NOISE VOLTAGE DENSITY (nV/√Hz)
ZERO-SCALE AND FULL-SCALE ERROR
vs. TEMPERATURE
MX7841 toc04
TEMPERATURE (°C)
ERROR (LSB)
806020 400-20
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
-0.8
-40
FULL SCALE
ZERO SCALE
IDD AND ISS
vs. TEMPERATURE
MX7841 toc05
TEMPERATURE (°C)
IDD, ISS (mA)
80655035205-10-25
5.5
6.0
6.5
7.0
7.5
8.0
5.0
-40
IDD
ISS
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MX7841 toc06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT, ICC (µA)
806535 50-10 520-25
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
20.0
-40
Typical Operating Characteristics (continued)
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA=
+25°C, unless otherwise noted.)
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
6 _______________________________________________________________________________________
ZERO-SCALE ERROR
vs. VREF (VREF+ - VREF-)
MX7841 toc17
VREF (V)
ZSE (LSB)
862 4
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
010
OUT
LDAC
5V/div
5mV/div
MAJOR CARRY GLITCH IMPULSE
(0xFFFF–0x10000)
MX7841 toc13
2µs/div
MX7841 toc14
2µs/div
OUT
LDAC
MAJOR CARRY GLITCH IMPULSE
(0x1000–0xFFF)
5V/div
5mV/div
GAIN ERROR vs. VREF
(VREF+ - VREF-)
MX7841 toc15
VREF (V)
GAIN ERROR (LSB)
8642
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
-0.5
010
DNL (MAX, MIN)
vs. VREF (VREF+ - VREF-)
MX7841 toc16
VREF (V)
DNL (MAX, MIN) (LSB)
862 4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.4
010
FULL-SCALE ERROR
vs. VREF (VREF+ - VREF-)
MX7841 toc18
VREF (V)
FSE (LSB)
862 4
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
010
-40
-20
-30
0
-10
20
10
30
-40 -10 5-25 20 35 50 65 80
SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
MX7841 toc20
TEMPERATURE (°C)
SHORT CIRCUIT CURRENT (mA)
ZERO-SCALE OUTPUT,
SINKING CURRENT
FULL-SCALE OUTPUT,
SOURCING CURRENT
Typical Operating Characteristics (continued)
(VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA=
+25°C, unless otherwise noted.)
INL (MAX, MIN)
vs. VREF (VREF+ - VREF-)
MX7841 toc19
VREF (V)
INL (MAX, MIN) (LSB)
8642
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
010
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________ 7
Pin Description
PIN
Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced
to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB.
DUTGNDAB1
FUNCTIONNAME
DAC A Buffered Output VoltageOUTA2
Positive Reference Input for DACs A and BREFAB+4
Negative Reference Input for DACs A and B REFAB-3
Negative Analog Power Supply. Normally set to -15V. See the Power Supplies, Grounding, and
Bypassing section for bypass requirements.
VSS
6
Address Bit 2 (MSB)A28
Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their
respective DAC latches. DAC latches are transparent when LDAC is low and latched when LDAC is
high.
LDAC
7
Positive Analog Power Supply. Normally set to +15V. Connect both pins to the supply voltage. See the
Power Supplies, Grounding, and Bypassing section for bypass requirements.
VDD
5, 38
Address Bit 1A19
Chip Select. Active-low input.
CS
11
Address Bit 0 (LSB)A010
Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transpar-
ent when WR and CS are both low. WR latches data into the DAC input latch selected by A2, A1, A0 on
the rising edge of CS.
WR
12
Digital Power Supply. Normally set to +5V. See the Power Supplies, Grounding, and Bypassing section
for bypass requirements.
VCC
13
Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _.
Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes
high.
Data Bits 0–13. Offset binary coding.DB0–DB1315–28
GroundGND14
CLR
29
Positive Reference Input for DACs G and HREFGH+30
Negative Reference Input for DACs G and HREFGH-31
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
8 _______________________________________________________________________________________
Pin Description (continued)
FUNCTIONNAMEPIN
DAC H Buffered Output VoltageOUTH32
DAC G Buffered Output VoltageOUTG34
Device Sense Ground Input for OUTE and OUTF. In normal operation, OUTE and OUTF are referenced
to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF.
DUTGNDEF36
DAC F Buffered Output VoltageOUTF35
Device Sense Ground Input for OUTG and OUTH. In normal operation, OUTG and OUTH are referenced
to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH.
DUTGNDGH33
Positive Reference Input for DACs C, D, E, and FREFCDEF+39
DAC D Buffered Output VoltageOUTD41
Negative Reference Input for DACs C, D, E, and FREFCDEF-40
DAC C Buffered Output VoltageOUTC43
DAC B Buffered Output VoltageOUTB44
Device Sense Ground Input for OUTC and OUTD. In normal operation, OUTC and OUTD are referenced
to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD.
DUTGNDCD42
DAC E Buffered Output VoltageOUTE37
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________________________________________________________________________________ 9
_______________Detailed Description
Analog Section
The MX7841 contains eight 14-bit voltage-output DACs.
These DACs are inverted R-2R ladder networks that
convert 14-bit digital inputs into equivalent analog out-
put voltages, in proportion to the applied reference volt-
ages (Figure 1). The MX7841 has three positive
reference inputs (REF_ _ _ _+) and three negative refer-
ence inputs (REF_ _ _ _-). The difference from
REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the
DAC output span.
In addition to the differential reference inputs, the
MX7841 has four analog-ground input pins
(DUTGND_ _). When CLR is high (unasserted), the volt-
age on DUTGND_ _ offsets the DAC output voltage
range. If CLR is asserted, the output amplifier is forced
to the voltage present on DUTGND_ _.
Reference and DUTGND Inputs
All of the MX7841’s reference inputs are buffered with
precision amplifiers. This allows the flexibility of using
resistive dividers to set the reference voltages. Because
of the relatively high multiplying bandwidth of the refer-
ence input (188kHz), any signal present on the reference
pin within this bandwidth is replicated on the DAC output.
The DUTGND pins of the MX7841 are connected to the
negative source resistor (nominally 115kΩ) of the out-
put amplifier. The DUTGND pins are typically connect-
ed directly to analog ground. Each of these pins has an
input current that varies with the DAC digital code. If
the DUTGND pins are driven by external circuitry, bud-
get ±200µA per DAC for load current.
Output-Buffer Amplifiers
The MX7841’s voltage outputs are internally buffered by
precision gain-of-two amplifiers with a typical slew rate
of 1V/µs. With a full-scale transition at its output, the
typical settling time to ±1/2 LSB is 31µs. This settling
time does not significantly vary with capacitive loads
less than 10,000pF.
Output Deglitching Circuit
The MX7841’s internal connection from the DAC ladder
to the output amplifier contains special deglitch circuitry.
REF-
REF+
2R 2R 2R 2R 2R
OUT
DUTGND
2R
CLR RR
D0 D12 D13
Figure 1. DAC Simplified Circuit
VOUT_
CLR
t10 t10
Figure 2b. Digital Timing Diagram
CS
WR
A0–A2
DB0–DB13
LDAC
NOTES:
(NOTE 3)
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. tr = tf = 5ns.
2.
3.
t1
t2
t8
t9
t6t7
t4t5
t3
t3
MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2.
IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW
FOR t3 OR LONGER AFTER WR GOES HIGH.
Figure 2a. Digital Timing Diagram
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
10 ______________________________________________________________________________________
This glitch/deglitch circuitry is enabled on the falling
edge of LDAC to remove the glitch from the R-2R DAC.
This enables the MX7841 to exhibit a fraction of the glitch
impulse energy of parts without the deglitching circuit.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MX7841 interfaces with microproces-
sors using a data bus at least 14 bits wide. The inter-
face is double buffered, allowing simultaneous
updating of all DACs. There are two latches for each
DAC (see the Functional Diagram): an input latch that
receives data from the data bus, and a DAC latch that
receives data from the input latch. Address lines A0,
A1, and A2 select which DAC’s input latch receives
data from the data bus as shown in Table 1. Both the
input latches and the DAC latches are transparent
when CS, WR, and LDAC are all low. Any change of
DB0–DB13 during this condition appears at the output
instantly. Transfer data from the input latches to the
DAC latches by asserting the asynchronous LDAC sig-
nal. Each DAC’s analog output reflects the data held in
its DAC latch. All control inputs are level triggered.
Table 2 is an interface truth table.
Input Write Cycle
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch, and LDAC transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low,
and the DAC latch is transparent when LDAC is low.
The address lines (A0, A1, A2) must be valid for the
duration that CS and WR are low (Figure 2a) to prevent
data from being inadvertently written to the wrong DAC.
Data is latched within the input latch when either CS or
WR is high.
Loading the DACs
Taking LDAC high latches data into the DAC latches. If
LDAC is brought low when WR and CS are low, the
DAC addressed by A0, A1, and A2 is directly con-
trolled by the data on DB0–DB13. This allows the maxi-
mum digital update rate; however, it is sensitive to any
glitches or skew in the input data stream.
Asynchronous Clear
The MX7841 has an asynchronous clear pin (CLR) that,
when asserted, sets all DAC outputs to the voltage pre-
sent on their respective DUTGND pins. Deassert CLR to
return the DAC output to its previous voltage. Note that
CLR does not clear any of the internal digital registers.
See Figure 2b.
Applications Information
Multiplying Operation
The MX7841 can be used for multiplying applications.
Its reference accepts both DC and AC signals. Since
the reference inputs are unipolar, multiplying operation
is limited to two quadrants. See the graphs in the
Typical Operating Characteristics for dynamic perfor-
mance of the DACs and output buffers.
Digital Code and
Analog Output Voltage
The MX7841 uses offset binary coding. A 14-bit two’s
complement code is converted to a 14-bit offset binary
code by adding 213 = 8192.
Output Voltage Range
For typical operation, connect DUTGND to signal ground,
VREF+ to +5V, and VREF- to -5V. Table 3 shows the rela-
tionship between digital code and output voltage.
A2 FUNCTION
DAC A input latch0
DAC C input latch0
DAC B input latch0
DAC D input latch0
DAC H input latch1
DAC E input latch1
DAC G input latch1
DAC F input latch1
A1
1
0
1
1
0
0
1
0
A0
1
0
0
1
1
0
0
1
CLR
DAC register transparent
FUNCTION
X
Input register transparentX
Input register latchedX
Input register latchedX
DAC register latchedX
Outputs of DACs set to volt-
age defined by the DAC
register, the references,
and the corresponding
DUTGND_ _
1
Outputs of DACs at
DUTGND_ _
0
LD
0
X
X
X
1
1
X
WR
X
0
1
X
X
X
X
Table 1. MX7841 DAC Addressing
Table 2. Interface Truth Table
CS
X
0
X
1
X
X
X
X = Don’t care.
The DAC digital code controls each leg of the 14-bit
R-2R ladder. A code of 0x0 connects all legs of the lad-
der to REF-, corresponding to a DAC output voltage
(VDAC) equal to REF-. A code of 0x3FFF connects all
legs of the ladder to REF+, corresponding to a VDAC
approximately equal to REF+.
The output amplifier multiplies VDAC by 2, yielding an out-
put voltage range of 2 ✕REF- to 2 ✕REF+ (Figure 1).
Further manipulation of the output voltage span is accom-
plished by offsetting DUTGND. The output voltage of the
MX7841 is described by the following equation:
where DATA is the numeric value of the DAC’s binary
input code, and DATA ranges from 0 to 16,383
(214 - 1). The resolution of the MX7841, defined as
1 LSB, is described by the following equation:
Reference Selection
Because the MX7841 has precision buffers on its refer-
ence inputs, the requirements for interfacing to these
inputs are minimal. Select a low-drift, low-noise refer-
ence within the recommended REF+ and REF- voltage
ranges. The MX7841 does not require bypass capaci-
tors on its reference inputs. Add capacitors only if the
reference voltage source requires them to meet system
specifications.
Minimizing Output Glitch
The MX7841’s internal deglitch circuitry is enabled on
the falling edge of LDAC. Therefore, to achieve opti-
mum performance, drive LDAC low after the inputs are
either latched or steady state. This is best accom-
plished by having the falling edge of LDAC occur at
least 50ns after the rising edge of CS.
Power Supplies, Grounding,
and Bypassing
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal operation,
connect the four DUTGND pins directly to the ground
plane. Avoid sharing the connections of these sensitive
pins with other ground traces.
As with any sensitive data-acquisition system, connect
the digital and analog ground planes together at a sin-
gle point, preferably directly underneath the MX7841.
Avoid routing digital signals underneath the MX7841 to
minimize their coupling into the IC.
For normal operation, bypass VDD and VSS with 0.1µF
ceramic chip capacitors to the analog ground plane. To
enhance transient response and capacitive drive capa-
bility, add 10µF tantalum capacitors in parallel with the
ceramic capacitors. Note, however, that the MX7841
does not require the additional capacitance for stability.
Bypass VCC with a 0.1µF ceramic chip capacitor to the
digital ground plane.
Power-Supply Sequencing
To guarantee proper operation of the MX7841, ensure
that power is applied to VDD before VSS and VCC. Also
ensure that VSS is never more than 300mV above
ground. To prevent this situation, connect a Schottky
diode between VSS and the analog ground plane, as
shown in Figure 3. Do not power up the logic input pins
LSB REF REF
=+− −
()
2
214
V 2 V V DATA
2
V
V
OUT REF REF 14 REF
DUTGND
=−
()
+
−
+− −
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
______________________________________________________________________________________ 11
Note: Output voltage is based on REF+ = +5V, REF- = -5V, and
DUTGND = 0.
GND
VSS
SYSTEM GND
1N5817
MX7839
VSS
VSS
Figure 3. Schottky Diode Between VSS and GND
Table 3. Analog Voltage vs. Digital Code
INPUT CODE OUTPUT
VOLTAGE (V)
11 1111 1111 1111 +9.998779
10 0000 0000 0000 0
01 0011 1011 0010 -3.845215
00 0000 0000 0001 -9.998779
00 0000 0000 0000 -10
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
12 ______________________________________________________________________________________
before establishing the supply voltages. If this is not
possible and the digital lines can drive more than
10mA, place current-limiting resistors (e.g., 470Ω) in
series with the logic pins.
Driving Capacitive Loads
The MX7841 typically drives capacitive loads up to
0.01µF without a series output resistor. However, when-
ever driving high capacitive loads, it is prudent to use a
220Ωseries resistor between the MX7841 output and
the capacitive load.
Chip Information
TRANSISTOR COUNT: 13,225
PROCESS: BiCMOS
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
______________________________________________________________________________________ 13
Functional Diagram
REFGH+
REFGH-
REFCDEF+
REFCDEF-
REFAB+
REFAB-
OUTH
DUTGNDGH
DB0–
DB13
VCC
GND
A2
A1
A0
CS
14
RDAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DIGITAL
POWER
SUPPLY
ADDRESS
DECODE
LOGIC
ANALOG
POWER
SUPPLY
WR
LDAC
OUTG
OUTF
DUTGNDEF
OUTE
OUTD
DUTGNDCD
OUTC
OUTB
DUTGNDAB
OUTA
VDD
VSS
CLR
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
DAC
REG
A
DATA
REG
A
DAC
REG
B
DATA
REG
B
DAC
REG
C
DATA
REG
C
DAC
REG
D
DATA
REG
D
DAC
REG
E
DATA
REG
E
DAC
REG
F
DATA
REG
F
DAC
REG
G
DATA
REG
G
DAC
REG
H
DATA
REG
H
MX7841
MX7841
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MQFP44.EPS
D
1
1
21-0826
PACKAGE OUTLINE
44L MQFP, 1.60 LEAD FORM
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
