DAC7612U/2K5G4 - Texas Instruments

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DAC7612

Dual, 12-Bit Serial Input

DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION

The DAC7612 is a dual, 12-bit digital-to-analog con-

verter (DAC) with guaranteed 12-bit monotonicity

performance over the industrial temperature range. It

requires a single +5V supply and contains an input

shift register, latch, 2.435V reference, a dual DAC, and

high speed rail-to-rail output amplifiers. For a full-

scale step, each output will settle to 1 LSB within 7µs

while only consuming 3.7mW.

The synchronous serial interface is compatible with a

wide variety of DSPs and microcontrollers. Clock

(CLK), Serial Data In (SDI), Chip Select (CS) and

Load DACs (LOADDACS) comprise the serial inter-

face.

The DAC7612 is available in an 8-lead SOIC package

and is fully specified over the industrial temperature

range of –40°C to +85°C.

FEATURES

●LOW POWER: 3.7mW

●FAST SETTLING: 7µs to 1 LSB

●1mV LSB WITH 4.095V FULL-SCALE

RANGE

●COMPLETE WITH REFERENCE

●12-BIT LINEARITY AND MONOTONICITY

OVER INDUSTRIAL TEMP RANGE

●3-WIRE INTERFACE: Up to 20MHz Clock

●SMALL PACKAGE: 8-Lead SOIC

APPLICATIONS

●PROCESS CONTROL

●DATA ACQUISITION SYSTEMS

●CLOSED-LOOP SERVO-CONTROL

●PC PERIPHERALS

●PORTABLE INSTRUMENTATION

DAC7612

12-Bit DAC A

DAC Register A

14-Bit Serial Shift Register

DAC Register B Ref

LOADDACS

CLK

SDI

GND

OUTA

DAC7612

12-Bit DAC B V

OUTB

SBAS106

DAC7612

SPECIFICATIONS

At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

DAC7612U DAC7612UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 12 ✻Bits

ACCURACY

Relative Accuracy(1) –2 ±1/2 +2 –1 ±1/4 +1 LSB

Differential Nonlinearity Guaranteed Monotonic –1 ±1/2 +1 –1 ±1/4 +1 LSB

Zero-Scale Error Code 000H–1 +1 +3 ✻✻✻ LSB

Zero Scale Match Code 000H1/2 1/2 2 LSB

Full-Scale Voltage Code FFFH4.079 4.095 4.111 4.087 4.095 4.103 V

Full-Scale Match Code FFFH1/2 1/2 2 LSB

ANALOG OUTPUT

Output Current Code 800H±5±7✻✻ mA

Load Regulation RLOAD ≥ 402Ω, Code 800H13 ✻✻ LSB

Capacitive Load No Oscillation 500 ✻pF

Short-Circuit Current ±15 ✻mA

Short-Circuit Duration GND or VDD Indefinite ✻

DIGITAL INPUT

Data Format Serial ✻

Data Coding Straight Binary ✻

Logic Family CMOS ✻

Logic Levels

VIH 0.7 • VDD ✻V

VIL 0.3 • VDD ✻V

IIH ±10 ✻µA

IIL ±10 ✻µA

DYNAMIC PERFORMANCE

Settling Time(2) (tS) To ±1 LSB of Final Value 7 ✻µs

DAC Glitch 2.5 ✻nV-s

Digital Feedthrough 0.5 ✻nV-s

POWER SUPPLY

VDD +4.75 +5.0 +5.25 ✻✻✻ V

IDD

= 5V, V

= 0V, No Load, at Code 000

0.75 1.5 ✻✻ mA

Power Dissipation VIH = 5V, VIL = 0V, No Load 3.5 7.5 ✻✻ mW

Power Supply Sensitivity ∆VDD = ±5% 0.0025 0.002 ✻✻%/%

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Same specification as for DAC7612U.

NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where

the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.

DAC7612

PIN CONFIGURATION

Top View SO-8

VDD to GND .......................................................................... –0.3V to 6V

Digital Inputs to GND .............................................. –0.3V to VDD + 0.3V

VOUT to GND ...........................................................–0.3V to VDD + 0.3V

Power Dissipation ........................................................................ 325mW

Thermal Resistance,

JA ........................................................... 150°C/W

Maximum Junction Temperature..................................................+150°C

Operating Temperature Range ...................................... –40°C to +85°C

Storage Temperature Range ....................................... –65°C to +150°C

Lead Temperature (soldering, 10s)..............................................+300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

PIN DESCRIPTIONS

PIN LABEL DESCRIPTION

1 SDI Serial Data Input. Data is clocked into the internal

serial register on the rising edge of CLK.

2 CLK Synchronous Clock for the Serial Data Input.

3 LOADDACS Loads the internal DAC registers. All DAC registers

are transparent latches and are transparent when

LOADDACS is LOW (regardless of the state of CS

or CLK).

4 CS Chip Select. Active LOW.

OUTB DAC B Output Voltage

6 GND Ground

DD Positive Power Supply

OUTA DAC A Output Voltage

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE

ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT

PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER(1) NUMBER(2) MEDIA

DAC7612U ±2±1 –40°C to +85°C SO-8 182 DAC7612U Rails

"" " " ""DAC7612U/2K5 Tape and Reel

DAC7612UB ±1±1 –40°C to +85°C SO-8 182 DAC7612UB Rails

"" " " ""DAC7612UB/2K5 Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single

2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

SDI

CLK

LOADDACS

OUTA

GND

OUTB

DAC7612U

DAC7612

EQUIVALENT INPUT LOGIC

Serial Shift Register

DAC B Register

DAC A Register

DAC Switches

Data

DAC Switches

ESD protection

diodes to V

and GND

LOADDACS

SDI

CLK

DAC7612

TIMING DIAGRAMS

LOGIC TRUTH TABLE TIMING SPECIFICATIONS

TA = –40°C to +85°C and VDD = +5V.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCH Clock Width HIGH 30 ns

tCL Clock Width LOW 30 ns

tLDW Load Pulse Width 20 ns

tDS Data Setup 15 ns

tDH Data Hold 15 ns

tLD1 Load Setup 15 ns

tLD2 Load Hold 10 ns

tCSS Select 30 ns

tCSH Deselect 20 ns

NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%

of +5V) and timed from a voltage level of 2.5V. These parameters are

guaranteed by design and are not subject to production testing.

SDI

CLK

tCL tCH

tDH

tDS

SERIAL SHIFT DAC DAC

A1 A0

CLK

LOADDACS

X X X H H No Change No Change No Change

↑

L H Shifts One Bit No Change No Change

LXXH

(1) L No Change Loads Serial Loads Serial

Data Word Data Word

H L X H L No Change Loads Serial No Change

Data Word

H H X H L No Change No Change Loads Serial

Data Word

↑ Positive Logic Transition; X = Don’t Care.

NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from

advancing the shift register and changing the DAC voltage.

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA INPUT TABLE

(MSB) (LSB)

SDI

CLK

LOADDACS

A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CSS

LD1

LD2

CSH

LOADDACS

OUT

LDW

±1 LSB

Error Band

DAC7612

TYPICAL PERFORMANCE CURVES

At TA = +25°, and VDD = 5V, unless otherwise specified.

5.0

4.8

4.6

4.4

4.2

4.0

MINIMUM SUPPLY VOLTAGE vs LOAD

Minimum (V)

Output Load Current (mA)

0.01 0.1 1 10

OUTPUT SWING vs LOAD

Output Voltage (V)

Load Resistance (Ω)

10 100 1k 10k 100k

tied to V

Data = 000

tied to GND

Data = FFF

POWER SUPPLY REJECTION vs FREQUENCY

PSR (dB)

Frequency (Hz)

10 100 1k 10k 100k 1M

Data = FFFH

VDD = 5V

±200mV AC

Time (2ms/div)

Code = FFFH, BW = 1MHz

BROADBAND NOISE

Noise Voltage (500µV/div)

100

0.1

0.01

PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT

Delta VOUT (mV)

Current (mA)

0.001 0.01 0.1 1 10 100

+85°C

Data = 000H

–40°C

+25°C

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

Supply Current (mA)

Logic Voltage (V)

012345

DAC7612

RISE TIME DETAIL

OUT

(1mV/div)

Time (10µs/div)

LOADDACS

= 100pF

= No Load

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

–5

–10

–15

–20

SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE

Output Current (mA)

Output Voltage (V)

01 423 56

Positive

Current

Limit Data = 800

Output tied to I

SOURCE

Negative

Current

Limit

MIDSCALE GLITCH PERFORMANCE

OUT

(5mV/div)

Time (500ns/div)

7FF

to 800

LOADDACS

MIDSCALE GLITCH PERFORMANCE

OUT

(5mV/div)

Time (500ns/div)

800

to 7FF

LOADDACS

LARGE-SIGNAL SETTLING TIME

OUT

(1V/div)

Time (20µs/div)

= 100pF

= No Load

LOADDACS

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

SUPPLY CURRENT vs TEMPERATURE

Supply Current (mA)

Temperature (°C)

–50 –30 –10 10 30 50 70 90 110 130

LOGIC

= 3.5V

Data = FFF

No Load

= 4.75V

At worst-case digital inputs.

= 5.25V V

= 5.0V

DAC7612

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

10.000

1.000

0.100

0.010

OUTPUT VOLTAGE NOISE vs FREQUENCY

Noise (µV/√Hz)

Frequency (Hz)

10 100 1k 10k 100k

Data = FFF

–1

–2

–3

–4

–5

LONG-TERM DRIFT ACCELERATED BY BURN-IN

Output Voltage Change at FS (mV)

Hours of Operation at +150°C

0 168 336 504 672 840 1008

Max

Avg

Min

4.111

4.103

4.095

4.087

4.079

FULL-SCALE VOLTAGE vs TEMPERATURE

Full-Scale Output (V)

Temperature (°C)

–40 –15 10 35 60 85

Avg + 3σ

Avg – 3σ

Avg

–12 –10 –8 –6 –4 –2 0 2 84 6 10 12

T.U.E = Σ (INL + Z

+ FSE)

Sample Size = 200 Units

= +25°C

Number of Units

TOTAL UNADJUSTED ERROR HISTOGRAM

FALL TIME DETAIL

OUT

(1mV/div)

Time (10µs/div)

= 100pF

= No Load

LOADDACS

–1

ZERO-SCALE VOLTAGE vs TEMPERATURE

Zero-Scale Output (mV)

Temperature (°C)

–40 –15 10 35 60 85

Avg – 3σ

Avg

Avg + 3σ

DAC7612

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC A at +85°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC B at +85°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC A at +25°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC B at +25°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC A at –40°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

LINEARITY ERROR vs DIGITAL CODE

(DAC B at –40°C)

Linearity Error (LSBs)

Code

0 512 1024 1536 2048 2560 3072 3584 4096

DAC7612

next 12 bits are the code (MSB-first) sent to the DAC. The

data format is Straight Binary and is loaded MSB-first into

the shift registers after loading the address bits. Table I shows

the relationship between input code and output voltage.

The digital data into the DAC7612 is double-buffered. This

means that new data can be entered into the chosen DAC

without disturbing the old data and the analog output of the

converter. At some point after the data has been entered into

the serial shift register, this data can be transferred into the

DAC registers. This transfer is accomplished with a HIGH

to LOW transition of the LOADDACS pin. The LOADDACS

pin makes the DAC registers transparent. If new data is

shifted into the shift register while LOADDACS is LOW,

the DAC output voltages will change as each new bit is

entered. To prevent this, LOADDACS must be returned

HIGH prior to shifting in new serial data.

DIGITAL-TO-ANALOG CONVERTER

The internal DAC section is a 12-bit voltage output

device that swings between ground and the internal ref-

erence voltage. The DAC is realized by a laser-trimmed

R-2R ladder network which is switched by N-channel

MOSFETs. Each DAC output is internally connected to a

rail-to-rail output operational amplifier.

OUTPUT AMPLIFIER

A precision, low-power amplifier buffers the output of each

DAC section and provides additional gain to achieve a 0V to

4.095V range. Each amplifier has low offset voltage, low

OPERATION

The DAC7612 is a dual, 12-bit digital-to-analog converter

(DAC) complete with a serial-to-parallel shift register, DAC

registers, laser-trimmed 12-bit DACs, on-board reference,

and rail-to-rail output amplifiers. Figure 1 shows the basic

operation of the DAC7612.

INTERFACE

Figure 1 shows the basic connection between a

microcontroller and the DAC7612. The interface consists of

a Serial Clock (CLK), Serial Data (SDI), and a Load DAC

signal (LOADDACS). In addition, a chip select (CS) input is

available to enable serial communication when there are

multiple serial devices. Loading either DAC A or DAC B is

done by shifting 14 serial bits in via the SDI input. The first

2 bits represent the address of the DAC to be updated and the

DAC7612 Full-Scale Range = 4.095V

Least Significant Bit = 1mV

DIGITAL INPUT CODE ANALOG OUTPUT

STRAIGHT OFFSETBINARY (V) DESCRIPTION

FFFH+4.095 Full Scale

801H+2.049 Midscale + 1 LSB

800H+2.048 Midscale

7FFH+2.047 Midscale – 1 LSB

000H0 Zero Scale

TABLE I. Digital Input Code and Corresponding Ideal

Analog Output.

FIGURE 1. Basic Operation of the DAC7612.

SDI

CLK

LOADDACS

VOUTA

VDD

GND

VOUTB

DAC7612U

Serial Data

Serial Clock

Load DACs

Chip Select

0.1µF

0V to +4.095V

10µF

DAC7612

noise, and a set gain of 1.682V/V (4.095/2.435). See Figure

2 for an equivalent circuit schematic of the analog portion of

the DAC7612.

The output amplifier has a 7µs typical settling time to ±1

LSB of the final value. Note that there are differences in the

settling time for negative-going signals versus positive-

going signals.

The rail-to-rail output stage of the amplifier provides the full-

scale range of 0V to 4.095V while operating on a supply voltage

as low as 4.75V. In addition to its ability to drive resistive loads,

the amplifier will remain stable while driving capacitive loads

of up to 500pF. See Figure 3 for an equivalent circuit schematic

of the amplifier’s output driver and the Typical Performance

Curves section for more information regarding settling time,

load driving capability, and output noise.

POWER SUPPLY

A BiCMOS process and careful design of the bipolar and

CMOS sections of the DAC7612 result in a very low power

device. Bipolar transistors are used where tight matching

and low noise are needed to achieve analog accuracy, and

CMOS transistors are used for logic, switching functions

and for other low power stages.

If power consumption is critical, it is important to keep the

logic levels on the digital inputs (SDI, CLK, CS,

LOADDACS) as close as possible to either VDD or ground.

This will keep the CMOS inputs (see “Supply Current vs

Logic Input Voltages” in the Typical Performance Curves)

from shunting current between VDD and ground.

The DAC7612 power supply should be bypassed as shown

in Figure 1. The bypass capacitors should be placed as close

to the device as possible, with the 0.1µF capacitor taking

priority in this regard. The “Power Supply Rejection vs

Frequency” graph in the Typical Performance Curves sec-

tion shows the PSRR performance of the DAC7612. This

should be taken into account when using switching power

supplies or DC/DC converters.

In addition to offering guaranteed performance with VDD in

the 4.75V to 5.25V range, the DAC7612 will operate with

reduced performance down to 4.5V. Operation between

4.5V and 4.75V will result in longer settling time, reduced

performance, and current sourcing capability. Consult the

“VDD vs Load Current” graph in the Typical Performance

Curves section for more information.

FIGURE 2. Simplified Schematic of Analog Portion.

FIGURE 3. Simplified Driver Section of Output Amplifier.

N-Channel

P-Channel

OUT

GND

RR1

Output Amplifier

R-2R DAC

Bandgap

Reference 2.435V

Typical of DAC A or DAC B

Buffer

DAC7612

FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System.

APPLICATIONS

POWER AND GROUNDING

The DAC7612 can be used in a wide variety of situations—

from low power, battery operated systems to large-scale

industrial process control systems. In addition, some appli-

cations require better performance than others, or are par-

ticularly sensitive to one or two specific parameters. This

diversity makes it difficult to define definite rules to follow

concerning the power supply, bypassing, and grounding.

The following discussion must be considered in relation to

the desired performance and needs of the particular system.

A precision analog component requires careful layout, ad-

equate bypassing, and a clean, well-regulated power supply.

As the DAC7612 is a single-supply, +5V component, it will

often be used in conjunction with digital logic,

microcontrollers, microprocessors, and digital signal proces-

sors. The more digital logic present in the design and the

higher the switching speed, the more difficult it will be to

achieve good performance.

Because the DAC7612 has a single ground pin, all return

currents, including digital and analog return currents, must

flow through this pin. The GND pin is also the ground

reference point for the internal bandgap reference. Ideally,

GND would be connected directly to an analog ground

plane. This plane would be separate from the ground con-

nection for the digital components until they are connected

at the power entry point of the system (see Figure 4).

The power applied to VDD should be well regulated and low-

noise. Switching power supplies and DC/DC converters will

often have high-frequency glitches or spikes riding on the

output voltage. In addition, digital components can create

similar high frequency spikes as their internal logic switches

states. This noise can easily couple into the DAC output

voltage through various paths between VDD and VOUT.

As with the GND connection, VDD should be connected to

a +5V power supply plane or trace that is separate from the

connection for digital logic until they are connected at the

power entry point. In addition, the 10µF and 0.1µF capaci-

tors shown in Figure 4 are strongly recommended and

should be installed as close to VDD and ground as possible.

In some situations, additional bypassing may be required

such as a 100µF electrolytic capacitor or even a “Pi” filter

made up of inductors and capacitors—all designed to essen-

tially lowpass filter the +5V supply, removing the high

frequency noise (see Figure 4).

+5V

GND

100µF

Digital Circuits

+5V

GND

+5V

Power

Supply

Other

Analog

Components

GND

DAC7612

+10µF0.1µF

Optional

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

DAC7612U ACTIVE SOIC D 8 75 Green (RoHS &