SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 632 The MC14007UB multi-purpose device consists of three N-channel and three P-channel enhancement mode devices packaged to provide access to each device. These versatile parts are useful in inverter circuits, pulse- shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating. P SUFFIX PLASTIC CASE 646 * Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Pin-for-Pin Replacement for CD4007A or CD4007UB * This device has 2 outputs without ESD Protection. Anti-static precautions must be taken. D SUFFIX SOIC CASE 751A IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII ORDERING INFORMATION MC14XXXUBCP MC14XXXUBCL MC14XXXUBD MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit - 0.5 to + 18.0 V Plastic Ceramic SOIC TA = - 55 to 125C for all packages. Vin, Vout Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package 500 mW D-PB 1 14 VDD Tstg Storage Temperature - 65 to + 150 _C S-PB 2 13 D-PA 260 _C GATEB 3 12 OUTC S-NB 4 11 S-PC D-NB 5 10 GATEC GATEA 6 9 S-NC VSS 7 8 D-NA TL Lead Temperature (8-Second Soldering) PIN ASSIGNMENT * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C A A 12 B B 1 C 2 3 INPUT 1 0 Substrates of P-channel devices internally connected to VDD; substrates of N-channel devices internally connected to VSS. 2 1 11 6 12 13 INPUT A = C, B = OPEN A = B, C = OPEN 13 C 11 INPUT OUTPUT CONDITION SCHEMATIC 14 4 5 VDD 14 D = DRAIN S = SOURCE 9 6 8 7 10 VSS 7 8 3 4 5 VDD = PIN 14 VSS = PIN 7 10 9 Figure 1. Typical Application: 2-Input Analog Multiplexer REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14007UB 31 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIII IIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIII IIII III III IIII III IIII III IIII III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIII III IIII III IIII III III IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit Output Voltage Vin = VDD or 0 "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc Vin = 0 or VDD "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc "0" Level VIL 5.0 10 15 -- -- -- 1.0 2.0 2.5 -- -- -- 2.25 4.50 6.75 1.0 2.0 2.5 -- -- -- 1.0 2.0 2.5 5.0 10 15 4.0 8.0 12.5 -- -- -- 4.0 8.0 12.5 2.75 5.50 8.25 -- -- -- 4.0 8.0 12.5 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 5.0 - 1.0 - 2.5 - 10 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 1.0 2.5 10 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 0.25 0.5 1.0 -- -- -- 0.0005 0.0010 0.0015 0.25 0.5 1.0 -- -- -- 7.5 15 30 Adc IT 5.0 10 15 Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) "1" Level VIH Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Total Supply Current** (Dynamic plus Quiescent, Per Gate) (CL = 50 pF) Sink Vdc mAdc IT = (0.7 A/kHz) f + IDD/6 IT = (1.4 A/kHz) f + IDD/6 IT = (2.2 A/kHz) f + IDD/6 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14007UB 32 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (1.2 ns/pF) CL + 30 ns tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.4 ns/pF) CL + 15 ns tTLH Output Fall Time tTHL = (1.2 ns/pF) CL + 15 ns tTHL = (0.5 ns/pF) CL + 15 ns tTHL = (0.4 ns/pF) CL + 10 ns tTHL Turn-Off Delay Time tPLH = (1.5 ns/pF) CL + 35 ns tPLH = (0.2 ns/pF) CL + 20 ns tPLH = (0.15 ns/pF) CL + 17.5 ns tPLH Turn-On Delay Time tPHL = (1.0 ns/pF) CL + 10 ns tPHL = (0.3 ns/pF) CL + 15 ns tPHL = (0.2 ns/pF) CL + 15 ns tPHL VDD Vdc Min Typ # Max 5.0 10 15 -- -- -- 90 45 35 180 90 70 5.0 10 15 -- -- -- 75 40 30 150 80 60 5.0 10 15 -- -- -- 60 30 25 125 75 55 5.0 10 15 -- -- -- 60 30 25 125 75 55 Unit ns ns ns ns * The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD = - VGS VDD = VGS 14 IOH 7 14 VDS = VOH - VDD IOL VSS 7 All unused inputs connected to ground. 20 - 8.0 b a c b - 12 b c - 10 Vdc - 16 - 15 Vdc a a - 20 - 10 IOL , DRAIN CURRENT (mAdc) IOH , DRAIN CURRENT (mAdc) VGS = - 5.0 Vdc a VGS = 15 Vdc b c a TA = - 55C b TA = + 25C c TA = + 125C VSS All unused inputs connected to ground. 0 - 4.0 VDS = VOL c 16 a 10 Vdc 12 b c a TA = - 55C b TA = + 25C c TA = + 125C 8.0 a 4.0 b 5.0 Vdc c 0 - 8.0 - 6.0 - 4.0 VDS, DRAIN VOLTAGE (Vdc) - 2.0 -0 Figure 2. Typical Output Source Characteristics 0 2.0 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 10 Figure 3. Typical Output Sink Characteristics These typical curves are not guarantees, but are design aids. Caution: The maximum current rating is 10 mA per pin. MOTOROLA CMOS LOGIC DATA MC14007UB 33 VDD 500 F 0.01 F CERAMIC ID VDD VSS tPHL Vout 7 20 ns 90% 50% 10% Vin 14 Vin PULSE GENERATOR 20 ns VOH 90% 50% 10% Vout CL VSS tPLH VOL tTHL tTLH Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms APPLICATIONS The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications. Figures 1, 5, and 6 are a few examples of the device flexibility. VDD 14 OUT = A+B*C 13 + VDD 2 11 2 DISABLE 3 12 10 B 1 1 8 OUTPUT 11 9 INPUT 10 7 5 12 OUTPUT 3 C 9 4 8 6 A DISABLE 6 7 INPUT DISABLE OUTPUT 1 0 X 0 0 1 0 1 OPEN Substrates of P-channel devices internally connected to VDD; Substrates of N-channel devices internally connected to VSS. Figure 6. AOI Functions Using Tree Logic X = Don't Care Figure 5. 3-State Buffer MC14007UB 34 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y -A- 14 9 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C -T- L K SEATING PLANE F G D N M J 14 PL 0.25 (0.010) M T A S 14 PL 0.25 (0.010) M T B P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 8 1 7 B A F L C J N H G D SEATING PLANE MOTOROLA CMOS LOGIC DATA K M S DIM A B C D F G J K L M N INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 MC14007UB 35 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G M F -T- M K D 14 PL 0.25 (0.010) M T B S M R X 45 _ C SEATING PLANE B A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14007UB 36 *MC14007UB/D* MOTOROLA CMOSMC14007UB/D LOGIC DATA