0.1 GHz to 6 GHz Silicon SP5T Switch
Data Sheet
ADRF5250
Rev. 0 Document Feedback
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Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Nonreflective 50 Ω design
Low insertion loss: 1.5 dB at 4 GHz
High isolation: 50 dB at 4 GHz
High input linearity
0.1 dB compression (P0.1dB): 34 dBm typical
Third-order intercept (IP3): 57 dBm typical
High power handling at 85°C
33 dBm through path
27 dBm terminated path
ESD rating
3.5 kV HBM, Class 2
Single-supply or dual-supply operation
Optional internal negative voltage generator (NVG)
1.8 V logic-compatible control
4 mm × 4 mm, 24-lead LFCSP
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Mobile radios
Test equipment
FUNCTIONAL BLOCK DIAGRAM
VDD
V1
V2
V3
RFC
50Ω
RF2
RF3
RF4
RF5
ADRF5250
RF1
50Ω 50Ω 50Ω
50Ω
15506-001
DIGITAL
CONTROL
BIAS
NEGATIVE
VOLTAGE
GENERATOR
VSS
Figure 1.
GENERAL DESCRIPTION
The ADRF5250 is a general-purpose, single-pole, five-throw
(SP5T), nonreflective switch manufactured using a silicon
process. The ADRF5250 is available in a 4 mm × 4 mm, 24-lead
lead frame chip scale package (LFCSP) and provides high
isolation and low insertion loss from 100 MHz to 6 GHz.
The ADRF5250 incorporates a negative voltage generator to
operate with a single positive supply voltage from 3.3 V to 5 V
applied to the VDD pin when the VSS pin is connected to
ground. The negative voltage generator can be disabled when
an external negative supply voltage of −3.3 V is applied to the
VSS pin. The ADRF5250 provides a 1.8 V logic-compatible,
3-pin control interface.
ADRF5250 Data Sheet
Rev. 0 | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics .....................................................................7
Typical Performance Characterics ..................................................8
Insertion Loss, Return Loss, And Isolation ...............................8
Input Power Compression and Third-Order Intercept (IP3) .... 9
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Evaluation Board ........................................................................ 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
6/2017—Revision 0: Initial Version
Data Sheet ADRF5250
Rev. 0 | Page 3 of 15
SPECIFICATIONS
VDD = 5 V, V SS = 0 V, V 1 = V2 = V3 = 0 V/VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 0.1 6 GHz
INSERTION LOSS
Between RFC and RFx (On) 0.1 GHz to 2 GHz 1.3 dB
2 GHz to 4 GHz 1.5 dB
4 GHz to 6 GHz 1.8 dB
ISOLATION
Between RFC and RFx (Off ) 0.1 GHz to 2 GHz 55 dB
2 GHz to 4 GHz 50 dB
4 GHz to 6 GHz 46 dB
RETURN LOSS
RFC and RFx (On) 0.1 GHz to 2 GHz 15 dB
2 GHz to 4 GHz 13 dB
4 GHz to 6 GHz 13 dB
RFx (Off ) 0.1 GHz to 2 GHz 17 dB
2 GHz to 4 GHz 15 dB
4 GHz to 6 GHz 8 dB
SWITCHING
Rise Time tRISE 10% to 90% of radio frequency (RF) output 40 ns
Fall Time tFALL 10% to 90% of RF output 80 ns
On and Off Time tON, tOFF 50% of digital control voltage (V1, V2, V3) to 90% of
RF output
150 ns
Settling Time (RFx to RFx)
0.1 dB 50% of V1, V2, V3 to 0.1 dB of final RF output 400 ns
0.05 dB
50% of V
1
, V
2
, V
3
to 0.05 dB of final RF output
500
ns
INPUT LINEARITY
0.1 dB Compression P0.1dB 34 dB
Third-Order Intercept IP3 57 dBm
SUPPLY CURRENT VDD, VSS pins
Positive IDD NVG enabled (VSS = 0 V) 360 µA
NVG disabled (VSS = −3.3 V) 280 µA
Negative ISS NVG disabled (VSS = −3.3 V) −60 µA
DIGITAL CONTROL INPUTS
V1, V2, V3 pins
Voltage
Low VINL VDD = 3.3 V 0 0.8 V
VDD = 5 V 0 1.2 V
High VINH VDD = 3.3 V 1.3 3.3 V
V
DD
= 5 V
1.6
5
V
Current
Low and High IINL, IINH VDD = 3.3 V to 5 V <1 µA
ADRF5250 Data Sheet
Rev. 0 | Page 4 of 15
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Positive VDD 3.0 5.25 V
Negative VSS −3.45 −3.15 V
Digital Control Voltage
V
1
, V
2
, V
3
0
V
DD
V
Maximum RF Input Power1 PIN
TCASE = 105°C Through path (VDD = 3.3 V to 5 V) 30 dBm
Terminated path 24 dBm
Hot switching 24 dBm
TCASE = 85°C Through path (VDD = 3.3 V to 5 V) 33 dBm
Terminated path 27 dBm
Hot switching 27 dBm
Case Temperature TCASE −40 +105 °C
1 Exposure to levels between the recommended operating conditions and the absolute maximum rating conditions for extended period may affect device reliability.
Data Sheet ADRF5250
Rev. 0 | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Positive Supply Voltage (VDD) −0.3 V to +5.5 V
Negative Supply Voltage (VSS) −3.6 V to +0.3 V
Digital Control Input Voltage (V1, V2, V3) −0.3 V to VDD + 0.5 V
RF Input Power
Through Path 35 dBm
Terminated Path 34 dBm
All Off State, RFC as Input
24 dBm
Hot Switching
RFC as Input
RFx to RFx 32 dBm
All Off to RFx 24 dBm
RFx as Input
RFx to RFx 34 dBm
All Off to RFx 34 dBm
Temperature
Junction, TJ 135°C
Storage −65°C to +150°C
Reflow (MSL3 Rating) 260°C
Junction to Case Thermal Resistance, θJC
Through Path 90°C/W
Terminated Path 100°C/W
ESD Sensitivity
Human Body Model (HBM) 3.5 kV (Class 2)
Field Induced Device Model (FICDM)
1.25 kV (Class IV)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADRF5250 Data Sheet
Rev. 0 | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
GND
RF4
GND
GND
RF5
GND
GND
RF1
GND
VDD
V1
V2
8
9
10
11
7
RF3
GND
GND
RF2
12
GND
GND
20
19
21
VSS
V3
GND
22 RFC
23 GND
24 GND
ADRF5250
TOP VIEW
(No t t o Scal e)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNE CTED TO THE RF/ DC GRO UND OF
THE P CB.
15506-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 4, 6, 7, 9,
10, 12, 13, 15,
21, 23, 24
GND Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
2 RF5 RF Throw Port 5. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential
is within 0 V dc.
5 RF4 RF Throw Port 4. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential
is within 0 V dc.
8 RF3 RF Throw Port 3. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential
is within 0 V dc.
11 RF2 RF Throw Port 2. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential
is within 0 V dc.
14 RF1 RF Throw Port 1. This pin is dc coupled and no dc blocking capacitor is necessary when the RF line potential
is within 0 V dc.
16 VDD Positive Supply Voltage.
17 V1 Digital Input Voltage Applied to the Least Significant Bit (LSB) of Digital Interface for Controlling RF Path
State. See Table 5.
18 V2 Digital Input Voltage Applied to the Second Bit of Digital Interface for Controlling RF Path State. See Table 5.
19 V3 Digital Input Voltage Applied to the Most Significant Bit (MSB) of Digital Interface for Controlling RF Path
State. See Table 5.
20 VSS Optional Negative Supply Voltage. This pin can be connected to ground to operate with the internal
negative voltage generator. The internal negative voltage generator is disabled when this pin is connected
to an external 3.3 V supply.
22 RFC RF Common Port. This pin is dc-coupled and no dc blocking capacitor is necessary when the RF line
potential is within 0 V dc.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
ADRF5250 Data Sheet
Rev. 0 | Page 8 of 15
TYPICAL PERFORMANCE CHARACTERICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
0 8
FREQUENCY ( GHz)
0
INSERTION LOSS (dB)
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
1234567
15506-005
RF1 O N
RF2 O N
RF3 O N
RF4 O N
RF5 O N
Figure 5. Insertion Loss on RF Paths at Room Temperature
0
–35
RET URN LOS S ( dB)
–30
–25
–20
–15
–10
–5
0 8
FREQUENCY ( GHz)
1234567
RFC
RF1 O N
RF2 O N
RF3 O N
RF4 O N
RF5 O N
15506-006
Figure 6. Return Loss on Selected RFx Ports and RFC
0
–40
RET URNLOS S ( dB)
–35
–30
–25
–20
–15
–10
–5
0 8
FREQUENCY ( GHz)
1234567
RF1 ( RF2 ON)
RF2 ( RF1 ON)
RF3 ( RF2 ON)
RF4 ( RF5 ON)
RF5 ( RF4 ON)
15506-008
Figure 7. Return Loss on Terminated RFx Ports
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
012345678
INSERTION LOSS (dB)
FREQUENCY (GHz)
TA = +105°C
TA = +85°C
TA = +25°C
TA = –40° C
15506-107
Figure 8. Insertion Loss on RF Paths over Temperature
0
–100
WORST CASE ISOLATION (dB)
RF1 TO RFC (RF2 O N)
RF2 TO RFC (RF1 O N)
RF3 TO RFC (RF2 O N)
RF4 TO RFC (RF5 O N)
RF5 TO RFC (RF4 O N)
–90
–80
–70
–60
–50
–40
–30
–20
–10
08
FREQUENCY ( GHz)
1234 5 6 7
15506-007
Figure 9. Worst Case Isolation on RF Paths
Data Sheet ADRF5250
Rev. 0 | Page 9 of 15
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3)
40
200.5 6.0
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( GHz)
22
24
26
28
30
32
34
36
38
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF5
15506-010
Figure 10. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency,
VDD = 3.3 V, VSS = 0 V
40
200.5 6.0
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( GHz)
22
24
26
28
30
32
34
36
38
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF5
15506-009
Figure 11. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency,
VDD = 5 V, VSS = 0 V
65
30
INPUT I P 3 ( dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY ( GHz)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF5
15506-013
Figure 12. Input IP3 vs. Frequency, VDD = 5 V, VSS = 0 V
40
200.5 6.0
INPUT P0.1 d B ( dBm)
FREQUENCY ( GHz)
22
24
26
28
30
32
34
36
38
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
15506-012
TA = +105°C
TA = +85°C
TA = +25°C
TA = –40° C
Figure 13. Input 0.1 dB Power Compression vs. Frequency over Temperature,
VDD = 3.3 V, VSS = 0 V
40
200.5 6.0
INPUT P0.1 d B ( dBm)
FREQUENCY ( GHz)
22
24
26
28
30
32
34
36
38
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TA = +105°C
TA = +85°C
TA = +25°C
TA = –40° C
15506-011
Figure 14. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Temperature, VDD = 5 V, VSS = 0 V
65
30
INPUT I P 3 ( dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY ( GHz)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
15506-014
TA = +105°C
TA = +85°C
TA = +25°C
TA = –40° C
Figure 15. Input IP3 vs. Frequency over Temperature,
VDD = 5 V, VSS = 0 V
ADRF5250 Data Sheet
Rev. 0 | Page 10 of 15
65
30
INPUT I P 3 ( dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY ( GHz)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF5
15506-015
Figure 16. Input IP3 vs. Frequency, VDD = 3.3 V, VSS = 0 V
65
30
INPUT I P 3 ( dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY ( GHz)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
15506-016
TA = +105°C
TA = +85°C
TA = +25°C
TA = –40° C
Figure 17. Input IP3 vs. Frequency over Temperature,
VDD = 3.3 V, VSS = 0 V
Data Sheet ADRF5250
Rev. 0 | Page 11 of 15
THEORY OF OPERATION
The ADRF5250 requires a positive supply voltage applied to
the VDD pin and 0 V or −3.3 V supply voltage applied to the
VSS pin. Bypass capacitors are recommended on the supply and
digital control lines to minimize RF coupling. An incorporated
negative supply generator is enabled or disabled depending on
the applied VSS supply voltage. Table 4 describes the operation
mode of that negative supply generator.
Table 4. Negative Voltage Generator Operation Mode
VSS Test Conditions/Comments
0 V The incorporated negative voltage generator is
enabled
−3.3 V The incorporated negative voltage generator is
disabled
The ADRF5250 is internally matched to 50 Ω at the RF common
port (RFC) and the RF throw ports (RF1 to RF5); therefore, no
external matching components are required. All of the RF ports
are dc-coupled to 0 V, and no dc blocking is required at the RF
ports when the RF line potential is equal to 0 V. The design is
bidirectional; the RF input signal can be applied to the RFC port
while the RF throw port (RF1 to RF5) is output, or vice versa.
The ADRF5250 has a 3-bit, 1.8 V logic-compatible control
interface that is controlled through the V1, V2, and V3 digital
control voltage pins. A small bypassing capacitor is recommended
on these digital signal lines to improve the RF signal isolation.
The V1 and V3 test points correspond to the LSB and MSB of
the digital control interface of the ADRF5250. The modes of the
RF paths are determined as shown in Table 5.
When an RF path is on, the RF signal is conducted equally well in
both directions between its throw port (RFx) and common port
(RFC). Otherwise, each RFx path is terminated to an internal
50 Ω resistor that provides high loss between the insertion loss
path and its throw ports.
Table 5. Control Voltage Truth Table
V3 V2 V1 Mode
Low Low Low All Off
Low Low High RF1 on
Low High Low RF2 on
Low
High
High
RF3 on
High Low Low RF4 on
High Low High RF5 on
High High Low All off
High High High All off
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD and VSS. The relative order is not
important.
3. Power up the digital control inputs. The relative order of
the logic control inputs is not important. However,
powering the digital control inputs before the VDD supply
can inadvertently forward bias and damage the internal
ESD protection structures.
4. Apply an RF input signal.
ADRF5250 Data Sheet
Rev. 0 | Page 12 of 15
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 18 and Figure 19 show the top and cross sectional views
of the evaluation board, which uses 4-layer construction with a
copper thickness of 0.5 oz (0.7 mil) and dielectric materials
between each copper layer.
1400mil
2200mil
15506-117
Figure 18. Evaluation Board Layout Top View
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
10mil ROG E RS 4350B
10mil ROG E RS 4350B
8mil ROG E RS 4450F
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l ) 0.5oz Cu (0. 7m i l )
TO TAL THICKNESS
~30mil
W = 8m i l G = 10m il
15506-118
Figure 19. Evaluation Board Cross Sectional View
All RF traces are routed on Layer 2; the V1, V3, and VSS dc
traces are routed on Layer 3; the V2 and VDD dc traces are
routed on the top layer; and the other remaining layers are
grounded planes that provide a solid ground for RF transmission
lines. The top and bottom dielectric material are Rogers 4350B,
offering low loss performance. The middle dielectric material is
Rogers 4450F and is used to achieve an overall board thickness
of 30 mil. The RF transmission lines were designed using a
coplanar waveguide (CPWG) model with a width of 8 mil and
ground spacing of 10 mil for a characteristic impedance of 50 Ω.
For optimal RF and thermal grounding, as many plated through
vias as possible are arranged around the transmission lines and
under the exposed pad of the package.
Figure 20 shows the actual ADRF5250 evaluation board with
component placement. Two power supply ports are connected
to the VDD and VSS test points, TP3 and TP5, and the ground
reference is connected to the GND test point, TP6. On the digital
control and VDD supply traces, bypass capacitors are used.
15506-018
Figure 20. ADRF5250-EVALZ Evaluation Board
Three control ports are connected to the V1, V2, and V3 test
points, TP1, TP2, and TP4, respectively. On each control trace,
a resistor position is available to improve the isolation between
the RF and control signals. The RF ports are connected to the
RFC, RF1, RF2, RF3, RF4, and RF5 connectors (J6, J8, J7, J5, J2,
and J1), which are end launch jack SMA RF connectors. A
through transmission line that connects unpopulated RF
connectors (J3 and J4) is also available to measure the loss of
the PCB. Figure 22 and Table 6 show the evaluation board
schematic and bill of materials, respectively.
The evaluation board shown in Figure 20 is available for order
from the Analog Devices, Inc., website at www.analog.com.
Data Sheet ADRF5250
Rev. 0 | Page 13 of 15
60 SECO NDS
TO 180 SECONDS 20 SECONDS
TO 40 SECONDS
480 SECO NDS M AX
TEMPERATURE (°C)
TIME (Seconds)
260°C –5°C/ + 0°C
150°C TO 200°C
RAMP DOWN
6°C/SE C M AX
217°C
RAMP UP
3°C/SE C M AX
60 SECO NDS
TO
150 SECO NDS
15506-120
Figure 21. Pb-Free Reflow Solder Profile
Table 6. Bill of Materials for the ADRF5250-EVALZ
Evaluation Board
Item Description
J1, J2, J5 to J8 RF SMA connectors
TP1 to TP6 DC bias test pins
C2 to C5 100 pF capacitors, 0402 package
C6 to C9 0.01 µF capacitor, 0402 package
C10 10 µF capacitor, tantalum package
08-042239 Evaluation PCB, Rogers 4350B circuit board
material
J5
ADRF5250
J1
J2
J8
J7
J6
U1
TP1
TP6
RF3 RF2
RFC
RF1
RF4
RF5
V1
V3
VDD
VSS
V2
1
3
4
6
7
9
10
12
13
15
21
23
24
PAD
14
11
8
5
2
22
17
18
19
16
20
GND
PAD
GND
GND
RFC
GND
VSS
V3
V2
V1
VDD
GND
RF1
GND
GND
RF2
GND
GND
RF3
GND
GND
RF4
GND
GND
RF5
GND
GND
TP3
TP5
TP4
TP2
R4
0Ω
R3
0Ω
R2
0Ω
R1
0Ω
C10
10µF
+
GND
C9
0.1µF
GND
C5
100pF
GND
C8
0.01µF
GND
C4
100pF
GND
C7
0.01µF
GND
C3
100pF
GND
C6
0.01µF
GND
C2
100pF
GND
15506-017
Figure 22. ADRF5250-EVALZ Evaluation Board Schematic
ADRF5250 Data Sheet
Rev. 0 | Page 14 of 15
OUTLINE DIMENSIONS
0.50
BSC
0.45
0.40
0.35
COMPLIANT
TO
JEDEC S TANDARDS MO-220- WG GD-6.
BOTTOM VIEW
TOP VIEW
4.10
4.00 S Q
3.90
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.203 RE F
COPLANARITY
0.08
PI N 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTI ON DESCRIPTI ONS
SECTION OF THIS DATA SHEET.
04-27-2017-A
0.30
0.25
0.20
0.20 M IN
2.80
2.70 S Q
2.60
EXPOSED
PAD
PKG-005108
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-23)
Dimensions shown in millimeters
06-02-2017-A
NOTES:
1. MEASURED F ROM THE CENTE RLINE OF SPROCKET HOLE TO CENTERL INE OF THE
POCKE T HOLE
2.
10 SPROCKET HOL E PITCH CUMUL ATIVE TOL ERANCE IS
± 0.20
3. THICKNES S IS APPLICABLE AS M E ASURED AT EDGE O F TAPE
4. BLACK P OLYSTYRENE MATERIAL
5. ALLOWABLE CAMBER TO BE 1 mm PE R 10 0 m m I N L ENGHT, NON-CUM ULATIVE OVER 25 0 m m
6.
MEASURE M E NT POINT TO BE 0.3 mm FROM BOTTO M POCKET
7. SUR FACE RESISTI VITY FRO M
105
TO
1011
Ω/SQ
8. KO M E ASUREMENT POINT SHOULD NOT BE REFE RED ON POCKET RIDGE
(NOTE 2)
(NOTE 1)
(NOTE 1)
12.30
12.00
11.70
5.60
5.50
5.40
A
A
DIRECTION OF FEED
Ø 1. 50 M IN
TOP VIEW
1.60
Ø 1. 55
1.50
DETAI L A
2.05
2.00
1.95
4.10
4.00
3.90
1.85
1.75
1.65
8.00
0.50
0.40
0.30
DETAI L A
R 0.50
R 0.50
3° BSC
(NOTE 6)
SECT IO N A- A
(NOTE 8)
(NOTE 3)
0.35
0.30
0.25
4.40
4.30
4.20
1.35
1.25
1.15
Figure 24. LFCSP Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADRF5250BCPZ −40°C to +105°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-23
ADRF5250BCPZ-R7 −40°C to +105°C 24-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel CP-24-23
ADRF5250BCPZRL −40°C to +105°C 24-Lead Lead Frame Chip Scale Package [LFCSP], 13” Tape and Reel CP-24-23
ADRF5250-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
