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77
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SAM3S8/SD8
RBIT Rd, Rn Reverse Bits - page 117
REV Rd, Rn Reverse byte order in a word - page 117
REV16 Rd, Rn Reverse byte order in each halfword - page 117
REVSH Rd, Rn Reverse byte order in bottom halfword
and sign extend -page 117
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C page 110
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C page 110
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V page 105
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V page 105
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - page 127
SDIV {Rd,} Rn, Rm Signed Divide - page 122
SEV - Send Event - page 146
SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x
32 + 64), 64-bit result -page 121
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result - page 121
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q page 123
STM Rn{!}, reglist Store Multiple registers, increment after - page 97
STMDB,
STMEA Rn{!}, reglist Store Multiple registers, decrement
before -page 97
STMFD,
STMIA Rn{!}, reglist Store Multiple registers, increment after - page 97
STR Rt, [Rn, #offset] Store Register word - page 92
STRB,
STRBT Rt, [Rn, #offset] Store Register byte - page 92
STRD Rt, Rt2, [Rn, #offset] Store Register two words - page 92
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive - page 100
STREXB Rd, Rt, [Rn] Store Register Exclusive byte - page 100
STREXH Rd, Rt, [Rn] Store Register Exclusive halfword - page 100
STRH,
STRHT Rt, [Rn, #offset] Store Register halfword - page 92
STRT Rt, [Rn, #offset] Store Register word - page 92
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V page 105
SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V page 105
SVC #imm Supervisor Call - page 147
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - page 128
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - page 128
TBB [Rn, Rm] Table Branch Byte - page 135
TBH [Rn, Rm, LSL #1] Table Branch Halfword - page 135
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page