Features
•Core
– ARM® Cortex®-M3 revision 2.0 running at up to 64 MHz
– Memory Protection Unit (MPU)
–Thumb
®-2 instruction set
•Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1
products
•Memories
– 512 Kbytes Single Plane (SAM3S8) embedded Flash, 128-bit wide access, memory
accelerator
– 512 Kbytes Dual Plane (SAM3SD8) embedded Flash, 128-bit wide access, memory
accelerator
– 64 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
support
•System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in low-
power modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 130 MHz for device clock and for USB
– Temperature Sensor
– Up to 24 peripheral DMA (PDC) channels
•Low Power Modes
– Sleep and Backup modes, down to < 2 µA in Backup mode
– Ultra low-power RTC
•Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
Transceiver
– Up to 3 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper
Motor
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
•I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
•Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
AT91SAM
ARM-based
Flash MCU
SAM3S8/SD8
Series
11090A–ATARM–10-Feb-12
2
11090A–ATARM–10-Feb-12
SAM3S8/SD8
1. Description
The Atmel SAM3S8/SD8 series is a member of a family of Flash microcontrollers based on the
high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of
64 MHz and features up to 512 Kbytes of Flash (dual plane on SAM3SD8) and up to 64 Kbytes
of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver,
a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Con-
troller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2(3)x
USARTs, (3 on SAM3SD8C) 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, 6x
general-purpose 16-bit timers (with stepper motor and quadrature decoder logic support), an
RTC, a 12-bit ADC, a 12-bit DAC and an analog comparator.
The SAM3S8/SD8 series is ready for capacitive touch thanks to the QTouch® library, offering an
easy way to implement buttons, wheels and sliders.
The SAM3S8/SD8 device is a medium range general purpose microcontroller with the best ratio
in terms of reduced power consumption, processing power and peripheral set. This enables the
SAM3S8/SD8 to sustain a wide range of applications including consumer, industrial control, and
PC peripherals.
It operates from 1.62V to 3.6V and is available in 64- and 100-pin QFP, 64-pin QFN, and 100-pin
BGA packages.
The SAM3S8/SD8 series is the ideal migration path from the SAM7S series for applications that
require more performance. The SAM3S8/SD8 series is pin-to-pin compatible with the
SAM7Sseries.
3
11090A–ATARM–10-Feb-12
SAM3S8/SD8
1.1 Configuration Summary
The SAM3S8/SD8 series devices differ in memory size, package and features. Table 1-1 sum-
marizes the configurations of the device family.
Notes: 1. Full Modem support on USART1.
2. One channel is reserved for internal temperature sensor.
Table 1-1. Configuration Summary
Feature SAM3S8B SAM3S8C SAM3SD8B SAM3SD8C
Flash 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes
SRAM 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Package LQFP64
QFN64
LQFP100
BGA100
LQFP64
QFN64
LQFP100
BGA100
Number of PIOs 47 79 47 79
12-bit ADC 11 channels(2) 16 channels(2) 11 channels(2) 16 channels(2)
12-bit DAC 2 channels 2 channels 2 channels 2 channels
Timer Counter
Channels 666 6
PDC Channels 22 22 24 24
USART/UART 2/2(1) 2/2(1) 2/2(1) 3/2(1)
HSMCI 1 port/4 bits 1 port/4 bits 1 port/4 bits 1 port/4 bits
External Bus
Interface -
8-bit data,
4 chip selects,
24-bit address
-
8-bit data,
4 chip selects,
24-bit address
4
11090A–ATARM–10-Feb-12
SAM3S8/SD8
2. Block Diagram
Figure 2-1. SAM3S8/SD8 100-pin version Block Diagram
PLLA
System Controller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
N
V
I
C
3-layer AHB Bus Matrix Fmax 64 MHz
USART2
(SAM3SD8 Only)
ADC Ch.
PLLB
PMC
PIOA / PIOB / PIOC
WKUPx
PIO
External Bus
Interface
D[7:0]
PIODC[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
High Speed MCI
DATRG
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter B
Timer Counter B
TC[3..5]
TC[0..2]
TIOA[3:5]
TIOB[3:5]
TCLK[3:5]
AD[0..14]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
NAND Flash
Logic
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD2
TXD2
SCK2
RTS2
CTS2
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Static Memory
Controller
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
Bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
ROM
16 KBytes
SRAM
64 KBytes
512 KBytes FLASH
SAM3S8 Single Bank
SAM3SD8 Dual Bank
Flash
Unique
Identifier
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex M-3 Processor
Fmax 64 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-Bit
SysTick Counter
5
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Figure 2-2. SAM3S8/SD8 64-pin version Block Diagram
PLLA
System Controller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
N
V
I
C
3-layer AHB Bus Matrix Fmax 64 MHz
ADC Ch.
PLLB
PMC
PIOA / PIOB
PIODC[7:0]
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter A
TC[0..2]
AD[0..14]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
Bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
ROM
16 KBytes
SRAM
64 KBytes
512 KBytes FLASH
SAM3S8 Single Bank
SAM3SD8 Dual Bank
Flash
Unique
Identifier
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex M-3 Processor
Fmax 64 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-Bit
SysTick Counter
PIO
PIO
WKUPx
6
11090A–ATARM–10-Feb-12
SAM3S8/SD8
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type
Active
Level
Voltage
reference Comments
Power Supplies
VDDIO Peripherals I/O Lines and USB transceiver
Power Supply Power 1.62V to 3.6V
VDDIN Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply Power 1.8V to 3.6V(4)
VDDOUT Voltage Regulator Output Power 1.8V Output
VDDPLL Oscillator and PLL Power Supply Power 1.62 V to 1.95V
VDDCORE Power the core, the embedded memories
and the peripherals Power 1.62V to 1.95V
GND Ground Ground
Supply Controller
WKUPx Wake Up input pins input VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
PCK0 - PCK2 Programmable Clock Output Output
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Real Time Clock
RTCOUT0 Programmable RTC waveform output Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
RTCOUT1 Programmable RTC waveform output Output
Serial Wire/JTAG Debug Port - SWJ-DP
7
11090A–ATARM–10-Feb-12
SAM3S8/SD8
TCK/SWCLK Test Clock/Serial Wire Clock Input
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
TDI Test Data In Input
TDO/TRACESWO Test Data Out / Trace Asynchronous Data
Out Output
TMS/SWDIO Test Mode Select /Serial Wire Input/Output Input / I/O
JTAGSEL JTAG Selection Input High Permanent Internal
pull-down
Table 3-1. Signal Description List (Continued)
Signal Name Function Type
Active
Level
Voltage
reference Comments
8
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Flash Memory
ERASE Flash and NVM Configuration Bits Erase
Command Input High VDDIO
Reset State:
- Erase Input
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST Synchronous Microcontroller Reset I/O Low VDDIO
Permanent Internal
pull-up
TST Test Select Input Permanent Internal
pull-down
Universal Asynchronous Receiver Transceiver - UARTx
URXDx UART Receive Data Input
UTXDx UART Transmit Data Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31 Parallel IO Controller A I/O
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PB0 - PB14 Parallel IO Controller B I/O
PC0 - PC31 Parallel IO Controller C I/O
PIO Controller - Parallel Capture Mode
PIODC0-PIODC7 Parallel Capture Mode Data Input
VDDIOPIODCCLK Parallel Capture Mode Clock Input
PIODCEN1-2 Parallel Capture Mode Enable Input
External Bus Interface
D0 - D7 Data Bus I/O
A0 - A23 Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0 - NCS3 Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NAND Flash Logic
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
High Speed Multimedia Card Interface - HSMCI
MCCK Multimedia Card Clock I/O
MCCDA Multimedia Card Slot A Command I/O
MCDA0 - MCDA3 Multimedia Card Slot A Data I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type
Active
Level
Voltage
reference Comments
9
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
DTR1 USART1 Data Terminal Ready I/O
DSR1 USART1 Data Set Ready Input
DCD1 USART1 Data Carrier Detect Output
RI1 USART1 Ring Indicator Input
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Sync I/O
RF SSC Receive Frame Sync I/O
Timer/Counter - TC
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Pulse Width Modulation Controller- PWMC
PWMHx PWM Waveform Output High for channel x Output
PWMLx PWM Waveform Output Low for channel x Output
only output in
complementary mode when
dead time insertion is
enabled.
PWMFI0 PWM Fault Input Input
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPI_NPCS1 -
SPI_NPCS3 SPI Peripheral Chip Select Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type
Active
Level
Voltage
reference Comments
10
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Note: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System I/Os.
3. Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB Mode.
4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this
PIO line must be enabled to avoid current consumption due to floating input.
Two-Wire Interface- TWI
TWDx TWIx Two-wire Serial Data I/O
TWCKx TWIx Two-wire Serial Clock I/O
Analog
ADVREF ADC, DAC and Analog Comparator
Reference Analog
12-bit Analog-to-Digital Converter - ADC
AD0 - AD14 Analog Inputs Analog,
Digital
ADTRG ADC Trigger Input VDDIO
12-bit Digital-to-Analog Converter - DAC
DAC0 - DAC1 Analog output Analog,
Digital
DACTRG DAC Trigger Input VDDIO
Fast Flash Programming Interface - FFPI
PGMEN0-PGMEN2 Programming Enabling Input VDDIO
PGMM0-PGMM3 Programming Mode Input
VDDIO
PGMD0-PGMD15 Programming Data I/O
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
USB Full Speed Device
DDM USB Full Speed Data - Analog,
Digital VDDIO
Reset State:
- USB Mode
- Internal Pull-down(3)
DDP USB Full Speed Data +
Table 3-1. Signal Description List (Continued)
Signal Name Function Type
Active
Level
Voltage
reference Comments
11
11090A–ATARM–10-Feb-12
SAM3S8/SD8
4. Package and Pinout
SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin
version. Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in
Table 4-1, Table 4-3.
4.1 SAM3S8C/8DC Package and Pinout
4.1.1 100-Lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
4.1.2 100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its
dimensions are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA
Package.
Figure 4-2. Orientation of the 100-ball TFBGA Package
125
26
50
5175
76
100
1
3
4
5
6
7
8
9
10
2
ABCDEFGHJK
TOP VIEW
BALL A1
12
11090A–ATARM–10-Feb-12
SAM3S8/SD8
4.1.3 100-Lead LQFP Pinout
Table 4-1. SAM3S8C/SD8C 100-lead LQFP pinout
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/
PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20
8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10
14 PA18/PGMD6/AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11
15 PA21/PGMD9/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/PGMD10/AD
945 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/
PGMM0 73 PC16 98 VDDIO
24 PA20/PGMD8/AD3 49 PA7/XIN32/
PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
13
11090A–ATARM–10-Feb-12
SAM3S8/SD8
4.1.4 100-Ball TFBGA Pinout
Table 4-2. SAM3S8C/SD8C 100-ball TFBGA pinout
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4
A2 PC29 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11
A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12
B1 PC30 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13
B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1 PA17/PGMD5/AD
0G6 PA26/PGMD14 K1 PA22/PGMD10/AD
9
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/AD3
B10 TDO/TRACESWO/
PB5 E5 GND G10 PA5/PGMRDY K5 PC5
C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/AD2 K6 PC3
C2 VDDPLL E7 PA29/AD13 H2 PA23/PGMD11 K7 PC2
C3 PC25 E8 PA30/AD14 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/PGM
M0
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/
PGMNVALID
14
11090A–ATARM–10-Feb-12
SAM3S8/SD8
4.2 SAM3S8B/D8B Package and Pinout
4.2.1 64-Lead LQFP Package Outline
Figure 4-3. Orientation of the 64-lead LQFP Package
4.2.2 64-lead QFN Package Outline
Figure 4-4. Orientation of the 64-lead QF N Package
33
49
48
32
17
16
1
64
1
16
17 32
33
48
4964
TOP VIEW
15
11090A–ATARM–10-Feb-12
SAM3S8/SD8
4.2.3 64-Lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-3. 64-pin SAM3S8B/D8B pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/
PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10
9PA 1 7 / P G M D 5 /
AD025 PA25/PGMD13 41 PA29 57 DDP/PB11
10 PA 1 8 / P G M D 6 /
AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA 2 1 / P G M D 9 /
AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA 1 9 / P G M D 7 /
AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/
AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA 8 / XOUT32/
PGMM0 47 PA1/PGMEN1 63 PB14/DAC1
16 PA 2 0 / P G M D 8 /
AD3 32 PA 7 / XIN32/
PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
16
11090A–ATARM–10-Feb-12
SAM3S8/SD8
5. Power Considerations
5.1 Power Supplies
The SAM3S8/SD8 has several types of power supply pins:
• VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage
ranges from 1.62V to 1.95V.
• VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup
part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
• VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply.
Voltage ranges from 1.8V to 3.6V.
• VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage
ranges from 1.62V to 1.95V.
5.2 Voltage Regulator
The SAM3S8/SD8 embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM3S8/SD8. It features two
operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 7 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach
Normal mode is less than 100 µs.
For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regula-
tor” section in the “Electrical Characteristics” section of the datasheet.
5.3 Typical Powering Schematics
The SAM3S8/SD8 supports a 1.62V-3.6V single supply mode. The internal regulator input is
connected to the source and its output feeds VDDCORE. Figure 5-1 below shows the power
schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the
user does not want to use the embedded voltage regulator, it can be disabled by software via
the SUPC (note that this is different from Backup mode).
17
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Figure 5-1. Single Supply
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-2. Core Externally Supplied
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.
Main Supply
(1.8V-3.6V) ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
Main Supply
(1.62V-3.6V)
Can be the
same supply
VDDCORE Supply
(1.62V-1.95V)
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
18
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Figure 5-3. Backup Battery
5.4 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLLA. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5 Low-power Modes
The various low-power modes of the SAM3S8/SD8 are described below:
5.5.1 Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
which is performing periodic wake-ups to perform tasks but not requiring fast startup time
(<0.1ms). Total current consumption is 1.5 µA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The
regulator and the core supply are off.
Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.
The SAM3S8/SD8 can be awakened from this mode through WUP0-15 pins, the supply monitor
(SM), the RTT or RTC wake-up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the Cortex-M3
System Control Register set to 1. (See the Power management description in The ARM Cortex-
M3 Processor section of the product datasheet).
Exit from Backup mode happens if one of the following enable wake up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
3.3V
LDO
Backup
Battery +
-
ON/OFF
IN OUT VDDOUT
Main Supply
VDDCORE
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
VDDIO
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
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11090A–ATARM–10-Feb-12
SAM3S8/SD8
• Supply Monitor alarm
•RTC alarm
• RTT alarm
5.5.2 Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the
whole device in a powered state for a startup time of less than 10 µs. Current Consumption in
Wait mode is typically 20 µA (total current consumption) if the internal voltage regulator is used
or 12 µA if an external regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core,
peripherals and memories power supplies are still powered. From this mode, a fast start up is
available.
This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in
PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to
wake-up the core (WFE). This is done by configuring the external lines WUP0-15 as fast startup
wake-up pins (refer to Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events
can be used to wake up the CPU (exit from WFE).
Entering Wait Mode:
• Select the 4/8/12 MHz fast RC oscillator as Main Clock
• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
• Execute the Wait-For-Event (WFE) instruction of the processor
Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN
bit and the effective entry in Wait mode. Depending on the user application, waiting for
MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired
instructions.
5.5.3 Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response
time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The
current consumption in this mode is application dependent.
This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with
LPM = 0 in PMC_FSMR.
The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or
from an event if the WFE instruction is used to enter this mode.
20
11090A–ATARM–10-Feb-12
SAM3S8/SD8
5.5.4 Low Power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off sep-
arately and wake up sources can be individually configured. Table 5-1 below shows a summary
of the configurations of the low-power modes.
Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works
with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up
time is defined as the time taken for wake up until the first instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. Supply Monitor current consumption is not included.
4. Total Current consumption.
5. Total current consumption (without using internal voltage regulator) / Total current consumption (using internal voltage
regulator).
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
Table 5-1. Low-power Mode Configuration Summary
Mode
SUPC,
32 kHz
Oscillator,
RTC, RTT
Backup
Registers,
POR
(Backup
Region) Regulator
Core
Memory
Peripherals Mode Entry
Potential Wake Up
Sources
Core at
Wake Up
PIO State
while in Low
Power Mode
PIO State
at Wake Up
Consumption
(2)
(3)
Wake-up
Time(1)
Backup
Mode ON OFF OFF
(Not powered)
WFE
+SLEEPDEEP
bit = 1
WUP0-15 pins
SM alarm
RTC alarm
RTT alarm
Reset Previous
state saved
PIOA &
PIOB &
PIOC
Inputs with
pull ups
< 2 µA typ(4) < 0.1 ms
Wait
Mode ON ON Powered
(Not clocked)
WFE
+SLEEPDEEP
bit = 0
+LPM bit = 1
Any Event from: Fast
startup through
WUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back
Previous
state saved Unchanged 12 µA/20 µA (5) < 10 µs
Sleep
Mode ON ON Powered(7)
(Not clocked)
WFE or WFI
+SLEEPDEEP
bit = 0
+LPM bit = 0
Entry mode =WFI
Interrupt Only; Entry
mode =WFE Any
Enabled Interrupt
and/or Any Event
from: Fast start-up
through WUP0-15
pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back
Previous
state saved Unchanged (6) (6)
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11090A–ATARM–10-Feb-12
SAM3S8/SD8
5.6 Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is
detected, the Supply Controller performs a sequence which automatically reenables the core
power supply and the SRAM power supply, if they are not already enabled.
Figure 5-4. Wake-up Source
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
Falling/Rising
Edge
Detector
WKUPT0
Falling/Rising
Edge
Detector
WKUPT1
Falling/Rising
Edge
Detector
WKUP0
WKUP1
RTTEN
rtt_alarm
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11090A–ATARM–10-Feb-12
SAM3S8/SD8
5.7 Fast Startup
The SAM3S8/SD8 allows the processor to restart in a few microseconds while the processor is
in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of
the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-
up signal to the Power Management Controller. As soon as the fast start-up signal is asserted,
the PMC automatically restarts the embedded 4 MHz Fast RC oscillator, switches the master
clock on this 4MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-Up Sources
RTCEN
rtc_alarm
RTTEN
rtt_alarm
USBEN
usb_wakeup
fast_restart
WKUP15
FSTT15
WKUP1
WKUP0
FSTT0
FSTT1
Falling/Rising
Edge
Detector
Falling/Rising
Edge
Detector
Falling/Rising
Edge
Detector
23
11090A–ATARM–10-Feb-12
SAM3S8/SD8
6. Input/Output Lines
The SAM3S8/SD8 has several kinds of input/output (I/O) lines such as general purpose I/Os
(GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities
of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed
peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
6.1 General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such
as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing
or input change interrupt. Programming of these modes is performed independently for each I/O
line through the PIO controller user interface. For more details, refer to the product “PIO Control-
ler” section.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM3S8/SD8 embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2),
45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section of the
datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of
an internal series resistor termination scheme for impedance matching between the driver out-
put (SAM3S8/SD8) and the PCB trace impedance preventing signal reflection. The series
resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also
decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
6.2 System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few.
Described below in Table 6-1are the SAM3S8/SD8 system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup the
default function of these pins is always used.
PCB Trace
Z0 ~ 50 Ohms
Receiver
SAM3 Driver with
Rodt
Zout ~ 10 Ohms
Z0 ~ Zout + Rodt
ODT
36 Ohms Ty p.
24
11090A–ATARM–10-Feb-12
SAM3S8/SD8
Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode,
2. In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section.
3. In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1 on page 6.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” Section.
Table 6-1. System I/O Configuration Pin List.
SYSTEM_IO
bit number
Default function
after reset Other function
Constraints for
normal start Configuration
12 ERASE PB12 Low Level at startup(1)
In Matrix User Interface Registers
(Refer to the System I/O
Configuration Register in the “Bus
Matrix” section of the datasheet.)
10 DDM PB10 -
11 DDP PB11 -
7 TCK/SWCLK PB7 -
6 TMS/SWDIO PB6 -
5 TDO/TRACESWO PB5 -
4 TDI PB4 -
- PA7 XIN32 - See footnote (2) below
- PA8 XOUT32 -
- PB9 XIN - See footnote (3) below
- PB8 XOUT -
25
11090A–ATARM–10-Feb-12
SAM3S8/SD8
6.3 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3S8/SD8 series. The TST pin integrates a permanent pull-down resistor of
about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast pro-
gramming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the
manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-
troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of
this pin must be low to prevent unwanted erasing. Refer to Section 9.3 “Peripheral Signal Multi-
plexing on I/O Lines” on page 34. Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
26
11090A–ATARM–10-Feb-12
SAM3S8/SD8
7. Memories
Figure 7-1. SAM3S8/SD8 Product Mapping
Address memory space
Code
1 MByte
bit band
regiion
1 MByte
bit band
regiion
1 MByte
bit band
regiion
0x00000000
SRAM
0x20000000
0x20100000
0x22000000
0x24000000
0x40000000
offset
ID
peripheral
block
Code
Boot Memory
0x00000000
0x00400000
0x00800000
Reserved
0x00C00000
0x1FFFFFFF
Peripherals
HSMCI
18
0x40000000
SSC
22
0x40004000
SPI
21
0x40008000
0x4000C000
TC0 TC0
0x40010000
23
TC0 TC1
+0x40
24
TC0 TC2
+0x80
25
TC1 TC3
0x40014000
26
TC1 TC4
+0x40
27
TC1 TC5
+0x80
28
TWI0
19
0x40018000
TWI1
20
0x4001C000
PWM
31
0x40020000
USART0
14
0x40024000
USART1
15
0x40028000
USART2
0x4002C000
Reserved
0x40030000
UDP
33
0x40034000
ADC
29
0x40038000
DACC
30
0x4003C000
ACC
34
0x40040000
CRCCU
35
0x40044000
0x40048000
System Controller
0x400E0000
0x400E2600
0x40100000
0x40200000
0x40400000
0x60000000
External RAM
SMC Chip Select 0
0x60000000
SMC Chip Select 1
Undefined
32 MBytes
bit band alias
0x61000000
SMC Chip Select 2
0x62000000
SMC Chip Select 3
0x63000000
0x64000000
0x9FFFFFFF
System Controller
SMC
10
0x400E0000
MATRIX
0x400E0200
PMC
5
0x400E0400
UART0
UART1
8
0x400E0600
CHIPID
0x400E0740
9
0x400E0800
EFC
6
0x400E0A00
0x400E0C00
PIOA
11
0x400E0E00
PIOB
12
0x400E1000
PIOC
13
0x400E1200
RSTC
0x400E1400
1
SUPC
+0x10
RTT
+0x30
3
WDT
+0x50
4
RTC
+0x60
2
GPBR
+0x90
0x400E1600
0x4007FFFF
Internal Flash
Internal ROM
Reserved
Peripherals
External SRAM
0x60000000
0xA0000000
System
0xE0000000
0xFFFFFFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
32 MBytes
bit band alias
Reserved
16
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11090A–ATARM–10-Feb-12
SAM3S8/SD8
7.1 Embedded Memories
7.1.1 Internal SRAM
The SAM3S8 device (512-Kbytes, single bank flash) embeds a total of 64-Kbytes high-speed
SRAM.
The SAM3SD8 device (512-Kbytes, dual bank flash) embeds a total of 64-Kbytes high-speed
SRAM.
The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and
0x23FF FFFF.
7.1.2 Internal ROM
The SAM3S8/SD8 embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA),
In Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
7.1.3 Embedded Flash
7.1.3.1 Flash Overview
The Flash of the SAM3S8 (512-Kbytes single bank flash) is organized in one bank of 2048
pages of 256 bytes.
The Flash of the SAM3SD8 (512-Kbytes, dual bank flash) is organized in two banks of 1024
pages of 256 bytes each.
The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
7.1.3.2 Flash Power Supply
The Flash is supplied by VDDCORE.
7.1.3.3 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas-
ters of the system. It enables reading the Flash and writing the write buffer. It also contains a
User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-
bit internal bus. Its 128-bit wide memory interface increases performance.
The user can choose between high performance or lower current consumption by selecting
either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking
sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
7.1.3.4 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to the “AC Characteristics” sub-section of the product “Electrical
Characteristics”.
28
11090A–ATARM–10-Feb-12
SAM3S8/SD8
7.1.3.5 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock region has its associated lock bit.
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
7.1.3.6 Security Bit Feature
The SAM3S8/SD8 features a security bit, based on a specific General Purpose NVM bit
(GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers
and Internal Peripherals either through the ICE interface or through the Fast Flash Programming
Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of
the EEFC User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,
all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
7.1.3.7 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are
factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal-
ibration bits.
7.1.3.8 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the unique identifier.
7.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
Table 7-1. Lock bit number
Product Number of Lock Bits Lock Region Size
SAM3S8/SD8 16 32 kbytes (128 pages)
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11090A–ATARM–10-Feb-12
SAM3S8/SD8
7.1.3.10 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
7.1.3.11 GPNVM Bits
The SAM3S8 features two GPNVM bits, whereas SAM3SD8 features three GPNVM bits. These
bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set
GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM3S8 is composed of 512 Kbytes in a single bank, while the SAM3SD8
Flash is composed of dual banks, each containing 256 Kbytes. The dual-bank function enables
programming one bank while the other one is read (typically while the application code is run-
ning). Only one EEFC (Flash controller) controls the two banks. Note that it is not possible to
program simultaneously, or read simultaneously, the dual banks of the Flash.
The first bank of 256 Kbytes is called Bank 0 and the second bank of 256 Kbytes, Bank 1.
The SAM3SD8 embeds an additional GPNVM bit: GPNVM2.
7.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting
ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.
7.2 External Memories
The SAM3S8/SD8 features one External Bus Interface to provide an interface to a wide range of
external memories and to any parallel peripheral.
Table 7-2. General-purpose Non volatile Memory Bits
GPNVMBit[#] Function
0 Security bit
1 Boot mode selection
2 Bank selection (Bank 0 or Bank 1) Only on SAM3SD8
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8. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the sys-
tem, such as power, resets, clocks, time, interrupts, watchdog, etc...
See the system controller block diagram in Figure 8-1 on page 31.
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Figure 8-1. System Controller Block Diagram
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8.1 System Controller and Peripherals Mapping
Please refer to Section 7-1 “SAM3S8/SD8 Product Mapping” on page 26.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
8.2 Power-on-Reset, Brownout and Supply Monitor
The SAM3S8/SD8 embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDIO
• Brownout Detector on VDDCORE
• Supply Monitor on VDDIO
8.2.1 Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but
also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For
more information, refer to the Electrical Characteristics section of the datasheet.
8.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft-
ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it
during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor-
mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the
datasheet.
8.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software
and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled
by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply mon-
itor power consumption by a factor of up to 2048. For more information, refer to the SUPC and
Electrical Characteristics sections of the datasheet.
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9. Peripherals
9.1 Peripheral Identifiers
Table 9-1 defines the Peripheral Identifiers of the SAM3S8/SD8. A peripheral identifier is
required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller
and control of the peripheral clock with the Power Management Controller.
Table 9-1. Peripheral Identifiers
Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description
0SUPC X Supply Controller
1RSTC X Reset Controller
2RTC X Real Time Clock
3RTT X Real Time Timer
4WDT X Watchdog Timer
5PMC X Power Management Controller
6 EEFC X Enhanced Embedded Flash Controller
7- - Reserved
8UART0 X XUART 0
9UART1 X XUART 1
10 SMC X X Static Memory Controller
11 PIOA X X Parallel I/O Controller A
12 PIOB X X Parallel I/O Controller B
13 PIOC X X Parallel I/O Controller C
14 USART0 X X USART 0
15 USART1 X X USART 1
16 USART2 X X USART 2 (SAM3SD8 100 pins only)
17 - - - Reserved
18 HSMCI X X Multimedia Card Interface
19 TWI0 X X Two Wire Interface 0
20 TWI1 X X Two Wire Interface 1
21 SPI X X Serial Peripheral Interface
22 SSC X X Synchronous Serial Controller
23 TC0 X X Timer/Counter 0
24 TC1 X X Timer/Counter 1
25 TC2 X X Timer/Counter 2
26 TC3 X X Timer/Counter 3
27 TC4 X X Timer/Counter 4
28 TC5 X X Timer/Counter 5
29 ADC X X Analog To Digital Converter
30 DACC X X Digital To Analog Converter
31 PWM X X Pulse Width Modulation
32 CRCCU X X CRC Calculation Unit
33 ACC X X Analog Comparator
34 UDP X X USB Device Port
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9.2 APB/AHB Bridge
The SAM3S8/SD8 embeds One Peripheral Bridge:
The peripherals of the bridge are clocked by MCK.
9.3 Peripheral Signal Multiplexing on I/O Lines
The SAM3S8/SD8 features 2 PIO controllers on 64-pin versions (PIOA and PIOB) or 3 PIO con-
trollers on the 100-pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the
peripheral set.
The SAM3S8/SD8 64-pin and 100-pin PIO Controllers control up to 32 lines. Each line can be
assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following
paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO
Controllers. The column “Comments” has been inserted in this table for the user’s own com-
ments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
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9.3.1 PIO Controller A Multiplexing
Table 9-2. Multiplexing on PIO Controller A (PIOA)
I/O Line Peripheral A Peripheral B Peripheral C Peripheral D Extra Function System Function Comments
PA0 PWMH0 TIOA0 A17 WKUP0
PA1 PWMH1 TIOB0 A18 WKUP1
PA2 PWMH2 SCK0 DATRG WKUP2
PA 3 T W D 0 N P C S 3
PA4 TWCK0 TCLK0 WKUP3
PA5 RXD0 NPCS3 WKUP4
PA 6 T X D 0 P C K 0
PA 7 R T S 0 P W M H 3 X I N 3 2
PA8 CTS0 ADTRG WKUP5 XOUT32
PA9 URXD0 NPCS1 PWMFI0 WKUP6
PA10 UTXD0 NPCS2
PA11 NPCS0 PWMH0 WKUP7
PA 1 2 M I S O P W M H 1
PA13 MOSI PWMH2
PA14 SPCK PWMH3 WKUP8
PA15 TF TIOA1 PWML3 PIODCEN1 WKUP14
PA16 TK TIOB1 PWML2 PIODCEN2 WKUP15
PA17 TD PCK1 PWMH3 AD0
PA18 RD PCK2 A14 AD1
PA19 RK PWML0 A15 AD2/WKUP9
PA20 RF PWML1 A16 AD3/WKUP10
PA21 RXD1 PCK1 AD8 64/100 pins versions
PA22 TXD1 NPCS3 NCS2 AD9 64/100 pins versions
PA23 SCK1 PWMH0 A19 PIODCCLK 64/100 pins versions
PA 2 4 R T S 1 P W M H 1 A20 PIODC0 64/100 pins versions
PA25 CTS1 PWMH2 A23 PIODC1 64/100 pins versions
PA26 DCD1 TIOA2 MCDA2 PIODC2 64/100 pins versions
PA27 DTR1 TIOB2 MCDA3 PIODC3 64/100 pins versions
PA28 DSR1 TCLK1 MCCDA PIODC4 64/100 pins versions
PA29 RI1 TCLK2 MCCK PIODC5 64/100 pins versions
PA30 PWML2 NPCS2 MCDA0 PIODC6 WKUP11 64/100 pins versions
PA31 NPCS1 PCK2 MCDA1 PIODC7 64/100 pins versions
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9.3.2 PIO Controller B Multiplexing
Table 9-3. Multiplexing on PIO Controller B (PIOB)
I/O
Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments
PB0 PWMH0 AD4/RTCOUT0
PB1 PWMH1 AD5/RTCOUT1
PB2 URXD1 NPCS2 AD6/WKUP12
PB3 UTXD1 PCK2 AD7
PB4 TWD1 PWMH2 TDI
PB5 TWCK1 PWML0 WKUP13 TDO/TRACESWO
PB6 TMS/SWDIO
PB7 TCK/SWCLK
PB8 XOUT
PB9 XIN
PB10 DDM
PB11 DDP
PB12 PWML1 ERASE
PB13 PWML2 PCK0 DAC0 64/00 pins versions
PB14 NPCS1 PWMH3 DAC1 64/100 pins versions
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9.3.3 PIO Controller C Multiplexing
Note: 1. USART2 only on SAM3SD8 in 100 pin package.
Table 9-4. Multiplexing on PIO Controller C (PIOC)
I/O Line Peripheral A Peripheral B Peripheral C
Extra
Function
System
Function Comments
PC0 D0 PWML0 100 pin version
PC1 D1 PWML1 100 pin version
PC2 D2 PWML2 100 pin version
PC3 D3 PWML3 100 pin version
PC4 D4 NPCS1 100 pin version
PC5 D5 100 pin version
PC6 D6 100 pin version
PC7 D7 100 pin version
PC8 NWE 100 pin version
PC9 NANDOE RXD2(1) 100 pin version
PC10 NANDWE TXD2(1) 100 pin version
PC11 NRD 100 pin version
PC12 NCS3 AD12 100 pin version
PC13 NWAIT PWML0 AD10 100 pin version
PC14 NCS0 SCK2(1) 100 pin version
PC15 NCS1 PWML1 AD11 100 pin version
PC16 A21/NANDALE RTS2(1) 100 pin version
PC17 A22/NANDCLE CTS2(1) 100 pin version
PC18 A0 PWMH0 100 pin version
PC19 A1 PWMH1 100 pin version
PC20 A2 PWMH2 100 pin version
PC21 A3 PWMH3 100 pin version
PC22 A4 PWML3 100 pin version
PC23 A5 TIOA3 100 pin version
PC24 A6 TIOB3 100 pin version
PC25 A7 TCLK3 100 pin version
PC26 A8 TIOA4 100 pin version
PC27 A9 TIOB4 100 pin version
PC28 A10 TCLK4 100 pin version
PC29 A11 TIOA5 AD13 100 pin version
PC30 A12 TIOB5 AD14 100 pin version
PC31 A13 TCLK5 100 pin version
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10. ARM Cortex® M3 Processor
10.1 About this section
This section provides the information required for application and system-level software devel-
opment. It does not provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have
no experience of ARM products.
Note: The information in this section is reproduced from source material provided to Atmel by
ARM Ltd. in terms of Atmel’s license for the ARM Cortex™-M3 processor core. This information
is copyright ARM Ltd., 2008 - 2009.
10.2 About the Cortex-M3 processor and core peripherals
• The Cortex-M3 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
• outstanding processing performance combined with fast interrupt handling
• enhanced system debug with extensive breakpoint and trace capabilities
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep modes
• platform security, with integrated memory protection unit (MPU).
Figure 10-1. Typical Cortex-M3 implementation
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
Processor
Core
NVIC
Debug
Access
Port
Memory
Protection Unit
Serial
Wire
Viewer
Bus Matrix
Code
Interface
SRAM and
Peripheral Interface
Data
Watchpoints
Flash
Patch
Cortex-M3
Processor
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mized design, providing high-end processing hardware including single-cycle 32x32
multiplication and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M3 processor implements a version of the
Thumb® instruction set, ensuring high code density and reduced program memory requirements.
The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-
bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to
deliver industry-leading interrupt performance. The NVIC provides up to 16 interrupt priority lev-
els. The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to suspend load-multiple and store-multiple opera-
tions. Interrupt handlers do not require any assembler stubs, removing any code overhead from
the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from
one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep
sleep function that enables the entire device to be rapidly powered down.
10.2.1 System level interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain memory
control, enabling applications to implement security privilege levels, separating code, data and
stack on a task-by-task basis. Such requirements are becoming critical in many embedded
applications.
10.2.2 Integrated configurable debug
The Cortex-M3 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
10.2.3 Cortex-M3 processor features and benefits summary
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast multiplier
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• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
10.2.4 Cortex-M3 core peripherals
These are:
10.2.4.1 Nested Vectored Interrupt Controller
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
10.2.4.2 System control block
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
10.2.4.3 System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
10.2.4.4 Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memory regions. It provides up to eight different regions, and an optional predefined
background region.
10.3 Programmers model
This section describes the Cortex-M3 programmers model. In addition to the individual core reg-
ister descriptions, it contains information about the processor modes and privilege levels for
software execution and stacks.
10.3.1 Processor mode and privilege levels for software execution
The processor modes are:
10.3.1.1 Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
10.3.1.2 Handler mode
Used to handle exceptions. The processor returns to Thread mode when it has finished excep-
tion processing.
The privilege levels for software execution are:
10.3.1.3 Unprivileged
The software:
• has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
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• cannot access the system timer, NVIC, or system control block
• might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
10.3.1.4 Privileged
The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
In Thread mode, the CONTROL register controls whether software execution is privileged or
unprivileged, see “CONTROL register” on page 51. In Handler mode, software execution is
always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for
software execution in Thread mode. Unprivileged software can use the SVC instruction to make
a supervisor call to transfer control to privileged software.
10.3.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the last
stacked item on the stack memory. When the processor pushes a new item onto the stack, it
decrements the stack pointer and then writes the item to the new memory location. The proces-
sor implements two stacks, the main stack and the process stack, with independent copies of
the stack pointer, see “Stack Pointer” on page 44.
In Thread mode, the CONTROL register controls whether the processor uses the main stack or
the process stack, see “CONTROL register” on page 51. In Handler mode, the processor always
uses the main stack. The options for processor operations are:
Note: 1. “CONTROL register” on page 51
Table 10-1. Summary of processor mode, execution privilege level, and stack use options
Processor
mode
Used to
execute
Privilege level for
software execution Stack used
Thread Applications Privileged or unprivileged(1) Main stack or process stack(1)
Handler Exception handlers Always privileged Main stack
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10.3.3 Core registers
The processor core registers are:
Table 10-2. Core register set summary
Name
Type
(1)
Required
privilege
(2)
Reset
value Description
R0-R12 RW Either Unknown “General-purpose registers” on page 44
MSP RW Privileged See
description “Stack Pointer” on page 44
PSP RW Either Unknown “Stack Pointer” on page 44
LR RW Either 0xFFFFFFFF “Link Register” on page 44
PC RW Either See
description “Program Counter” on page 44
PSR RW Privileged
0x01000000
“Program Status Register” on page 45
ASPR RW Either 0x00000000 “Application Program Status Register” on
page 46
IPSR RO Privileged 0x00000000 “Interrupt Program Status Register” on page
47
EPSR RO Privileged 0x01000000 “Execution Program Status Register” on page
48
PRIMASK RW Privileged 0x00000000 “Priority Mask Register” on page 49
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP‡
PSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
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10.3.3.1 General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
10.3.3.2 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indi-
cates the stack pointer to use:
•0 = Main Stack Pointer (MSP). This is the reset value.
•1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address
0x00000000
.
10.3.3.3 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function
calls, and exceptions. On reset, the processor loads the LR value
0xFFFFFFFF
.
10.3.3.4 Program Counter
The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is
always 0 because instruction fetches must be halfword aligned. On reset, the processor loads
the PC with the value of the reset vector, which is at address
0x00000004
.
FAULTMASK RW Privileged 0x00000000 “Fault Mask Register” on page 49
BASEPRI RW Privileged 0x00000000 “Base Priority Mask Register” on page 50
CONTROL RW Privileged 0x00000000 “CONTROL register” on page 51
1. Describes access type during program execution in thread mode and Handler mode. Debug
access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
Table 10-2. Core register set summary (Continued)
Name
Type
(1)
Required
privilege
(2)
Reset
value Description
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10.3.3.5 Program Status Register
The Program Status Register (PSR) combines:
•Application Program Status Register (APSR)
•Interrupt Program Status Register (IPSR)
•Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are:
• APSR:
• IPSR:
• EPSR:
31 30 29 28 27 26 25 24
N Z C V Q Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved ISR_NUMBER
76543210
ISR_NUMBER
31 30 29 28 27 26 25 24
Reserved ICI/IT T
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
ICI/IT Reserved
76543210
Reserved
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The PSR bit assignments are:
Access these registers individually or as a combination of any two or all three registers, using
the register name as an argument to the MSR or MRS instructions. For example:
• read all of the registers using PSR with the MRS instruction
• write to the APSR using APSR with the MSR instruction.
The PSR combinations and attributes are:
See the instruction descriptions “MRS” on page 143 and “MSR” on page 144 for more informa-
tion about how to access the program status registers.
10.3.3.6 Application Program Status Register
The APSR contains the current state of the condition flags from previous instruction executions.
See the register summary in Table 10-2 on page 43 for its attributes. The bit assignments are:
•N
Negative or less than flag:
0 = operation result was positive, zero, greater than, or equal
1 = operation result was negative or less than.
•Z
Zero flag:
0 = operation result was not zero
1 = operation result was zero.
31 30 29 28 27 26 25 24
N Z C V Q ICI/IT T
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
ICI/IT Reserved ISR_NUMBER
76543210
ISR_NUMBER
Table 10-3. PSR register combinations
Register Type Combination
PSR RW (1), (2)
1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the proces-
sor ignores writes to the these bits.
APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
IAPSR RW(1) APSR and IPSR
EAPSR RW(2) APSR and EPSR
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•C
Carry or borrow flag:
0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1 = add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
•V
Overflow flag:
0 = operation did not result in an overflow
1 = operation resulted in an overflow.
•Q
Sticky saturation flag:
0 = indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1 = indicates when an
SSAT
or
USAT
instruction results in saturation.
This bit is cleared to zero by software using an
MRS
instruction.
10.3.3.7 Interrupt Program Status Register
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
See the register summary in Table 10-2 on page 43 for its attributes. The bit assignments are:
•ISR_NUMBER
This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
50 = IRQ34
see “Exception types” on page 63 for more information.
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10.3.3.8 Execution Program Status Register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
•If-Then (IT) instruction
•Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in Table 10-2 on page 43 for the EPSR attributes. The bit assign-
ments are:
•ICI
Interruptible-continuable instruction bits, see “Interruptible-continuable instructions” on page 48.
•IT
Indicates the execution state bits of the
IT
instruction, see “IT” on page 133.
•T
Always set to 1.
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the opera-
tion that is at fault. See “Exception entry and return” on page 68
10.3.3.9 Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
10.3.3.10 If-Then block
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruc-
tion in the block is conditional. The conditions for the instructions are either all the same, or
some can be the inverse of others. See “IT” on page 133 for more information.
10.3.3.11 Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruc-
tion to change the value of PRIMASK or FAULTMASK. See “MRS” on page 143, “MSR” on page
144, and “CPS” on page 139 for more information.
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10.3.3.12 Priority Mask Register
The PRIMASK register prevents activation of all exceptions with configurable priority. See the
register summary in Table 10-2 on page 43 for its attributes. The bit assignments are:
•PRIMASK
0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
10.3.3.13 Fault Mask Register
The FAULTMASK register prevents activation of all exceptions. See the register summary in
Table 10-2 on page 43 for its attributes. The bit assignments are:
•FAULTMASK
0 = no effect
1 = prevents the activation of all exceptions.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved PRIMASK
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved FAULTMASK
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10.3.3.14 Base Priority Mask Register
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with same or lower priority
level as the BASEPRI value. See the register summary in Table 10-2 on page 43 for its attri-
butes. The bit assignments are:
• BASEPRI
Priority mask bits:
0x0000
= no effect
Nonzero = defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field,
bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” on page 158 for more information. Remember
that higher priority field values correspond to lower exception priorities.
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
BASEPRI
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10.3.3.15 CONTROL register
The CONTROL register controls the stack used and the privilege level for software execution
when the processor is in Thread mode. See the register summary in Table 10-2 on page 43 for
its attributes. The bit assignments are:
• Active stack pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
• Thread mode privilege level
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CON-
TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and
exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruc-
tion to set the Active stack pointer bit to 1, see “MSR” on page 144.
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This
ensures that instructions after the ISB execute using the new stack pointer. See “ISB” on page 142
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved Active Stack
Pointer
Thread Mode
Privilege
Level
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10.3.4 Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses handler mode to handle all
exceptions except for reset. See “Exception entry” on page 69 and “Exception return” on page
70 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller” on
page 151 for more information.
10.3.5 Data types
The processor:
• supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
• supports 64-bit data transfer instructions.
• manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See “Memory regions, types and
attributes” on page 54 for more information.
10.3.6 The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard
(CMSIS) defines:
• a common way to:
– access peripheral registers
– define exception vectors
• the names of:
– the registers of the core peripherals
– the core exception vectors
• a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cor-
tex-M3 processor. It also includes optional interfaces for middleware components comprising a
TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combi-
nation of CMSIS-compliant software components from various middleware vendors. Software
vendors can expand the CMSIS to include their peripheral definitions and access functions for
those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions
of the CMSIS functions that address the processor core and the core peripherals.
This document uses the register short names defined by the CMSIS. In a few cases these differ
from the architectural short names that might be used in other documents.
The following sections give more information about the CMSIS:
•“Power management programming hints” on page 74
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•“Intrinsic functions” on page 78
•“The CMSIS mapping of the Cortex-M3 NVIC registers” on page 151
•“NVIC programming hints” on page 163.
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10.4 Memory model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4GB of
addressable memory. The memory map is:
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data, see “Bit-banding” on page 58.
The processor reserves regions of the Private peripheral bus (PPB) address range for core
peripheral registers, see “About the Cortex-M3 peripherals” on page 150.
This memory mapping is generic to ARM Cortex-M3 products. To get the specific memory map-
ping of this product, refer to the Memories section of the datasheet.
10.4.1 Memory regions, types and attributes
The memory map and the programming of the MPU split the memory map into regions. Each
region has a defined memory type, and some regions have additional memory attributes. The
memory type and attributes determine the behavior of accesses to the region.
The memory types are:
Vendor-specific
memory
External device
External RAM
Peripheral
SRAM
Code
0xFFFFFFFF
Private peripheral
bus
0xE0100000
0xE00FFFFF
0x9FFFFFFF
0xA0000000
0x5FFFFFFF
0x60000000
0x3FFFFFFF
0x40000000
0x1FFFFFFF
0x20000000
0x00000000
0x40000000 Bit band region
Bit band alias
32MB
1MB
0x400FFFFF
0x42000000
0x43FFFFFF
Bit band region
Bit band alias
32MB
1MB
0x20000000
0x200FFFFF
0x22000000
0x23FFFFFF
1.0GB
1.0GB
0.5GB
0.5GB
0.5GB
0xDFFFFFFF
0xE0000000
1.0MB
511MB
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10.4.1.1 Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
10.4.1.2 Device
The processor preserves transaction order relative to other transactions to Device or Strongly-
ordered memory.
10.4.1.3 Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include.
10.4.1.4 Shareable
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must ensure data
coherency between the bus masters.
10.4.1.5 Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an
XN region causes a memory management fault exception.
10.4.2 Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, software must insert a memory barrier instruction between the memory access instruc-
tions, see “Software ordering of memory accesses” on page 57.
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before
A2 in program order, the ordering of the memory accesses caused by two instructions is:
Normal access
Device access, non-shareable
Device access, shareable
Strongly-ordered access
Normal
access Non-shareable Shareable
Strongly-
ordered
access
Device access
A1
A2
-
-
-
-
-
<
-
<
-
-
<
<
-
<
<
<
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Where:
- Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
10.4.3 Behavior of memory accesses
The behavior of accesses to each region in the memory map is:
Note: 1. See “Memory regions, types and attributes” on page 54 for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory protection unit” on page 196.
Table 10-4. Memory access behavior
Address
range
Memory
region
Memory
type XN Description
0x00000000
-
0x1FFFFFFF
Code Normal(1) -Executable region for program code. You can also put
data here.
0x20000000
-
0x3FFFFFFF
SRAM Normal(1) -
Executable region for data. You can also put code
here.
This region includes bit band and bit band alias areas,
see Table 10-6 on page 59.
0x40000000
-
0x5FFFFFFF
Peripheral Device(1) XN This region includes bit band and bit band alias areas,
see Table 10-6 on page 59.
0x60000000
-
0x9FFFFFFF
External
RAM Normal(1) - Executable region for data.
0xA0000000
-
0xDFFFFFFF
External
device Device(1) XN External Device memory
0xE0000000
-
0xE00FFFFF
Private
Peripheral
Bus
Strongly-
ordered(1) XN This region includes the NVIC, System timer, and
system control block.
0xE0100000
-
0xFFFFFFFF
Reserved Device(1) XN Reserved
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10.4.3.1 Additional memory access constraints for shared memory
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as Table 10-5 shows:
Notes: 1. See “Memory regions, types and attributes” on page 54 for more information.
2. The Peripheral and Vendor-specific device regions have no additional access constraints.
10.4.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
• the processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
“Memory system ordering of memory accesses” on page 55 describes the cases where the
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering. The
processor provides the following memory barrier instructions:
10.4.4.1
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See “DMB” on page 140.
Table 10-5. Memory region share ability policies
Address range Memory region Memory type Shareability
0x00000000
-
0x1FFFFFFF
Code Normal(1) -
0x20000000
-
0x3FFFFFFF
SRAM Normal(1) -
0x40000000
-
0x5FFFFFFF
Peripheral(2) Device(1) -
0x60000000
-
0x7FFFFFFF
External RAM Normal(1) -
WBWA(2)
0x80000000
-
0x9FFFFFFF
WT(2)
0xA0000000
-
0xBFFFFFFF
External device Device(1)
Shareable(1)
-
0xC0000000
-
0xDFFFFFFF
Non-
shareable(1)
0xE0000000
-
0xE00FFFFF
Private Peripheral
Bus
Strongly-
ordered(1) Shareable(1) -
0xE0100000
-
0xFFFFFFFF
Vendor-specific
device(2) Device(1) --
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10.4.4.2
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See “DSB” on page 141.
10.4.4.3
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See “ISB” on page 142.
Use memory barrier instructions in, for example:
• MPU programming:
– Use a DSB instruction to ensure the effect of the MPU takes place immediately at
the end of context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was
accessed using a branch or call. If the MPU configuration code is entered using
exception mechanisms, then an ISB instruction is not required.
• Vector table. If the program changes an entry in the vector table, and then enables the
corresponding exception, use a DMB instruction between the operations. This ensures that if
the exception is taken immediately after being enabled the processor uses the new exception
vector.
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
immediately after the code modification in the program. This ensures subsequent instruction
execution uses the updated program.
• Memory map switching. If the system contains a memory map switching mechanism, use a
DSB instruction after switching the memory map in the program. This ensures subsequent
instruction execution uses the updated memory map.
• Dynamic exception priority change. When an exception priority has to change when the
exception is pending or active, use DSB instructions after the change. This ensures the
change takes effect on completion of the DSB instruction.
• Using a semaphore in multi-master system. If the system contains more than one bus
master, for example, if another processor is present in the system, each processor must use
a DMB instruction after any semaphore instructions, to ensure other bus masters see the
memory transactions in the order in which they were executed.
Memory accesses to Strongly-ordered memory, such as the system control block, do not require
the use of DMB instructions.
10.4.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions.
The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
• accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown
in Table 10-6
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• accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as
shown in Table 10-7.
A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM
or peripheral bit-band region.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
•
Bit_word_offset
is the position of the target bit in the bit-band memory region.
•
Bit_word_addr
is the address of the word in the alias memory region that maps to the
targeted bit.
•
Bit_band_base
is the starting address of the alias region.
•
Byte_offset
is the number of the byte in the bit-band region that contains the targeted bit.
•
Bit_number
is the bit position, 0-7, of the targeted bit.
Figure 10-2 shows examples of bit-band mapping between the SRAM bit-band alias region and
the SRAM bit-band region:
• The alias word at
0x23FFFFE0
maps to bit[0] of the bit-band byte at
0x200FFFFF
:
0x23FFFFE0
=
0x22000000
+ (
0xFFFFF
*32) + (0*4).
• The alias word at
0x23FFFFFC
maps to bit[7] of the bit-band byte at
0x200FFFFF
:
0x23FFFFFC
=
0x22000000
+ (
0xFFFFF
*32) + (7*4).
• The alias word at
0x22000000
maps to bit[0] of the bit-band byte at
0x20000000
:
0x22000000
=
0x22000000
+ (0*32) + (0 *4).
• The alias word at
0x2200001C
maps to bit[7] of the bit-band byte at
0x20000000
:
0x2200001C
=
0x22000000
+ (0*32) + (7*4).
Table 10-6. SRAM memory bit-banding regions
Address
range
Memory
region Instruction and data accesses
0x20000000
-
0x200FFFFF
SRAM bit-band
region
Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x22000000
-
0x23FFFFFF SRAM bit-band alias
Data accesses to this region are remapped to bit band
region. A write operation is performed as read-modify-write.
Instruction accesses are not remapped.
Table 10-7. Peripheral memory bit-banding regions
Address
range
Memory
region Instruction and data accesses
0x40000000-
0x400FFFFF
Peripheral bit-band
alias
Direct accesses to this memory range behave as peripheral
memory accesses, but this region is also bit addressable
through bit-band alias.
0x42000000-
0x43FFFFFF
Peripheral bit-band
region
Data accesses to this region are remapped to bit band
region. A write operation is performed as read-modify-write.
Instruction accesses are not permitted.
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Figure 10-2. Bit-band mapping
10.4.5.1 Directly accessing an alias region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the tar-
geted bit in the bit-band region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit,
and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing
0x01
has the same effect as
writing
0xFF
. Writing
0x00
has the same effect as writing
0x0E
.
Reading a word in the alias region:
•
0x00000000
indicates that the targeted bit in the bit-band region is set to zero
•
0x00000001
indicates that the targeted bit in the bit-band region is set to 1
10.4.5.2 Directly accessing a bit-band region
“Behavior of memory accesses” on page 56 describes the behavior of direct byte, halfword, or
word accesses to the bit-band regions.
10.4.6 Memory endianness
The processor views memory as a linear collection of bytes numbered in ascending order from
zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored
word. or “Little-endian format” describes how words of data are stored in memory.
0x23FFFFE4
0x22000004
0x23FFFFE00x23FFFFE80x23FFFFEC0x23FFFFF00x23FFFFF40x23FFFFF80x23FFFFFC
0x220000000x220000140x220000180x2200001C 0x220000080x22000010 0x2200000C
32MB alias region
0
7 0
07
0x200000000x200000010x200000020x20000003
6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1
07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1
0x200FFFFC0x200FFFFD0x200FFFFE0x200FFFFF
1MB SRAM bit-band region
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10.4.6.1 Little-endian format
In little-endian format, the processor stores the least significant byte of a word at the lowest-
numbered byte, and the most significant byte at the highest-numbered byte. For example:
10.4.7 Synchronization primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-
blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
10.4.7.1 A Load-Exclusive instruction
Used to read the value of a memory location, requesting exclusive access to that location.
10.4.7.2 A Store-Exclusive instruction
Used to attempt to write to the same memory location, returning a status bit to a register. If this
bit is:
0: it indicates that the thread or process gained exclusive access to the memory, and the write
succeeds,
1: it indicates that the thread or process did not gain exclusive access to the memory, and no
write is performed,
The pairs of Load-Exclusive and Store-Exclusive instructions are:
• the word instructions LDREX and STREX
• the halfword instructions LDREXH and STREXH
• the byte instructions LDREXB and STREXB.
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive
instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
• Use a Load-Exclusive instruction to read the value of the location.
• Update the value, as required.
• Use a Store-Exclusive instruction to attempt to write the new value back to the memory
location, and tests the returned status bit. If this bit is:
0: The read-modify-write completed successfully,
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
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1: No write was performed. This indicates that the value returned the first step might be out
of date. The software must retry the read-modify-write sequence,
Software can use the synchronization primitives to implement a semaphores as follows:
• Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
• If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
• If the returned status bit from the second step indicates that the Store-Exclusive succeeded
then the software has claimed the semaphore. However, if the Store-Exclusive failed, another
process might have claimed the semaphore after the software performed the first step.
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has
executed a Load-Exclusive instruction. If the processor is part of a multiprocessor system, the
system also globally tags the memory locations addressed by exclusive accesses by each
processor.
The processor removes its exclusive access tag if:
• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means the processor can resolve semaphore conflicts between
different threads.
In a multiprocessor implementation:
• executing a CLREX instruction removes only the local exclusive access tag for the processor
• executing a Store-Exclusive instruction, or an exception. removes the local exclusive access
tags, and all global exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX”
on page 100 and “CLREX” on page 102.
10.4.8 Programming hints for the synchronization primitives
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide
intrinsic functions for generation of these instructions:
The actual exclusive access instruction generated depends on the data type of the pointer
passed to the intrinsic function. For example, the following C code generates the require
LDREXB operation:
__ldrex((volatile char *) 0xFF);
Table 10-8. C compiler intrinsic functions for exclusive access instructions
Instruction Intrinsic function
LDREX
,
LDREXH
, or
LDREXB
unsigned int __ldrex(volatile void *ptr)
STREX
,
STREXH
, or
STREXB
int __strex(unsigned int val, volatile void *ptr)
CLREX void __clrex(void)
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10.5 Exception model
This section describes the exception model.
10.5.1 Exception states
Each exception is in one of the following states:
10.5.1.1 Inactive
The exception is not active and not pending.
10.5.1.2 Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the correspond-
ing interrupt to pending.
10.5.1.3 Active
An exception that is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case both
exceptions are in the active state.
10.5.1.4 Active and pending
The exception is being serviced by the processor and there is a pending exception from the
same source.
10.5.2 Exception types
The exception types are:
10.5.2.1 Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at
any point in an instruction. When reset is deasserted, execution restarts from the address pro-
vided by the reset entry in the vector table. Execution restarts as privileged execution in Thread
mode.
10.5.2.2 Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is
the highest priority exception other than reset. It is permanently enabled and has a fixed priority
of -2.
NMIs cannot be:
• Masked or prevented from activation by any other exception.
• Preempted by any exception other than Reset.
10.5.2.3 Hard fault
A hard fault is an exception that occurs because of an error during exception processing, or
because an exception cannot be managed by any other exception mechanism. Hard faults have
a fixed priority of -1, meaning they have higher priority than any exception with configurable
priority.
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10.5.2.4 Memory management fault
A memory management fault is an exception that occurs because of a memory protection
related fault. The MPU or the fixed memory protection constraints determines this fault, for both
instruction and data memory transactions. This fault is used to abort instruction accesses to
Execute Never (XN) memory regions, even if the MPU is disabled.
10.5.2.5 Bus fault
A bus fault is an exception that occurs because of a memory related fault for an instruction or
data memory transaction. This might be from an error detected on a bus in the memory system.
10.5.2.6 Usage fault
A usage fault is an exception that occurs because of a fault related to instruction execution. This
includes:
• an undefined instruction
• an illegal unaligned access
• invalid state on instruction execution
• an error on exception return.
The following can cause a usage fault when the core is configured to report them:
• an unaligned address on word and halfword memory access
• division by zero.
10.5.2.7 SVCall
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS envi-
ronment, applications can use SVC instructions to access OS kernel functions and device
drivers.
10.5.2.8 PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use
PendSV for context switching when no other exception is active.
10.5.2.9 SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software
can also generate a SysTick exception. In an OS environment, the processor can use this
exception as system tick.
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10.5.2.10 Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software
request. All interrupts are asynchronous to instruction execution. In the system, peripherals use
interrupts to communicate with the processor.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 10-9 on page 65 shows as having con-
figurable priority, see:
•“System Handler Control and State Register” on page 179
Table 10-9. Properties of the different exception types
Exception
number (1)
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative
values for exceptions other than interrupts. The IPSR returns the Exception number, see
“Interrupt Program Status Register” on page 47.
IRQ
number(
1)
Exception
type Priority
Vector address
or offset (2)
2. See “Vector table” on page 67 for more information.
Activation
1-Reset -3, the
highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 Hard fault -1 0x0000000C -
4 -12
Memory
management
fault
Configurable
(3)
3. See “System Handler Priority Registers” on page 176.
0x00000010 Synchronous
5-11Bus fault Configurable
(3) 0x00000014
Synchronous when
precise,
asynchronous when
imprecise
6 -10 Usage fault Configurable
(3) 0x00000018 Synchronous
7-10 - - - Reserved -
11 -5 SVCall Configurable
(3) 0x0000002C Synchronous
12-13 - - - Reserved -
14 -2 PendSV Configurable
(3) 0x00000038 Asynchronous
15 -1 SysTick Configurable
(3)
0x0000003C
Asynchronous
16 and
above
0 and
above (4)
4. See the “Peripheral Identifiers” section of the datasheet.
Interrupt (IRQ) Configurable
(5)
5. See “Interrupt Priority Registers” on page 158.
0x00000040
and
above (6)
6. Increasing in steps of 4.
Asynchronous
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•“Interrupt Clear-enable Registers” on page 154.
For more information about hard faults, memory management faults, bus faults, and usage
faults, see “Fault handling” on page 70.
10.5.3 Exception handlers
The processor handles exceptions using:
10.5.3.1 Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs.
10.5.3.2 Fault handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the
fault handlers.
10.5.3.3 System handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are han-
dled by system handlers.
10.5.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses, also
called exception vectors, for all exception handlers. Figure 10-3 on page 67 shows the order of
the exception vectors in the vector table. The least-significant bit of each vector must be 1, indi-
cating that the exception handler is Thumb code.
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Figure 10-3. Vector table
On system reset, the vector table is fixed at address
0x00000000
. Privileged software can write to
the VTOR to relocate the vector table start address to a different memory location, in the range
0x00000080
to
0x3FFFFF80
, see “Vector Table Offset Register” on page 170.
10.5.5 Exception priorities
As Table 10-9 on page 65 shows, all exceptions have an associated priority, with:
• a lower priority value indicating a higher priority
• configurable priorities for all exceptions except Reset, Hard fault.
If software does not configure any priorities, then all exceptions with a configurable priority have
a priority of 0. For information about configuring exception priorities see
•“System Handler Priority Registers” on page 176
•“Interrupt Priority Registers” on page 158.
Initial SP value
Reset
Hard fault
Reserved
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
Systick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ29
17
0x0048
0x004C
45
.
.
.
.
.
.
0x00B4
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
29
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Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and
NMI exceptions, with fixed negative priority values, always have higher priority than any other
exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1]
means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1]
is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest
exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and
have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception
being handled, the handler is not preempted, irrespective of the exception number. However,
the status of the new interrupt changes to pending.
10.5.6 Interrupt priority grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
divides each interrupt priority register entry into two fields:
• an upper field that defines the group priority
• a lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines the
order in which they are processed. If multiple pending interrupts have the same group priority
and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
“Application Interrupt and Reset Control Register” on page 171.
10.5.7 Exception entry and return
Descriptions of exception handling use the following terms:
10.5.7.1 Preemption
When the processor is executing an exception handler, an exception can preempt the exception
handler if its priority is higher than the priority of the exception being handled. See “Interrupt pri-
ority grouping” on page 68 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception entry” on page 69 more information.
10.5.7.2 Return
This occurs when the exception handler is completed, and:
• there is no pending exception with sufficient priority to be serviced
• the completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the
interrupt occurred. See “Exception return” on page 70 for more information.
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10.5.7.3 Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there
is a pending exception that meets the requirements for exception entry, the stack pop is skipped
and control transfers to the new exception handler.
10.5.7.4 Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving
for a previous exception, the processor switches to handle the higher priority exception and initi-
ates the vector fetch for that exception. State saving is not affected by late arrival because the
state saved is the same for both exceptions. Therefore the state saving continues uninterrupted.
The processor can accept a late arriving exception until the first instruction of the exception han-
dler of the original exception enters the execute stage of the processor. On return from the
exception handler of the late-arriving exception, the normal tail-chaining rules apply.
10.5.7.5 Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and either:
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case the
new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask regis-
ters, see “Exception mask registers” on page 48. An exception with less priority than this is
pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred as
stacking and the structure of eight data words is referred as stack frame. The stack frame con-
tains the following information:
•R0-R3, R12
• Return address
• PSR
•LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the
STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is
performed during stacking.
The stack frame includes the return address. This is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the excep-
tion handler start address from the vector table. When stacking is complete, the processor starts
executing the exception handler. At the same time, the processor writes an EXC_RETURN
value to the LR. This indicates which stack pointer corresponds to the stack frame and what
operation mode the was processor was in before the entry occurred.
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If no higher priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt
to active.
If another higher priority exception occurs during exception entry, the processor starts executing
the exception handler for this exception and does not change the pending status of the earlier
exception. This is the late arrival case.
10.5.7.6 Exception return
Exception return occurs when the processor is in Handler mode and executes one of the follow-
ing instructions to load the EXC_RETURN value into the PC:
•a
POP
instruction that includes the PC
•a
BX
instruction with any register.
•an
LDR
or
LDM
instruction with the PC as the destination.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism
relies on this value to detect when the processor has completed an exception handler. The low-
est four bits of this value provide information on the return stack and processor mode. Table 10-
10 shows the EXC_RETURN[3:0] values with a description of the exception return behavior.
The processor sets EXC_RETURN bits[31:4] to
0xFFFFFFF
. When this value is loaded into the PC
it indicates to the processor that the exception is complete, and the processor initiates the
exception return sequence.
10.6 Fault handling
Faults are a subset of the exceptions, see “Exception model” on page 63. The following gener-
ate a fault:
– a bus error on:
– an instruction fetch or vector table load
– a data access
Table 10-10. Exception return behavior
EXC_RETURN[3:0] Description
bXXX0 Reserved.
b0001
Return to Handler mode.
Exception return gets state from MSP.
Execution uses MSP after return.
b0011 Reserved.
b01X1 Reserved.
b1001
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
b1101
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
b1X11 Reserved.
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• an internally-detected error such as an undefined instruction or an attempt to change state
with a BX instruction
• attempting to execute an instruction from a memory region marked as Non-Executable (XN).
• an MPU fault because of a privilege violation or an attempt to access an unmanaged region.
10.6.1 Fault types
Table 10-11 shows the types of fault, the handler used for the fault, the corresponding fault sta-
tus register, and the register bit that indicates that the fault has occurred. See “Configurable
Fault Status Register” on page 181 for more information about the fault status registers.
10.6.2 Fault escalation and hard faults
All faults exceptions except for hard fault have configurable exception priority, see “System Han-
dler Priority Registers” on page 176. Software can disable execution of the handlers for these
faults, see “System Handler Control and State Register” on page 179.
Table 10-11. Faults
Fault Handler Bit name Fault status register
Bus error on a vector read Hard fault VECTTBL “Hard Fault Status
Register” on page 187
Fault escalated to a hard fault FORCED
MPU mismatch:
Memory
managem
ent fault
--
on instruction access IACCVIOL (1)
1. Occurs on an access to an XN region even if the MPU is disabled.
“Memory Management
Fault Address Register” on
page 188
on data access DACCVIOL
during exception stacking MSTKERR
during exception unstacking MUNSKERR
Bus error:
Bus fault
--
during exception stacking STKERR
“Bus Fault Status Register”
on page 183
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISER
R
Attempt to access a coprocessor
Usage
fault
NOCP
“Usage Fault Status
Register” on page 185
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction
set state (2)
2. Attempting to use an instruction set other than the Thumb instruction set.
INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
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Usually, the exception priority, together with the values of the exception mask registers, deter-
mines whether the processor enters the fault handler, and whether a fault handler can preempt
another fault handler. as described in “Exception model” on page 63.
In some situations, a fault with configurable priority is treated as a hard fault. This is called prior-
ity escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same
priority as the current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
because the handler for the new fault cannot preempt the currently executing fault handler.
• An exception handler causes a fault for which the priority is the same as or lower than the
currently executing exception.
• A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but the
stack contents are corrupted.
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
10.6.3 Fault status registers and fault address registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused
the fault, as shown in Table 10-12.
10.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the hard fault han-
dlers. When the processor is in lockup state it does not execute any instructions. The processor
remains in lockup state until:
• it is reset
Table 10-12. Fault status and fault address registers
Handler
Status register
name
Address register
name Register description
Hard fault HFSR - “Hard Fault Status Register” on page
187
Memory
management fault MMFSR MMFAR
“Memory Management Fault Status
Register” on page 182
“Memory Management Fault Address
Register” on page 188
Bus fault BFSR BFAR
“Bus Fault Status Register” on page 183
“Bus Fault Address Register” on page
189
Usage fault UFSR - “Usage Fault Status Register” on page
185
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10.7 Power management
The Cortex-M3 processor sleep modes reduce power consumption:
• Backup Mode
•Wait Mode
• Sleep Mode
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see “System Control Regis-
ter” on page 173. For more information about the behavior of the sleep modes see “Low Power
Modes” in the PMC section of the datasheet.
This section describes the mechanisms for entering sleep mode, and the conditions for waking
up from sleep mode.
10.7.1 Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the
processor. Therefore software must be able to put the processor back into sleep mode after
such an event. A program might have an idle loop to put the processor back to sleep mode.
10.7.1.1 Wait for interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the proces-
sor executes a WFI instruction it stops executing instructions and enters sleep mode. See “WFI”
on page 149 for more information.
10.7.1.2 Wait for event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an
one-bit event register. When the processor executes a WFE instruction, it checks this register:
• if the register is 0 the processor stops executing instructions and enters sleep mode
• if the register is 1 the processor clears the register to 0 and continues executing instructions
without entering sleep mode.
See “WFE” on page 148 for more information.
10.7.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of
an exception handler it returns to Thread mode and immediately enters sleep mode. Use this
mechanism in applications that only require the processor to run when an exception occurs.
10.7.2 Wakeup from sleep mode
The conditions for the processor to wakeup depend on the mechanism that cause it to enter
sleep mode.
10.7.2.1 Wakeup from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to
cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1
and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than
current exception priority, the processor wakes up but does not execute the interrupt handler
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until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULT-
MASK see “Exception mask registers” on page 48.
10.7.2.2 Wakeup from WFE
The processor wakes up if:
• it detects an exception with sufficient priority to cause exception entry
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an
event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about the SCR see “System Control Register” on
page 173.
10.7.3 Power management programming hints
ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the follow-
ing intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFE(void) // Wait for Interrupt
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10.8 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 10-13 lists the sup-
ported instructions.
In Table 10-13:
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 10-13. Cortex-M3 instructions
Mnemonic Operands Brief description Flags Page
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V page 105
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V page 105
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V page 105
ADR Rd, label Load PC-relative address - page 88
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C page 108
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C page 110
B label Branch - page 130
BFC Rd, #lsb, #width Bit Field Clear - page 126
BFI Rd, Rn, #lsb, #width Bit Field Insert - page 126
BIC, BICS
{Rd,}
Rn, Op2
Bit Clear N,Z,C page 108
BKPT #imm Breakpoint - page 138
BL label Branch with Link - page 130
BLX Rm Branch indirect with Link - page 130
BX Rm Branch indirect - page 130
CBNZ Rn, label Compare and Branch if Non Zero - page 132
CBZ Rn, label Compare and Branch if Zero - page 132
CLREX - Clear Exclusive - page 102
CLZ Rd, Rm Count leading zeros - page 112
CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V page 113
CMP, CMPS Rn, Op2 Compare N,Z,C,V page 113
CPSID iflags Change Processor State, Disable
Interrupts -page 139
CPSIE iflags Change Processor State, Enable
Interrupts -page 139
DMB - Data Memory Barrier - page 140
DSB - Data Synchronization Barrier - page 141
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C page 108
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ISB - Instruction Synchronization Barrier - page 142
IT - If-Then condition block - page 133
LDM Rn{!}, reglist Load Multiple registers, increment after - page 97
LDMDB,
LDMEA Rn{!}, reglist Load Multiple registers, decrement
before -page 97
LDMFD,
LDMIA Rn{!}, reglist Load Multiple registers, increment after - page 97
LDR Rt, [Rn, #offset] Load Register with word - page 92
LDRB,
LDRBT Rt, [Rn, #offset] Load Register with byte - page 92
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes - page 92
LDREX Rt, [Rn, #offset] Load Register Exclusive - page 92
LDREXB Rt, [Rn] Load Register Exclusive with byte - page 92
LDREXH Rt, [Rn] Load Register Exclusive with halfword - page 92
LDRH,
LDRHT Rt, [Rn, #offset] Load Register with halfword - page 92
LDRSB,
LDRSBT Rt, [Rn, #offset] Load Register with signed byte - page 92
LDRSH,
LDRSHT Rt, [Rn, #offset] Load Register with signed halfword - page 92
LDRT Rt, [Rn, #offset] Load Register with word - page 92
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C page 110
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C page 110
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result - page 120
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result - page 120
MOV, MOVS Rd, Op2 Move N,Z,C page 114
MOVT Rd, #imm16 Move Top - page 116
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C page 114
MRS Rd, spec_reg Move from special register to general
register -page 143
MSR spec_reg, Rm Move from general register to special
register N,Z,C,V page 144
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z page 120
MVN, MVNS Rd, Op2 Move NOT N,Z,C page 114
NOP - No Operation - page 145
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C page 108
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C page 108
POP reglist Pop registers from stack - page 99
PUSH reglist Push registers onto stack - page 99
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page
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RBIT Rd, Rn Reverse Bits - page 117
REV Rd, Rn Reverse byte order in a word - page 117
REV16 Rd, Rn Reverse byte order in each halfword - page 117
REVSH Rd, Rn Reverse byte order in bottom halfword
and sign extend -page 117
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C page 110
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C page 110
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V page 105
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V page 105
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - page 127
SDIV {Rd,} Rn, Rm Signed Divide - page 122
SEV - Send Event - page 146
SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x
32 + 64), 64-bit result -page 121
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result - page 121
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q page 123
STM Rn{!}, reglist Store Multiple registers, increment after - page 97
STMDB,
STMEA Rn{!}, reglist Store Multiple registers, decrement
before -page 97
STMFD,
STMIA Rn{!}, reglist Store Multiple registers, increment after - page 97
STR Rt, [Rn, #offset] Store Register word - page 92
STRB,
STRBT Rt, [Rn, #offset] Store Register byte - page 92
STRD Rt, Rt2, [Rn, #offset] Store Register two words - page 92
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive - page 100
STREXB Rd, Rt, [Rn] Store Register Exclusive byte - page 100
STREXH Rd, Rt, [Rn] Store Register Exclusive halfword - page 100
STRH,
STRHT Rt, [Rn, #offset] Store Register halfword - page 92
STRT Rt, [Rn, #offset] Store Register word - page 92
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V page 105
SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V page 105
SVC #imm Supervisor Call - page 147
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - page 128
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - page 128
TBB [Rn, Rm] Table Branch Byte - page 135
TBH [Rn, Rm, LSL #1] Table Branch Halfword - page 135
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page
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10.9 Intrinsic functions
ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic func-
tions that can generate these instructions, provided by the CMIS and that might be provided by a
C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to
use inline assembler to access some instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ANSI cannot
directly access:
TEQ Rn, Op2 Test Equivalence N,Z,C page 118
TST Rn, Op2 Test N,Z,C page 118
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract - page 127
UDIV {Rd,} Rn, Rm Unsigned Divide - page 122
UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result -page 121
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit
result -page 121
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q page 123
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte - page 128
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword - page 128
WFE - Wait For Event - page 148
WFI - Wait For Interrupt - page 149
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page
Table 10-14. CMSIS intrinsic functions to generate some Cortex-M3 instructions
Instruction CMSIS intrinsic function
CPSIE I void __enable_irq(void)
CPSID I void __disable_irq(void)
CPSIE F void __enable_fault_irq(void)
CPSID F void __disable_fault_irq(void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB void __DMB(void)
REV uint32_t __REV(uint32_t int value)
REV16 uint32_t __REV16(uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
RBIT uint32_t __RBIT(uint32_t int value)
SEV void __SEV(void)
WFE void __WFE(void)
WFI void __WFI(void)
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The CMSIS also provides a number of functions for accessing the special registers using MRS
and MSR instructions:
10.10 About the instruction descriptions
The following sections give more information about using the instructions:
•“Operands” on page 79
•“Restrictions when using PC or SP” on page 79
•“Flexible second operand” on page 80
•“Shift Operations” on page 81
•“Address alignment” on page 83
•“PC-relative expressions” on page 84
•“Conditional execution” on page 84
•“Instruction width selection” on page 86.
10.10.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination register.
When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant. See
“Flexible second operand” .
10.10.2 Restrictions when using PC or SP
Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack
Pointer (SP) for the operands or destination register. See instruction descriptions for more
information.
Table 10-15. CMSIS intrinsic functions to access the special registers
Special register Access CMSIS function
PRIMASK Read uint32_t __get_PRIMASK (void)
Write void __set_PRIMASK (uint32_t value)
FAULTMASK Read uint32_t __get_FAULTMASK (void)
Write void __set_FAULTMASK (uint32_t value)
BASEPRI Read uint32_t __get_BASEPRI (void)
Write void __set_BASEPRI (uint32_t value)
CONTROL Read uint32_t __get_CONTROL (void)
Write void __set_CONTROL (uint32_t value)
MSP Read uint32_t __get_MSP (void)
Write void __set_MSP (uint32_t TopOfMainStack)
PSP Read uint32_t __get_PSP (void)
Write void __set_PSP (uint32_t TopOfProcStack)
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Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be
1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3
processor only supports Thumb instructions.
10.10.3 Flexible second operand
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
•“Constant”
•“Register with optional shift” on page 80
10.10.3.1 Constant
You specify an Operand2 constant in the form:
#constant
where constant can be:
• any constant that can be produced by shifting an 8-bit value left by any number of bits within
a 32-bit word
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS,
EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is
greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
10.10.3.2 Instruction substitution
Your assembler might be able to produce an equivalent instruction in cases where you specify a
constant that is not permitted. For example, an assembler might assemble the instruction CMP
Rd
, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
10.10.3.3 Register with optional shift
You specify an Operand2 register in the form:
Rm {, shift}
where:
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
ASR #narithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #nlogical shift left n bits, 1 ≤ n ≤ 31.
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LSR #nlogical shift right n bits, 1 ≤ n ≤ 32.
ROR #nrotate right n bits, 1 ≤ n ≤ 31.
RRX rotate right one bit, with extend.
- if omitted, no shift occurs, equivalent to LSL #0.
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used
by the instruction. However, the contents in the register Rm remains unchanged. Specifying a
register with shift also updates the carry flag when used with certain instructions. For information
on the shift operations and how they affect the carry flag, see “Shift Operations”
10.10.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the
shift length. Register shift can be performed:
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
destination register
• during the calculation of Operand2 by the instructions that specify the second operand as a
register with shift, see “Flexible second operand” on page 80. The result is used by the
instruction.
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or “Flexible second operand” on page 80. If the shift length is 0, no shift
occurs. Register shift operations update the carry flag except when the specified shift length is 0.
The following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift
length.
10.10.4.1 ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register
into the left-hand n bits of the result. See Figure 10-4 on page 81.
You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result
being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
•If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
•If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 10-4. ASR #3
31 10
Carry
Flag
...
2345
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10.10.4.2 LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0.
See Figure 10-5.
You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is
regarded as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
•If n is 32 or more, then all the bits in the result are cleared to 0.
•If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 10-5. LSR #3
10.10.4.3 LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0.
See Figure 10-6 on page 82.
You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value is
regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur
without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the
instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is
updated to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect
the carry flag when used with LSL #0.
•If n is 32 or more, then all the bits in the result are cleared to 0.
•If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 10-6. LSL #3
31 10
Carry
Flag
...
000
2345
31 10
Carry
Flag ...
000
2345
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10.10.4.4 ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places,
into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into
the left-hand n bits of the result. See Figure 10-7.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
rotation, bit[n-1], of the register Rm.
•If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is
updated, it is updated to bit[31] of Rm.
• ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
Figure 10-7. ROR #3
10.10.4.5 RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies
the carry flag into bit[31] of the result. See Figure 10-8 on page 83.
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of
the register Rm.
Figure 10-8. RRX
10.10.5 Address alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word,
or multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
The Cortex-M3 processor supports unaligned access only for the following instructions:
• LDR, LDRT
• LDRH, LDRHT
• LDRSH, LDRSHT
•STR, STRT
• STRH, STRHT
31 10
Carry
Flag
...
2345
31 30 10
Carry
Flag
... ...
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All other load and store instructions generate a usage fault exception if they perform an
unaligned access, and therefore their accesses must be address aligned. For more information
about usage faults see “Fault handling” on page 70.
Unaligned accesses are usually slower than aligned accesses. In addition, some memory
regions might not support unaligned accesses. Therefore, ARM recommends that programmers
ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use
the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses,
see “Configuration and Control Register” on page 174.
10.10.6 PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or lit-
eral data. It is represented in the instruction as the PC value plus or minus a numeric offset. The
assembler calculates the required offset from the label and the address of the current instruc-
tion. If the offset is too big, the assembler produces an error.
• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
instruction plus 4 bytes.
• For all other instructions that use labels, the value of the PC is the address of the current
instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus
or minus a number, or an expression of the form [PC, #number].
10.10.7 Conditional execution
Most data processing instructions can optionally update the condition flags in the Application
Program Status Register (APSR) according to the result of the operation, see “Application Pro-
gram Status Register” on page 46. Some instructions update all flags, and some only update a
subset. If a flag is not updated, the original value is preserved. See the instruction descriptions
for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another instruc-
tion, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See Table 10-16 on page 85 for a list of the suffixes to add to instructions
to make them conditional instructions. The condition code suffix enables the processor to test a
condition based on the flags. If the condition test of a conditional instruction fails, the instruction:
• does not execute
• does not write any value to its destination register
• does not affect any of the flags
• does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction
block. See “IT” on page 133 for more information and restrictions when using the IT instruction.
Depending on the vendor, the assembler might automatically insert an IT instruction if you have
conditional instructions outside the IT block.
Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch
on the result.
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This section describes:
•“The condition flags”
•“Condition code suffixes” .
10.10.7.1 The condition flags
The APSR contains the following condition flags:
N Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR see “Program Status Register” on page 45.
A carry occurs:
• if the result of an addition is greater than or equal to 232
• if the result of a subtraction is positive or zero
• as the result of an inline barrel shifter operation in a move or logical instruction.
Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or
less than –231.
Most instructions update the status flags only if the S suffix is specified. See the instruction
descriptions for more information.
10.10.7.2 Condition code suffixes
The instructions that can be conditional have an optional condition code, shown in syntax
descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction
with a condition code is only executed if the condition code flags in the APSR meet the specified
condition. Table 10-16 shows the condition codes to use.
You can use conditional execution with the IT instruction to reduce the number of branch instruc-
tions in code.
Table 10-16 also shows the relationship between condition code suffixes and the N, Z, C, and V
flags.
Table 10-16. Condition code suffixes
Suffix Flags Meaning
EQ Z = 1 Equal
NE Z = 0 Not equal
CS or
HS C = 1 Higher or same, unsigned ≥
CC or
LO C = 0 Lower, unsigned <
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
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10.10.7.3 Absolute value
The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1).
MOVS R0, R1 ; R0 = R1, setting flags
IT MI ; IT instruction for the negative condition
RSBMI R0, R1, #0 ; If negative, R0 = -R1
10.10.7.4 Compare and update value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater
than R1 and R2 is greater than R3.
CMP R0, R1 ; Compare R0 and R1, setting flags
ITT GT ; IT instruction for the two GT conditions
CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags
MOVGT R4, R5 ; If still 'greater than', do R4 = R5
10.10.8 Instruction width selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding
depending on the operands and destination register specified. For some of these instructions,
you can force a specific instruction size by using an instruction width suffix. The .W suffix forces
a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction
encoding of the requested width, it generates an error.
In some cases it might be necessary to specify the .W suffix, for example if the operand is the
label of an instruction or literal data, as in the case of branch instructions. This is because the
assembler might not automatically generate the right size encoding.
10.10.8.1 Instruction width selection
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The exam-
ple below shows instructions with the instruction width suffix.
BCS.W label ; creates a 32-bit instruction even for a short branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N = V Greater than or equal, signed ≥
LT N != V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N != V Less than or equal, signed ≤
AL Can have any
value
Always. This is the default when no suffix is
specified.
Table 10-16. Condition code suffixes (Continued)
Suffix Flags Meaning
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10.11 Memory access instructions
Table 10-17 shows the memory access instructions:
Table 10-17. Memory access instructions
Mnemonic Brief description See
ADR Load PC-relative address “ADR” on page 88
CLREX Clear Exclusive “CLREX” on page 102
LDM{mode} Load Multiple registers “LDM and STM” on page 97
LDR{type} Load Register using immediate
offset
“LDR and STR, immediate offset” on
page 89
LDR{type} Load Register using register offset “LDR and STR, register offset” on page
92
LDR{type}T Load Register with unprivileged
access “LDR and STR, unprivileged” on page 94
LDR Load Register using PC-relative
address “LDR, PC-relative” on page 95
LDREX{type} Load Register Exclusive “LDREX and STREX” on page 100
POP Pop registers from stack “PUSH and POP” on page 99
PUSH Push registers onto stack “PUSH and POP” on page 99
STM{mode} Store Multiple registers “LDM and STM” on page 97
STR{type} Store Register using immediate
offset
“LDR and STR, immediate offset” on
page 89
STR{type} Store Register using register offset “LDR and STR, register offset” on page
92
STR{type}T Store Register with unprivileged
access “LDR and STR, unprivileged” on page 94
STREX{type} Store Register Exclusive “LDREX and STREX” on page 100
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10.11.1 ADR
Load PC-relative address.
10.11.1.1 Syntax
ADR{cond} Rd, label
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
label is a PC-relative expression. See “PC-relative expressions” on page 84.
10.11.1.2 Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to
the destination register.
ADR produces position-independent code, because the address is PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that
bit[0] of the address you generate is set to1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
You might have to use the .W suffix to get the maximum offset range or to generate addresses
that are not word-aligned. See “Instruction width selection” on page 86.
10.11.1.3 Restrictions
Rd must not be SP and must not be PC.
10.11.1.4 Condition flags
This instruction does not change the flags.
10.11.1.5 Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
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10.11.2 LDR and STR, immediate offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate
offset.
10.11.2.1 Syntax
op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional execution” on page 84.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to load or store for two-word operations.
10.11.2.2 Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
10.11.2.3 Offset addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The
result is used as the address for the memory access. The register Rn is unaltered. The assem-
bly language syntax for this mode is:
[Rn, #offset]
10.11.2.4 Pre-indexed addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The
result is used as the address for the memory access and written back into the register Rn. The
assembly language syntax for this mode is:
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[Rn, #offset]!
10.11.2.5 Post-indexed addressing
The address obtained from the register Rn is used as the address for the memory access. The
offset value is added to or subtracted from the address, and written back into the register Rn.
The assembly language syntax for this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can
either be signed or unsigned. See “Address alignment” on page 83.
Table 10-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
10.11.2.6 Restrictions
For load instructions:
•Rt can be SP or PC for word loads only
•Rt must be different from Rt2 for two-word loads
•Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
•Rt can be SP for word stores only
•Rt must not be PC
•Rn must not be PC
•Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
10.11.2.7 Condition flags
These instructions do not change the flags.
Table 10-18. Offset ranges
Instruction type Immediate offset Pre-indexed Post-indexed
Word, halfword, signed
halfword, byte, or signed
byte
−255 to 4095 −255 to 255 −255 to 255
Two words
multiple of 4 in the
range −1020 to
1020
multiple of 4 in the
range −1020 to
1020
multiple of 4 in the
range −1020 to
1020
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10.11.2.8 Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNER2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
;bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
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10.11.3 LDR and STR, register offset
Load and Store with register offset.
10.11.3.1 Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional execution” on page 84.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #nis an optional shift, with n in the range 0 to 3.
10.11.3.2 Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is
specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See “Address alignment” on page 83.
10.11.3.3 Restrictions
In these instructions:
•Rn must not be PC
•Rm must not be SP and must not be PC
•Rt can be SP only for word loads and word stores
•Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
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10.11.3.4 Condition flags
These instructions do not change the flags.
10.11.3.5 Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
;sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
;sum of R5 and two times R1, sign extended it
;to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
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10.11.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
10.11.4.1 Syntax
op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional execution” on page 84.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
10.11.4.2 Operation
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see “LDR and STR, immediate offset” on page 89. The difference is that
these instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as nor-
mal memory access instructions with immediate offset.
10.11.4.3 Restrictions
In these instructions:
•Rn must not be PC
•Rt must not be SP and must not be PC.
10.11.4.4 Condition flags
These instructions do not change the flags.
10.11.4.5 Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
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10.11.5 LDR, PC-relative
Load register from memory.
10.11.5.1 Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label ; Load two words
where:
type is one of:
B unsigned byte, zero extend to 32 bits.
SB signed byte, sign extend to 32 bits.
H unsigned halfword, zero extend to 32 bits.
SH signed halfword, sign extend to 32 bits.
- omit, for word.
cond is an optional condition code, see “Conditional execution” on page 84.
Rt is the register to load or store.
Rt2 is the second register to load or store.
label is a PC-relative expression. See “PC-relative expressions” on page 84.
10.11.5.2 Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is
specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See “Address alignment” on page 83.
label must be within a limited range of the current instruction. Table 10-19 shows the possible
offsets between label and the PC.
You might have to use the .W suffix to get the maximum offset range. See “Instruction width
selection” on page 86.
10.11.5.3 Restrictions
In these instructions:
•Rt can be SP or PC only for word loads
•Rt2 must not be SP and must not be PC
•Rt must be different from Rt2.
When Rt is PC in a word load instruction:
Table 10-19. Offset ranges
Instruction type Offset range
Word, halfword, signed halfword, byte, signed
byte −4095 to 4095
Two words −1020 to 1020
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• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
10.11.5.4 Condition flags
These instructions do not change the flags.
10.11.5.5 Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable
LDRSB R7, localdata ; Load a byte value from an address labelled
;as localdata, sign extend it to a word
; value, and put it in R7
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10.11.6 LDM and STM
Load and Store Multiple registers.
10.11.6.1 Syntax
op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
LDM Load Multiple registers.
STM Store Multiple registers.
addr_mode is any one of the following:
IA Increment address After each access. This is the default.
DB Decrement address Before each access.
cond is an optional condition code, see “Conditional execution” on page 84.
Rn is the register on which the memory addresses are based.
! is an optional writeback suffix.
If ! is present the final address, that is loaded from or stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can
contain register ranges. It must be comma separated if it contains more than one register or reg-
ister range, see “Examples” on page 98.
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full
Descending stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending
stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto
Empty Ascending stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending
stacks
10.11.6.2 Operation
LDM instructions load the registers in reglist with word values from memory addresses based on
Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on
Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the
accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of reg-
isters in reglist. The accesses happens in order of increasing register numbers, with the lowest
numbered register using the lowest memory address and the highest number register using the
highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written
back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at
4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
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The accesses happen in order of decreasing register numbers, with the highest numbered regis-
ter using the highest memory address and the lowest number register using the lowest memory
address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” on page
99 for details.
10.11.6.3 Restrictions
In these instructions:
•Rn must not be PC
•reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
•reglist must not contain Rn if you specify the writeback suffix.
When PC is in reglist in an LDM instruction:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to
this halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
10.11.6.4 Condition flags
These instructions do not change the flags.
10.11.6.5 Examples
LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM
STMDB R1!,{R3-R6,R11,R12}
10.11.6.6 Incorrect examples
STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
LDM R2, {} ; There must be at least one register in the list
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10.11.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
10.11.7.1 Syntax
PUSH{cond} reglist
POP{cond} reglist
where:
cond is an optional condition code, see “Conditional execution” on page 84.
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges.
It must be comma separated if it contains more than one register or register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for
the access based on SP, and with the final address for the access written back to the SP. PUSH
and POP are the preferred mnemonics in these cases.
10.11.7.2 Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest
numbered register using the highest memory address and the lowest numbered register using
the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest num-
bered register using the lowest memory address and the highest numbered register using the
highest memory address.
See “LDM and STM” on page 97 for more information.
10.11.7.3 Restrictions
In these instructions:
•reglist must not contain SP
• for the PUSH instruction, reglist must not contain PC
• for the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to
this halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
10.11.7.4 Condition flags
These instructions do not change the flags.
10.11.7.5 Examples
PUSH {R0,R4-R7}
PUSH {R2,LR}
POP {R0,R10,PC}
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10.11.8 LDREX and STREX
Load and Store Register Exclusive.
10.11.8.1 Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register for the returned status.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
10.11.8.2 Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory
address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a
memory address. The address used in any Store-Exclusive instruction must be the same as the
address in the most recently executed Load-exclusive instruction. The value stored by the Store-
Exclusive instruction must also have the same data size as the value loaded by the preceding
Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see “Syn-
chronization primitives” on page 61
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does
not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction
writes 0 to the destination register, it is guaranteed that no other process in the system has
accessed the memory location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-
Exclusive and Store-Exclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
10.11.8.3 Restrictions
In these instructions:
• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
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10.11.8.4 Condition flags
These instructions do not change the flags.
10.11.8.5 Examples
MOV R1, #0x1 ; Initialize the ‘lock taken’ value
try
LDREX R0, [LockAddr] ; Load the lock value
CMP R0, #0 ; Is the lock free?
ITT EQ ; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr] ; Try and claim the lock
CMPEQ R0, #0 ; Did this succeed?
BNE try ; No – try again
.... ; Yes – we have the lock
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10.11.9 CLREX
Clear Exclusive.
10.11.9.1 Syntax
CLREX{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.11.9.2 Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination
register and fail to perform the store. It is useful in exception handler code to force the failure of
the store exclusive if the exception occurs between a load exclusive instruction and the match-
ing store exclusive instruction in a synchronization operation.
See “Synchronization primitives” on page 61 for more information.
10.11.9.3 Condition flags
These instructions do not change the flags.
10.11.9.4 Examples
CLREX
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10.12 General data processing instructions
Table 10-20 shows the data processing instructions:
Table 10-20. Data processing instructions
Mnemonic Brief description See
ADC Add with Carry “ADD, ADC, SUB, SBC, and RSB” on
page 105
ADD Add “ADD, ADC, SUB, SBC, and RSB” on
page 105
ADDW Add “ADD, ADC, SUB, SBC, and RSB” on
page 105
AND Logical AND “AND, ORR, EOR, BIC, and ORN” on
page 108
ASR Arithmetic Shift Right “ASR, LSL, LSR, ROR, and RRX” on page
110
BIC Bit Clear “AND, ORR, EOR, BIC, and ORN” on
page 108
CLZ Count leading zeros “CLZ” on page 112
CMN Compare Negative “CMP and CMN” on page 113
CMP Compare “CMP and CMN” on page 113
EOR Exclusive OR “AND, ORR, EOR, BIC, and ORN” on
page 108
LSL Logical Shift Left “ASR, LSL, LSR, ROR, and RRX” on page
110
LSR Logical Shift Right “ASR, LSL, LSR, ROR, and RRX” on page
110
MOV Move “MOV and MVN” on page 114
MOVT Move Top “MOVT” on page 116
MOVW Move 16-bit constant “MOV and MVN” on page 114
MVN Move NOT “MOV and MVN” on page 114
ORN Logical OR NOT “AND, ORR, EOR, BIC, and ORN” on
page 108
ORR Logical OR “AND, ORR, EOR, BIC, and ORN” on
page 108
RBIT Reverse Bits “REV, REV16, REVSH, and RBIT” on
page 117
REV Reverse byte order in a word “REV, REV16, REVSH, and RBIT” on
page 117
REV16 Reverse byte order in each halfword “REV, REV16, REVSH, and RBIT” on
page 117
REVSH Reverse byte order in bottom halfword and
sign extend
“REV, REV16, REVSH, and RBIT” on
page 117
ROR Rotate Right “ASR, LSL, LSR, ROR, and RRX” on page
110
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RRX Rotate Right with Extend “ASR, LSL, LSR, ROR, and RRX” on page
110
RSB Reverse Subtract “ADD, ADC, SUB, SBC, and RSB” on
page 105
SBC Subtract with Carry “ADD, ADC, SUB, SBC, and RSB” on
page 105
SUB Subtract “ADD, ADC, SUB, SBC, and RSB” on
page 105
SUBW Subtract “ADD, ADC, SUB, SBC, and RSB” on
page 105
TEQ Test Equivalence “TST and TEQ” on page 118
TST Test “TST and TEQ” on page 118
Table 10-20. Data processing instructions (Continued)
Mnemonic Brief description See
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10.12.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
10.12.1.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.
See “Flexible second operand” on page 80 for details of the options.
imm12 is any value in the range 0-4095.
10.12.1.2 Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is
clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see “Multiword arithmetic examples” on
page 107.
See also “ADR” on page 88.
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the
SUB syntax that uses the imm12 operand.
10.12.1.3 Restrictions
In these instructions:
•Operand2 must not be SP and must not be PC
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•Rd can be SP only in ADD and SUB, and only with the additional restrictions:
–Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
•Rn can be SP only in ADD and SUB
•Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
– you must not specify the S suffix
–Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and
SUB, and only with the additional restrictions:
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
–
– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
– If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler
automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
10.12.1.4 Condition flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
10.12.1.5 Examples
ADD R2, R1, R3
SUBS R8, R6, #240 ; Sets the flags on the result
RSB R4, R4, #1280; Subtracts contents of R4 from 1280
ADCHI R11, R0, R3 ; Only executed if C flag set and Z
; flag clear
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10.12.1.6 Multiword arithmetic examples
10.12.1.7 64-bit addition
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer con-
tained in R0 and R1, and place the result in R4 and R5.
ADDS R4, R0, R2 ; add the least significant words
ADCR5, R1, R3 ; add the most significant words with carry
10.12.1.8 96-bit subtraction
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit
integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9,
and R2.
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBCR2, R8, R11 ; subtract the most significant words with carry
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10.12.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
10.12.2.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
AND logical AND.
ORR logical OR, or bit set.
EOR logical Exclusive OR.
BIC logical AND NOT, or bit clear.
ORN logical OR NOT.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
cond is an optional condition code, see See “Conditional execution” on page 84..
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for
details of the options.
10.12.2.2 Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations
on the values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
10.12.2.3 Restrictions
Do not use SP and do not use PC.
10.12.2.4 Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see “Flexible second operand” on
page 80
• do not affect the V flag.
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10.12.2.5 Examples
AND R9, R2, #0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BICR0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
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10.12.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
10.12.3.1 Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
Rd is the destination register.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 1 to 31.
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
10.12.3.2 Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see “Shift Oper-
ations” on page 81.
10.12.3.3 Restrictions
Do not use SP and do not use PC.
10.12.3.4 Condition flags
If S is specified:
• these instructions update the N and Z flags according to the result
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• the C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift
Operations” on page 81.
10.12.3.5 Examples
ASR R7, R8, #9 ; Arithmetic shift right by 9 bits
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend
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10.12.4 CLZ
Count Leading Zeros.
10.12.4.1 Syntax
CLZ{cond} Rd, Rm
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Rm is the operand register.
10.12.4.2 Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result
in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set.
10.12.4.3 Restrictions
Do not use SP and do not use PC.
10.12.4.4 Condition flags
This instruction does not change the flags.
10.12.4.5 Examples
CLZ R4,R9
CLZNER2,R3
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10.12.5 CMP and CMN
Compare and Compare Negative.
10.12.5.1 Syntax
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for
details of the options.
10.12.5.2 Operation
These instructions compare the value in a register with Operand2. They update the condition
flags on the result, but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as
a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an
ADDS instruction, except that the result is discarded.
10.12.5.3 Restrictions
In these instructions:
• do not use PC
•Operand2 must not be SP.
10.12.5.4 Condition flags
These instructions update the N, Z, C and V flags according to the result.
10.12.5.5 Examples
CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
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10.12.6 MOV and MVN
Move and Move NOT.
10.12.6.1 Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for
details of the options.
imm16 is any value in the range 0-65535.
10.12.6.2 Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred
syntax is the corresponding shift instruction:
• ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
• LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n!= 0
• LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
• ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
• RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift
instructions:
• MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX” on page 110.
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on
the value, and places the result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16
operand.
10.12.6.3 Restrictions
You can use SP and PC only in the MOV instruction, with the following restrictions:
• the second operand must be a register without shift
• you must not specify the S suffix.
When Rd is PC in a MOV instruction:
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• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of
a BX or BLX instruction to branch for software portability to the ARM instruction set.
10.12.6.4 Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see “Flexible second operand” on
page 80
• do not affect the V flag.
10.12.6.5 Example
MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10, flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
;to the R2 and update flags
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10.12.7 MOVT
Move Top.
10.12.7.1 Syntax
MOVT{cond} Rd, #imm16
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
imm16 is a 16-bit immediate constant.
10.12.7.2 Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination
register. The write does not affect Rd[15:0].
The MOV, MOVT instruction pair enables you to generate any 32-bit constant.
10.12.7.3 Restrictions
Rd must not be SP and must not be PC.
10.12.7.4 Condition flags
This instruction does not change the flags.
10.12.7.5 Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged
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10.12.8 REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
10.12.8.1 Syntax
op{cond} Rd, Rn
where:
op is any of:
REV
Reverse byte order in a word.
REV16
Reverse byte order in each halfword independently.
REVSH
Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT
Reverse the bit order in a 32-bit word.
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Rn is the register holding the operand.
10.12.8.2 Operation
Use these instructions to change endianness of data:
REV
converts 32-bit big-endian data into little-endian data or 32-bit little-endian data
into big-endian data.
REV16
converts 16-bit big-endian data into little-endian data or 16-bit little-endian data
into big-endian data.
REVSH
converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
10.12.8.3 Restrictions
Do not use SP and do not use PC
.
10.12.8.4 Condition flags
These instructions do not change the flags.
10.12.8.5 Examples
REV R3, R7 ; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5 ; Reverse Signed Halfword
REVHS R3, R7 ; Reverse with Higher or Same condition
RBIT R7, R8; Reverse bit order of value in R8 and write the result to R7
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10.12.9 TST and TEQ
Test bits and Test Equivalence.
10.12.9.1 Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible second operand” on page 80 for
details of the options.
10.12.9.2 Operation
These instructions test the value in a register against Operand2. They update the condition flags
based on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has
that bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value
of Operand2. This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical
Exclusive OR of the sign bits of the two operands.
10.12.9.3 Restrictions
Do not use SP and do not use PC
.
10.12.9.4 Condition flags
These instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see “Flexible second operand” on
page 80
• do not affect the V flag.
10.12.9.5 Examples
TST R0, #0x3F8; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded
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10.13 Multiply and divide instructions
Table 10-21 shows the multiply and divide instructions:
Table 10-21. Multiply and divide instructions
Mnemonic Brief description See
MLA Multiply with Accumulate, 32-bit result “MUL, MLA, and MLS” on page 120
MLS Multiply and Subtract, 32-bit result “MUL, MLA, and MLS” on page 120
MUL Multiply, 32-bit result “MUL, MLA, and MLS” on page 120
SDIV Signed Divide “SDIV and UDIV” on page 122
SMLAL Signed Multiply with Accumulate
(32x32+64), 64-bit result
“UMULL, UMLAL, SMULL, and SMLAL” on
page 121
SMULL Signed Multiply (32x32), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on
page 121
UDIV Unsigned Divide “SDIV and UDIV” on page 122
UMLAL Unsigned Multiply with Accumulate
(32x32+64), 64-bit result
“UMULL, UMLAL, SMULL, and SMLAL” on
page 121
UMULL Unsigned Multiply (32x32), 64-bit
result
“UMULL, UMLAL, SMULL, and SMLAL” on
page 121
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10.13.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro-
ducing a 32-bit result.
10.13.1.1 Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see “Conditional execution” on page 84.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see “Conditional execution” on page 84.
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
10.13.1.2 Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32
bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places
the least significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value
from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
10.13.1.3 Restrictions
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the MUL instruction:
•Rd, Rn, and Rm must all be in the range R0 to R7
•Rd must be the same as Rm
• you must not use the cond suffix.
10.13.1.4 Condition flags
If S is specified, the MUL instruction:
• updates the N and Z flags according to the result
• does not affect the C and V flags.
10.13.1.5 Examples
MUL R10, R2, R5 ; Multiply, R10 = R2 x R5
MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2
MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2
MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6)
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10.13.2 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro-
ducing a 64-bit result.
10.13.2.1 Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional execution” on page 84.
RdHi, RdLo are the destination registers.
For UMLAL and SMLAL they also hold the accumulating value.
Rn, Rm are registers holding the operands.
10.13.2.2 Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most signifi-
cant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo,
and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
10.13.2.3 Restrictions
In these instructions:
• do not use SP and do not use PC
•RdHi and RdLo must be different registers.
10.13.2.4 Condition flags
These instructions do not affect the condition code flags.
10.13.2.5 Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
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10.13.3 SDIV and UDIV
Signed Divide and Unsigned Divide.
10.13.3.1 Syntax
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the value to be divided.
Rm is a register holding the divisor.
10.13.3.2 Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded
towards zero.
10.13.3.3 Restrictions
Do not use SP and do not use PC
.
10.13.3.4 Condition flags
These instructions do not change the flags.
10.13.3.5 Examples
SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1
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10.14 Saturating instructions
This section describes the saturating instructions, SSAT and USAT.
10.14.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
10.14.1.1 Syntax
op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
n specifies the bit position to saturate to:
n ranges from 1 to 32 for SSAT
n ranges from 0 to 31 for USAT.
Rm is the register containing the value to saturate.
shift #s is an optional shift applied to Rm before saturating. It must be one of the following:
ASR #s where s is in the range 1 to 31
LSL #s where s is in the range 0 to 31.
10.14.1.2 Operation
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range −2n–
1≤x≤2n–1−1.
The USAT instruction applies the specified shift, then saturates to the unsigned range
0≤x≤2n−1.
For signed n-bit saturation using SSAT, this means that:
• if the value to be saturated is less than −2n−1, the result returned is −2n-1
• if the value to be saturated is greater than 2n−1−1, the result returned is 2n-1−1
• otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation using USAT, this means that:
• if the value to be saturated is less than 0, the result returned is 0
• if the value to be saturated is greater than 2n−1, the result returned is 2n−1
• otherwise, the result returned is the same as the value to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If satura-
tion occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag
unchanged. To clear the Q flag to 0, you must use the MSR instruction, see “MSR” on page 144.
To read the state of the Q flag, use the MRS instruction, see “MRS” on page 143.
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10.14.1.3 Restrictions
Do not use SP and do not use PC
.
10.14.1.4 Condition flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
10.14.1.5 Examples
SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
;saturate it as a signed 16-bit value and
; write it back to R7
USATNER0, #7, R5 ; Conditionally saturate value in R5 as an
;unsigned 7 bit value and write it to R0
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10.15 Bitfield instructions
Table 10-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields:
Table 10-22. Packing and unpacking instructions
Mnemonic Brief description See
BFC Bit Field Clear “BFC and BFI” on page 126
BFI Bit Field Insert “BFC and BFI” on page 126
SBFX Signed Bit Field Extract “SBFX and UBFX” on page 127
SXTB Sign extend a byte “SXT and UXT” on page 128
SXTH Sign extend a halfword “SXT and UXT” on page 128
UBFX Unsigned Bit Field Extract “SBFX and UBFX” on page 127
UXTB Zero extend a byte “SXT and UXT” on page 128
UXTH Zero extend a halfword “SXT and UXT” on page 128
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10.15.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
10.15.1.1 Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield.
lsb must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32−lsb.
10.15.1.2 Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb.
Other bits in Rd are unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at
the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
10.15.1.3 Restrictions
Do not use SP and do not use PC.
10.15.1.4 Condition flags
These instructions do not affect the flags.
10.15.1.5 Examples
BFCR4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2
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10.15.2 SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
10.15.2.1 Syntax
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield.
lsb must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32−lsb.
10.15.2.2 Operation
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the
destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the
destination register.
10.15.2.3 Restrictions
Do not use SP and do not use PC
.
10.15.2.4 Condition flags
These instructions do not affect the flags.
10.15.2.5 Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18(10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8
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10.15.3 SXT and UXT
Sign extend and Zero extend.
10.15.3.1 Syntax
SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
Rm is the register holding the value to extend.
ROR #nis one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
10.15.3.2 Operation
These instructions do the following:
• Rotate the value from
Rm
right by 0, 8, 16 or 24 bits.
• Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
10.15.3.3 Restrictions
Do not use SP and do not use PC.
10.15.3.4 Condition flags
These instructions do not affect the flags.
10.15.3.5 Examples
SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower
; halfword of the result and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero
;extend it, and write the result to R3
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10.16 Branch and control instructions
Table 10-23 shows the branch and control instructions:
Table 10-23. Branch and control instructions
Mnemonic Brief description See
BBranch “B, BL, BX, and BLX” on page 130
BL Branch with Link “B, BL, BX, and BLX” on page 130
BLX Branch indirect with Link “B, BL, BX, and BLX” on page 130
BX Branch indirect “B, BL, BX, and BLX” on page 130
CBNZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 132
CBZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 132
IT If-Then “IT” on page 133
TBB Table Branch Byte “TBB and TBH” on page 135
TBH Table Branch Halfword “TBB and TBH” on page 135
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10.16.1 B, BL, BX, and BLX
Branch instructions.
10.16.1.1 Syntax
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (immediate).
BL is branch with link (immediate).
BX is branch indirect (register).
BLX is branch indirect with link (register).
cond is an optional condition code, see “Conditional execution” on page 84.
label is a PC-relative expression. See “PC-relative expressions” on page 84.
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must
be 1, but the address to branch to is created by changing bit[0] to 0.
10.16.1.2 Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
• The BL and BLX instructions write the address of the next instruction to LR (the link register,
R14).
• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All
other branch instructions must be conditional inside an IT block, and must be unconditional out-
side the IT block, see “IT” on page 133.
Table 10-24 shows the ranges for the various branch instructions.
You might have to use the .W suffix to get the maximum branch range. See “Instruction width
selection” on page 86.
10.16.1.3 Restrictions
The restrictions are:
Table 10-24. Branch ranges
Instruction Branch range
B label −16 MB to +16 MB
B
cond
label
(outside IT block) −1 MB to +1 MB
B
cond
label
(inside IT block) −16 MB to +16 MB
BL{cond} label −16 MB to +16 MB
BX{cond} Rm Any value in register
BLX{cond} Rm Any value in register
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• do not use PC in the BLX instruction
• for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target
address created by changing bit[0] to 0
• when any of these instructions is inside an IT block, it must be the last instruction of the IT
block.
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it
has a longer branch range when it is inside an IT block.
10.16.1.4 Condition flags
These instructions do not change the flags.
10.16.1.5 Examples
B loopA ; Branch to loopA
BLEng ; Conditionally branch to label ng
B.W target; Branch to target within 16MB range
BEQtarget; Conditionally branch to target
BEQ.W target; Conditionally branch to target within 1MB
BL funC; Branch with link (Call) to function funC, return address
;stored in LR
BX LR ; Return from function call
BXNER0 ; Conditionally branch to address stored in R0
BLX R0 ; Branch with link and exchange (Call) to a address stored
; in R0
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10.16.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
10.16.2.1 Syntax
CBZ Rn, label
CBNZ Rn, label
where:
Rn is the register holding the operand.
label is the branch destination.
10.16.2.2 Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the
number of instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BEQ label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BNElabel
10.16.2.3 Restrictions
The restrictions are:
•Rn must be in the range of R0 to R7
• the branch destination must be within 4 to 130 bytes after the instruction
• these instructions must not be used inside an IT block.
10.16.2.4 Condition flags
These instructions do not change the flags.
10.16.2.5 Examples
CBZ R5, target; Forward branch if R5 is zero
CBNZ R0, target; Forward branch if R0 is not zero
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10.16.3 IT
If-Then condition instruction.
10.16.3.1 Syntax
IT{x{y{z}}} cond
where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruction in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be either:
T Then. Applies the condition cond to the instruction.
E Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of
the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omit-
ted but not E.
10.16.3.2 Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all
the same, or some of them can be the logical inverse of the others. The conditional instructions
following the IT instruction form the IT block.
The instructions in the IT block, including any branches, must specify the condition in the {cond}
part of their syntax.
Your assembler might be able to generate the required IT instructions for conditional instructions
automatically, so that you do not need to write them yourself. See your assembler documenta-
tion for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an
IT block. Such an exception results in entry to the appropriate exception handler, with suitable
return information in LR and stacked PSR.
Instructions designed for use for exception returns can be used as normal to return from the
exception, and execution of the IT block resumes correctly. This is the only way that a PC-modi-
fying instruction is permitted to branch to an instruction in an IT block.
10.16.3.3 Restrictions
The following instructions are not permitted in an IT block:
•IT
• CBZ and CBNZ
• CPSID and CPSIE.
Other restrictions when using an IT block are:
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• a branch or any instruction that modifies the PC must either be outside an IT block or must be
the last instruction inside the IT block. These are:
– ADD PC, PC, Rm
– MOV PC, Rm
– B, BL, BX, BLX
– any LDM, LDR, or POP instruction that writes to the PC
– TBB and TBH
• do not branch to any instruction inside an IT block, except when returning from an exception
handler
• all conditional instructions except Bcond must be inside an IT block. Bcond can be either
outside or inside an IT block but has a larger branch range if it is inside one
• each instruction inside the IT block must specify a condition code suffix that is either the
same or logical inverse as for the other instructions in the block.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the
use of assembler directives within them.
10.16.3.4 Condition flags
This instruction does not change the flags.
10.16.3.5 Example
ITTENE; Next 3 instructions are conditional
ANDNER0, R0, R1 ; ANDNE does not update condition flags
ADDSNE R2, R2, #1 ; ADDSNE updates condition flags
MOVEQ R2, R3 ; Conditional move
CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
ITEGT ; Next 2 instructions are conditional
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLER1, R0, #48; Convert 0x0 -> '0'
IT GT ; IT block with only one conditional instruction
ADDGT R1, R1, #1 ; Increment R1 conditionally
ITTEE EQ;Next 4 instructions are conditional
MOVEQ R0, R1 ; Conditional move
ADDEQ R2, R2, #10 ; Conditional add
ANDNER3, R3, #1 ; Conditional AND
BNE.W dloop ; Branch instruction can only be used in the last
; instruction of an IT block
IT NE;Next instruction is conditional
ADD R0, R0, R1 ; Syntax error: no condition code used in IT block
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10.16.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
10.16.4.1 Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths. If Rn is PC,
then the address of the table is the address of the byte immediately following the TBB or TBH
instruction.
Rm is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
10.16.4.2 Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index
into the table. For TBB the branch offset is twice the unsigned value of the byte returned from
the table. and for TBH the branch offset is twice the unsigned value of the halfword returned
from the table. The branch occurs to the address at that offset from the address of the byte
immediately after the TBB or TBH instruction.
10.16.4.3 Restrictions
The restrictions are:
•Rn must not be SP
•Rm must not be SP and must not be PC
• when any of these instructions is used inside an IT block, it must be the last instruction of the
IT block.
10.16.4.4 Condition flags
These instructions do not change the flags.
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10.16.4.5 Examples
ADR.W R0, BranchTable_Byte
TBB [R0, R1] ; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB0 ; Case1 offset calculation
DCB((Case2-Case1)/2) ; Case2 offset calculation
DCB((Case3-Case1)/2) ; Case3 offset calculation
TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI((CaseA - BranchTable_H)/2) ; CaseA offset calculation
DCI((CaseB - BranchTable_H)/2) ; CaseB offset calculation
DCI((CaseC - BranchTable_H)/2) ; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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10.17 Miscellaneous instructions
Table 10-25 shows the remaining Cortex-M3 instructions:
Table 10-25. Miscellaneous instructions
Mnemonic Brief description See
BKPT Breakpoint “BKPT” on page 138
CPSID Change Processor State, Disable
Interrupts “CPS” on page 139
CPSIE Change Processor State, Enable
Interrupts “CPS” on page 139
DMB Data Memory Barrier “DMB” on page 140
DSB Data Synchronization Barrier “DSB” on page 141
ISB Instruction Synchronization Barrier “ISB” on page 142
MRS Move from special register to register “MRS” on page 143
MSR Move from register to special register “MSR” on page 144
NOP No Operation “NOP” on page 145
SEV Send Event “SEV” on page 146
SVC Supervisor Call “SVC” on page 147
WFE Wait For Event “WFE” on page 148
WFI Wait For Interrupt “WFI” on page 149
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10.17.1 BKPT
Breakpoint.
10.17.1.1 Syntax
BKPT #imm
where:
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
10.17.1.2 Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to
investigate system state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional informa-
tion about the breakpoint.
The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaf-
fected by the condition specified by the IT instruction.
10.17.1.3 Condition flags
This instruction does not change the flags.
10.17.1.4 Examples
BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can
;extract the immediate value by locating it using the PC)
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10.17.2 CPS
Change Processor State.
10.17.2.1 Syntax
CPSeffect iflags
where:
effect is one of:
IE Clears the special purpose register.
ID Sets the special purpose register.
iflags is a sequence of one or more flags:
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
10.17.2.2 Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception mask
registers” on page 48 for more information about these registers.
10.17.2.3 Restrictions
The restrictions are:
• use CPS only from privileged software, it has no effect if used in unprivileged software
• CPS cannot be conditional and so must not be used inside an IT block.
10.17.2.4 Condition flags
This instruction does not change the condition flags.
10.17.2.5 Examples
CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f; Enable interrupts and fault handlers (clear FAULTMASK)
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10.17.3 DMB
Data Memory Barrier.
10.17.3.1 Syntax
DMB{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.17.3.2 Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in
program order, before the DMB instruction are completed before any explicit memory accesses
that appear, in program order, after the DMB instruction. DMB does not affect the ordering or
execution of instructions that do not access memory.
10.17.3.3 Condition flags
This instruction does not change the flags.
10.17.3.4 Examples
DMB ; Data Memory Barrier
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10.17.4 DSB
Data Synchronization Barrier.
10.17.4.1 Syntax
DSB{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.17.4.2 Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the
DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction
completes when all explicit memory accesses before it complete.
10.17.4.3 Condition flags
This instruction does not change the flags.
10.17.4.4 Examples
DSB ; Data Synchronisation Barrier
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10.17.5 ISB
Instruction Synchronization Barrier.
10.17.5.1 Syntax
ISB{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.17.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that
all instructions following the ISB are fetched from memory again, after the ISB instruction has
been completed.
10.17.5.3 Condition flags
This instruction does not change the flags.
10.17.5.4 Examples
ISB ; Instruction Synchronisation Barrier
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10.17.6 MRS
Move the contents of a special register to a general-purpose register.
10.17.6.1 Syntax
MRS{cond} Rd, spec_reg
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rd is the destination register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
10.17.6.2 Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR,
for example to clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be
saved, including relevant PSR contents. Similarly, the state of the process being swapped in
must also be restored. These operations use MRS in the state-saving instruction sequence and
MSR in the state-restoring instruction sequence.
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR” on page 144.
10.17.6.3 Restrictions
Rd must not be SP and must not be PC.
10.17.6.4 Condition flags
This instruction does not change the flags.
10.17.6.5 Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
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10.17.7 MSR
Move the contents of a general-purpose register into the specified special register.
10.17.7.1 Syntax
MSR{cond} spec_reg, Rn
where:
cond is an optional condition code, see “Conditional execution” on page 84.
Rn is the source register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
10.17.7.2 Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can
only access the APSR, see “Application Program Status Register” on page 46. Privileged soft-
ware can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
•Rn is non-zero and the current BASEPRI value is 0
•Rn is non-zero and less than the current BASEPRI value.
See “MRS” on page 143.
10.17.7.3 Restrictions
Rn must not be SP and must not be PC.
10.17.7.4 Condition flags
This instruction updates the flags explicitly based on the value in Rn.
10.17.7.5 Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
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10.17.8 NOP
No Operation.
10.17.8.1 Syntax
NOP{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.17.8.2 Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might
remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
10.17.8.3 Condition flags
This instruction does not change the flags.
10.17.8.4 Examples
NOP ; No operation
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10.17.9 SEV
Send Event.
10.17.9.1 Syntax
SEV{cond}
where:
cond is an optional condition code, see “Conditional execution” on page 84.
10.17.9.2 Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multipro-
cessor system. It also sets the local event register to 1, see “Power management” on page 73.
10.17.9.3 Condition flags
This instruction does not change the flags.
10.17.9.4 Examples
SEV ; Send Event