© 1997
MOS INTEGRATED CIRCUIT
MC-458CB646
8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
DATA SHEET
The mark •
••
• shows major revised points.
Document No. M13049EJ3V0DS00 (3rd edition)
Date Published April 1998 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice.
Description
The MC-458CB646 is a 8,388,608 words by 64 bits synchronous dynamic RAM module on which 8 pieces of 64 M
SDRAM:
µ
PD4564841 (Revision E) are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and clock access time
Famil y /CAS l at ency Clock f requency Clock ac cess ti me Power consumpt i on (MAX.)
(MAX.) (MAX.) Active Standby
MC-458CB646-A80 CL = 3 125 MHz 6 ns 3,888 mW 14.4 mW
CL = 2 100 MHz 6 ns 3,744 mW (CMOS level input )
MC-458CB646-A10 CL = 3 100 MHz 6 ns 3,888 mW
CL = 2 77 MHz 7 ns 3,744 mW
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length: 1, 2, 4, 8 and full page
• Programmable wrap sequence (sequential / interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
★
2
MC-458CB646
Ordering Information
Part number Clock frequency
MHz (MAX.)
Package Mounted devices
MC-458CB646F-A80 125 MHz 168-pin Dual In-li ne Memory Module
(Socket Type)
8 pieces of
µ
PD4564841G5 (Revision E)
(400 mil TSOP (II))
MC-458CB646F-A10 100 MHz Edge connector : Gold plated
34.93 m m (1.375 inch) hei ght
[Double side]
3
MC-458CB646
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
[MC-458CB646F]
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
NC
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
NC
/RAS
V
SS
A1
A3
A5
A7
A9
BA0
(A13)
A11
Vcc
CLK1
NC
V
SS
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
V
SS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
(A12)
Vcc
Vcc
CLK0
V
SS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
SDA
SCL
Vcc
DQ46
DQ47
NC
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0 (A13), BA1 (A12) : SDRAM Bank Select
DQ0 - DQ63 : Data Inputs/Outputs
CLK0 - CLK3 : Clock Input
CKE0 : Clock Enable Input
/CS0, /CS2 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
VCC : Power Supply
VSS : Ground
WP : Write Protect Note
NC : No Connection
Note WP is not used yet. It is connected to
ground.
/xxx indicates active low signal.
4
MC-458CB646
Block Diagram
DQMB0
/CS0
/WE
DQMB2
/CS2
DQM
D0
/CS /WE
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
D1
DQM /CS /WE
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
D6
DQM /CS /WE
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
D7
DQM /CS /WE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
D3
DQM /CS /WE
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 4
DQM
D2
/CS /WE
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQMB1
DQMB7
DQMB6
DQMB3
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
D4
DQM /CS /WE
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
D5
DQM /CS /WE
DQ 5
DQ 7
DQ 6
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQMB4
DQMB5
A0 - A11 A0 - A11 : D0 - D7
BA0 A13 : D0 - D7
BA1 A12 : D0 - D7
SERIAL PD
SCL SDA
A0 A1 A2
SA0 SA1 SA2
WP
47
kΩ
/RAS /RAS : D0 - D7
/CAS /CAS : D0 - D7
CKE0 CKE : D0 - D7
V
CC
D0 - D7
D0 - D7
SS
VC
CLK1, CLK3
10
pF
CLK2 CLK : D2, D3, D6, D7
3.3
pF
CLK0 CLK : D0, D1, D4, D5
3.3
pF
Remarks 1. The value of all resistors is 10 Ω except WP.
2. WP is not used yet. It is connected to ground.
3. D0 - D7:
µ
PD4564841 (Rev.E) (2M words × 8 bits × 4 banks)
5
MC-458CB646
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100
µ
s and then, execute power on sequence and auto refresh before proper device
operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin rel ative to GND VCC –0.5 to +4.6 V
Voltage on input pin relative t o GND VT–0.5 to +4. 6 V
Short ci rcuit output current IO50 mA
Power dissipat i on PD8W
Operating ambient temperature TA0 to +70 °C
Storage temperature Tstg –55 t o +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply volt age VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL −0.3 +0.8 V
Operating ambient temperature TA070
°C
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Symbol Test conditi on MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11, BA0(A13), BA1(A12), /RAS,
/CAS, /WE 38 62 pF
CI2 CLK0, CLK2 24 40
CI3 CKE0 32 52
CI4 /CS0, /CS2 17 29
CI5 DQMB0 - DQMB7 7 13
Data input/ output capaci t ance CI/O DQ0 - DQ63 7 13 pF
★
6
MC-458CB646
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test c ondi t i on Grade MIN. MAX. Unit Notes
Operating current I CC1 B urst length = 1/CAS latency = 2 -A80 640 mA 1
tRC ≥ tRC(MIN.), IO = 0 mA -A10 560
/CAS latency = 3 -A80 680
-A10 600
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns 8 mA
power down mode ICC2PS CKE ≤ VIL(MAX.), tCK = ∞4
Precharge standby c urrent in
non power down mode ICC2NCKE
≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input si gnal s are changed one time during 30 ns. 160 mA
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞
Input si gnal s are stable. 48
Act i ve standby current i n ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns 40 mA
power down mode ICC3PS CKE ≤ VIL(MAX.), tCK = ∞32
Act i ve standby current i n ICC3NCKE
≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.), 200 mA
non power down mode Input si gnal s are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞
Input si gnal s are stable. 80
Operating current I CC4 tCK ≥ tCK(MIN.) /CAS latency = 2 -A80 840 mA 2
(Burst mode) IO = 0 mA -A10 640
/CAS latency = 3 -A80 1,000
-A10 840
Refresh current ICC5 tRC ≥ tRC(MIN.) /CAS latency = 2 -A80 1,040 mA 3
-A10 1,040
/CAS latency = 3 -A80 1,080
-A10 1,080
Self ref resh current ICC6 CKE ≤ 0.2 V8mA
Input leak age current II(L) VI = 0 to 3.6 V, All ot her pi ns not under test = 0 V – 8+
8
µ
A
Output leak age current IO(L) DOUT is disabled, V O = 0 to 3.6 V–
1.5 + 1.5
µ
A
High level out put voltage VOH IO = – 4.0 mA 2.4 V
Low level output voltage VOL IO = + 4.0 mA 0.4 V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2.I
CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
★
7
MC-458CB646
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
•AC measurements assume tT = 1 ns.
•Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL.
•If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.).
•An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
2.0 V
1.4 V
0.8 V
Input
t
SETUP
t
HOLD
Output
t
AC
t
OH
8
MC-458CB646
Synchronous Characteristics
Parameter Symbol -A80 -A10 Unit Note
MIN. MAX. MIN. MAX.
Clock cycle time /CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) ns
/CAS latency = 2 tCK2 10 (100 MHz) 13 (77 MHz) ns
Access time from CLK /CAS latency = 3 tAC3 66ns1
/CAS latency = 2 tAC2 67ns1
CLK high level width tCH 33ns
CLK low level width tCL 33ns
Data-out hold t i me tOH 33ns1
Data-out low-im pedance tim e tLZ 00ns
Data-out high-i mpedance time /CAS latenc y = 3 tHZ3 3636ns
/CAS latency = 2 tHZ2 3637ns
Data-in set up time tDS 22ns
Data-in hold t i me tDH 11ns
Address setup time tAS 22ns
Address hol d time tAH 11ns
CKE setup time tCKS 22ns
CKE hold t i me tCKH 11ns
CKE setup time (Power down exit) tCKSP 22ns
Command (/CS0, / CS2, /RAS , /CAS, /WE,
DQMB0 - DQMB7) setup t i me
tCMS 22ns
Command (/CS0, / CS2, /RAS , /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH 11ns
Note 1. Output load
Output Z = 50
Ω
1.4 V
50 pF
50
Ω
Remark These specifications are applied to the monolithic device.
★
★
9
MC-458CB646
Asynchronous Characteristics
Parameter Symbol -A80 -A10 Unit Note
MIN. MAX. MIN. MAX.
REF to REF/ A CT c ommand period tRC 70 70 ns
ACT to PRE c ommand period tRAS 48 120,000 50 120,000 ns
PRE to ACT c ommand period tRP 20 20 ns
Delay time ACT to READ/WRITE command tRCD 20 20 ns
ACT(0) to ACT(1) c ommand peri od tRRD 16 20 ns
Data-in to P RE command period tDPL 810ns
Data-in to A CT(RE F) command period /CA S latency = 3 tDAL3 1CLK+20 1CLK+20 ns
(Auto precharge) /CAS l at ency = 2 tDAL2 1CLK+20 1CLK+20 ns
Mode register set cycle ti me tRSC 22CLK
Transiti on t i me tT0.5 30 1 30 ns
Refresh ti me tREF 64 64 ms
10
MC-458CB646
Serial PD (1/2)
Byte No . Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of byt es written into
serial PD memory 80H 1 0 0 0 0 0 0 0 128 bytes
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundam ental memory type 04H00000100SDRAM
3 Number of rows 0CH0000110012 rows
4 Number of colum ns 09H000010019 columns
5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank
6 Data width 40H0100000064 bits
7 Data width (cont i nued) 00H000000000
8 Volt age i nterface 01H00000001LVTTL
9 CL = 3 Cycle t i me (-A80) 80H 1 0 0 0 0 0 0 0 8 ns
(-A10) A0H 1 0 1 0 0 0 0 0 10 ns
10 CL = 3 Access time (-A80) 60H 0 1 1 0 0 0 0 0 6 ns
(-A10) 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 Non-parity
12 Refresh rate/type 80H10000000Normal
13 SDRAM width 08H00001000
×8
14 Error checking SDRA M width 00H00000000None
15 Minim um clock delay 01H000000011 clock
16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each S DRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency s upported 06H000001102, 3
19 /CS l atency supported 01H000000010
20 /WE l atency supporte d 01H000000010
21 SDRAM module attribut es 00H00000000
22 SDRAM devic e attributes : General 0EH00001110
23 CL = 2 Cycle t i me (-A80) A0H 1 0 1 0 0 0 0 0 10 ns
(-A10) D0H 1 1 0 1 0 0 0 0 13 ns
24 CL = 2 Access time (-A80) 60H 0 1 1 0 0 0 0 0 6 ns
(-A10) 70H 0 1 1 1 0 0 0 0 7 ns
25-26 00H 0 0 0 0 0 0 0 0
(-A80) 14H 0 0 0 1 0 1 0 0 20 ns27 tRP(MIN.)
(-A10) 14H 0 0 0 1 0 1 0 0 20 ns
28 tRRD(MIN.) (-A80) 10H 0 0 0 1 0 0 0 0 16 ns
(-A10) 14H 0 0 0 1 0 1 0 0 20 ns
(-A80) 14H 0 0 0 1 0 1 0 0 20 ns29 tRCD(MIN.)
(-A10) 14H 0 0 0 1 0 1 0 0 20 ns
30 tRAS(MIN.) (-A80) 30H 0 0 1 1 0 0 0 0 48 ns
(-A10) 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank densi ty 10H 0 0 0 1 0 0 0 0 64M bytes
11
MC-458CB646
(2/2)
Byte No . Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Comm and and address signal i nput
setup ti me 20H001000002 ns
33 Comm and and address signal i nput
hold time
10H000100001 ns
34 Data signal input setup time 20H 0 0 1 0 0 0 0 0 2 ns
35 Data signal input hold time 10H 0 0 0 1 0 0 0 0 1 ns
36-61 00H 0 0 0 0 0 0 0 0
62 SPD revision 12H 0 0 0 1 0 0 1 0 1.2
63 Checksum for bytes 0 - 62 (-A80) DFH 1 1 0 1 1 1 1 1
(-A10)45H01000101
64-71 Manufacture’ s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel s pecification frequency 64H 0 1 1 0 0 1 0 0 100 MHz
127 Intel s pecification /CAS (-A 80) A7H 1 0 1 0 0 1 1 1
latency support (-A 10) A5H 1 0 1 0 0 1 0 1
Timing Chart
Please refer to NEC Synchronous DRAM Data sheet.
12
MC-458CB646
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
N
M
T
U
W
G
V
X
P
D
Y
R
S
L
Q
Z
J
H
C
B
K
GI BDE
A
(OPTIONAL HOLES)
A
detail of part detail of part ITEM MILLIMETERS INCHES
U 4.0 MIN. 0.157 MIN.
S
T 1.27±0.1 0.05±0.004
A
B 11.43
133.35±0.13 5.250±0.006
0.450
C
D 6.35
36.83 1.450
0.250
E
G 6.35
54.61 2.150
0.250
H 1.27 (T.P.) 0.050 (T.P.)
I 8.89 0.350
J 24.495 0.964
K 42.18 1.661
L 17.78 0.700
M
N
R 4.0±0.1 0.157
Q
V 0.2±0.15 0.00787±0.0059
R2.0 R0.079
+0.005
–0.004
4.00 MAX. 0.158 MAX.
3.0
φφ
0.118
P1.0 0.039
Y 3.0 MIN. 0.118 MIN.
W
X 2.54 MIN.
1.0±0.05
0.100±0.004
Z 3.0 MIN. 0.118 MIN.
0.039+0.003
–0.002
34.93 1.375
B' C'
A'
A' 2.26 0.089
B' 9.528 0.375
C' 3.175 0.125
★
13
MC-458CB646
[MEMO]
14
MC-458CB646
[MEMO]
15
MC-458CB646
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the
device. Immediately after the power source is turned ON, the devices with
reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not
initialized until the reset signal is received. Reset operation must be
executed imme-diately after power-on for devices having reset function.
NOTES FOR CMOS DEVI CES
MC-458CB646
[MEMO]
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
