D a t a S h e et , R e v . 2 .0 , A p r . 20 0 5 FlexiSLIC Subscriber Line Interface Circuit PBL 38630/2, Version 2 Wireline Communications N e v e r s t o p t h i n k i n g . ABM(R), ACE(R), AOP(R), ARCOFI(R), ASM(R), ASP(R), DigiTape(R), DuSLIC(R), EPIC(R), ELIC(R), FALC(R), GEMINAX(R), IDEC(R), INCA(R), IOM(R), IPAT(R)-2, ISAC(R), ITAC(R), IWE(R), IWORX(R), MUSAC(R), MuSLIC(R), OCTAT(R), OptiPort(R), POTSWIRE(R), QUAT(R), QuadFALC(R), SCOUT(R), SICAT(R), SICOFI(R), SIDEC(R), SLICOFI(R), SMINT(R), SOCRATES(R), VINETIC(R), 10BaseV(R), 10BaseVX(R) are registered trademarks of Infineon Technologies AG. 10BaseSTM, EasyPortTM, FlexiSLICTM, VDSLiteTM are trademarks of Infineon Technologies AG. Microsoft(R) is a registered trademark of Microsoft Corporation, Linux(R) of Linus Torvalds, Visio(R) of Visio Corporation, and FrameMaker(R) of Adobe Systems Incorporated. The information in this document is subject to change without notice. Edition 2005-04-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain FlexiSLIC Revision History: 2005-04-14 Previous Version: DS1 Rev. 2.0 Page Subjects (major changes since last revision) all Package P-DSO-24-1 changed to P-/PG-DSO-24-8 all Package type abbreviation SOIC changed to PDSO all Package P-LCC-28-2 changed to P-/PG-LCC-28-3 all Package P-SSOP-24-1 changed to P-/PG-SSOP-24-1 Page 17 Table 5: Thermal resistance for 24-pin PDSO changed from 80.2 C/W to 50.3 C/W Page 27 Figure 8: SLIC/codec circuitry changed Page 28 Table 6: values of RR, RT, RRX, RTX, RB changed, RFB removed Page 33 Figure 10 changed FlexiSLIC PBL 38630/2 Table of Contents Page 1 1.1 1.2 1.3 1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Characterictics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 4.1 4.2 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Design Supporting Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Four-Wire to Two-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Four-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longitudinal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitors CTC and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC - DC Separation Capacitor, CHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-pass Transmit Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitor CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 31 32 32 32 34 34 34 34 34 6 6.1 6.2 6.3 Battery Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CODEC Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Overhead Voltage (POV) . . . . . . . . . . . . . . . . . . . . . . . . . Analog Temperature Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 39 40 7 7.1 7.2 Loop Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Loop Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Ring Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 9.1 9.2 9.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Circuit (C2, C1 = 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing (C2, C1 = 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10.1 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Overvoltage Protection - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Data Sheet 4 42 42 42 42 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Table of Contents Page 10.2 Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12 Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13 13.1 13.2 13.3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-pin SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-pin PDSO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 5 45 45 46 47 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Data Sheet Page Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view).. Overhead Level, VTRO, Two-Wire Port . . . . . . . . . . . . . . . . . . . . . . . . . Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance . . . . . Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE . . . . . Overhead Level, VTXO, Four-Wire Transmit Port . . . . . . . . . . . . . . . . . Frequency Response, Insertion Loss, Gain Tracking . . . . . . . . . . . . . Application Example of PBL 38630/2 with SICOFI(R)4 Codec . . . . . . . . Simplified AC Model of PBL 38630/2 . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Codec Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Overhead Voltage (POV). RL= 600 or Infinite . . . . . P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package) . . . . . . . . . P-/PG-DSO-24-8 (Plastic Dual Small Outline Package) . . . . . . . . . . . P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package) . . . . . . . . . . 6 10 11 24 25 25 25 26 27 30 33 37 38 40 45 46 47 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Data Sheet Page Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feeding Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Bias Current of RSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 14 15 16 17 28 28 29 35 36 37 Rev. 2.0, 2005-04-14 FlexiSLIC Subscriber Line Interface Circuit PBL 38630/2 Version 2 1 Overview 1.1 Features * * * * * * * * * * * * * * * * 24-pin SSOP package High and low battery with automatic switching 65 mW on-hook power dissipation in active state On-hook transmission Long loop battery feed tracks Vbat for maximum line voltage Selectable transmit gain (1x or 0.5 x) No power-up sequence 43 V open loop voltage @ -48 V battery feed Close tolerance current feeding Constant loop voltage for line leakage < 5 mA (RLeak ~ > 10 k @ -48 V) Full longitudinal current capability during on-hook state Longitudinal balance > 60 dB Analog overtemperature protection permits transmission while the protection circuits is active Integrated Ring Relay driver Programmable signal headroom -40 oC to +85 oC ambient temperature range 1.2 * * Typical Applications P-/PG-SSOP-24-1 P/PG-SSOP-24-1 P-SSOP-24-1 P-/PG-DSO-24-8 P-DSO-24-1, -3 P-/PG-LCC-28-3 P-LCC-28-2 P/PG-LCC-28-3 Basic functionality Central Office Line card Digital Loop Carriers (DLC) Type Package PBL 38630/2 SH P-/PG-SSOP-24-1 PBL 38630/2 SO P-/PG-DSO-24-8 PBL 38630/2 QN P-/PG-LCC-28-3 Data Sheet 8 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Overview 1.3 Description The PBL 38630/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in PBX, Terminal adapters and other telecommunications equipment. The PBL 38630/2 SLIC has been optimized for low total line interface cost and for a high degree of flexibility in different applications. The PBL 38630/2 SLIC emulates resistive loop feed, programmable between 2x50 and 2x900 , with short loop current limiting adjustable to maximum 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30 k. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current and ring-trip detection functions. The PBL 38630/2 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, for example SiCoFi PEB 2466. The programmable twowire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 38630/2 SLIC package options are 24-pin SSOP, 24-pin PDSO or 28-pin PLCC. Data Sheet 9 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Overview 1.4 Block Diagram DT DR RRLY VCC AGND Ring Trip Comparator Ring Relay Driver Ground Key Detector TIPX HP Two-wire Interface RINGX C1 C2 DET Line Feed Controller and Longitudinal Signal Suppression POV PSG PLC LP Off - Hook Detector PLD VF signal Transmission BGND Input Decoder and Control VBAT REF RSN VTX PTG VBAT2 bl_sch_30 Figure 1 Data Sheet Block Diagram 10 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Pin Configuration Pin Configuration RINGX 4 21 REF BGND 5 TIPX 6 24-pin PDSO and 24- pin SSOP VBAT 7 3 2 1 28 27 26 R SN 4 VT X PT G 22 RSN R RLY HP 3 HP 23 AGND RRLY 2 AGND 24 VTX PTG 1 NC 2 RINGX 5 25 NC 20 PLC BGND 6 24 REF 19 POV TIPX 7 18 PLD 23 PLC 28-pin PLCC VBAT 8 22 POV VBAT2 9 21 PLD VBAT2 8 17 VCC PSG 10 20 VCC PSG 9 16 DET NC 11 19 NC DET C1 13 NU C2 DR 12 NU 14 C2 DR DT 11 12 13 14 15 16 17 18 DT 15 C1 LP LP 10 pinout_30 Figure 2 Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view). Table 1 Pin Definition and Functions PDSO SSOP Pin No. PLCC Pin No. Name Pin Function Type 1 1 PTG - Programmable transmit gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB. 2 2 RRLY O Ring relay driver output. The relay coil may be connected to maximum +14 V. 3 3 HP - Connection for high pass filter capacitor, CHP. Other end of CHP connects to TIPX. Data Sheet 11 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Pin Configuration Table 1 Pin Definition and Functions (cont'd) PDSO SSOP Pin No. PLCC Pin No. Name Pin Function Type 4 5 RINGX - The RINGX pin connects to the ring lead of the two-wire interface via over voltage protection components and ring relay (and optional test relay). 5 6 BGND - Battery ground, should be tied together with AGND. 6 7 TIPX - The TIPX pin connects to the tip lead of the two-wire interface via over voltage protection components and ring relay (and optional test relay). 7 8 VBAT - Battery supply voltage. Negative with respect to GND. 8 9 VBAT2 - An optional second (2) Battery Voltage connects to this pin via an external diode. 9 10 PSG - Programmable saturation guard. The resistive part of the DC feed characteristics is programmed by a resistor connected from this pin to VBAT. 10 12 LP - Connection for low pass filter capacitor, CLP. Other end of CLP connects to VBAT. 11 13 DT I Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input. 12 14 DR I Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input. 13 15 NU - Pin not used. Must be connected to AGND. 14 16 C2 I 15 17 C1 I C1and C2 are digital inputs (positive logic, internal pull-up), which control the SLIC operating states. Refer to Table 2 for details. Data Sheet 12 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Pin Configuration Table 1 Pin Definition and Functions (cont'd) PDSO SSOP Pin No. PLCC Pin No. Name Pin Function Type 16 18 DET O Detector output. Active low when indicating loop or ring-trip detection, active high when indicating ground key detection. 17 20 VCC - +5 V power supply. 18 21 PLD - Programmable loop detector threshold. The loop detection threshold os programmed by a resistor connected from this pin to AGND. 19 22 POV - Programmable overhead voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in off- hook and min 1.1 V in onhook. If a resistor is connected between this pin and AGND: The overhead voltage can be set to higher values. 20 23 PLC - Programmable line current, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. 21 24 REF - A reference, 49.9 k, resistor should be connected from this pin to AGND. 22 26 RSN - Receive summing node. 200 times the AC current flowing into this pin equals the metallic (transversal) AC current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive node. A resistor should be connected from this pin to AGND. 23 27 AGND - Analog ground, should be tied together with BGND. Data Sheet 13 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Pin Configuration Table 1 Pin Definition and Functions (cont'd) PDSO SSOP Pin No. PLCC Pin No. Name Pin Function Type 24 28 VTX O Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG). The two-wire impedance programming network connects between VTX and RSN. - 4, 11, 19, NC 25 - Not Connected. Table 2 SLIC Operating States State C2 C1 SLIC Operating State Active Detector (DET Response) 0 0 0 Open circuit No active detector (DET is set high) 1 0 1 Ringing Ring-trip detector (DET active low) 2 1 0 Active Loop detector (DET active low) 3 1 1 Not applicable - Data Sheet 14 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics 3 Electrical Characteristics Table 3 Absolute Maximum Ratings Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. TStg TAmb -55 - 150 C - -40 - 110 C - TJ -40 - 140 C - VCC with respect to A/BGND VCC VBAT2 with respect to VBAT2 -0.4 - 6.5 V - VBAT - 0.4 V - VBAT with respect to VBAT -75 - 0.4 V - VBAT with respect to VBAT -80 - 0.4 V - PD - - 1.5 W TAmb +85 C -0.3 - 0.3 V - - - BGND +14 V - - AGND V - - 5 mA - -0.4 - V - -0.4 - VCC VCC V - Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range1) Power Supply (-40 C TAmb +85 C) A/BGND A/BGND, continuous A/BGND, 10 ms Power Dissipation Continuous power dissipation Ground Voltage between AGND and VG BGND Relay Driver Ring relay supply voltage - Ring Trip Comparator Input voltage Input current VDT, VDR VBAT IDT, IDR -5 Digital Inputs, Outputs (C1, C2, DET) Input voltage Output voltage Data Sheet VID VOD 15 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 3 Absolute Maximum Ratings (cont'd) Parameter Symbol Values Min. Typ. Unit Max. Note/Test Condition TIPX and RINGX Terminals (-40 C TAmb +85 C, VBAT = -50 V) TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND)2) TIPX or RINGX2) ITIPX, -100 IRINGX VTA, VRA -80 - 100 mA - - 2 V - VTA, VRA VBAT - 5 V pulse < 10 ms, tRep > 10 s VTA, VRA VBAT - 10 V pulse < 1 s, tRep > 10 s VTA, VRA VBAT - 15 V pulse < 250 ns, tRep > 10 s - 10 TIPX or RINGX2) - 25 TIP or RING2)3) - 35 1) The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. 2) With the diodes DVB and DVB2 included, see Figure 8. 3) RF1 and RF2 > 20 is also required. Pulse is supplied to RING and TIP outside RF1 and RF2. Attention: Stresses above those values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 4 Operating Range Parameter Symbol TAmb VCC with respect to AGND VCC VBAT with respect to AGND VBAT AGND with respect to BGND VG Ambient temperature Data Sheet Values Min. Typ. Unit Note/Test Condition Max. -40 - 85 C - 4.75 - 5.25 V - -58 - -8 V - -100 - 100 mV - 16 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics 3.1 Characterictics The specification is made with following setup: -40 C TAmb +85 C, PTG = open (see pin description), VCC = +5 V 5%, VBAT = -58 V to -40 V, VBAT2 = -32 V, RLC = 32.4 k, IL = 27 mA, RL = 600 , RF1 = RF2 = 0, RREF = 49.9 k, CHP = 47 nF, CLP = 0.15 F, RT = 120 k, RSG = 0 k, RRX = 60 k, RR = 52.3 k, ROV = infinite. Current definition: current is positive if flowing into a pin unless stated otherwise. Table 5 Characteristics Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. 2.7 - - VPeak - 1.1 - - VPeak On-Hook, ILDC 5 mA Two-Wire Port Overhead level1), 18 mA ILDC Active, 1% THD ROV = infinite see Figure 3 VTRO Input impedance2) ZTRX - ZT / 200 - - Longitudinal impedance ZLOT, ZLOR - 20 35 /wire 0 < f < 100 Hz Longitudinal current limit ILOT, ILOR 28 - - mArms/ wire Active Longitudinal to metallic BLM balance (IEEE standard 455-1985), ZTRX = 736 63 66 - dB 0.2 kHz f 1.0 kHz TAMB 0-70 oC 60 66 - dB 1.0 kHz < f < 3.4 kHz TAMB 0-70 oC 60 66 55 66 Data Sheet 17 0.2 kHz f 1.0 kHz TAMB -40-85 oC - dB 1.0 kHz < f < 3.4 kHz TAMB -40-85 oC Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Parameter Characteristics (cont'd) Symbol Values Unit Note/Test Condition Min. Typ. Max. 63 66 - dB 0.2 kHz f 1.0 kHz TAMB 0-70 oC 60 66 - dB 1.0 kHz < f < 3.4 kHz TAMB 0-70 oC 60 66 55 66 - dB 1.0 kHz < f < 3.4 kHz TAMB -40-85 oC 63 66 - dB 0.2 kHz f 1.0 kHz TAMB 0-70 oC 60 66 - dB 1.0 kHz < f < 3.4 kHz TAMB 0-70 oC 60 66 55 66 - dB 1.0 kHz < f < 3.4 kHz TAMB -40-85 oC Metallic to longitudinal BMLE balance BMLE = 20 x log|VTR/VLO|, ERX = 0 V, see Figure 5 40 50 - dB 0.2 kHz < f < 3.4 kHz Four-wire to longitudinal BFLE balance BFLE = 20 x log|ERX/VLO|, see Figure 5 40 50 - dB 0.2 kHz < f < 3.4 kHz Longitudinal to metallic BLME balance BLME = 20 x log|ELO/VTR|, see Figure 4 Longitudinal to four-wire BLFE balance BLFE = 20 x log|ELO/VTX|, see Figure 4 Data Sheet 18 0.2 kHz f 1.0 kHz TAMB -40-85 oC 0.2 kHz f 1.0 kHz TAMB -40-85 oC Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Characteristics (cont'd) Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. 30 35 - dB 0.2 kHz < f < 1.0 kHz 20 22 - dB 1.0 kHz < f < 3.4 kHz Two-wire return loss3) Z TRX + Z L r = 20 x log ----------------------Z TRX - Z L r TIPX idle voltage VTI - -1.3 - V Active, IL < 5 mA RINGX idle voltage VRI - VBAT+ - 3.0 V Active, IL < 5 mA Open loop voltage VTR - VBAT+ - 4.3 V Active, IL < 5 mA 2.7 - - VPeak IL > 18 mA 1.1 - - VPeak On-Hook, IL 5 mA, Four-Wire Transmit Port (VTX) Overhead level4), Load imp. > 20 k 1% THD see Figure 6 VTXO Output offset voltage VTX -100 - 100 mV - Output impedance ZTX - 15 50 0.2 kHz < f < 3.4 kHz Four-Wire Receive Port (receive summing node = RSN) 1.15 1.25 1.35 V IRSN = -55 A - 8 20 0.2 kHz < f < 3.4 kHz RSN - 200 - ratio 0.3 kHz < f < 3.4 kHz Two-wire to four-wire, relative to 0 dBm, 1.0 kHz, ERX = 0 V, see Figure 7 g2-4 -0.20 - 0.10 dB 0.3 kHz < f < 3.4 kHz -1.0 - 0.1 dB f = 8 kHz, 12 kHz, 16 kHz Four-wire to two-wire, relative to 0 dBm, 1.0 kHz, EL = 0 V, see Figure 7 g4-2 -0.2 - 0.1 dB 0.3 kHz < f < 3.4 kHz -1.0 - 0 dB f = 8 kHz, 12 kHz -2.0 - 0 dB f = 16 kHz RSN DC voltage VRSNdc RSN impedance RSN current (IRSN ) to metallic loop current (IL) gain Frequency Response Data Sheet 19 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Characteristics (cont'd) Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. g4-4 -0.2 - 0.1 dB 0.3 kHz < f < 3.4 kHz Two-wire to four-wire5), G2-4 = 20 x log|VTX/VTR| 0 dBm, 1.0 kHz ERX = 0 V G2-4 -0.2 - 0.2 dB PTG = Open see Figure 7 -6.22 -6.02 -5.82 dB PTG = AGND Four-wire to two-wire6), G4-2 = 20 x log|VTR/VRX|, EL = 0 V, see Figure 7 G4-2 -0.2 - 0.2 dB 0 dBm, 1.0 kHz Two-wire to four-wire7), Ref. -10 dBm, 1.0 kHz, see Figure 7 -0.1 - 0.1 dB -40 dBm to +3 dBm -0.2 - 0.2 dB -55 dBm to 40 dBm Four-wire to two-wire, Ref. -10 dBm, 1.0 kHz, see Figure 7 -0.1 - 0.1 dB -40 dBm to +3 dBm -0.2 - 0.2 dB -55 dBm to 40 dBm - - 12 dBrnC C-message weighting - - -78 dBmp Psophometrical weighting Two-wire to four-wire, see Figure 7 - -67 -50 dB Four-wire to two-wire - -67 -50 dB 0 dBm 0.3 kHz < f < 3.4 kHz Four-wire to four-wire, relative to 0 dBm, 1.0 kHz, EL = 0 V, see Figure 7 Insertion Loss Gain Tracking Noise Idle channel noise at two-wire port8) (TIPXRINGX) or four-wire (VTX) output Harmonic Distortion Data Sheet 20 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Characteristics (cont'd) Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. 0.92 x IL IL 1.08 x IL mA 18 mA IL 45 mA -100 0 100 A RL = 0 0.85 x ILTh ILTh 1.15 x ILTh mA RLD in k, 7 mA ILTh Battery Feed Characteristics Loop current in the current limited region, reference A, B & C see Figure 12 IL Open circuit loop current ILOC Loop Detector Programmable threshold, ILTh = 500/RLD ILTh Ringing Trip Comparator Offset voltage VDTDR -20 0 20 mV Source resistance, RS = 0 Input bias current IB -200 -20 200 nA IB=(IDT +IDR)/2 Input common mode range VDT, VDR VBAT +1 - -1 V - - 0.2 0.5 V IOL = 50 mA - - 10 A VOH = 12 V Ring Relay Driver Saturation voltage VOL Off state leakage current ILK Digital Inputs (C1, C2) Input low voltage VIL 0 - 0.5 V - Input high voltage VIH 2.5 - VCC V - Input low current IIL - - -50 A VIL = 0.5 V Input high current IIH - - 50 A VIH = 2.5 V VOL - - 0.7 V IOL = 0.5 mA - 15 - k - 15 mW Open circuit Detector Output (DET) Output low voltage Internal pull-up resistor to VCC Power Dissipation (VBAT -48 V, VBAT2 = -32 V) Power Dissipation Data Sheet P1 - 10 21 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Characteristics (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note/Test Condition Power Dissipation P2 - 65 85 mW Active (On-hook) Long current = 0 mA Power Dissipation P3 - 730 - mW Active (Off-hook) RL = 300 Power Dissipation P4 - 360 - mW Active (Off-hook) RL = 800 Power Supply Currents (VBAT = -48 V) VCC current ICC - 1.2 2.0 mA Open circuit (C1, C2, C3 = 0) VBAT current IBAT -0.1 -0.05 - mA Open circuit (C1, C2, C3 = 0) VCC current ICC - 2.8 4.0 mA Active, On-hook, Long current = 0 mA VBAT current IBAT -1.5 -1.0 - mA Active, On-hook, Long current = 0 mA VCC to 2- or 4-wire port 30 42 - dB Active, f = 1 kHz, Vn = 100 mV VBAT2 to 2- or 4-wire port 40 60 - dB Active, f = 1 kHz, Vn = 100 mV VBAT to 2- or 4-wire port 36 45 - dB Active, f = 1 kHz, Vn = 100 mV Power Supply Rejection Ratios Data Sheet 22 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics Table 5 Characteristics (cont'd) Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. TJG - 145 - C - Rth, jp - 55 - C/W - Rth, jA - 66.9 - C/W P-/PG-SSOP-241, 4-layer PCB; Junction to ambient thermal resistance in JEDEC still air chamber Rth, jp - 43 - C/W - Rth, jA - 50.3 - C/W P-/PG-DSO-24-8, 4-layer PCB; Junction to ambient thermal resistance in JEDEC still air chamber Rth, jp - 39 - C/W - Rth, jA - 50.4 - C/W P-/PG-LCC-28-3, 4-layer PCB; Junction to ambient thermal resistance in JEDEC still air chamber Temperature Guard Junction threshold temperature Thermal Resistance 24-pin SSOP 24-pin PDSO 28-pin PLCC 1) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is specified at the two-wire port with the signal source at the four-wire receive port. Data Sheet 23 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics 2) The two-wire impedance is programmable by selection of external component values according to: ZTRX = ZT/(|G2-4S x RSN|) where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4S = transmit gain, nominally = 1 (or 0.5, see pin PTG) RSN = receive current gain, nominally 200 (current defined as positive flowing into the receive summing node, RSN, and when flowing from ring to tip). 3) Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, for example by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is specified at the four-wire transmit port, (VTX) with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5, see pin PTG). 5) Pin PTG = Open sets transmit gain to nom. 0.0 dB. Pin PTG = AGND sets transmit gain to nom. -6.02 dB Secondary protection resistor RF (see Figure 8) impacts the insertion loss as explained in Chapter 5. The specified insertion loss is valid for RF = 0. 6) The specified insertion loss tolerance does not include errors caused by external components. 7) The level is specified at the two-wire port. 8) The two-wire idle noise is specified with the port terminated in 600 (RL), and with the four-wire receive port grounded (ERX = 0; see Figure 7). The four-wire idle noise at VTX is specified with the two-wire port terminated in 600 (RL). The noise specification is referenced to a 600 programmed two-wire impedance level at VTX. The four-wire receive port is grounded (ERX = 0). C TIPX RL V TRO I LDC VTX PBL 38630 RINGX RT E RX RSN R RX Fig3_30 Figure 3 Overhead Level, VTRO, Two-Wire Port 1/C << RL, RL = 600 , RT = 120 k, RRX = 60 k Data Sheet 24 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics E LO TIPX C VTX R LT V TR PBL 38630 RT R LR RINGX V TX RSN R RX Fig4_30 Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance Figure 4 1/C << 150 , RLT = RLR = RL /2 = 300 , RT = 120 k, RRX = 60 k C TIPX V TR V LO VTX R LT PBL 38630 RT R LR RINGX E RX RSN R RX Fig5_30 Figure 5 Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE 1/C << 150 , RLT = RLR = RL /2 = 300 , RT = 120 k, RRX = 60 k C TIPX RL EL I LDC VTX PBL 38630 RINGX V TXO RT RSN R RX Fig6_30 Figure 6 Overhead Level, VTXO, Four-Wire Transmit Port 1/C << RL, RL = 600 , RT = 120 k, RRX = 60 k Data Sheet 25 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Electrical Characteristics C TIPX RL EL V TR I LDC VTX PBL 38630 RINGX RT V TX E RX RSN R RX Fig7_30 Figure 7 Frequency Response, Insertion Loss, Gain Tracking 1/C << RL, RL = 600 , RT = 120 k, RRX = 60 k Data Sheet 26 Rev. 2.0, 2005-04-14 Figure 8 Data Sheet 27 VB VB2 TIP E RG D VB RR T R F2 VB RF1 R2 R1 DBB D VB2 OVP C GG C1 CVB2 CVB R 3R 4 C2 DR DT LP NC NU C2 C1 D ET NC VCC VBAT2 PSG PLD POV PLC R EF NC VBAT TIPX BGND R IN GX NC RSN HP SLIC No.2 etc R SG C LP CTC CR C CH P AGND VTX R RLY PTG RR X RB C TX SYSTEM C ONT RO L IN TE RF ACE R LD R OV RLC RREF RR RT R TX C VCC SIC O F I(R) 4 Codec V OU T V IN VC C 4 RING +5 / + 12 V KR PBL38630 FlexiSLIC PBL 38630/2 Application Schematic Application Schematic sch_30 Application Example of PBL 38630/2 with SICOFI(R)4 Codec Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Application Schematic 4.1 Table 6 Recommended Components Resistors Resistor Value Tolerance Specification RSG RLD ROV RLC RREF RR RT RRX RTX RB R1 R2 R3 R4 RRT RF1, RF2 0 - 1/10 W 49.9 k 1% 1/10 W User programmable - - 32.4 k 1% 1/10 W 49.9 k 1% 1/10 W 22.7 k 1% 1/10 W 51 k 1% 1/10 W 51 k 1% 1/10 W 3.6 k 1% 1/10 W 6.2 k 1% 1/10 W 604 k 1% 1/10 W 604 k 1% 1/10 W 249 k 1% 1/10 W 280 k 1% 1/10 W 330 5% 2W Line resistor, 40 1% - Table 7 Capacitors Capacitor Value Tolerance Specification CVB CVB2 CTC CRC CHP CVCC CLP CTX CGG 100 nF 10% 100 V 150 nF 10% 100 V 2.2 nF 10% 100 V 2.2 nF 10% 100 V 47 nF 10% 100 V 100 nF 10% 10 V 150 nF 10% 100 V 100 nF 10% 10 V 220 nF 10% 100 V Data Sheet 28 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Application Schematic Table 7 C1 C2 Table 8 Capacitors (cont'd) 330 nF 10% 63 V 330 nF 10% 63 V Diodes Diode Value DVB DVB2 DBB 1N4448 Tolerance Specification 1N4448 1N4448 OVP Secondary protection (Bournes TISP PBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferably to a ground plane. 4.2 Design Supporting Tools The following supporting tools are available for the PBL 38630/2: * * * Test board TB208 for PLCC package Test board TB208SSOP for SSOP package Pspice model for PBL 38630/2 Data Sheet 29 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Transmission 5 Transmission 5.1 General A simplified AC model of the transmission circuit is shown in Figure 9. TIP RF TIPX IL HP VTR ZL ZTR RHP EL + _ VTX G2- 4S RING RF VTX IL RINGX ZT IL /RSN ZRX RSN PBL 38630 VRX ac_sch_30 Figure 9 Simplified AC Model of PBL 38630/2 Circuit analysis from the AC model in Figure 9 yields following equations: V TX V TR = --------------- + IL x 2 RF [1] G 2 - 4S I V V L TX RX ------------ = -------- + -------- RSN Z T Z RX [2] V TR = E L - I L x Z L [3] Data Sheet 30 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Transmission where: VTX Is the ground referenced version of the AC metallic voltage between the TIPX and RINGX terminals. VTR EL IL RF Is the AC metallic voltage between TIP and RING. G2-4S Is the programmable SLIC two-wire to four-wire gain (transmit direction)1). ZL ZRX ZT VRX Is the line impedance. RSN Is the receive summing node current to metallic loop current gain. RSN = 200 Is the line open circuit AC metallic voltage. Is the AC metallic current. Is a fuse resistor. Controls four- to two-wire gain. Determines the SLIC TIPX to RINGX impedance at voice frequencies. Is the analog ground referenced receive signal. 1) The SLIC two-wire to four-wire gain, G2-4S, is user programmable between two fixed values. See Table 5. 5.2 Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse resistor RF, let VRX = 0. From Equation [1] and Equation [2]: ZT Z TR = ---------------------------------- + 2RF [4] RSN x G 2 - 4S Thus with ZTR, G2-4S, RSN and RF known: Z T = RSN x G2 - 4S x ( Z TR - 2 R F ) 5.3 [5] Two-Wire to Four-Wire Gain From Equation [1] and Equation [2] with VRX = 0: Z T RSN V TX = ---------------------------------------------------G 2 - 4 = --------V TR ZT ---------------------------------- + 2 RF RSN x G 2 - 4S Data Sheet [6] 31 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Transmission 5.4 Four-Wire to Two-Wire Gain From Equation [1] to Equation [3] with EL = 0: ZT ZL V TR 1 - x ---------------- x ---------------------------------------------------------------G 4 - 2 = --------- = - -------Z RX G 2 - 4S ZT V RX ----------------------------------- + Z L + 2 R F RSN x G 2 - 4S [7] For applications where Z T ---------------------------------- + 2 RF = ZL RSN x G 2 - 4S [8] the expression for G4-2 simplifies to: ZT 1 G 4 - 2 = - --------x ------------------------Z RX 2 x G 2 - 4S 5.5 [9] Four-Wire to Four-Wire Gain From Equation [1] to Equation [3] with EL = 0: ZT ZL + 2 RF V TX - x ---------------------------------------------------------------G 4 - 4 = --------- = - -------Z RX ZT V RX ----------------------------------- + Z L + 2 R F RSN x G 2 - 4S 5.6 [10] Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional non software programmable codec/filters. Please, refer to Figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination codec/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain, G4-4, a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be cancelled by letting: V TX V RX --------- + ---------- = 0 R TX Z B Data Sheet ( EL = 0 ) [11] 32 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Transmission The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: Z T ---------------------------------- + ZL + 2 RF x G 2 - 4S V RX Z RX RSN Z B = - R TX x ---------- = R TX x --------- x ----------------------------------------------------------------V TX ZT ZL + 2 RF [12] When selecting the RTX resistance value, make sure the load resistance on the VTX terminal is at least 20 k. If calculation of the ZB formula above yields a balance network containing an inductor, please contact Infineon`s support group for assistance. The PBL 38630/2 SLIC may also be used together with programmable CODEC/filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accomodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. RFB RTX VTX PBL 38630 VT ZB ZT Codec/Filter ZRX VRX RSN ZR Hybrid_30 Figure 10 Data Sheet Hybrid Function 33 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Transmission 5.7 Longitudinal Impedance A feedback loop within the SLIC counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLOT and ZLOR, appears as typically 20 to longitudinal disturbances. It should be noted that longitudinal currents may exceed the DC loop current without disturbing the VF transmission. 5.8 Capacitors CTC and CRC The capacitors designated CTC and CRC in Figure 8, connected between TIPX and ground as well as between RINGX and ground, can be used for RFI filtering. The recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. CTC and CRC contribute to a metallic impedance of 1/( x f x CTC) = 1/( x f x CRC), a TIPX to ground impedance of 1/(2 x f x CTC) and a RINGX to ground impedance of 1/(2 x f x CRC). 5.9 AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and TIPX provides the separation of the AC and DC signals, such that only AC signals are forwarded to the VTX terminal. CHP positions the low end frequency response break point of the AC feedback loop in the SLIC. A CHP value of 150 nF will position the low end frequency response 3 dB break point of the AC loop at 1.8 Hz (f3dB) according to f3dB = 1/(2 x RHP x CHP) where RHP = 600 k (see Table 9). 5.10 High-pass Transmit Filter The capacitor CTX in Figure 8 connected between the VTX output and the CODEC/filter forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a faster response for the DC steps that may occur at DTMF signalling. 5.11 Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT, positions the high end frequency break point of the low pass filter in the DC feedback loop (battery feed controlling loop) of the SLIC. CLP together with CHP and ZT(see Chapter 5.2) forms the total two-wire output impedance of the SLIC. The choice of these programmable Data Sheet 34 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed components have an influence on the power supply rejection ratio (PSRR) from VBAT to the two-wire side at sub audio frequencies.At these frequencies CLP also influences the transversal to longitudinal balance in the SLIC. Table 9 suggests a suitable value for CLP. The typical value of the transversal to longitudinal balance at 200 Hz is given in the table below, for the chosen value of CLP. Table 9 Feeding Setup Symbol Value Unit RFeed RSG CLP 2x50 2x200 2x400 2x800 0 60.4 147 301 k 150 100 47 22 nF T-L bal. @ 200 Hz -46 -46 -43 -36 dB CHP 47 150 150 150 nF 6 Battery Feed The PBL 38630/2 SLIC emulates resistive loop feed, programmable between 2x50 and 2x900 , with adjustable current limitation. In the current limited region the loop current has a slight slope corresponding to 2x30 , see Figure 12 reference B. The open loop voltage measured between the TIPX and RINGX terminals tracks the battery voltage VBAT. The signalling headroom, or overhead voltage VTRO, is programmable with a resistor ROV connected between terminal POV on the SLIC and ground. Please refer to Chapter 6.2. The battery voltage overhead,VOH, depends on the programmed signal overhead voltage VTRO. VOH defines the TIP and RING voltage at open loop conditions according to VTR(at IL = 0 mA) = |VBAT| - VOH Refer to Table 10 for the typical value of VOH and VOHvirt. The overhead voltage is changed when line corrent is approaching open loop conditions. To ensure maximum open loop voltage, even with a leaking telephone line, this occurs at a line current of approximately 6 mA. When the overhead voltage has changed, the line voltage is kept nearly constant with a steep slope corresponding to 2x25 (reference G in Figure 12). The virtual battery overhead, VOHvirt , is defined as the difference between the battery voltage and the crossing point of all possible resistive feeding slopes, see Figure 12 reference J. The virtual battery overhead is a theoretical constant needed to be able to calculate the feeding characteristics. Data Sheet 35 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed Table 10 Battery Overhead Value (typ) 3.0 + VTRO 4.9 + VTRO Symbol VOH VOHvirt Unit Specification V - V - The resistive loop feed (reference D in Figure 12) is programmed by connecting a resistor, RSG , between terminals PSG and VBAT according to the equation: 4 R Feed R SG + 2 x10 = ------------------------------+ 2R F 200 [13] where RFeed is in for RSG and RF in . The current limit (reference C in Figure 12) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: 1000 I LProg = ------------ - 4.0 R LC [14] where RLC is in k for ILProg in mA. A second lower battery voltage may be connected to the device at terminal VBAT2 to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external control. the silent battery switching occurs when the line voltage passes the value |VB2| - 40 x IL - (VOHvirt - 1.3), if IL > 6 mA. For correct functionality it is important to connect the terminal VBAT2 to the second power supply via the diode DVB2, see Figure 8. An optional diode DBB connected between terminal VB and the VB2 power supply, see Figure 8, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. If a second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and CVB2, DBB and DVB2 are removed. 6.1 CODEC Receive Interface The PBL 38630/2 SLIC has got a receive interface at the four- wire side which makes it possible to reduce the number of capacitors in the applications and to fit both single and dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output via the resistor RRX, is DC biased with +1.25 V. This makes it possible to compensate for currents floating due to DC voltage differences between RSN and the CODEC output without using any capacitors. This is done by connecting a resistor RR between the RSN Data Sheet 36 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed terminal and ground. With current directions defined as in Figure 12, current summation gives: 1.25 1.25 - V CODEC 1.25 - I RSN = I RT + I RRX + I RR = ---------- + -------------------------------------- + ---------- RT R RX [15] RR where VCODEC is the reference voltage of the CODEC at the receive output. From this equation the resistor RR can be calculated as 1.25 R R = -----------------------------------------------------------------------------1.25 1.25 - V CODEC - I RSN - ---------- - --------------------------------------RT R RX [16] For the value on IRSN, see Table 11.7 If RSN is DC decoupled from the CODEC output, then infinite. The resistor RR has no influence in the AC transmission. Table 11 RRX can be considered to be Internal Bias Current of RSN Symbol Value (typ) Unit IRSN -55 A VTX RT I RSN +1.25 IRSN IRT CODEC I RX I RR RRX + _ DC-GND UREFcodec RR codecIF Figure 11 Data Sheet Codec Receive Interface 37 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed A B A B C C IL [mA] D D E G F F H J VTR [V] Figure 12 batfeed30 Battery Feed Characteristics A -3 I L ( V TR B C V Bat - V OHvirt - RFeed x ( I LProg + 4 x10 ) = 0V ) = I LProg + -------------------------------------------------------------------------------------------------------------3 60 x10 RFeed = 2x30 k 3 -3 10 ILConst(typ) = ILProg = --------- - 4 x10 R LC VTR = |VBAT| - VOHvirt - RFeed x (ILProg + 4x10-3) Data Sheet 38 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed D 4 R Feed R SG + 2 x10 = ------------------------------+ 2R F 200 E IL = 6 mA F Apparent battery VBat (@ IL = 0) = |VBAT| - VOHvirt - (RFeed x 4x10-3) G RFeed = 2x25 VTROpen = |VBAT| - VOH Virtual battery VBatVirt (@ IL = 4 mA) = |VBAT| - VOHvirt H J 6.2 Programmable Overhead Voltage (POV) With the POV function the overhead voltage can be increased. If the POV pin is left open the overhead voltage is internally set to 3.2 VPeak in off-hook and 1.3 VPeak on-hook.. If a resistor ROV is connected between the POV pin and AGND, the overhead voltage can be set to higher values, typical values can be seen in Figure 13. The ROV and corresponding VTRO (signal headroom) are typical values for THD < 1% and the signal frequency 1000 Hz. Observe that the four-wire output terminal VTX cannot handle more than 3.2 VPeak. So if the two- to four-wire gain is 0 dB, 3.2 VPeak is maximum also for the two-wire side. Signal levels between 3.2 and 6.4 VPeak on the two-wire side can be handled with the PTG shorted so that the gain G2-4S becomes -6.02 dB. Please note that: * * * ZT RR G4 - 4 has to be recalculated if the PTG is shorted. Please note that the maximum signal current at the two-wire side can not be higher than 9 mA. How to use POV: 1. Decide what overhead voltage (VTRO) is needed. The POV function is only needed if the overhead voltage exceeds 3.2 VPeak. 2. In Figure 13 the corresponding ROV for the decided VTRO can be found. 3. If the overhead voltage exceeds 3.2 VPeak, the G2-4S gain has to be changed to 6.02 dB by connecting pin PTG to AGND. Please note, that the 2-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated. Data Sheet 39 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Battery Feed 7 6 V TRO (V Peak) 5 4 of f -hook on-hook 3 2 1 0 0 5 10 15 20 25 30 35 40 Rov (Kohm) Figure 13 6.3 45 50 55 60 65 POV Programmable Overhead Voltage (POV). RL= 600 or Infinite Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 38630/2 SLIC reduces the DC line current when the chip temperature reaches approximately 145 oC and increases line current again automatically when the temperature drops. Accordingly transmission is not lost under high ambient temperature conditions. The detector output, DET, is forced to a logic low level when the temperature guard is active. Data Sheet 40 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Loop Monitoring Functions 7 Loop Monitoring Functions The loop current, ground key and ring-trip detectors report their status through a common output, DET. The particular detector to be connected to the detector pin, DET, is selected via the two bit control interface C1and C2. Please refer to Chapter 9 for a description of the control interface. 7.1 Loop Current Detector The loop current detector indicates that the telephone is off-hook and that DC current is flowing in the loop by setting the output pin DET to a logic low level when selected. The loop current detector threshold value, ILTh, where the loop current detector changes state, is programmable with the RLD resistor. RLD connects between pin PLD and ground and is calculated according to: R LD = 500 ---------I Lth [17] The loop current detector is internally filtered and is not influenced by the AC signal at the two-wire side. 7.2 Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced superimposed on VB or GND. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring. The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no DC current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is energized, DC current flows and the comparator input voltage reverses polarity. Figure 8 gives an example of a ring trip detector network. This network is applicable when the ring voltage is superimposed on VB and is injected on the ring lead of the twowire port. The DC voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the network R1,R2 ,R3 ,R4 ,C1 and C2. When the line is on-hook (no DC current), DT is more positive than DR and the DET output will report logic level high, that is the detector is not tripped. When the line goes off-hook, while ringing, a DC current will flow through the loop including sense resistor RRT and will cause input DT to become more negative than input DR. This changes output DET to logic level low, that is tripped detector conditions. The system controller (or line card processor) responds by de-energizing the ring relay, that is ring trip. Data Sheet 41 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Relay Driver Complete filtering of the 20 Hz AC component at terminal DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the duty cycle. When the DET output is at logic level low for more than half the time, off-hook conditions is indicated. 8 Relay Driver The PBL 38630/2 SLIC incorporates a ring relay driver designed as open collector (npn), with a current sinking capability of 50 mA. The drive transistor emitter is connected to BGND. The relay driver has an internal zener diode clamp for inductive kick back voltages. 9 Control Inputs The SLIC has two digital control inputs, C1 and C2 (see Table 2). A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 and C2 are internally pulled up. 9.1 Open Circuit (C2, C1 = 0, 0) In the Open Circuit state, the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active. DET output is set high. 9.2 Ringing (C2, C1 = 0, 1) The ring relay driver and the ring trip detector are activated and the ring trip detector is indicating off-hook with a logic low level at the detector output. The SLIC is in the active normal state. 9.3 Active state TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. VF signal transmission is normal. The loop current detector is activated. The loop current detector indicates off-hook with a logic low level and the ground key detector is indicating active ground key with a logic high level present at the detector output. Data Sheet 42 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Overvoltage Protection 10 Overvoltage Protection 10.1 Overvoltage Protection - General The SLIC must be protected against foreign voltages on the telephone line. Overvoltages can result from lightning, AC power contact, induction and other causes. Refer to Table 3, TIPX and RINGX terminals, for maximum continuous and transient voltages that may be applied to the SLIC. 10.2 Secondary Protection The circuit shown in Figure 8 utilizes series resistors (RF1, RF2) together with a programmable overvoltage protector (OVP, for example Bournes TISP PBL2) as secondary protection. The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to the negative supply voltage (that is the battery voltage, VB). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG should be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VB supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non-destructive energy dissipators when transients are clamped, and of being fuses when the line is exposed to a power cross. If a PTC is choosen for RF, note that it is important to always use PTC's in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC. 11 Power-Up Sequence No special power-up sequence is necessary, except that ground has to be present before all other power supply voltages. 12 Printed Circuit Board Layout Care in Printed Circuit Board (PCB) layout is essential for proper function. The components connected to the RSN input should be placed in close proximity to that pin, Data Sheet 43 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Printed Circuit Board Layout such that no interference is injected into the receive summing node (RSN). Ground plane surrounding the RSN pin is advisable. Analog Ground (AGND) should be connected to Battery Ground (BGND) on the PCB, in one point. The capacitors for the battery should be connected with short wide leads of the same length. Data Sheet 44 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Package Outlines 13 Package Outlines The SLIC is provided in three different packages: 24-pin SSOP, 24-pin PDSO and 28pin PLCC. 0.65 5.3 0.11) 0.9 0.2 0.15 M A C 24x 7.8 +0.1 -0.05 24 13 1 12 8.2 0.13 1) 8 MAX. -0.06 0.1 C 2) 0.3 +0.08 -0.05 B 0.15 +0.05 1.99 MAX. 1.73 0.05 24-pin SSOP Package 0.13 0.08 13.1 0.2 M B 24x A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.13 max. GPS01027 Figure 14 P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 45 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Package Outlines 1.27 +0.0 9 7.6 -0.2 1) 8 MAX. 0.35 x 45 0.23 2.65 MAX. 2.45 -0.2 24-pin PDSO Package 0.2 -0.1 13.2 0.4 +0.8 0.1 0.35 +0.15 2) 0.2 24x 24 1 10.3 0.3 13 15.6 -0.4 1) 12 Index Marking 1) 2) Does not include plastic or metal protrusion of 0.15 max. per side Lead width can be 0.61 max. in dambar area gps05144 Figure 15 P-/PG-DSO-24-8 (Plastic Dual Small Outline Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 46 Rev. 2.0, 2005-04-14 FlexiSLIC PBL 38630/2 Package Outlines 11.51 0.08 1) 0.25 0.04 0.73 0.07 4.57 MAX. 28-pin PLCC Package 0.5 MIN. 3.05 MAX. 13.3 1.27 10.4 0.5 0.1 7.62 0.43 0.1 1.27 x 45 C 12.45 0.13 0.18 M C A-B D 28x D A B Index Marking 28 1 1) 11.510.08 1.45 x 45 12.45 0.13 1) Does not include mold protrusion of 0.25 max. per side GPL01023 Figure 16 P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 47 Rev. 2.0, 2005-04-14 http://www.infineon.com Published by Infineon Technologies AG