Never stop thinking.
FlexiSLIC
Subscriber Line Interface Circuit
PBL 38630/2, Version 2
Data Sheet, Rev. 2.0, Apr. 2005
Wireline Communications
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The information in this document is subject to change without notice.
Edition 2005-04-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
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circuits, descriptions and charts stated herein.
Information
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FlexiSLIC
Revision History: 2005-04-14 Rev. 2.0
Previous Version: DS1
Page Subjects (major changes since last revision)
all Package P-DSO-24-1 changed to P-/PG-DSO-24-8
all Package type abbreviation SOIC changed to PDSO
all Package P-LCC-28-2 changed to P-/PG-LCC-28-3
all Package P-SSOP-24-1 changed to P-/PG-SSOP-24-1
Page 17 Table 5: Thermal resistance for 24-pin PDSO changed from 80.2 °C/W to
50.3 °C/W
Page 27 Figure 8: SLIC/codec circuitry changed
Page 28 Table 6: values of RR, RT, RRX, RTX, RB changed, RFB removed
Page 33 Figure 10 changed
FlexiSLIC
PBL 38630/2
Table of Contents Page
Data Sheet 4 Rev. 2.0, 2005-04-14
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Characterictics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Design Supporting Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Two-Wire Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Two-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 Four-Wire to Two-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5 Four-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6 Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.7 Longitudinal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.8 Capacitors CTC and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.9 AC - DC Separation Capacitor, CHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.10 High-pass Transmit Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.11 Capacitor CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Battery Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 CODEC Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Programmable Overhead Voltage (POV) . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3 Analog Temperature Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Loop Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Loop Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 Ring Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 Open Circuit (C2, C1 = 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 Ringing (C2, C1 = 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.1 Overvoltage Protection - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FlexiSLIC
PBL 38630/2
Table of Contents Page
Data Sheet 5 Rev. 2.0, 2005-04-14
10.2 Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12 Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.1 24-pin SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.2 24-pin PDSO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.3 28-pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FlexiSLIC
PBL 38630/2
List of Figures Page
Data Sheet 6 Rev. 2.0, 2005-04-14
Figure 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2 Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view).. 11
Figure 3 Overhead Level, VTRO, Two-Wire Port . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4 Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance . . . . . 25
Figure 5 Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE . . . . . 25
Figure 6 Overhead Level, VTXO, Four-Wire Transmit Port . . . . . . . . . . . . . . . . . 25
Figure 7 Frequency Response, Insertion Loss, Gain Tracking . . . . . . . . . . . . . 26
Figure 8 Application Example of PBL 38630/2 with SICOFI®4 Codec . . . . . . . . 27
Figure 9 Simplified AC Model of PBL 38630/2. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10 Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11 Codec Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12 Battery Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13 Programmable Overhead Voltage (POV). RL= 600 Ω or Infinite . . . . . 40
Figure 14 P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package) . . . . . . . . . 45
Figure 15 P-/PG-DSO-24-8 (Plastic Dual Small Outline Package) . . . . . . . . . . . 46
Figure 16 P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package) . . . . . . . . . . 47
FlexiSLIC
PBL 38630/2
List of Tables Page
Data Sheet 7 Rev. 2.0, 2005-04-14
Table 1 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2 SLIC Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8 Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9 Feeding Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10 Battery Overhead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11 Internal Bias Current of RSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Type Package
PBL 38630/2 SH P-/PG-SSOP-24-1
PBL 38630/2 SO P-/PG-DSO-24-8
PBL 38630/2 QN P-/PG-LCC-28-3
FlexiSLIC
Subscriber Line Interface Circuit
PBL 38630/2
Version 2
P/PG-SSOP-24-1
P-SSOP-24-1
P-/PG-SSOP-24-1
P-DSO-24-1, -3
P-/PG-DSO-24-8
P/PG-LCC-28-3
P-LCC-28-2
P-/PG-LCC-28-3
Data Sheet 8 Rev. 2.0, 2005-04-14
1Overview
1.1 Features
• 24-pin SSOP package
• High and low battery with automatic switching
• 65 mW on-hook power dissipation in active state
• On-hook transmission
• Long loop battery feed tracks Vbat for maximum line
voltage
• Selectable transmit gain (1x or 0.5 x)
• No power-up sequence
•43 V open loop voltage @ -48 V battery feed
• Close tolerance current feeding
• Constant loop voltage for line leakage < 5 mA
(RLeak ~ > 10 kΩ @ -48 V)
• Full longitudinal current capability during
on-hook state
• Longitudinal balance > 60 dB
• Analog overtemperature protection permits transmis-
sion while the protection circuits is active
• Integrated Ring Relay driver
• Programmable signal headroom
•-40 oC to +85 oC ambient temperature range
1.2 Typical Applications
• Basic functionality Central Office Line card
• Digital Loop Carriers (DLC)
FlexiSLIC
PBL 38630/2
Overview
Data Sheet 9 Rev. 2.0, 2005-04-14
1.3 Description
The PBL 38630/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX, Terminal adapters and other telecommunications equipment. The
PBL 38630/2 SLIC has been optimized for low total line interface cost and for a high
degree of flexibility in different applications.
The PBL 38630/2 SLIC emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with short loop current limiting adjustable to maximum 45 mA. In the
current limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30 kΩ.
A second lower battery voltage may be connected to the device to reduce short loop
power dissipation. The SLIC automatically switches between the two battery supply
voltages without need for external components or external control.
The SLIC incorporates loop current and ring-trip detection functions. The PBL 38630/2
is compatible with loop start signalling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with
a programmable CODEC/filter, for example SiCoFi PEB 2466. The programmable two-
wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 38630/2 SLIC package options are 24-pin SSOP, 24-pin PDSO or 28-pin
PLCC.
FlexiSLIC
PBL 38630/2
Overview
Data Sheet 10 Rev. 2.0, 2005-04-14
1.4 Block Diagram
Figure 1 Block Diagram
Two-wire
Interface
Ring Tri p
Compar ator
Li ne Feed
Controller
and
Longi tudi nal
Si gnal
Suppr essi on
Off - Hook
Detector
VF si gnal
Transmission
C1
C2
DET
Input
Decoder
and
Contr ol
AGND
VCC
POV
PSG
REF
PLD
RSN
VTX
PTG
RINGX
HP
TIPX
DT
DR
RRLY
bl_sch_3
0
PLC
Ring Relay
Dri ver
Ground Key
Detector
LP
BGND
VBAT
VBAT2
FlexiSLIC
PBL 38630/2
Pin Configuration
Data Sheet 11 Rev. 2.0, 2005-04-14
2 Pin Configuration
Figure 2 Pin Configuration, 24L-PDSO, 24L-SSOP and 28L-PLCC (top view).
Table 1 Pin Definition and Functions
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name Pin
Type
Function
1 1 PTG –Programmable transmit gain. Left open
transmit gain = 0.0 dB, connected to AGND
transmit gain = -6.02 dB.
2 2 RRLY ORing relay driver output. The relay coil may
be connected to maximum +14 V.
3 3 HP –Connection for high pass filter capacitor, CHP.
Other end of CHP connects to TIPX.
pinout_30
4
5
6
7
8
9
10
11
PTG
24- pi n PDSO
and
24- pi n SSOP
1
2
3
4
5
6
7
8
9
10
11
12 13
14
24
23
22
21
20
19
18
17
16
15
RRLY
HP
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
LP
DT
DR
VTX
AGND
RSN
REF
PLC
POV
PLD
VCC
DET
C1
C2
NU
3 2 1 28 27 26
25
24
23
22
21
20
19
PTG
12 13 14 15 16 17 18
LP
NC
REF
PLC
POV
PLD
VCC
NC
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
VTX
AGND
RSN
RRLY
HP
NC
28- pi n PLCC
DT
DR
NU
C2
C1
DET
FlexiSLIC
PBL 38630/2
Pin Configuration
Data Sheet 12 Rev. 2.0, 2005-04-14
4 5 RINGX –The RINGX pin connects to the ring lead of
the two-wire interface via over voltage
protection components and ring relay (and
optional test relay).
5 6 BGND –Battery ground, should be tied together with
AGND.
6 7 TIPX –The TIPX pin connects to the tip lead of the
two-wire interface via over voltage protection
components and ring relay (and optional test
relay).
7 8 VBAT –Battery supply voltage. Negative with respect
to GND.
8 9 VBAT2 –An optional second (2) Battery Voltage
connects to this pin via an external diode.
910 PSG –Programmable saturation guard. The
resistive part of the DC feed characteristics is
programmed by a resistor connected from
this pin to VBAT.
10 12 LP –Connection for low pass filter capacitor, CLP.
Other end of CLP connects to VBAT.
11 13 DT IInput to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
12 14 DR IInput to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
13 15 NU –Pin not used. Must be connected to AGND.
14 16 C2 IC1and C2 are digital inputs (positive logic,
internal pull-up), which control the SLIC
operating states. Refer to Table 2 for details.
15 17 C1 I
Table 1 Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name Pin
Type
Function
FlexiSLIC
PBL 38630/2
Pin Configuration
Data Sheet 13 Rev. 2.0, 2005-04-14
16 18 DET ODetector output. Active low when indicating
loop or ring-trip detection, active high when
indicating ground key detection.
17 20 VCC –+5 V power supply.
18 21 PLD –Programmable loop detector threshold. The
loop detection threshold os programmed by a
resistor connected from this pin to AGND.
19 22 POV –Programmable overhead voltage. If pin is left
open: The overhead voltage is internally set
to min 2.7 V in off- hook and min 1.1 V in on-
hook. If a resistor is connected between this
pin and AGND: The overhead voltage can be
set to higher values.
20 23 PLC –Programmable line current, the constant
current part of the DC feed characteristic is
programmed by a resistor connected from
this pin to AGND.
21 24 REF –A reference, 49.9 kΩ, resistor should be
connected from this pin to AGND.
22 26 RSN –Receive summing node. 200 times the AC
current flowing into this pin equals the
metallic (transversal) AC current flowing from
RINGX to TIPX. Programming networks for
two-wire impedance and receive gain
connect to the receive node. A resistor should
be connected from this pin to AGND.
23 27 AGND –Analog ground, should be tied together with
BGND.
Table 1 Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name Pin
Type
Function
FlexiSLIC
PBL 38630/2
Pin Configuration
Data Sheet 14 Rev. 2.0, 2005-04-14
24 28 VTX OTransmit vf output. The AC voltage difference
between TIPX and RINGX, the AC metallic
voltage, is reproduced as an unbalanced
GND referenced signal at VTX with a gain of
one (or one half, see pin PTG). The two-wire
impedance programming network connects
between VTX and RSN.
–4, 11, 19,
25
NC –Not Connected.
Table 2 SLIC Operating States
State C2 C1 SLIC Operating
State
Active Detector
(DET Response)
0 00Open circuit No active detector
(DET is set high)
1 01Ringing Ring-trip detector
(DET active low)
2 10Active Loop detector
(DET active low)
3 11Not applicable –
Table 1 Pin Definition and Functions (cont’d)
PDSO
SSOP
Pin No.
PLCC
Pin No.
Name Pin
Type
Function
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 15 Rev. 2.0, 2005-04-14
3 Electrical Characteristics
Table 3 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
Temperature, Humidity
Storage temperature range TStg -55 –150 °C –
Operating temperature
range
TAmb -40 –110 °C –
Operating junction
temperature range1)
TJ-40 –140 °C –
Power Supply (-40 °C ≤ TAmb ≤ +85 °C)
VCC with respect to A/BGND VCC -0.4 –6.5 V –
VBAT2 with respect to
A/BGND
VBAT2 VBAT –0.4 V –
VBAT with respect to
A/BGND, continuous
VBAT -75 –0.4 V –
VBAT with respect to
A/BGND, 10 ms
VBAT -80 –0.4 V –
Power Dissipation
Continuous power
dissipation
PD– – 1.5 WTAmb ≤ +85
°C
Ground
Voltage between AGND and
BGND
VG-0.3 –0.3 V –
Relay Driver
Ring relay supply voltage – – – BGND
+14
V –
Ring Trip Comparator
Input voltage VDT, VDR VBAT -AGND V –
Input current IDT, IDR -5 - 5 mA –
Digital Inputs, Outputs (C1, C2, DET)
Input voltage VID -0.4 –VCC V –
Output voltage VOD -0.4 –VCC V –
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 16 Rev. 2.0, 2005-04-14
Attention: Stresses above those values listed here may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these
values may cause irreversible damage to the integrated circuit.
TIPX and RINGX Terminals (-40 °C ≤ TAmb ≤ +85 °C, VBAT = -50 V)
TIPX or RINGX current ITIPX,
IRINGX
-100 –100 mA –
TIPX or RINGX voltage,
continuous (referenced to
AGND)2)
VTA, VRA -80 – 2 V –
TIPX or RINGX2) VTA, VRA VBAT
- 10
– 5 V pulse <
10 ms,
tRep > 10 s
TIPX or RINGX2) VTA, VRA VBAT
- 25
–10 Vpulse < 1 µs,
tRep > 10 s
TIP or RING2)3) VTA, VRA VBAT
- 35
–15 Vpulse <
250 ns,
tRep > 10 s
1) The circuit includes thermal protection. Operation above max. junction temperature may degrade device
reliability.
2) With the diodes DVB and DVB2 included, see Figure 8.
3) RF1 and RF2 > 20 Ω is also required. Pulse is supplied to RING and TIP outside RF1 and RF2.
Table 4 Operating Range
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
Ambient temperature TAmb -40 –85 °C –
VCC with respect to AGND VCC 4.75 –5.25 V –
VBAT with respect to AGND VBAT -58 –-8 V –
AGND with respect to BGND VG-100 –100 mV –
Table 3 Absolute Maximum Ratings (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 17 Rev. 2.0, 2005-04-14
3.1 Characterictics
The specification is made with following setup: -40 °C ≤ TAmb ≤ +85 °C, PTG = open (see
pin description), VCC = +5 V ± 5%, VBAT = -58 V to -40 V, VBAT2 = -32 V, RLC = 32.4 kΩ,
IL = 27 mA, RL = 600 Ω, RF1 = RF2 = 0, RREF = 49.9 kΩ, CHP = 47 nF, CLP = 0.15 µF,
RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ, ROV = infinite.
Current definition: current is positive if flowing into a pin unless stated otherwise.
Table 5 Characteristics
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
Two-Wire Port
Overhead level1),
18 mA ≤ ILDC
Active, 1% THD
ROV = infinite
see Figure 3
VTRO 2.7 – – VPeak –
1.1 – – VPeak On-Hook,
ILDC ≤ 5 mA
Input impedance2) ZTRX –ZT/
200
–Ω–
Longitudinal impedance ZLOT,
ZLOR
–20 35 Ω/wire 0 < f < 100 Hz
Longitudinal current limit ILOT,
ILOR
28 – – mArms/
wire
Active
Longitudinal to metallic
balance (IEEE standard
455-1985), ZTRX = 736 Ω
BLM 63 66 –dB 0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60 66 0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
55 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 18 Rev. 2.0, 2005-04-14
Longitudinal to metallic
balance
BLME = 20 × log|ELO/VTR|,
see Figure 4
BLME 63 66 –dB 0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60 66 0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
55 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Longitudinal to four-wire
balance
BLFE = 20 × log|ELO/VTX|,
see Figure 4
BLFE 63 66 –dB 0.2 kHz ≤ f ≤
1.0 kHz
TAMB 0-70 oC
60 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB 0-70 oC
60 66 0.2 kHz ≤ f ≤
1.0 kHz
TAMB -40-85 oC
55 66 –dB 1.0 kHz < f <
3.4 kHz
TAMB -40-85 oC
Metallic to longitudinal
balance
BMLE = 20 × log|VTR/VLO|,
ERX = 0 V, see Figure 5
BMLE 40 50 –dB 0.2 kHz < f <
3.4 kHz
Four-wire to longitudinal
balance
BFLE = 20 × log|ERX/VLO|,
see Figure 5
BFLE 40 50 –dB 0.2 kHz < f <
3.4 kHz
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 19 Rev. 2.0, 2005-04-14
Two-wire return loss3) r30 35 –dB 0.2 kHz < f <
1.0 kHz
20 22 –dB 1.0 kHz < f <
3.4 kHz
TIPX idle voltage VTI –-1.3 – V Active, IL < 5 mA
RINGX idle voltage VRI –VBAT+
3.0
– V Active, IL < 5 mA
Open loop voltage VTR –VBAT+
4.3
– V Active, IL < 5 mA
Four-Wire Transmit Port (VTX)
Overhead level4),
Load imp. > 20 kΩ
1% THD
see Figure 6
VTXO 2.7 – – VPeak IL > 18 mA
1.1 – – VPeak On-Hook, IL ≤
5 mA,
Output offset voltage ∆VTX -100 –100 mV –
Output impedance ZTX –15 50 Ω0.2 kHz < f <
3.4 kHz
Four-Wire Receive Port (receive summing node = RSN)
RSN DC voltage VRSNdc 1.15 1.25 1.35 VIRSN = -55 µA
RSN impedance –820 Ω0.2 kHz < f <
3.4 kHz
RSN current (IRSN ) to
metallic loop current (IL)
gain
αRSN –200 –ratio 0.3 kHz < f <
3.4 kHz
Frequency Response
Two-wire to four-wire,
relative to 0 dBm,
1.0 kHz, ERX = 0 V,
see Figure 7
g2-4 -0.20 –0.10 dB 0.3 kHz < f <
3.4 kHz
-1.0 –0.1 dB f = 8 kHz, 12 kHz,
16 kHz
Four-wire to two-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
g4-2 -0.2 –0.1 dB 0.3 kHz < f <
3.4 kHz
-1.0 – 0 dB f = 8 kHz, 12 kHz
-2.0 – 0 dB f = 16 kHz
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
r20 log×ZTRX ZL
+
ZTRX ZL
–
------------------------
=
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 20 Rev. 2.0, 2005-04-14
Four-wire to four-wire,
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
g4-4 -0.2 –0.1 dB 0.3 kHz < f <
3.4 kHz
Insertion Loss
Two-wire to four-wire5),
G2-4 = 20 × log|VTX/VTR|
0 dBm, 1.0 kHz
ERX = 0 V
G2-4 -0.2 –0.2 dB PTG = Open
see Figure 7
-6.22 -6.02 -5.82 dB PTG = AGND
Four-wire to two-wire6),
G4-2 = 20 × log|VTR/VRX|,
EL = 0 V, see Figure 7
G4-2 -0.2 – 0.2 dB 0 dBm, 1.0 kHz
Gain Tracking
Two-wire to four-wire7),
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1 –0.1 dB -40 dBm to
+3 dBm
-0.2 –0.2 dB -55 dBm to -
40 dBm
Four-wire to two-wire,
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1 –0.1 dB -40 dBm to
+3 dBm
-0.2 –0.2 dB -55 dBm to -
40 dBm
Noise
Idle channel noise at
two-wire port8) (TIPX-
RINGX) or four-wire
(VTX) output
––12 dBrnC C-message
weighting
––-78 dBmp Psophometrical
weighting
Harmonic Distortion
Two-wire to four-wire,
see Figure 7
–-67 -50 dB 0 dBm
0.3 kHz < f <
3.4 kHz
Four-wire to two-wire –-67 -50 dB
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 21 Rev. 2.0, 2005-04-14
Battery Feed Characteristics
Loop current in the
current limited region,
reference A, B & C
see Figure 12
IL0.92
×
IL
IL1.08
×
IL
mA 18 mA ≤ IL ≤ 45 mA
Open circuit loop current ILOC -100 0100 µARL = 0 Ω
Loop Detector
Programmable
threshold,
ILTh = 500/RLD
ILTh 0.85
×
ILTh
ILTh 1.15
×
ILTh
mA RLD in kΩ,
7 mA ≤ ILTh
Ringing Trip Comparator
Offset voltage ∆VDTDR -20 020 mV Source
resistance,
RS = 0 Ω
Input bias current IB-200 -20 200 nA IB=(IDT +IDR)/2
Input common mode
range
VDT, VDR VBAT
+1
–-1 V –
Ring Relay Driver
Saturation voltage VOL –0.2 0.5 VIOL = 50 mA
Off state leakage current ILK ––10 µAVOH = 12 V
Digital Inputs (C1, C2)
Input low voltage VIL 0–0.5 V –
Input high voltage VIH 2.5 –VCC V –
Input low current IIL ––-50 µAVIL = 0.5 V
Input high current IIH ––50 µAVIH = 2.5 V
Detector Output (DET)
Output low voltage VOL –– 0.7 VIOL = 0.5 mA
Internal pull-up resistor
to VCC
–15 – kΩ–
Power Dissipation (VBAT -48 V, VBAT2 = -32 V)
Power Dissipation P1–10 15 mW Open circuit
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 22 Rev. 2.0, 2005-04-14
Power Dissipation P2–65 85 mW Active (On-hook)
Long current =
0 mA
Power Dissipation P3–730 –mW Active (Off-hook)
RL = 300 Ω
Power Dissipation P4–360 –mW Active (Off-hook)
RL = 800 Ω
Power Supply Currents (VBAT = -48 V)
VCC current ICC –1.2 2.0 mA Open circuit (C1,
C2, C3 = 0)
VBAT current IBAT -0.1 -0.05 –mA Open circuit (C1,
C2, C3 = 0)
VCC current ICC –2.8 4.0 mA Active, On-hook,
Long current =
0 mA
VBAT current IBAT -1.5 -1.0 –mA Active, On-hook,
Long current =
0 mA
Power Supply Rejection Ratios
VCC to 2- or 4-wire port 30 42 –dB Active, f = 1 kHz,
Vn = 100 mV
VBAT2 to 2- or 4-wire port 40 60 –dB Active, f = 1 kHz,
Vn = 100 mV
VBAT to 2- or 4-wire port 36 45 –dB Active, f = 1 kHz,
Vn = 100 mV
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 23 Rev. 2.0, 2005-04-14
Temperature Guard
Junction threshold
temperature
TJG –145 – °C –
Thermal Resistance
24-pin SSOP Rth, jp – 55 –°C/W –
Rth, jA –66.9 –°C/W P-/PG-SSOP-24-
1,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
24-pin PDSO Rth, jp – 43 –°C/W –
Rth, jA –50.3 –°C/W P-/PG-DSO-24-8,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
28-pin PLCC Rth, jp – 39 –°C/W –
Rth, jA –50.4 –°C/W P-/PG-LCC-28-3,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
1) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the two-wire port with the signal source at the four-wire receive port.
Table 5 Characteristics (cont’d)
Parameter Symbol Values Unit Note/Test
Condition
Min. Typ. Max.
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 24 Rev. 2.0, 2005-04-14
Figure 3 Overhead Level, VTRO, Two-Wire Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
2) The two-wire impedance is programmable by selection of external component values according to:
ZTRX = ZT/(|G2-4S × αRSN|) where:
ZTRX = impedance between the TIPX and RINGX terminals
ZT = programming network between the VTX and RSN terminals
G2-4S = transmit gain, nominally = 1 (or 0.5, see pin PTG)
αRSN = receive current gain, nominally 200 (current defined as positive flowing into the receive summing node,
RSN, and when flowing from ring to tip).
3) Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating
impedance programming resistance, for example by dividing RT into two equal halves and connecting a
capacitor from the common point to ground.
4) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the four-wire transmit port, (VTX) with the signal source at the two-wire port. Note that the gain
from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5, see pin PTG).
5) Pin PTG = Open sets transmit gain to nom. 0.0 dB.
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistor RF (see Figure 8) impacts the insertion loss as explained in Chapter 5. The
specified insertion loss is valid for RF = 0.
6) The specified insertion loss tolerance does not include errors caused by external components.
7) The level is specified at the two-wire port.
8) The two-wire idle noise is specified with the port terminated in 600 Ω (RL), and with the four-wire receive port
grounded (ERX = 0; see Figure 7). The four-wire idle noise at VTX is specified with the two-wire port terminated
in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX.
The four-wire receive port is grounded (ERX = 0).
PBL 38630
TIPX
RINGX
VTX
RSN
R
T
R
RX
Fig3_3
0
C
R
L
V
TRO
E
RX
I
LDC
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 25 Rev. 2.0, 2005-04-14
Figure 4 Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
Figure 5 Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
Figure 6 Overhead Level, VTXO, Four-Wire Transmit Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
PBL 38630
TIPX
RINGX
VTX
RSN
Fig4_30
C
V
TR
R
LT
R
LR
E
LO
R
T
R
RX
V
TX
PBL 38630
TIPX
RINGX
VTX
RSN
R
T
R
RX
Fig5_30
C
V
TR
E
RX
R
LT
R
LR
V
LO
PBL 38630
TIPX
RINGX
VTX
RSN
R
T
R
RX
Fig6_3
0
V
TXO
C
R
L
E
L
I
LDC
FlexiSLIC
PBL 38630/2
Electrical Characteristics
Data Sheet 26 Rev. 2.0, 2005-04-14
Figure 7 Frequency Response, Insertion Loss, Gain Tracking
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
PBL 38630
TIPX
RINGX
VTX
RSN
R
T
R
RX
Fig7_3
0
V
TX
C
R
L
E
L
V
TR
E
RX
I
LDC
FlexiSLIC
PBL 38630/2
Application Schematic
Data Sheet 27 Rev. 2.0, 2005-04-14
4 Application Schematic
Figure 8 Application Example of PBL 38630/2 with SICOFI®4 Codec
VB
OVP
VB
R
F1
C
GG
C
TC
NC
DET
C1
C2
PSG
NC
LP
DT
AGND
RSN
NC
REF
NC
RRLY
HP
RINGX
PTG VTX
PBL38630
POV
BGND PLC
PLD
VCC
TIPX
VBAT
VBAT2
TIP
RING
C
2
DR NU
C
HP
sch_30
K
R
C
RC
R
F2
+5 /
+12 V
R
3
R
4
C
1
R
1
R
2
C
LP
R
SG
SLIC No.2 etc
D
VB2
D
VB
VB2
D
BB
C
VB2
C
VB
R
RT
E
RG
VCC
SYSTEM CONTROL
INTERFACE
C
VCC
R
REF
R
LC
R
OV
R
LD
R
TX
R
RX
R
T
R
B
R
R
C
TX
SICOFI
®
4
Codec
V
IN
V
OUT
FlexiSLIC
PBL 38630/2
Application Schematic
Data Sheet 28 Rev. 2.0, 2005-04-14
4.1 Recommended Components
Table 6 Resistors
Resistor Value Tolerance Specification
RSG 0 Ω–1/10 W
RLD 49.9 kΩ1% 1/10 W
ROV User programmable – –
RLC 32.4 kΩ1% 1/10 W
RREF 49.9 kΩ1% 1/10 W
RR22.7 kΩ1% 1/10 W
RT51 kΩ1% 1/10 W
RRX 51 kΩ1% 1/10 W
RTX 3.6 kΩ1% 1/10 W
RB6.2 kΩ1% 1/10 W
R1604 kΩ1% 1/10 W
R2604 kΩ1% 1/10 W
R3249 kΩ1% 1/10 W
R4280 kΩ1% 1/10 W
RRT 330 Ω5% 2 W
RF1, RF2 Line resistor, 40 Ω1% –
Table 7Capacitors
Capacitor Value Tolerance Specification
CVB 100 nF 10% 100 V
CVB2 150 nF 10% 100 V
CTC 2.2 nF 10% 100 V
CRC 2.2 nF 10% 100 V
CHP 47 nF 10% 100 V
CVCC 100 nF 10% 10 V
CLP 150 nF 10% 100 V
CTX 100 nF 10% 10 V
CGG 220 nF 10% 100 V
FlexiSLIC
PBL 38630/2
Application Schematic
Data Sheet 29 Rev. 2.0, 2005-04-14
OVP
Secondary protection (Bournes TISP PBL2). The ground terminals of the secondary
protection should be connected to the common ground on the Printed Board Assembly
with a track as short and wide as possible, preferably to a ground plane.
4.2 Design Supporting Tools
The following supporting tools are available for the PBL 38630/2:
• Test board TB208 for PLCC package
• Test board TB208SSOP for SSOP package
• Pspice model for PBL 38630/2
C1330 nF 10% 63 V
C2330 nF 10% 63 V
Table 8 Diodes
Diode Value Tolerance Specification
DVB 1N4448
DVB2 1N4448
DBB 1N4448
Table 7 Capacitors (cont’d)
FlexiSLIC
PBL 38630/2
Transmission
Data Sheet 30 Rev. 2.0, 2005-04-14
5 Transmission
5.1 General
A simplified AC model of the transmission circuit is shown in Figure 9.
Figure 9 Simplified AC Model of PBL 38630/2
Circuit analysis from the AC model in Figure 9 yields following equations:
[1]
[2]
[3]
EL
RF
RF
ZTR
TIP
VTX
HP
RINGXRING
ZL
VTR +
_
G2-4S
IL
RHP
RSN
ZT
ZRX
VRX
VTX
ac_sch_30
IL
TIPX
PBL 38630
IL/αRSN
VTR
VTX
G24S–
----------------IL
+2RF
×=
IL
αRSN
-------------VTX
ZT
--------- VRX
ZRX
----------+=
VTR ELILZL
×–=
FlexiSLIC
PBL 38630/2
Transmission
Data Sheet 31 Rev. 2.0, 2005-04-14
where:
5.2 Two-Wire Impedance
To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the
fuse resistor RF, let VRX = 0.
From Equation [1] and Equation [2]:
[4]
Thus with ZTR, G2-4S, αRSN and RF known:
[5]
5.3 Two-Wire to Four-Wire Gain
From Equation [1] and Equation [2] with VRX = 0:
[6]
VTX Is the ground referenced version of the AC metallic voltage between the
TIPX and RINGX terminals.
VTR Is the AC metallic voltage between TIP and RING.
ELIs the line open circuit AC metallic voltage.
ILIs the AC metallic current.
RFIs a fuse resistor.
G2-4S Is the programmable SLIC two-wire to four-wire gain (transmit
direction)1).
1) The SLIC two-wire to four-wire gain, G2-4S, is user programmable between two fixed values. See Table 5.
ZLIs the line impedance.
ZRX Controls four- to two-wire gain.
ZTDetermines the SLIC TIPX to RINGX impedance at voice frequencies.
VRX Is the analog ground referenced receive signal.
αRSN Is the receive summing node current to metallic loop current gain.
αRSN = 200
ZTR
ZT
αRSN G×24S–
----------------------------------- 2 RF
+=
ZTαRSN G24S–ZTR 2RF
–()××=
G24–
VTX
VTR
--------- ZTαRSN
⁄
ZT
αRSN G×24S–
----------------------------------- 2 RF
+
----------------------------------------------------
==
FlexiSLIC
PBL 38630/2
Transmission
Data Sheet 32 Rev. 2.0, 2005-04-14
5.4 Four-Wire to Two-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
[7]
For applications where
[8]
the expression for G4-2 simplifies to:
[9]
5.5 Four-Wire to Four-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
[10]
5.6 Hybrid Function
The hybrid function can easily be implemented utilizing the uncommitted amplifier in
conventional non software programmable codec/filters. Please, refer to Figure 10. Via
impedance ZB a current proportional to VRX is injected into the summing node of the
combination codec/filter amplifier. As can be seen from the expression for the four-wire
to four-wire gain, G4-4, a voltage proportional to VRX is returned to VTX. This voltage is
converted by RTX to a current flowing into the same summing node. These currents can
be cancelled by letting:
[11]
G42–
VTR
VRX
----------ZT
ZRX
--------- 1
G24S–
----------------
×ZL
ZT
αRSN G×24S–
----------------------------------- ZL2RF
++
-----------------------------------------------------------------
×–==
ZT
αRSN G×24S–
----------------------------------- 2 RFZL
=+
G42–
ZT
ZRX
---------
–1
2G
24S–
×
-------------------------
×=
G44–
VTX
VRX
----------ZT
ZRX
--------- ZL2RF
+
ZT
αRSN G×24S–
----------------------------------- ZL2RF
++
-----------------------------------------------------------------
×–==
VTX
RTX
--------- VRX
ZB
----------0=+ EL0=()
FlexiSLIC
PBL 38630/2
Transmission
Data Sheet 33 Rev. 2.0, 2005-04-14
The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the
balance network ZB can be calculated from:
[12]
When selecting the RTX resistance value, make sure the load resistance on the VTX
terminal is at least 20 kΩ.
If calculation of the ZB formula above yields a balance network containing an inductor,
please contact Infineon‘s support group for assistance.
The PBL 38630/2 SLIC may also be used together with programmable CODEC/filters.
The programmable CODEC/filter allows for system controller adjustment of hybrid
balance to accomodate different line impedances without change of hardware. In
addition, the transmit and receive gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets for design information.
Figure 10 Hybrid Function
ZBRTX
VRX
VTX
----------
×RTX
ZRX
ZT
---------
×
ZT
αRSN G×24S–
----------------------------------- ZL2RF
++
ZL2RF
+
-----------------------------------------------------------------
×=–=
Codec/Filter
VTX
RSN
Z
T
Z
RX
Hybrid_30
PBL 38630
R
TX
Z
B
V
RX
R
FB
V
T
Z
R
FlexiSLIC
PBL 38630/2
Transmission
Data Sheet 34 Rev. 2.0, 2005-04-14
5.7 Longitudinal Impedance
A feedback loop within the SLIC counteracts longitudinal voltages at the two-wire port by
injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will
appear as longitudinal currents and the TIPX and RINGX terminals will experience very
small longitudinal voltage excursions, leaving metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per wire, ZLOT and ZLOR, appears as typically 20 Ω to
longitudinal disturbances. It should be noted that longitudinal currents may exceed the
DC loop current without disturbing the VF transmission.
5.8 Capacitors CTC and CRC
The capacitors designated CTC and CRC in Figure 8, connected between TIPX and
ground as well as between RINGX and ground, can be used for RFI filtering. The
recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be
used, but care must be taken to prevent degradation of either longitudinal balance or
return loss. CTC and CRC contribute to a metallic impedance of 1/(π × f × CTC) =
1/(π × f × CRC), a TIPX to ground impedance of 1/(2π × f × CTC) and a RINGX to ground
impedance of 1/(2π × f × CRC).
5.9 AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected between terminals HP and TIPX provides the
separation of the AC and DC signals, such that only AC signals are forwarded to the VTX
terminal. CHP positions the low end frequency response break point of the AC feedback
loop in the SLIC. A CHP value of 150 nF will position the low end frequency response
3 dB break point of the AC loop at 1.8 Hz (f3dB) according to f3dB = 1/(2π × RHP × CHP)
where RHP = 600 kΩ (see Table 9).
5.10 High-pass Transmit Filter
The capacitor CTX in Figure 8 connected between the VTX output and the CODEC/filter
forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a
high-pass RC filter. It is recommended to position the 3 dB break point of this filter
between 30 and 80 Hz to get a faster response for the DC steps that may occur at DTMF
signalling.
5.11 Capacitor CLP
The capacitor CLP, which connects between the terminals LP and VBAT, positions the
high end frequency break point of the low pass filter in the DC feedback loop (battery
feed controlling loop) of the SLIC. CLP together with CHP and ZT(see Chapter 5.2) forms
the total two-wire output impedance of the SLIC. The choice of these programmable
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 35 Rev. 2.0, 2005-04-14
components have an influence on the power supply rejection ratio (PSRR) from VBAT
to the two-wire side at sub audio frequencies.At these frequencies CLP also influences
the transversal to longitudinal balance in the SLIC. Table 9 suggests a suitable value for
CLP. The typical value of the transversal to longitudinal balance at 200 Hz is given in the
table below, for the chosen value of CLP.
6 Battery Feed
The PBL 38630/2 SLIC emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with adjustable current limitation. In the current limited region the loop
current has a slight slope corresponding to 2x30 Ω, see Figure 12 reference B.
The open loop voltage measured between the TIPX and RINGX terminals tracks the
battery voltage VBAT. The signalling headroom, or overhead voltage VTRO, is
programmable with a resistor ROV connected between terminal POV on the SLIC and
ground. Please refer to Chapter 6.2. The battery voltage overhead,VOH, depends on the
programmed signal overhead voltage VTRO. VOH defines the TIP and RING voltage at
open loop conditions according to
VTR(at IL = 0 mA) = |VBAT| - VOH
Refer to Table 10 for the typical value of VOH and VOHvirt. The overhead voltage is
changed when line corrent is approaching open loop conditions. To ensure maximum
open loop voltage, even with a leaking telephone line, this occurs at a line current of
approximately 6 mA. When the overhead voltage has changed, the line voltage is kept
nearly constant with a steep slope corresponding to 2x25 Ω (reference G in Figure 12).
The virtual battery overhead, VOHvirt , is defined as the difference between the battery
voltage and the crossing point of all possible resistive feeding slopes, see Figure 12
reference J. The virtual battery overhead is a theoretical constant needed to be able to
calculate the feeding characteristics.
Table 9 Feeding Setup
Symbol Value Unit
RFeed 2x50 2x200 2x400 2x800 Ω
RSG 060.4 147 301 kΩ
CLP 150 100 47 22 nF
T-L bal. @
200 Hz
-46 -46 -43 -36 dB
CHP 47 150 150 150 nF
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 36 Rev. 2.0, 2005-04-14
The resistive loop feed (reference D in Figure 12) is programmed by connecting a
resistor, RSG , between terminals PSG and VBAT according to the equation:
[13]
where RFeed is in Ω for RSG and RF in Ω.
The current limit (reference C in Figure 12) is adjusted by connecting a resistor, RLC,
between terminal PLC and ground according to the equation:
[14]
where RLC is in kΩ for ILProg in mA.
A second lower battery voltage may be connected to the device at terminal VBAT2 to
reduce short loop power dissipation.
The SLIC automatically switches between the two battery supply voltages without need
for external control. the silent battery switching occurs when the line voltage passes the
value
|VB2| - 40 × IL - (VOHvirt - 1.3), if IL > 6 mA.
For correct functionality it is important to connect the terminal VBAT2 to the second power
supply via the diode DVB2, see Figure 8. An optional diode DBB connected between
terminal VB and the VB2 power supply, see Figure 8, will make sure that the SLIC
continues to work on the second battery even if the first battery voltage disappears. If a
second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and CVB2, DBB
and DVB2 are removed.
6.1 CODEC Receive Interface
The PBL 38630/2 SLIC has got a receive interface at the four- wire side which makes it
possible to reduce the number of capacitors in the applications and to fit both single and
dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output
via the resistor RRX, is DC biased with +1.25 V. This makes it possible to compensate for
currents floating due to DC voltage differences between RSN and the CODEC output
without using any capacitors. This is done by connecting a resistor RR between the RSN
Table 10 Battery Overhead
Symbol Value (typ) Unit Specification
VOH 3.0 + VTRO V –
VOHvirt 4.9 + VTRO V –
RFeed
RSG 24
×10+
200
------------------------------- 2 R F
+=
ILProg
1000
RLC
------------4.0–=
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 37 Rev. 2.0, 2005-04-14
terminal and ground. With current directions defined as in Figure 12, current summation
gives:
[15]
where VCODEC is the reference voltage of the CODEC at the receive output.
From this equation the resistor RR can be calculated as
[16]
For the value on IRSN, see Table 11.7
If RSN is DC decoupled from the CODEC output, then RRX can be considered to be
infinite.
The resistor RR has no influence in the AC transmission.
Figure 11 Codec Receive Interface
Table 11 Internal Bias Current of RSN
Symbol Value (typ) Unit
IRSN -55 µA
IRSN
–IRT IRRX IRR
++ 1.25
RT
---------- 1.25 VCODEC
–
RRX
---------------------------------------1.25
RR
----------++==
RR
1.25
IRSN
–1.25
RT
----------–1.25 VCODEC
–
RRX
---------------------------------------–
-------------------------------------------------------------------------------=
R
T
VTX
DC-GND
RSN
I
+1.25 R
R
R
RX
I
RSN
I
RT
I
RR
I
RX
+
_
U
REF c odec
CODEC
codecIF
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 38 Rev. 2.0, 2005-04-14
Figure 12 Battery Feed Characteristics
A
BRFeed = 2x30 kΩ
C
ILConst(typ) = ILProg =
VTR = |VBAT| - VOHvirt - RFeed x (ILProg + 4x10-3)
A
I
L
[mA]
B C
D
F
V
TR
[V]
bat f eed30
A CB
J
F
E
H
G
D
ILVTR 0V=()I=LProg
VBat VOHvirt
–RFeed ILProg 43–
×10+()×–
60 3
×10
---------------------------------------------------------------------------------------------------------------+
103
RLC
---------- 4 3–
×10–
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 39 Rev. 2.0, 2005-04-14
6.2 Programmable Overhead Voltage (POV)
With the POV function the overhead voltage can be increased. If the POV pin is left open
the overhead voltage is internally set to 3.2 VPeak in off-hook and 1.3 VPeak on-hook.. If a
resistor ROV is connected between the POV pin and AGND, the overhead voltage can be
set to higher values, typical values can be seen in Figure 13. The ROV and
corresponding VTRO (signal headroom) are typical values for THD < 1% and the signal
frequency 1000 Hz.
Observe that the four-wire output terminal VTX cannot handle more than 3.2 VPeak. So if
the two- to four-wire gain is 0 dB, 3.2 VPeak is maximum also for the two-wire side. Signal
levels between 3.2 and 6.4 VPeak on the two-wire side can be handled with the PTG
shorted so that the gain G2-4S becomes -6.02 dB. Please note that:
•ZT
•RR
•G4 - 4
has to be recalculated if the PTG is shorted.
Please note that the maximum signal current at the two-wire side can not be higher than
9 mA.
How to use POV:
1. Decide what overhead voltage (VTRO) is needed. The POV function is only needed if
the overhead voltage exceeds 3.2 VPeak.
2. In Figure 13 the corresponding ROV for the decided VTRO can be found.
3. If the overhead voltage exceeds 3.2 VPeak, the G2-4S gain has to be changed to -
6.02 dB by connecting pin PTG to AGND. Please note, that the 2-wire impedance,
RR and the 4-wire to 4-wire gain has to be recalculated.
D
EIL = 6 mA
FApparent battery VBat (@ IL = 0) = |VBAT| - VOHvirt - (RFeed x 4x10-3)
GRFeed = 2x25 Ω
HVTROpen = |VBAT| - VOH
JVirtual battery VBatVirt (@ IL = 4 mA) = |VBAT| - VOHvirt
RFeed
RSG 24
×10+
200
------------------------------- 2 R F
+=
FlexiSLIC
PBL 38630/2
Battery Feed
Data Sheet 40 Rev. 2.0, 2005-04-14
Figure 13 Programmable Overhead Voltage (POV). RL= 600 Ω or Infinite
6.3 Analog Temperature Guard
The widely varying environmental conditions in which SLICs operate may lead to the
chip temperature limitations being exceeded. The PBL 38630/2 SLIC reduces the DC
line current when the chip temperature reaches approximately 145 oC and increases line
current again automatically when the temperature drops. Accordingly transmission is not
lost under high ambient temperature conditions.
The detector output, DET, is forced to a logic low level when the temperature guard is
active.
0
1
2
3
4
5
6
7
0 5 10 15 20 25 30 35 40 45 50 55 60 65
R
ov
(Kohm)
V
TRO
(V
Peak
)
of f -hook
on-hook
POV
FlexiSLIC
PBL 38630/2
Loop Monitoring Functions
Data Sheet 41 Rev. 2.0, 2005-04-14
7 Loop Monitoring Functions
The loop current, ground key and ring-trip detectors report their status through a
common output, DET. The particular detector to be connected to the detector pin, DET,
is selected via the two bit control interface C1and C2. Please refer to Chapter 9 for a
description of the control interface.
7.1 Loop Current Detector
The loop current detector indicates that the telephone is off-hook and that DC current is
flowing in the loop by setting the output pin DET to a logic low level when selected. The
loop current detector threshold value, ILTh, where the loop current detector changes
state, is programmable with the RLD resistor. RLD connects between pin PLD and ground
and is calculated according to:
[17]
The loop current detector is internally filtered and is not influenced by the AC signal at
the two-wire side.
7.2 Ring Trip Detector
Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced
superimposed on VB or GND. The unbalanced ringing source may be applied to either
the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC
ring relay driver connects the ringing source to tip and ring.
The ring trip function is based on a polarity change at the comparator input when the line
goes off-hook. In the on-hook state no DC current flows through the loop and the voltage
at comparator input DT is more positive than the voltage at input DR. When the line goes
off-hook, while the ring relay is energized, DC current flows and the comparator input
voltage reverses polarity.
Figure 8 gives an example of a ring trip detector network. This network is applicable
when the ring voltage is superimposed on VB and is injected on the ring lead of the two-
wire port. The DC voltage across sense resistor RRT is monitored by the ring trip
comparator input DT and DR via the network R1,R2 ,R3 ,R4 ,C1 and C2.
When the line is on-hook (no DC current), DT is more positive than DR and the DET
output will report logic level high, that is the detector is not tripped. When the line goes
off-hook, while ringing, a DC current will flow through the loop including sense resistor
RRT and will cause input DT to become more negative than input DR. This changes
output DET to logic level low, that is tripped detector conditions. The system controller
(or line card processor) responds by de-energizing the ring relay, that is ring trip.
RLD
500
ILth
----------=
FlexiSLIC
PBL 38630/2
Relay Driver
Data Sheet 42 Rev. 2.0, 2005-04-14
Complete filtering of the 20 Hz AC component at terminal DT and DR is not necessary.
A toggling DET output can be examined by a software routine to determine the duty
cycle. When the DET output is at logic level low for more than half the time, off-hook
conditions is indicated.
8 Relay Driver
The PBL 38630/2 SLIC incorporates a ring relay driver designed as open collector (npn),
with a current sinking capability of 50 mA. The drive transistor emitter is connected to
BGND. The relay driver has an internal zener diode clamp for inductive kick back
voltages.
9 Control Inputs
The SLIC has two digital control inputs, C1 and C2 (see Table 2). A decoder in the SLIC
interprets the control input condition and sets up the commanded operating state. C1
and C2 are internally pulled up.
9.1 Open Circuit (C2, C1 = 0, 0)
In the Open Circuit state, the TIPX and RINGX line drive amplifiers as well as other circuit
blocks are powered down. This causes the SLIC to present a high impedance to the line.
Power dissipation is at a minimum and no detectors are active. DET output is set high.
9.2 Ringing (C2, C1 = 0, 1)
The ring relay driver and the ring trip detector are activated and the ring trip detector is
indicating off-hook with a logic low level at the detector output.
The SLIC is in the active normal state.
9.3 Active state
TIPX is the terminal closest to ground and sources loop current while RINGX is the more
negative terminal and sinks loop current. VF signal transmission is normal. The loop
current detector is activated. The loop current detector indicates off-hook with a logic low
level and the ground key detector is indicating active ground key with a logic high level
present at the detector output.
FlexiSLIC
PBL 38630/2
Overvoltage Protection
Data Sheet 43 Rev. 2.0, 2005-04-14
10 Overvoltage Protection
10.1 Overvoltage Protection - General
The SLIC must be protected against foreign voltages on the telephone line.
Overvoltages can result from lightning, AC power contact, induction and other causes.
Refer to Table 3, TIPX and RINGX terminals, for maximum continuous and transient
voltages that may be applied to the SLIC.
10.2 Secondary Protection
The circuit shown in Figure 8 utilizes series resistors (RF1, RF2) together with a
programmable overvoltage protector (OVP, for example Bournes TISP PBL2) as
secondary protection.
The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The
protector gate references the protection (clamping) voltage to the negative supply
voltage (that is the battery voltage, VB). As the protection voltage will track the negative
supply voltage the overvoltage stress on the SLIC is minimized.
Positive overvoltages are clamped to ground by a diode. Negative overvoltages are
initially clamped close to the SLIC negative supply rail voltage and the protector will
crowbar into a low voltage on-state condition, by firing an internal thyristor.
A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high
enough current to quickly turn on the thyristor in the protector. CGG should be placed
close to the overvoltage protection device. Without the capacitor even the low
inductance in the track to the VB supply will limit the current and delay the activation of
the thyristor clamp.
The fuse resistors RF serve the dual purposes of being non-destructive energy
dissipators when transients are clamped, and of being fuses when the line is exposed to
a power cross. If a PTC is choosen for RF, note that it is important to always use PTC’s
in series with resistors not sensitive to temperature, as the PTC will act as a capacitance
for fast transients and therefore will not protect the SLIC.
11 Power-Up Sequence
No special power-up sequence is necessary, except that ground has to be present
before all other power supply voltages.
12 Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout is essential for proper function. The
components connected to the RSN input should be placed in close proximity to that pin,
FlexiSLIC
PBL 38630/2
Printed Circuit Board Layout
Data Sheet 44 Rev. 2.0, 2005-04-14
such that no interference is injected into the receive summing node (RSN). Ground plane
surrounding the RSN pin is advisable.
Analog Ground (AGND) should be connected to Battery Ground (BGND) on the PCB, in
one point. The capacitors for the battery should be connected with short wide leads of
the same length.
FlexiSLIC
PBL 38630/2
Package Outlines
Data Sheet 45 Rev. 2.0, 2005-04-14
13 Package Outlines
The SLIC is provided in three different packages: 24-pin SSOP, 24-pin PDSO and 28-
pin PLCC.
13.1 24-pin SSOP Package
Figure 14 P-/PG-SSOP-24-1 (Plastic Shrink Small Outline Package)
GPS01027
2) Does not include dambar protrusion of 0.13 max.
1) Does not include plastic or metal protrusion of 0.15 max. per side
Index Marking
12
13
1
24
2)
1)
8˚ MAX.
C
±0.08
0.13
±0.05
1.73
1.99 MAX.
0.1
0.65
+0.08
-0.05
0.3 C
0.15 A
M
24x
±0.2
0.9
-0.06
+0.05
0.15
5.3
±0.1
B
7.8
+0.1
-0.05
0.2 24x
B
M
1)
±0.13
8.2 A
Y
ou can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
FlexiSLIC
PBL 38630/2
Package Outlines
Data Sheet 46 Rev. 2.0, 2005-04-14
13.2 24-pin PDSO Package
Figure 15 P-/PG-DSO-24-8 (Plastic Dual Small Outline Package)
Lead width can be 0.61 max. in dambar area
Does not include plastic or metal protrusion of 0.15 max. per side
Index Marking
1.27
+0.15
0.35
15.6
1
24
2)
-0.4
1) 12
0.2
13
24x
0.1
2.65 MAX.
0.2 -0.1
2.45 -0.2
0.4 +0.8
10.3 ±0.3
0.35 x 45˚
-0.2
7.6 1)
0.23
+0.09
MAX.8˚
1)
2)
gps05144
Y
ou can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
FlexiSLIC
PBL 38630/2
Package Outlines
Data Sheet 47 Rev. 2.0, 2005-04-14
13.3 28-pin PLCC Package
Figure 16 P-/PG-LCC-28-3 (Plastic Leaded Chip Carrier Package)
GPL01023
A B
1
28
±0.08
11.51
1)
12.45
±0.13
D
Index Marking
±0.07
0.73
1.27
±0.1
0.43 0.18 A-B
M
D28x
C
7.62
4.57 MAX.
3.05 MAX.
0.5 MIN.
0.1 C
0.25
±0.04
1.27 x 45˚
11.51
±0.081)
10.4
±0.5
12.45
±0.13
1) Does not include mold protrusion of 0.25 max. per side
1.45 x 45˚
Y
ou can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
http://www.infineon.com
Published by Infineon Technologies AG
