NC
IN−
NC
IN+
NC
THS4012
DORDGN†PACKAGE
(TOPVIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
−VCC
VCC+
2OUT
2IN−
2IN+
1
2
3
4
8
7
6
5
NULL
IN −
IN +
VCC−
NULL
VCC+
OUT
NC
THS4011
D,DGN,ORJGPACKAGE
(TOPVIEW)
NC − Nointernalconnection
Cross-sectionviewshowing
PowerPADoption(DGN)
†This packageisintheProductPreviewstageof
development. Pleasecontactyour localTIsalesof ficefor
availability.
192013 2
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
VCC+
NC
OUT
NC
NC
NULL
NC
NULL
NC
V
NC
NC
NC
NC
THS4011
FK PACKAGE
(TOPVIEW)
CC−
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
Check for Samples: THS4011,THS4012
1FEATURES
2• High Speed
– 290-MHz Bandwidth (G = 1, –3 dB)
– 310-V/ms Slew Rate
– 37-ns Settling Time (0.1%)
• Low Distortion
– THD = –80 dBc (f = 1 MHz, RL= 150 Ω)
• 110-mA Output Current Drive (Typical)
• 7.5-nV/√Hz Voltage Noise
• Excellent Video Performance
– 70-MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
• ±5-V to ±15-V Supply Voltage
• Available in Standard SOIC, MSOP
PowerPAD™, JG, or FK Packages
• Evaluation Module Available
DESCRIPTION
The THS4011 and THS4012 are high-speed,
single/dual, voltage feedback amplifiers ideal for a
wide range of applications. The devices offer good ac
performance, with 290-MHz bandwidth, 310-V/ms
slew rate, and 37-ns settling time (0.1%). These
amplifiers have a high output drive capability of 110
mA and draw only 7.8-mA supply current per
channel. For applications requiring low distortion, the
THS4011/4012 operate with a total harmonic
distortion (THD) of -80 dBc at f = 1 MHz. For video
applications, the THS4011/4012 offer 0.1-dB gain
flatness to 70 MHz, 0.006% differential gain error,
and 0.01° differential phase error.
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/4012 290-MHz low-distortion high-speed amplifiers
THS4031/4032 100-MHz low-noise high-speed-amplifiers
THS4061/4062 180-MHz high-speed amplifiers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
−40
−50
−60
−70
−80
−90
100k 1M 10M
f − Frequency − Hz
−100
Distortion − dB
−110
2ndHarmonic
VCC =±15V
RL=150 Ω
G=2
3rdHarmonic
DISTORTION
vs
FREQUENCY
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES(1) PACKAGED DEVICES
NUMBER OF MSOP EVALUATION
TAPLASTIC SMALL PLASTIC MSOP(2) CERAMIC DIP CHIP CARRIER
CHANNELS SYMBOL MODULE
OUTLINE(2) (D) (DGN) (JG) (FK)
1 THS4011CD THS4011CDGN TIACI — — THS4011EVM
0°C to
70°C 2 THS4012CD THS4012CDGN(3) TIABY — — THS4012EVM
1 THS4011ID THS4011DGN TIACJ — — —
–40°C to
85°C 2 THS4012ID THS4012IDGN(3) TIABZ — — —
–55°C to 1 — — — THS4011MJG THS4011MFK —
125°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
(3) This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
2Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
OUT
8
6
1
IN−
IN+
2
3
Null
−
+
1OUT
1IN−
1IN+
VCC
2OUT
2IN−
2IN+
−VCC
8
6
1
2
3
5
7
4
−
+
−
+
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
FUNCTIONAL BLOCK DIAGRAM
Figure 1. THS4011 – Single Channel
Figure 2. THS4012 – Dual Channel
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
VCC Supply voltage ±16.5 V
VIInput voltage ±VCC
IOOutput current 175 mA
VID Differential input voltage ±4 V
Continuous total power dissipation See Dissipation Rating Table
TJMaximum junction temperature 150 °C
THS401xC 0 to 70 °C
TAOperation free-air temperature range THS401xI –40 to 85 °C
THS4011M –55 to 125 °C
Tstg Storage temperature range –65 to 150 °C
DISSIPATION RATINGS
qJA qJC TA= 25°C
PACKAGE (°C/W) (°C/W) POWER RATING
D 167(1) 38.3 740 mW
DGN(2) 58.4 4.7 2.14 W
JG 119 28 1050 mW
FK 87.7 20 1375 mW
(1) This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC-proposed High-K test
PCB, the qJA is 95°C/W with a power rating at 1.32 W at TA= 25°C.
(2) This data was taken using 2-oz trace and copper pad that is soldered directly to a 3-in × 3-in PC. For
further information, refer to the Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Split supply ±4.5 ±16
VCC Supply voltage V
Single supply 9 32
C suffix 0 70
TAOperating free-air temperature I suffix –40 85 °C
M suffix –55 125
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Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
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SLOS216E –JUNE 1999–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS
VCC = ±15 V, RL= 150 Ω, TA= 25°C (unless otherwise noted) THS4011C/I
THS4012C/I
PARAMETER TEST CONDITIONS(1) UNIT
TYP
DYNAMIC PERFORMANCE
VCC = ±15 V 290
Unity-gain bandwidth (–3 dB) Gain = 1 MHz
VCC = ±5 V 270
VCC = ±15 V 70
BW Bandwidth for 0.1-dB flatness Gain = 1 MHz
VCC = ±5 V 35
VCC = ±15 V, RL= 150 ΩVO(PP) = 20 V 4.9 MHz
Full-power bandwidth(2) VCC = ±5 V, RL= 150 ΩVO(PP) = 5 V 16 MHz
VCC = ±15 V 310
SR Slew rate Gain = –1, RL= 150 ΩV/ms
VCC = ±5 V 260
VCC = ±15 V 37
Settling time to 0.1% VI= –2.5 V to 2.5 V, Gain = –12 ns
VCC = ±5 V 35
tsVCC = ±15 V 90
Settling time to 0.01% VI= –2.5 V to 2.5 V, Gain = –12 ns
VCC = ±5 V 70
NOISE/DISTORTION PERFORMANCE
THD Total harmonic distortion VCC = ±15 V, fc= 1 MHz, VO(PP) = 2 V –80 dBc
VnInput voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
VCC = ±15 V 0.01%
Differential gain error . Gain = 2, RL= 150 Ω, NTSC VCC = ±5 V 0.01%
VCC = ±15 V 0.01°
Differential phase error . Gain = 2, RL= 150 Ω, NTSC VCC = ±5 V 0.001°
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
(2) Full-power bandwidth = Slew rate/2pVO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL= 150 Ω, TA= 25°C (unless otherwise noted) THS4011C/I
THS4012C/I
PARAMETER TEST CONDITIONS(1) UNIT
MIN TYP MAX
DC PERFORMANCE
TA= 25°C 10 25
VCC = ±15 V, VO= ±10 V, RL= 1 kΩTA= Full range 8
Open loop gain V/mV
TA= 25°C 7 12
VCC = ±5 V, VO= ±2.5 V, RL= 250 ΩTA= Full range 5
TA= 25°C 1 6
VIO Input offset voltage VCC = ±5 V or ±15 V mV
TA= Full range 8
Input offset voltage drift 15 mV/°C
TA= 25°C 2 6
IIB Input bias current VCC = ±5 V or ±15 V mA
TA= Full range 8
TA= 25°C 25 250
IIO Input offset current VCC = ±5 V or ±15 V nA
TA= Full range 400
Offset current drift VCC = ±5 V or ±15 V 0.3 nA/°C
INPUT CHARACTERISTICS
VCC = ±15 V ±13 ±14.1
Common-mode input voltage
VICR V
range VCC = ±5 V ±3.8 ±4.3
TA= 25°C 82 110
VCC = ±15 V, VIC = ±12 V TA= Full range 77 dB
CMRR Common-mode rejection ratio TA= 25°C 90 95
VCC = ±5 V, VIC = ±2.5 V TA= Full range 83
RIInput resistance 2 MΩ
CIInput capacitance 1.2 pF
OUTPUT CHARACTERISTICS
VCC = ±15 V ±13 ±13.5
RL= 1 kΩ
VCC = ±5 V ±3.4 ±3.7
VOOutput voltage swing V
VCC = ±15 V, RL= 250 Ω±12 ±13
VCC = ±5 V, RL= 150 Ω±3 ±3.4
VCC = ±15 V 70 110
IOOutput current RL= 20 ΩmA
VCC = ±5 V 50 75
IOS Short-circuit output current VCC = ±15 V 150 mA
ROOutput resistance Open loop 12 Ω
POWER SUPPLY
Dual supply ±4.5 ±16.5
VCC Supply voltage V
Single supply 9 33
TA= 25°C 7.8 9.5
VCC = ±15 V TA= Full range 11
ICC Supply current (each amplifier) mA
TA= 25°C 6.9 8.5
VCC = ±5 V TA= Full range 10
TA= 25°C 75 83
PSRR Power-supply rejection ratio VCC = ±5 V to ±15 V dB
TA= Full range 68
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
6Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
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THS4012
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SLOS216E –JUNE 1999–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL= 150 Ω, TA= 25°C (unless otherwise noted) THS4011M
PARAMETER TEST CONDITIONS(1) UNIT
MIN TYP MAX
DYNAMIC PERFORMANCE
Unit-gain bandwidth Closed loop, RL= 1 kΩ, VCC = ±15 V 160(2) 200
VCC = ±15 V 70
Bandwidth for 0.1-dB flatness Gain = 1 VCC = ±5 V 35 MHz
BW VCC = ±2.5 V 30
VCC = ±15 V, RL= 150 Ω, VO(PP) = 20 V 2.5
Full-power bandwidth(3) VCC = ±5 V, RL= 150 Ω, VO(PP) = 20 V 8
SR Slew rate VCC = ±15 V, RL= 1 kΩ300(2) 400 V/ms
VCC = ±15 V 37
Settling time to 0.1% VI= –2.5 to 2.5 V, Gain = –1 VCC = ±5 V 35
tsns
VCC = ±15 V 90
Settling time to 0.01% VI= –2.5 to 2.5 V, Gain = –1 VCC = ±5 V 70
NOISE/DISTORTION PERFORMANCE
THD Total harmonic distortion VCC = ±15 V, fc= 1 MHz, VO(PP) = 1 V –80 dBc
VnInput voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 7.5 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V, f = 10 kHz 1 pA/√Hz
VCC = ±15 V 0.006%
Differential gain error Gain = 2, RL= 150 Ω, NTSC VCC = ±5 V 0.001%
VCC = ±15 V 0.01°
Differential phase error Gain = 2, RL= 150 Ω, NTSC VCC = ±5 V 0.002°
(1) Full range = –55°C to 125°C for the M suffix
(2) This parameter is not tested.
(3) Full-power bandwidth = Slew rate/2pVO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL= 1 kΩ, TA= full range (unless otherwise noted) THS4011M
PARAMETER TEST CONDITIONS(1) UNIT
MIN TYP MAX
DC PERFORMANCE
VCC = ±15 V, VO= ±10 V, RL= 1 kΩ6 14 V/mV
Open loop gain TA= Full range
VCC = ±5 V, VO= ±2.5 V, RL= 1 kΩ5 10
TA= 25°C 2 6
VIO Input offset voltage VCC = ±5 V or ±15 V mV
TA= Full range 2 8
Input offset voltage drift VCC = ±5 V or ±15 V 15 mV/°C
TA= 25°C 2 6
IIB Input bias current VCC = ±5 V or ±15 V mA
TA= Full range 4 8
IIO Input offset current VCC = ±5 V or ±15 V 25 250 nA
Offset current drift VCC = ±5 V or ±15 V TA= 25°C 0.3 nA/°C
INPUT CHARACTERISTICS
VCC = ±15 V ±13 ±14.1
Common-mode input voltage
VICR V
range VCC = ±5 V ±3.8 ±4.3
VCC = ±15 V, VIC = ±12 V 75 90
CMRR Common-mode rejection ratio dB
VCC = ±5 V, VIC = ±2.5 V 84 95
RIInput resistance 2 MΩ
CIInput capacitance 1.2 pF
OUTPUT CHARACTERISTICS
VCC = ±15 V ±13 ±13.5
RL= 1 kΩ
VCC = ±5 V ±3.4 ±3.7
VOOutput voltage swing V
VCC = ±15 V, RL= 250 Ω±12 ±13
VCC = ±5 V, RL= 150 Ω±3 ±3.4
VCC = ±15 V 65 115
IOOutput current RL= 20 ΩmA
VCC = ±5 V 40 75
IOS Short-circuit output current VCC = ±15 V, TA= 25°C 150 mA
ROOutput resistance Open loop 12 Ω
POWER SUPPLY
Dual supply ±4.5 ±16.5
VCC Supply voltage V
Single supply 9 33
TA= 25°C 7.8 9.5
VCC = ±15 V TA= Full range 11
ICC Quiescent current mA
TA= 25°C 6.9 8.5
VCC = ±5 V TA= Full range 10
TA= 25°C 80 86
PSRR Power-supply rejection ratio VCC = ±5 V to ±15 V dB
TA= Full range 78 83
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
8Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
_
+
1.5kΩ
50 Ω
150 Ω
VO1
VI1
1.5kΩ
CH1
_
+
50 Ω
150 Ω
VO2 VI2
CH2
1.5kΩ1.5kΩ
14
12
10
8
6
4
5 7 9 11 13 15
|V V
2
− OutputVoltageSwing −
±VCC − SupplyVoltage − V
O|
TA=25°C
RL=150 Ω
RL=1kΩ
1.2
1
0.8
0.6
0.4
0.2
−40 −20 0 20 40 60
TA− Free-Air Temperature − C
o
V
0
IO − Input Offset Voltage − mV
80 100
1.4
VCC =±15 V
IIB − Input Bias Current − Am
3
2.5
2
1.5
1
0
−40 −20 0 20 40 60 80 100
TA− Free-Air Temperature − C
o
VCC =±15 V or ±5 V
0.5
15
13
11
9
7
5
5 7 9 11 13 15
3
±VCC − SupplyVoltage − V
TA=25°C
− InputCommon-ModeRange − VVIC
Maximum Output Voltage Swing − V
12.5
12
4.5
4
3.5
2.5
−40 −20 0 20 40 60 80 100
TA− Free-Air Temperature − C
o
3
13.5
13
14
VCC =±5 V
RL= 150 Ω
VCC =±5 V
RL= 1 kW
VCC =±15 V
RL= 1 kW
VCC =±15 V
RL= 250 W
100
80
60
40
20
1k 10k 100k 1M
0
PSRR − Power-SupplyRejectionRatio − dB
f − Frequency − Hz
10M 100M
VCC =±15Vor ±5V
90
70
50
30
10
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
Figure 3. THS4012 Crosstalk Test Circuit
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT VOLTAGE
vs vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 4. Figure 5. Figure 6.
MAXIMUM OUTPUT VOLTAGE SWING COMMON-MODE INPUT VOLTAGE PSRR
vs vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE FREQUENCY
Figure 7. Figure 8. Figure 9.
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): THS4011 THS4012
120
100
80
60
40
20
1k 10k 100k 1M
0
CMRR − Common-ModeRejectionRatio − dB
f − Frequency − Hz
10M 100M
VCC =±5V
VCC =±15 V
−40
−60
100k 10M 100M
−90
Crosstalk − dB
f − Frequency − Hz
1M
−80
−50
−70
VI=CH1
VO=CH2
1G
VI=CH2
VO=CH1
0
−30
−20
−10
VCC =±15 V
80
1k 100K 1M
−20
Open-LoopGain − dB
f − Frequency − Hz
10K
0
60
20
40
100
10M 100M 1G
VCC =±5 V
VCC =±15 V
−40
−50
−60
−70
−80
−90
100k 1M 10M
f − Frequency − Hz
−100
Distortion − dB
−110
2ndHarmonic
VCC =±15V
RL=1kΩ
G=2
3rdHarmonic
−40
−50
−60
−70
−80
−90
100k 1M 10M
f − Frequency − Hz
−100
Distortion − dB
−110
2ndHarmonic
VCC =±5V
RL=1kΩ
G=2
3rdHarmonic
−40
−50
−60
−70
−80
−90
100k 1M 10M
f − Frequency − Hz
−100
Distortion − dB
−110
2ndHarmonic
VCC =±15V
RL=150 Ω
G=2
3rdHarmonic
−40
−50
−60
−70
−80
−90
100k 1M 10M
f − Frequency − Hz
−100
Distortion − dB
−110
2ndHarmonic
VCC =±5V
RL=150 Ω
G=2
3rdHarmonic
Output Amplitude − dB
5
0
−5
−10
−15
0
100k 1M 10M 100M 1G
f − Frequency − Hz
−20
−25
RF=270 Ω
VCC =±15V
RL=150 Ω
G=1
RF=100 Ω
Output Amplitude − dB
5
0
−5
−10
−15
100k 1M 10M 100M 1G
f − Frequency − Hz
−20
RF=270 Ω
VCC =±5V
RL=150 Ω
G=1
RF=100 Ω
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CMRR CROSSTALK OPEN-LOOP GAIN RESPONSE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
DISTORTION DISTORTION DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
DISTORTION OUTPUT AMPLITUDE OUTPUT AMPLITUDE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 16. Figure 17. Figure 18.
10 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
100
10 100 1k
f − Frequency − Hz
10
10k
1
100k
NoiseSpectralDensity
VCC =±15Vor ±5V
0.03
0.02
1 2 3 4
Numberof150-ΩLoads
0.01
DifferentialGain − %
0
Gain =2
RF=1kΩ
40IRE-NTSCModulation
Worst-Case ±100IRERamp
VCC =±5 V
VCC =±15 V
0.04
0.05
0.03
0.02
1 2 3 4
Numberof150-ΩLoads
0.01
DifferentialGain − %
0
0.04
0.05
0.06
Gain =2
RF=1kΩ
40IRE-PALModulation
Worst-Case ±100IRERamp
VCC =±15 V
VCC =±5 V
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued)
NOISE SPECTRAL DENSITY DIFFERENTIAL PHASE
vs vs
FREQUENCY NUMBER OF 150-ΩLOADS
Figure 19. Figure 20.
DIFFERENTIAL PHASE DIFFERENTIAL GAIN DIFFERENTIAL GAIN
vs vs vs
NUMBER OF 150-ΩLOADS NUMBER OF 150-ΩLOADS NUMBER OF 150-ΩLOADS
Figure 21. Figure 22. Figure 23.
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): THS4011 THS4012
IN −
IN +
NULL NULL
OUT
VCC −
VCC +
2
3
4
6
7
81
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process, with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
Pin numbers are for the D, DGN, and JG packages.
Figure 24. THS4011/4012 Simplified Schematic
Noise Calculations and Noise Figure (NF)
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
• en= Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
12 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
_
+
RF
RS
RG
eRg
eRf
eRs en
IN+
Noiseless
IN−
eni eno
eni +ǒenǓ2)ǒIN ) RSǓ2)ǒIN– ǒRFøRGǓǓ2)4 kTRs)4 kTǒRFøRGǓ
Ǹ
eno +eni AV+eniǒ1)RF
RGǓ(noninverting case)
NF +10logȧ
ȧ
ȱ
Ȳ
e2
ni
ǒeRsǓ2ȧ
ȧ
ȳ
ȴ
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
Figure 25. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
Where:
k = Boltzmann's constant = 1.380658 × 10-23
T = Temperature in degrees Kelvin (273 + °C)
RF|| RG= Parallel resistance of RFand RG
To get the equivalent output noise density of the amplifier, multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV):
As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, refer to the Noise Analysis section in the Operational Amplifier Circuits
Applications Report (SLVA043).
This brings up another noise measurement usually preferred in RF applications — the noise figure (NF). NF is a
measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is
typically 50 Ωin RF applications.
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, approximate NF as:
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): THS4011 THS4012
NF +10logȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)
ȧ
ȡ
ȢǒenǓ2
)ǒIN ) RSǓ2ȧ
ȣ
Ȥ
4 kTRS
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
20
5
0
10 100
NF − NoiseFigure − dB
25
NOISEFIGURE
vs
SOURCERESISTANCE
30
1k 100k
15
10
Source Resistance − Ω
f=10kHz
TA=25°C
10k
+
_
THS401x
CLOAD
1.3kΩ
Input
Output
1.3kΩ
20 Ω
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
Figure 26 shows the NF graph for the THS401x.
Figure 26. Noise Figure vs Source Resistance
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem, as long as certain precautions are
taken. The first precaution is to note that the THS401x has been internally compensated to maximize its
bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading
directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations.
Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with
the output of the amplifier, as shown in Figure 27. A minimum value of 20 Ωshould work well for most
applications. For example, in 75-Ωtransmission systems, setting the series-resistor value to 75 Ωboth isolates
any capacitance loading and provides the proper line-impedance matching at the source end.
Figure 27. Driving a Capacitive Load
14 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
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_
+
THS4011/4012
VCC −
VCC+
0.1 µF
0.1 µF
10kΩ
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
OFFSET NULLING
The THS401x has low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011/4012. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply (see
Figure 28).
Figure 28. Offset Nulling Schematic
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
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_
+
THS401x
100 Ω
Input
Output
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 29. Output Offset Voltage Model
OPTIMIZING UNITY GAIN RESPONSE
Internal frequency compensation of the THS401x was selected to provide very wideband performance, yet
maintain stability when operating in a noninverting unity gain configuration. When amplifiers are compensated in
this manner, there is usually peaking in the closed-loop response and some ringing in the step response for fast
input edges, depending on the application. This is because a minimum phase margin is maintained for the
G = +1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ωshould be
used (see Figure 30). Additional capacitance can also be used in parallel with the feedback resistance if even
finer optimization is required.
Figure 30. Noninverting Unity Gain Schematic
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 31).
Figure 31. Single-Pole Low-Pass Filter
16 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
VI
C2
R2R1
C1
RF
RG
R1=R2=R
C1=C2=C
Q=PeakingFactor
(ButterworthQ=0.707)
(
=1
Q
2 − )
RG
RF
_
+
f–3dB 1
2 RC
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the high-frequency performance levels of the THS401x, follow proper printed circuit board (PCB)
high-frequency design techniques. A general set of guidelines is given in the following paragraphs. In addition, a
THS401x evaluation board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 in between the device power terminals and the ceramic capacitors.
• Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to
the PCB are the best implementation.
• Short trace runs/compact part placements – Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the
input of the amplifier.
• Surface-mount passive components – Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS4011 THS4012
DIE
SideView(a)
EndView(b) BottomView(c)
DIE
Thermal
Pad
Thermal-padarea(68milsx70mils)with5vias
(viadiameter=13mils)
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Thermally-Enhanced DGN Package Views
Although there are many ways to properly heatsink this device, the following steps show the recommended
approach:
1. Prepare the PCB with a top-side etch pattern as shown in Figure 34. There should be etch for the leads, as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal-pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mils
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS401xDGN package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal-pad area. This
prevents solder from pulling away from the thermal-pad area during the reflow process.
7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
Figure 34. PowerPAD™ PCB Etch and Via Pattern
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 in × 3 in, the
expected thermal coefficient, qJA, is approximately 58.4°C/W. For comparison, the non-PowerPAD version of the
THS401x IC (SOIC) is shown. For a given qJA, the maximum power dissipation is shown in Figure 35 and is
calculated by the following formula:
18 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
PD+ǒTMAX *TA
qJA Ǔ
DGNPackage
θJA =58.4°C/W
2-ozTraceandCopperPad
WithSolder
DGNPackage
θJA =158°C/W
2-ozTraceand
CopperPad
WithoutSolder
SOICPackage
High-KTestPCB
θJA =98°C/W
TJ=150°C
SOICPackage
Low-KTestPCB
θJA =167°C/W
2
1.5
1
0
−40 −20 0 20 40
MaximumPowerDissipation − W
2.5
3
3.5
60 80 100
0.5
TA− Free-AirTemperature − °C
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
Where:
PD= Maximum power dissipation of THS401x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
qJA =qJC +qCA
qJC = Thermal coefficient from junction to case
qCA = Thermal coefficient from case to ambient air (°C/W)
A. Results are with no airflow and PCB size = 3 in × 3 in
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal-management techniques can be found
in the TI technical brief, PowerPAD™ Thermally-Enhanced Package. This document can be found at the TI web
site (www.ti.com) by searching on the keyword PowerPAD. The document can also be ordered through your
local TI sales office. Refer to literature number SLMA002 when ordering.
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multiple amplifier devices. Because these devices have linear output stages (Class A-B), most of the
heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect, along
with the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, there is generally not
a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited
in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are
mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should
always be soldered to a copper plane to fully use the heat-dissipation properties of the PowerPAD package. The
SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and
copper area is placed around the device, qJA decreases and the heat dissipation capability increases. The
currents and voltages shown in these graphs are for the total package. For the dual amplifier package
(THS4012), the sum of the RMS output currents and voltages should be used to choose the proper package.
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4011 THS4012
PackageWith
θJA <=120°C/W
SO-8Package
θJA =167°C/W
Low-KTestPCB
VCC =±5V
Tj=150°C
TA=50°C
100
80
40
0
0 1 2 3
− MaximumRMSOutputCurrent − mA
140
180
200
4 5
160
120
60
20
|VO| − RMSOutputVoltage − V
IO
| |
MaximumOutput
CurrentLimitLine
SafeOperating
Area
100
10
0 3 6 9
1000
12 15
MaximumOutput
CurrentLimitLine
SO-8Package
θJA =167°C/W
Low-KTestPCB
SO-8Package
θJA =98°C/W
High-KTestPCB
TJ=150°C
TA=50°C
|VO| − RMSOutputVoltage − V
− MaximumRMSOutputCurrent − mA
IO
| |
VCC =±15V
DGNPackage
θJA =58.4°C/W
SafeOperating
Area
PackageWith
θJA ≤60°C/W
SO-8Package
θJA =98°C/W
High-KTestPCB
VCC =±5V
TJ=150°C
TA=50°C
BothChannels
100
80
40
0
0 1 2 3
− MaximumRMSOutputCurrent − mA
140
180
200
4 5
160
120
60
20
|VO| − RMSOutputVoltage − V
IO
| |
MaximumOutput
CurrentLimitLine
SO-8Package
θJA =167°C/W
Low-KTestPCB
SafeOperatingArea
100
10
0 3 6 9
1000
12 15
MaximumOutput
CurrentLimitLine
|VO| − RMSOutputVoltage − V
− MaximumRMSOutputCurrent − mA
IO
| |
VCC =±15V
TJ=150°C
TA=50°C
BothChannels
1
SO-8Package
θJA =167°C/W
Low-KTestPCB
DGNPackage
θJA =58.4°C/W
SafeOperatingArea
SO-8Package
θJA =98°C/W
High-KTestPCB
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
THS4011 THS4011
MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT
vs vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Figure 36. Figure 37.
THS4012 THS4012
MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENT
vs vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Figure 38. Figure 39.
20 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
_
+
THS4011
VCC −
VCC+
C3
6.8 mF
C4
0.1 mF
C1
6.8 mF
C2
0.1 mF
R1
1kΩ
R5
1kΩ
R3
49.9 Ω
R2
49.9 Ω
R4
49.9 Ω
IN −
IN +
NULL
OUT
NULL
+
+
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
EVALUATION BOARD
An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for low parasitic capacitance in order to realize the full performance
of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, refer to the THS4011 EVM User's Guide (literature number SLOU028) or the THS4012 EVM User's
Guide (literature number SLOU041) To order the evaluation board, contact your local TI sales office or
distributor.
Figure 40. THS4011 Evaluation Board
Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
REVISION HISTORY
Changes from Original (June 1999) to Revision A Page
• Changed Feature List item From: 0.006% Differential Gain Error To: 0.01% Differential Gain Error .................................. 1
• Replaced the HIGH SPEED FAMILY of DEVICES table with the RELATED DEVICES table ............................................. 1
• Changed the Available Options table, THS4012ID MSOP Symbol From: TAIBG To: TIABZ .............................................. 2
• Changed the ELECTRICAL CHARACTERISTIC table ......................................................................................................... 5
• Changed the TYPICAL CHARACTERISTICS section .......................................................................................................... 9
• Changed Figure 26, Noise Figure vs Source Resistance ................................................................................................... 14
• Changed Figure 36 through Figure 39 ............................................................................................................................... 20
• Changed Figure 40, THS4011 Evaluation Board ............................................................................................................... 21
Changes from Revision A (February 2000) to Revision B Page
• Changed Feature List item From: 0.01% Differential Gain Error To: 0.006% Differential Gain Error .................................. 1
• Added THS4011M to the Abs Max table .............................................................................................................................. 4
• Added the ELECTRICAL CHARACTERISTICS for device number THS4011M .................................................................. 7
Changes from Revision B (February 2000) to Revision C Page
• Changed Figure 24, THS4011/4012 Simplified Schematic ................................................................................................ 12
Changes from Revision C (May 2006) to Revision D Page
• Changed Figure 29 - Output Offset Voltage Model docato-extra-info-title Output Offset Voltage Model ........................... 16
Changes from Revision D (June 2007) to Revision E Page
• Deleted Lead temperature and Case temperature from the Abs Max table ......................................................................... 4
• Changed Figure 5 label - From: Input Bias Current - A To: Input Bias Current - µA ........................................................... 9
22 Submit Documentation Feedback Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9959301Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9959301QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
THS4011CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4011MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
THS4011MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
THS4011MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4012CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4012IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4011, THS4011M :
•Catalog: THS4011
•Military: THS4011M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4011CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4011CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4011IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4012CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4012CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4012IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4011CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4011CDR SOIC D 8 2500 367.0 367.0 35.0
THS4011IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4012CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4012CDR SOIC D 8 2500 367.0 367.0 35.0
THS4012IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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