April 1998 Application Note 42037 ML4423 Application Guidelines INTRODUCTION Depending on the application, the focus of a given motor control design can fall on one of many specific parameters. Different applications may require that special attention be given to a specific control method to guarantee the desired performance. This Application Note defines and clarifies industry terminology for these control parameters, and will assist in utilizing the ML4423 for many different AC motor control applications. PHASE A PHASE C PHASE B VBUS H H L Q3 Q2 Q4 H L 3rd HARMONIC INJECTION Q1 GND L A review of basic inverter output waveforms will help introduce the concept of the 3rd harmonic injection. Figure 1. Power Inverter When 3-phase, 120 degree sinusoidal voltage PWM waveforms are supplied to the power inverter H and L inputs (Figure 1), the integrated PWM phase output waveforms will look like Figure 2 (phase C has been omitted for clarity). 2.0 B 1.5 For this discussion, VBUS is equal to the relative amplitude of 1.0. The VBUS ground (GND) will be referenced to the relative amplitude of -1.0. This constrains the peak value of the phase waveforms (Figure 2) to the maximum value of 1.0 (for unclipped sinusoidal waveforms). So, when the differential waveform is at its positive peak, (Figure 2, point B) the Q1 switch is modulating near VBUS and the Q4 switch is modulating near GND (Figure 1). When the differential waveform is at its negative peak, the Q3 switch is modulating near VBUS and the Q2 switch is modulating near GND. In this instance, neither phase amplitude (Figure 2, point A) is at its peak value when the differential amplitude is at its peak value (Figure 2, point B). For this condition, VBUS is not being fully utilized. The differential amplitude is 3 x VPHASE. The differential amplitude peaks when the phase amplitude is at 0.865 of its maximum. For a sinusoidal waveform, the bus voltage required is expressed in this formula: RELATIVE AMPLITUDE 1.0 A 0.5 0 -0.5 -1.0 VDIFF PHASE A PHASE B -1.5 -2.0 0 90 180 270 360 DEGREES Figure 2. Sinusoidal Waveforms 2.0 1.5 VBUS = VDIFFRMS x 2 0.865 (1) Reordering to solve for VDIFFRMS: VDIFFRMS = VBUS x 0.612 Figure 3 shows a phase voltage waveform and its 3rd harmonic. When the 3rd harmonic is summed with the phase waveform, a new 3rd harmonic+phase waveform is created. The amplitude of the 3rd harmonic signal has been equalized slightly to maintain a peak value of 1.0 in the resulting 3rd harmonic+phase waveform. RELATIVE AMPLITUDE 1.0 0.5 0.0 -0.5 -1.0 3rd-HARMONIC PHASE A PHASE A + 3rd -1.5 -2.0 0 90 180 270 360 DEGREES Figure 3. Creating 3rd Harmonic Waveform REV. 1.0 10/25/2000 Application Note 67 (Continued) Figure 4 shows two output phase waveforms with their 3rd harmonics added, and the resulting differential waveform. When the differential waveform is at its positive peak, the Q1 switch is at VBUS and the Q4 switch is at GND (Figure 1). When the differential waveform is at its negative peak the Q3 switch is at VBUS and the Q2 switch is at GND. The peak differential amplitude is VBUS. Since the differential waveform is higher in amplitude than in Figure 2, a new equation is used to derive VBUS. The equation is: VBUS = VDIFFRMS x 2 (2) VBUS = 220 x 2 = 311V 2.0 1.5 1.0 RELATIVE AMPLITUDE 3rd HARMONIC INJECTION 0.5 0 -0.5 -1.0 VDIFF PHASE A + 3rd PHASE B + 3rd -1.5 -2.0 It should also be noted that: 0 90 180 270 360 DEGREES VDIFF(PEAK) = VDIFFRMS x 2 VDIFF(PEAK) = 220 x 2 = 311V Figure 4. 3rd Harmonic Waveforms The ML4423 can be configured to provide similar results. Slight clipping will occur with the ML4423, because the phase voltages are trapezoidal in nature (when VSPEED is at 4.4V). Note that the 3rd harmonic phase waveforms have dips in the center (Figure 3). This slight dip keeps the differential waveform from saturating near its peak amplitude. For this case VBUS is fully utilized. Using the ML4423 in this way allows: V VDIFFRMS = BUS (3) 2 CONFIGURING THE ML4423 VMOTOR A, B, C R1 SENSEA, B, C R2 1k To configure the ML4423 for pseudo-3rd harmonic injection, determine the value of VBUS to satisfy the following parameters: * * * Figure 5. R1/R2 Divider VSPEED = 4.4V VSINEREF @ 1VRMS x 2, =1.5V peak VMOTOR = 220VRMS To find SENSEA, SENSEB, SENSEC feedback divider ratio, the desired output voltage is configured as indicated (see Figure 5): VMOTOR(PEAK ) = FG R1+ R2IJ x V H R2 K SINE(PEAK ) (4) SENSEB-C Solving for R1: FV x R2I GH V JK - R2 F 311V x 1000 IJ - 1000 = 206.3k R1 = G H 15. V K R1= SENSEA-B MOTOR(PEAK ) SINE(PEAK ) SENSEC-A FFT SENSEA-B Total harmonic distortion of 6% is shown in Figure 6. Figure 6. Fast Forier Transform of Sense A-B Waveforms 2 REV. 1.0 10/25/2000 Application Note 67 DC INJECTION BRAKING DC injection braking works on the principle that if a DC current is imposed on the motor windings, the resulting stationary flux will cause the rotor to slow. expires the VMIN signal will return to its original setting and the PWM will remain on. The values given should be adequate for a preliminary design. To utilize DC injection braking (Figure 7), provide a high signal on the DC brake, which will cause Q3 to pull the COAST signal low, and will briefly disable the output PWM. The COAST signal low state will remain for the time period set by the RC network of a 1F capacitor and a 100k resistor. At the same time Q2 will pull the VSPEED signal to 0V. Next, Q1 raises the voltage on the VMIN signal. Then Q3 releases the COAST signal after the RC network discharges and the PWM comes back on. At that time the motor will receive a near DC current to each winding for the time period set by the RC network of a 5F capacitor and a 1M resistor. When the RC time This technique forces the motor to slow down much faster than coasting. With regenerative schemes, a load dissipater, an added switch, and some support circuitry would be required. No overvoltage will develop at the inverter since the slip on the motor will be large during braking. 1M RMIN 100k SOFT START Increasing the capacitance on the VSPEED signal would allow a soft start to occur when the DC brake signal is pulled low. VMIN 5V/12V SEL 25 5 VSPEED HA 24 6 RSPEED HC 23 7 VREF HB 22 15k ML4423 RSPEED CSOFTSTART 100k RBRAKE 1N5818 Q1 5F 4 Q2 2N7000 GND 17 ISENSE 16 14 COAST F/R 15 Q3 2N7000 100k 12 C0 13 CPWM 2N7000 1F 100k DC BRAKE Figure 7. DC Braking Circuit REV. 1.0 10/25/2000 3 Application Note 67 LOOP CHARACTERISTICS OPEN LOOP CONTROL Differential Observer Circuit The ML4423 can be forced to operate in an open loop configuration. In order to do this, the PWM outputs must be fed back to the SENSEA, SENSEB, and SENSEC inputs. Open loop control offers a softer response to load variations. The ML4423 will not respond to a higher motor current demand (by adjusting the PWM duty cycle), limiting the available power to the motor. The circuit in Figure 9 will allow observation of the differential motor voltages without tying up scope channels. The circuit provides the voltage waveforms at the SENSEA, SENSEB, and SENSEC inputs of the ML4423. Changing to Exponential V/F Control Using the current sink circuit shown in Figure 11 with a range of zero to 100A in the place of resistor RSPEED will allow the output frequency to be varied over the range allowed by the CO capacitor (Figure 10). Blower and fan applications in this configuration can run quietly at low speed with no motor growling, unlike the closed loop linear V/F scheme. The V/F function can be further separated by connecting the Q1 base input to a voltage source other than the VSPEED potentiometer wiper. This controls the output frequency independently, while the output amplitude is controlled by the VSPEED potentiometer. R1 is selected to give the desired maximum operating frequency when VSPEED = 4.4V. Temperature coefficients require the transistors to be closely mounted to minimize drift over temperature. This may be a preferred manner of control since the resistors to select the proper motor voltage are now fixed and the available bus voltage will determine the available motor voltage. These characteristics are beneficial for low cost, offline applications dealing with a wide variety of motors and bus voltage variations. Note that the VMIN potentiometer may need to be adjusted to provide a voltage boost to the motor since the PWM signal is not modified based on motor loading. 5k 5k 5k 12V 1 2 3 SENSEA CGM2 SENSEC CGM1 SENSEB VCC 5V/12V SEL HA ML4423 1k HB LA 1k 0.15F 0.15F HC LC 0.15F 1k LB GND 28 27 26 1nF 1nF 5 25 24 23 10k 6 10k 22 21 10 20 19 17 10k 9 12V 10k 2 0.1F 10k - 8 - 10k 13 TL074 + 14 - 10k TO OUTPUT STAGE TL074 + TL074 + 10k 10k 3 7 - 10k 12 10k TL074 + 4 1 11 1/2VCC Figure 8. Open Loop Control Circuit 4 REV. 1.0 10/25/2000 Application Note 67 LOOP CHARACTERISTICS (Continued) FEEDBACK GAIN VS. FREQUENCY SPEED LOOP The internal GM amplifiers can operate with no bypass capacitors. In some cases it may be necessary to lower the loop gain to reduce the feedback bandwidth and eliminate subharmonic oscillations. The GM amplifiers have a high open loop gain, and with capacitance on the GM1 and GM2 outputs, the gain can be tailored to rolloff at predicted frequencies. Figures 12 through 17 are examples of gain vs. frequency for the given capacitance. Closing a speed loop using the ML4423 can be done by using a shaft speed sensor. The sensor generates an error signal, which is used to close a loop around a reference speed signal, and is then fed into the ML4423 speed input pin (Figure 18). There are additional benefits when using the slip control loop, which enables the motor slip to be set to a valve. When the motor accelerates, the motor current is limited to the value set by the slip control circuit. This ensures that the motor will accelerate at a predetermined rate, and will operate within the current limit of the ML4423. FOR OSCILLOSCOPE VIEWING 100k 100k SIGNAL INVERT A - C/C - A - A-B 8 + - 7 1 + 100k 100k - 100k 100k B-C 9 10 2 100k 6 5 100k 3 100k 100k 100k + 100k 2 3 SENSEA SENSEC SENSEB VCC 4 26 - 1 TO OUTPUT VOLTAGE DIVIDER NETWORK 14 13 10k 12 + 11 ML4423 GND 10k 17 Figure 9. Differential Observer Circuit 1.2 ML4423 1.0 5 SINE REFERENCE 6 7 0.8 0.6 12 10k 10k VSPEED RSPEED VREF CO GND 17 2N3904 0.4 VSPEED Q1 2N3906 0 CO 2N3904 0.2 0 20 40 R1 2.7k 60 FREQUENCY (Hz) Figure 10. Linear and Exponential V/F REV. 1.0 10/25/2000 Figure 11. Current Sink Circuit 5 Application Note 67 60 0 -20 40 PHASE (DEGREES) AMPLITUDE (dB) 50 30 20 -60 -80 10 0 .001 -40 .01 0.1 1 10 -100 .0001 100 .001 FREQUENCY (MHz) Figure 12. Bode Plot with no Capacitor PHASE (DEGREES) AMPLITUDE (dB) 40 30 20 -40 -60 -80 .01 0.1 1 10 -100 .001 100 .01 FREQUENCY (kHz) 0.1 1 10 100 FREQUENCY (kHz) Figure 14. Bode Plot with a 1nF Capacitor Figure 15. Phase Response with a 1nF Capacitor 60 0 50 -20 40 PHASE (DEGREES) AMPLITUDE (dB) 10 -20 10 30 20 -40 -60 -80 10 .01 0.1 1 10 100 FREQUENCY (kHz) Figure 16. Bode Plot with a 10nF Capacitor 6 1 0 50 0 .001 0.1 Figure 13. Phase Response with no Capacitor 60 0 .001 0.01 FREQUENCY (MHz) -100 .001 .01 0.1 1 10 100 FREQUENCY (kHz) Figure 17. Phase Response with a 10nF Capacitor REV. 1.0 10/25/2000 Application Note 67 12V SPEED IN 60PPR SPEED 100k 10k 11 2 3 - 10k 1 + 10 + 9 LM6134 - 4 8 LM6134 500k LM2907J 3.9nF 100k 1F 100k 1 2 3 4 5 10k 10k 3k 12 11 10 9 10k 11 2 3 - 5k 1 + LM6134 6 - 5 7 + 6 10k LM6134 20k ADJ 4 10k 5 - + 7 LM6134 VSPEED (ML4423) 10k 13 SLIP 100k 12 9 - + 14 LM6134 100k 10 - + 8 LM6134 10k Figure 18. Closing the Speed Loop REV. 1.0 10/25/2000 7 Application Note 67 OFFLINE OPERATION SINGLE & TWO-PHASE OPERATION Offline bias circuits can range from the leaky cap style to low cost 120V to 12V AC transformers (Figure 19). The transformer does offer isolation, but the power stage coupled to the line defeats it, since RSENSE provides a connection to the AC return. Fast rising and falling noise spikes coupled on the 12V supply will ruin a good PCB layout. The ML4423 and inverter bootstrap circuitry typically consume 50mA at 12V DC. The ML4423 can be used to operate single-phase motors. The IC would drive the appropriate gate buffers and H bridge transistors. The ML4423 HA, LA, HC, LC, SENSEA, and SENSEC pins would provide the necessary I/O functions. SENSEB input would be grounded, and the motor voltage would be fed back from phase A to SENSEA and phase C to SENSEC with a resistive divider network. The two phase mode is selected. OFF-LINE APPLICATIONS For the two-phase mode, the component count required is the same as for the three phase mode inverter configuration. The main motor winding is connected to A and C inverter outputs and the secondary motor winding is connected to B inverter output. The two phase mode is selected. The ML4423 contains no boost feature on the secondary winding, which is required for some two phase motors to produce adequate starting torque. A simple voltage doubler circuit will raise the 110V line to about 325VDC. This allows operation with 115V motors with sufficient headroom in the closed loop mode. In open loop mode the bus voltage determines the motor voltage. The capacitor RMS ripple current is equal to ISENSE / 2 / 3. AC HOT AC NEUTRAL +BUS CLOSE SWITCH FOR 120VAC -BUS IN OUT 12V 7812 GND GND Figure 19. Low Cost 12V AC Transformer/120V Boost 8 REV. 1.0 10/25/2000 Application Note 67 LAYOUT CONSTRAINTS Figure 20 shows the current loop areas relating to circuit layout and function. Critical loop areas are: * * * * Diode recovery Gate drives Bootstrap charging Motor di/dt Since the current sense resistor is utilized by three of the four loops, it needs to be a low inductance type. Diode recovery currents are diverted from the current sense resistor by the film capacitor, since the peak recovery currents can be higher than the actual motor current. This would prematurely trip the current limit. The film capacitor should have sufficient energy storage to handle the diode recovery time. An R/C filter on the ISENSE pin is needed to filter any spikes. Typical values range from 330pF to 1nF (R = 1k). Minor loops not highlighted include the voltage and current feedback paths to the ML4423. The PCB layout itself can make or break a successful design. Circuit layouts without these considerations will operate erratically under load, and may cause the output power stage, gate drivers, and/or ML4423 to fail. The PCB design examples on the following pages reflect loop area control. 12V VCC 26 LOOP AREA HA DIODE RECOVERY LOOP AREA 24 FILM CAP +VBUS ML4423 LA GND ISENSE 21 HIGH DI/DT 17 16 BOOTSTRAP CHARGING LOOP AREA GATE DRIVE LOOP AREA ELECTROLYTIC CAP MOTOR DI/DT LOOP AREA GND ISENSE Figure 20. Current Loops REV. 1.0 10/25/2000 9 Application Note 67 LAYOUT CONSTRAINTS (Continued) THROUGH-HOLE PCB EXAMPLE The ML4423 through-hole PCB in Figures 21a through 21f illustrates the use of a ground plane. A single sided layout should never be attempted. This is because of the possibility of ground bounce. Whenever ground referenced sensing is used the ground itself must be stable and low in noise. Single layer boards can't satisfy this requirement since the gradients, or differences, in voltages occur at different points on the board due to stray inductance. The voltage differences in ground traces creates voltage differences at the control IC. The CO pin on the ML4423 is susceptible to any form of noise because of its low amplitude of 300mVP-P. Therefore, proper layout is essential for reliable circuit operation. The most straightforward solution is a separate ground plane. This layer, either as the top or bottom layer of the PCB, reduces the gradient voltage effect across the PCB. The stray inductance is also reduced since the trace currents are mirrored on the ground plane. A possible difficulty occurs when a power inverter has to occupy the same PCB as the control IC. In this case, the phase Figure 21a. ML4423 Silkscreen 10 output tabs, upper gate drivers, and output voltage feedback resistors should have clearance away from the ground plane to reduce the opportunity of high frequency combined with high voltage switching transients being coupled by capacitance into the ground plane (see the ML44xx PCB layout). SURFACE MOUNT PCB EXAMPLE The surface mount PCB in Figures 22a through 22i follows the listed guidelines. The control IC has a ground plane and is a combination surface mount and through-hole. The power inverter does not have an active ground plane, but uses parallel traces to reduce loop area, uses surface mount devices, and uses the isolation of the FR-4 material for its dielectric withstand capability. The bus power PCB has the plus and minus bus on opposite sides, near critical power transistor collector/emitter connections, reducing the stray inductance loop area. The ground loops are managed locally, then connected together by traces. This assembly controls motors to 1/2HP with a suitable heatsink. Figure 21b. ML4423 Top Layer REV. 1.0 10/25/2000 Application Note 67 Figure 21c. ML4423 Bottom Layer REV. 1.0 10/25/2000 Figure 21d. ML44xx Silkscreen 11 Application Note 67 Figure 21e. ML44xx Top Layer 12 Figure 21f. ML44xx Bottom Layer REV. 1.0 10/25/2000 Application Note 67 Figure 22a. Control PCB Silkscreen Figure 22d. Power PCB Silkscreen Figure 22b. Control PCB Top Layer 10 2512 X 8 JUMPERS Figure 22c. Control PCB Bottom Layer REV. 1.0 10/25/2000 Figure 22e. Power PCB Top Layer 13 Application Note 67 COMPONENT SELECTION CAPACITORS Since the ML4423 uses an external R/C to set up the low frequency oscillator, drift over temperature is directly related to the component tolerances at this node. If tight frequency tolerance is necessary this should be reflected in the component tolerances for the anticipated operating temperature range. RESISTORS & CURRENT SENSE RESISTORS Figure 22f. Bus Power PCB Top Silkscreen For best results, use 1% resistors in the voltage feedback path. Wirewound resistors must not be used in the current feedback path. A wirewound resistor can add 200nH of circuit loop inductance, or the equivalent of a 20" long trace. With a 200ns fall time, 5A of current translates into a 5V spike across the current sense resistor for that period of time. This will trip the current limit on the ML4423 and cause problems with the bootstrap circuit and the associated level shifter. LEVEL SHIFTERS Figure 22g. Bus Power PCB Top Layer The ML4423 and the level shifter used to drive the upper IGBTs must provide the correct polarity signal to the IGBT or a shootthrough short circuit will occur. Some level shifters do not incorporate a pulse filter which rejects small pulse widths. This may cause the level shifter to latch in one mode and not reset. This typically occurs near the crest of the output phase waveform, so when the latch is not reset the ML4423 feedback error increases and you lose part of the output cycle. If the bootstrap cap discharges to the undervoltage lockout of the level shifter the output cycle may also drop out. BOOTSTRAP DIODES The diodes used for generating the bootstrap voltage must be ultra-fast (< 75ns). Slow devices will have a long recovery time and can cause dV/dt induced noise coupling problems. The diode should have at least 100V of margin over the maximum bus voltage. POWER DEVICES Figure 22h. Bus Power PCB Bottom Layer IGBTs are suited to compete with MOSFETs to 20kHz. The co-pack IGBT's have softer and faster internal diodes than MOSFETs. The relatively slow and snappy characteristics of MOSFET diodes (in freewheel mode, common for motor control) may cause chaos on ground referenced current limit schemes, and will require larger R/C filtering on the ISENSE pin. EMI considerations will also play a role in device selection. POTENTIAL DESIGN ISSUES Other design issues to consider include: power switch size, power dissipation and heatsinking, gate drive power, gate charge, cost and reliability, and PCB layout. Figure 22i. Bus Power PCB Bottom Silkscreen 14 REV. 1.0 10/25/2000 Application Note 67 COMPONENT SELECTION (Continued) EXAMPLE: SELECTING IGBT AND HEATSINK 4. Calculate diode conduction loss: The following exercise selects a suitable power device and heatsink for a 1/2 HP inverter. The selected IGBT is an IRGBC20UD2. The requirements are: Diode voltage drop = 1.6V @ 2.83A * * * * * * * 1/2 HP 220VAC three phase induction motor DC input (VBUS) 360V DC motor power factor (PF) 0.7 motor efficiency (ME) 0.7 inverter modulation index (D) = 0.612 (Eq.1, p.1) fPWM = 20kHz Ambient Temperature TA = 40C * * IJ (8) K 0.612I F = 283 . x 16 . V x G 0.125 + J x 0.7 = 0.60W H 3 K D COND D x PF 3 5. Calculate total losses: TPD = PON + PSW + D COND (9) . W + 452 . W + 0.6W = 587 . W TPD = 075 IGBT datasheet characteristics of interest are: * * * * * FG H DCOND = ICPK x VDIODE x 0.125 + VCEON @ IC VDIODE @ IC EON @ IC EOFF @ IC Gate charge JC CS 6. Calculate total power dissipation to select heatsink size. Total inverter losses: PINV = TPD x 6 (10) . W x 6 = 35.22W PINV = 587 7. Calculate heatsink size with TSINK selected at 125C. 1. Calculate motor phase current required: Thermal impedance is: IPHASE = IPHASE = PMOTOR (5) 3 x VBUS x Pf x D x ME FG 746W x 0.5HPIJ H HP K 3 x 360 V x 0.7 x 0.612 x 0.7 = 2A RMS SA = 125 C - 40 C = 2.4 C / W 35.22W (11) IGBT junction temperature is: b . A ICPK = IPHASE x 2 = 283 g d (12) i = 125 + a0.75 + 452 . f x a21 . + 0.5f = 1387 . C TJIGBT = TSINK + PON + PSW x JC + CS 2. Calculate IGBT conduction losses: TJIGBT VCEON for peak operating current 2V FG H PON = ICPK x VCEON x 0.125 + FG H TSINK - TA PINV 8. Calculate IGBT and diode junction temperature for the selected TSINK: Then peak device collector current is: . x 2V x 0.125 + PON = 283 SA = IJ K D x PF 3 IJ K Diode junction temperature is: (6) d TJDIODE = TSINK + D COND x JC + CS a f i (13) . + 0.5 = 126.6 C TJDIODE = 125 + 0.60 x 21 0.612 x 0.7 = 0.75W 3 3. Calculate IGBT switching losses: Note: For reliable operation, TJIGBT and TJDIODE should be lower than 125C., forcing a reduction in the RQSA requirement. ETOT switching losses = 0.71mJ 9. Calculate the RSENSE resistor value: PSW = E TOT (mJ) x FPWM(kHz) x PSW = 0.71 x 20 x REV. 1.0 10/25/2000 1 = 4.52W 1 (7) ISENSE(PEAK ) = IPHASE x 2 (14) ISENSE(PEAK) = 2A x 1414 . = 283 . A R SENSE = 0.5V ISENSE (15) 15 Application Note 67 COMPONENT SELECTION R SENSE = (Continued) 0.5V = 0.176 283 . A without being refreshed. This requires the bootstrap capacitor to be larger than the value initially calculated. As a quick approximation, 2F/HP works with the IR2118. For the following conditions: 10. Finally, calculate resistor power dissapation: FG I IJ x R H 2 K F 283 . AI =G H 2 JK x 0.176 = 0.7W 2 PDISS = SENSE(PEAK ) SENSE (16) 2 PDISS * * * * * IR2118 high side gate driver IQBS = 50uA, typical VCC = 12V TON = 5ms IGBT gate charge = 22nC (for the IRGBC20UD2) 2 x IQBS x TON Adjustment factors have not been included for lower bus voltages. CBOOT > 2 x Q G + GATE DRIVE CONSIDERATIONS CBOOT > 2 x 22nC + Choosing the bootstrap capacitor: The phase output referenced inverter waveforms pertain to the basic inverter design and operation. The formulas provided by IR for selecting the Bootstrap capacitor value address nonsaturating PWM designs. Since the phase waveforms clip even when the differential waveforms are sinusoidal, (Figure 22) the upper switch has to stay on for the duration (17) . - 10 VCC - 15 2 x 50A x 5ms > 0.544F 0.5 In this case use a 1F capacitor. Note: If IQBS increases to 240A, CBOOT = 4.88uF Selecting the value for the series gate resistor should be based on the available peak driver current of the driver IC used. Typically, datasheet RG values will work for most applications. A-B B-C C-A PHASE C Figure 23. Clipped Phase C 16 REV. 1.0 10/25/2000 Application Note 67 PHASE A SENSE A F1 5A PHASE B SENSE B R32 +HV IN R30 10 C13 0.1F 400V R36 10 Q1 Q5 R38 R43 1.0 R37 1.0 R31 1.0 C10 470F 400V R42 10 Q3 C14 0.1F 400V R44 SENSE C Q6 Q4 Q2 PHASE C HV GND ISENSE +12V D1 C1 1F 1 HA U1 C2 C3 1F 1F D2 8 1 U2 C4 C5 1F 1F D3 C6 1F 8 1 U3 8 7 2 7 2 3 6 3 6 3 6 4 5 4 5 4 5 2 IR2118 IR2118 7 IR2118 HB HC LC LB LA Q7 C7 1F Q8 Q9 R35 10 C8 1F R35 10 Q10 Q11 C9 1F Q12 R35 10 R49 0.1 GND Figure 24. Inverter Schematic REV. 1.0 10/25/2000 17 Application Note 67 SENSEA SENSEC SENSEB 12V ML4423 C3 0.15F R15 1k C2 0.15F R14 1k C1 0.15F R13 1k R27 100k VMIN R26 100k VSPEED C11 0.1F TP1 R16 160k TP2 R17 200k R18 200k C14 220pF C13 0.56F C21 1nF C8 0.1F C9 0.1F C22 1nF C4 1nF 1 28 2 27 3 26 4 25 5 24 HA 6 23 HC 7 22 HB 8 21 LA 9 20 LC 10 19 LB 11 18 12 17 13 16 14 15 SW1 COAST SW3 FWD/REV C5 1nF C15 1F C15 0.1F R19 1k ISENSE C15 1nF Figure 25. Controller Schematic 18 REV. 1.0 10/25/2000 Application Note 67 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com REV. 1.0 10/25/2000 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2000 Fairchild Semiconductor Corporation 19