82559 Fast Ethernet* Multifunction PCI/
CardBus Controller
Networking Silicon
Dat ash e et
Pr oduct Features
■Optimum Integration for Lowest Cost
Solution
—Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
—Glueless 32-bit PCI master interface
—Glueless CardBus master interface
—M o d em int e rface f or co mb i n atio n
solution s in PCI, CardBus, and MiniPCI
designs
—PXE Support in Combo Designs
—128 Kbyte Flash interface
—Integrated po wer mana gem ent functions
—Thin BGA 15mm2 package
■W ired for Manage ment and Reduced Tota l
Cost of Ownership
—Wired for Management support
—System Management Bus support for
Total Cos t of Ownership s upport
—Power management capabilities
—ACPI and PCI Power Management
standards compliance
—Wake on “interes ting” packets and link
status change support
—Magic Packet* support
—Remote power up support
■High P erformance Netw orking Functions
—C hain ed me mor y stru cture s imila r to t he
82558, 82557, and 82596
—I mpro ve d dynamic trans mi t cha ining
with multiple prio r itie s tra nsmit que ues
—B ackwar d compatible softwa r e to the
82558 and 82557
—Ful l Duple x support at both 10 and 100
Mbps
—I EE E 802. 3u Auto-Ne gotiation support
—3 Kbyte transmit and 3 Kbyte receive
FIFOs
—Fast back-to-back transmission support
with minimum interframe spacing
—I EEE 802. 3x 100BASE-TX Flow
Control support
—Ad aptive Technology
—TCP/UDP checks um offload capabilit ies
■Lo w Power Features
—Low power 3.3 V device
—Efficient dynamic standby mode
—Deep power do wn support
—Clockrun protocol support
Order Num be r : 74 3892 - 00 4
Revision 2.2
May 2001
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall hav e no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82559 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained b y calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2001, Intel Corporat ion.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ ben efit, without
intent to infringe.
Datasheet iii
Networking Silicon — 82559
Contents
1.0 Introduction.........................................................................................................................1
1.1 82559 Overview .................. ......... ............ ....... ............ ............ ......... ............ ....... ..1
1.2 Features, Enhancements, and Changes to the 82559 from the 82558............. ....1
1.3 Enhancem ent s to the 82559 C-Step................. ....................................................2
2.0 82559 Architectural Overview ............................. ......... ....... ............ ....... ....... ............ .........3
2.1 Parallel Su b syste m Overvi e w................................................................................3
2.2 FIF O Sub syste m Overvie w ...................................................................................4
2.3 10/100 Mbps Serial CSMA/CD Unit Overview ........................................ ..............5
2.4 10/100 Mbps Physical Layer Unit............................. .............................................5
3.0 Signal Descriptions........ ....... ....... ............ ....... ....... ............ ....... ............ ....... ....... ................7
3.1 Signal Type Definitions ................ .......... .. ....... ....... ............ ....... ..... ....... ....... ....... ..7
3.2 PCI Bus and CardBus Interface Signals ...............................................................7
3.2.1 Address and Data Signals ........ ....... ....... .. ............ ....... ....... .......... ....... .. ..7
3.2.2 Interface Control Signals .........................................................................8
3.2.3 System and Power Management Signals ................... ....... ............ ....... ..9
3.3 Local Mem ory Interface Signals................. ................... .............. ........................10
3.4 System Mana gem ent Bus (SMB) Interface Signals ............ .............. .................12
3.5 Testability Port Signals ............................................................... ................... .....12
3.6 PHY Sig n als .............................. ..... ..... .... .................................... .... ..... ..... .........12
4.0 82559 Medi a Access Control Function al Description.......................................................15
4.1 82559 Initialization.................................. ......... ................... .............. ...................15
4.1.1 Initialization Effects on 82559 Units .......................................................15
4.1.2 Initialization Effects on TCO Functionality............................. .................16
4.2 PCI and CardBus Interface .................................................................................16
4.2.1 82559 Bus Operations................. ....... ................... ....... ................... .......16
4.2.2 PCI Mode Pin.........................................................................................25
4.2.3 Clockrun S ignal ........................................... ...................................... .....25
4.2.4 Power Management Event and Card Status Change Signals................26
4.3 PCI Power Managem ent .. ................................. ............ ......................................26
4.3.1 Power States..........................................................................................26
4.3.2 Wa ke - u p Events.................................... .... ..... ..... ...................................31
4.4 CardBus Pow er Manage men t. .................................................... ................... .....32
4.5 Wake on LAN (Preboo t Wake-up).............. .............. ...........................................32
4.6 Parallel Fl a s h /Modem Interface.. ........................................... .... ..... ..... ................33
4.7 Serial EEPROM Interface....................................................................................33
4.8 10/100 Mbps CSMA/CD Unit ...............................................................................36
4.8.1 Full Duplex .............................................................................................37
4.8.2 Flo w Control...... ..... ..... ...........................................................................3 7
4.8.3 Add re ss Fi lteri n g Modi ficati o n s ...... .... ..... ..... ..... .....................................37
4.8.4 VLAN Su p port ... ..... ..... .... .......................................................................37
4.9 Media Independ ent Inte rface (MII) Management Interface .. ...............................38
5.0 82559 Physical Layer Funct iona l Description .. ................................................................39
5.1 100 BASE-TX PHY Unit..... .............. ..... .... ..... .............. ..... ..... .... ............... .... ..... ..39
82559 — Networking Silicon
iv Datasheet
5. 1 .1 100 BASE-TX Tran smit Clock Genera tion....... ..... .... ..... ..... ....................39
5.1.2 100BASE-TX Transmit Blocks ...............................................................39
5.1.3 100BASE-TX Receive Blocks................................................................42
5.1.4 100BASE-TX Collision Detection...........................................................43
5.1.5 100BASE-T X Link Integrity and Auto-Nego tiation Solution....................43
5.1.6 Auto 10/100 Mbps Speed Selection..................................................... ..43
5.2 10BASE-T Functionality......................................................................................44
5.2.1 10BASE-T Transmit Clock Generation............................ ....... ................44
5.2.2 10BASE-T Transmit Blocks....................................................................44
5.2.3 10BASE-T Receive Blocks .....................................................................44
5.2.4 10BASE-T Collision Detection................................................................45
5.2.5 10BASE-T Link Integrity.........................................................................45
5.2.6 10BASE-T Jabber Cont rol Function. .................................................... ..45
5.2.7 10BASE-T Full Duplex ...........................................................................46
5.3 Auto-Negotiation Functionality ........ .......... ......... ....... .......... ......... ....... .......... ......46
5.3.1 Description.............................................................................................46
5.3.2 Parallel Detect and Auto-Negotiation.................. ...................................46
5. 4 LED Descri p tion............................................. .....................................................47
6.0 82559 Modem Funct ionality. ...................................... ................................. .....................49
6.1 PCI Address Mapping to the Modem ................................................................ ..49
6. 2 Modem Read and Writ e Cycle s ...... ..... ..... ..... ........................................ .............49
6.3 Modem and Preboot eXtension Environment Coexistence................. ............ ....49
6. 3 .1 Pr o gramming Deta i ls. ..... .... ..... ...............................................................49
6.3.2 Su pport Circuitry ....................................................................................50
7.0 82559 TCO Funct ional ity ......................................................... ...................................... ..51
7.1 System Functionality with a TCO Controller .......................................................51
7.2 System Functionality without a TCO Controller ..................................................53
7. 3 TCO Int er fa c e.... .... ..... ..... ....................................................................................53
7.3.1 SMB Alert Signal (SMBALRT #)............... ...............................................53
7.3.2 Alert Response Addres s (ARA) Cycle........................ ............................54
8.0 PCI and CardBus Configuration Registers................. ................................. .....................55
8.1 Function 0: LAN (Ethernet) PCI Configuration Space.........................................55
8.1.1 PCI Ve ndor ID and Device ID Registers .................... ............................55
8.1.2 PCI Command Register .........................................................................56
8.1.3 PCI Status Register................................................................................57
8.1.4 PCI Revision ID Register........................................................................58
8. 1 .5 PCI Class Code Register...... ..... .... ............ ............ ............ ............ ........58
8.1.6 PCI Cache Line Size Register................................................................58
8.1.7 PCI Latency Timer .................................................................................59
8.1.8 PCI Header Type ...................................................................................59
8. 1 .9 PCI Bas e Add re ss Regist er s... ..... ..........................................................59
8. 1 .1 0 Base Address Registr y Sum mar y.. ..... ..... .... .................................... ..... .61
8. 1 .1 1 CardBu s Ca r d Inf o rmation Str u ctu re ( CIS) Po inter....... ..... .... ..... ..... ......61
8.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers.......................61
8.1.13 Capability Pointer................. ......................................................... .........62
8. 1 .1 4 In te r r u p t L ine Regi ste r.... .... ..... ..... ..........................................................62
8. 1 .1 5 In te r r u p t Pi n Register.. ..... ..... ................................... ..... ..... .... ................62
8.1.16 Minimum Grant Register ........................................................................62
Datasheet v
Networking Silicon — 82559
8.1.17 Maximum Latency Register....................................................................63
8.1.18 Capability ID Register.............................................................................63
8.1.19 Next It e m Pointe r.. .... ..... .........................................................................63
8.1.20 Power Managem ent Capabilities Register . ............................................63
8.1.21 P ower Man agem ent Control/Status Register (PMC SR). ........................64
8.1.22 Data Regi ste r .... .....................................................................................64
8.2 Function 1: Modem PCI Configuration Space.....................................................66
8.2.1 Modem Configuration ID Register. .................................................... .....66
8.2.2 Modem Command Register ............. ....... ....... ....... ....... ....... ............ .......67
8.2.3 Modem Status Register.................... ......... ............ ....... ............ ............ ..67
8.2.4 Modem Revision ID Register..................................................................68
8.2.5 Modem Header Type Register ...............................................................68
8.2.6 Modem I/O Base Address Registe r........................................................68
8.2.7 Modem Memory Base Address Register........ ....... ....... ....... ..... ....... .......68
8.2.8 M odem CardBu s CIS Pointer..................................................... ............68
8.2.9 M odem Subsystem Vendor ID Register. ................................................68
8.2.10 Modem Subsystem ID Register.......... ..... .. ..... ... .... ... .... ... .... ..... ... .... ... ....69
8.2.11 Modem Capabilities Pointer ...................... .......... ....... ......... .......... ....... ..69
8.2.12 Modem Interrupt Register................. ....... ............ ....... ....... ....... ....... .......69
8.2.13 Modem Power Managem ent Capabi lities Register ................................69
8.2.14 Modem Power Managem ent Control/Statu s Register.... ................... .....69
8.2.15 Modem Data Register .......... ....... ....... ....... .......... .. ....... ....... .......... ....... ..69
8.2.16 Modem Supp ort in PCI Mode.................................................................70
9.0 Contr o l/Sta tu s Regi sters .... ..............................................................................................71
9.1 LAN (Ethernet) Control/Status Registers ............................................................71
9.1.1 System Cont ro l Bl o ck Sta tu s Word.. .......................... .......................... ..73
9.1.2 System Cont ro l Bl o ck Comma n d Word... ..... ..... ........... ................... .......73
9.1.3 System Control Block General Pointer.. .. ....... ....... ....... ....... .......... ....... ..74
9.1.4 PORT .....................................................................................................74
9.1.5 Flash Cont ro l Regi ster............. .................. ................... ..........................7 4
9.1.6 EEPROM Control Register.....................................................................74
9.1.7 Managem ent Data Interface Control Register........................................74
9.1.8 R eceive Direct Memory Access Byte Count................... ............ ............74
9.1.9 Early Rec eive In te r r u p t.. ..... ..... .... ...........................................................75
9.1.10 Flow Control Register.... ............................................... ..........................7 5
9.1.11 P ower Man agem ent Driver Register................................................. .....75
9.1.12 General Control Register........................................................................76
9.1.13 General Status Register.........................................................................76
9.1.14 Ethernet Card Status Change Registers.......... ......................................76
9.2 Statistical Counters ............................. ............................................... .................79
9.3 Modem Control/Status Registers ........... .. ....... ....... .......... .. ....... ....... ..... ....... .......81
9.3.1 Modem Base M emo ry Addressing .........................................................81
9.3.2 Modem Base I/O Addres sing ................................................ .................82
9.3.3 Modem CardBus CSTCHG Registers....... ..... ..... .. ..... .. ..... .. ..... ..... .. ..... ..82
10.0 PHY Unit Registers.. ..... ..... .... ............ .............................................................. ............... .85
10.1 MDI Registers 0 - 7 .............................................................................................85
10.1.1 Register 0: Control Register Bit Definitions ...........................................85
10.1.2 Register 1: Status Register Bit Definitions ............................................86
82559 — Networking Silicon
vi Datasheet
10.1.3 Register 2: PHY Identifier Register Bit Definitions ................................87
10.1.4 Register 3: PHY Identifier Register Bit Definitions ................................87
10.1.5 R egister 4: Auto-Negotiation Advertisem ent Register Bit Definitions ....87
10.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .
87
10.1.7 Register 6: Auto-Negoti ation Expansion Register Bit Definitions ..........88
10.2 MDI Registers 8 - 15...........................................................................................88
10.3 MDI Register 16 - 31...........................................................................................88
10.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions .......88
10.3.2 Register 17: PHY Unit Special Control Bit Definitions ...........................89
10.3.3 Register 18: PHY Address Register.......................................................90
10.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions
90
10.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ...
90
10.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions .
90
10.3.7 Registe r 2 2: Recei ve Symbo l Erro r Co unt er Bit Defin it ions .. ..... ..... ..... .91
10.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions 91
10.3.9 Register 24: 10BASE-T Receive End of Frame E rror Counter Bit Defini-
tions 91
10.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ..
91
10.3.11 Register 26: Equalizer Control and Status Bit Definitions.................... ..91
10.3.12 Register 27: PHY Unit Special Control Bit Definitions ...........................92
11.0 82559 Test Port Functionality ................. ........................................................... ..............93
11.1 Introduction .........................................................................................................93
11.2 Asynchronous Test Mode ...................................................................................93
11.3 Tes t Fun ction Descript ion ..................................... .... ..... ..... ................................93
11.3.1 Tristate ...................................................................................................93
11.3.2 NAND Tree.............................................................................................93
12.0 Ele ctri ca l an d Timin g Specificati ons...... ...........................................................................97
12.1 Abs ol u te Maximum Ratin gs ... ..... .... ....................................................... .............97
12.2 DC Specifica tions ...............................................................................................97
12.3 AC Specifications..............................................................................................101
12.4 Ti mi n g Spe cifica tions... ..... ..... ................................... ..... ..... ..... .........................102
12.4.1 Clocks Sp e c i ficati o n s..... .... ..... ..... ....... ..... .... ..... ..... ..............................10 2
12.4.2 Ti mi n g Para mete r s.... ..... ............................ ..... ..... .... ............................103
13.0 Package and Pi n out Informa tion.... ..... ..................... ..... ..... .... ........................................111
13.1 Pac ka ge In fo r m a tion.... ..... ..... ..... ......................................................................111
13.2 Pinout Information...... ............ ....... ....... ............ ....... ....... ............ ....... ....... ....... ..112
13.2.1 82559 Pin Assignme nts .......................................................... ............112
13.2.2 82559 B all Grid Array Diagram .................................................... .......114
Datasheet vii
Networking Silicon — 82559
Figures 1 82559 Block Diagram.......... ....... ....... ....... ..... ....... ....... ....... ..... ....... .. .......... ....... ....3
2 Contr o l/Sta tu s Regi ster I/O Read Cycle...... .... ..... ............ ................... ............ ....1 7
3 Con tro l/St a tus Regi ster I/O Write Cycle... ..... ..... .... ..... ................... .....................18
4 Flash Bu ffer Read Cycle ................................................................ .....................19
5 Flash Buffer Write Cycle ......................................................................................20
6 PCI Retry Cycle...................................................................................................21
7 Memo ry Read Burst Cycle ............. ............ .........................................................22
8 Memory Write Burst Cycle...................................................................................22
9 Isolate Signal Behav ior to PCI Power G ood Signal. . ...........................................28
10 82559 Initialization Upon PCI RST # and ISOL ATE #.......................... .................30
11 64-word EEPROM Read Instruction Waveform..................................................34
12 82559 EEPROM Format ... .............. ..... .... ..... .............. ..... ..... .... ............... .... ..... ..35
13 NRZ to MLT-3 En co d ing Diag r a m................. .......................... ............................41
14 Co n ce p tu a l Tr ansm it Diffe r e ntial Wavef o r m........... ................... ................... .......41
15 Auto-N egotiation and Parallel Detect .. ................................................................47
16 T w o and Three LED Sche matic Diagra m...... .......................... ............................48
17 Modem Read/Write Cycles..................... .. ....... ....... .......... .. ....... ....... .......... .. .......49
18 Support Circuitry Example..... ..... ....... ..... ....... .. ..... ....... ..... ....... .. ....... ..... ..... ....... ..50
19 SMB Session.......................................................................................................53
20 Slave Request for Data Transfer.........................................................................54
21 PCI Configuration Registers................................................................................55
22 PCI Comm and Register ..................................................................... .................56
23 PCI Status Register.............................................................................................57
24 Cache Line Size Register....................................................................................58
25 Base Address Register for Memory Mapping......................................................59
26 Base Address Register for I/O Mapping..............................................................60
27 Modem PCI Configuration Registers. ..... ....... ....... ....... ....... ....... ..... ....... ....... .......66
28 82559 Control/Status Register.......... ....... ....... ....... .......... ....... ....... ....... ....... .......71
29 RBIAS100 Resistanc e Versus Transm itter Current ............................................99
30 RBIAS10 Resistance Versus Transmitter Current ............................................100
31 PCI/CardBus Clock Waveform..........................................................................1 02
32 Output Timing Measurement Con ditions...........................................................103
33 Input Timing Me asureme nt Conditions..............................................................103
34 F la sh /Modem Ti mi ngs for a Read Cycle.. ..... ..... ............ .......................... .........106
35 Flash/Modem Timings for a Write Cycle ...........................................................106
36 EEPROM Timings.............................................................................................107
37 1 0 BASE-T NLP Timings.................... ..... ..... .... ............... .... ..... ..... .............. ..... ..108
38 Auto-N egotiat ion FLP Timing s .................................................... ......................108
39 Dimension Diagram for the 82559 196-pin BGA................ ..... ....... .. .......... .. .....111
40 82559 Ball Grid Array Diagram ..................... .. ....... ..... ....... ..... ....... .. .......... .. .....114
Tables 1 EEPROM Words Field Descriptions....................................................................35
2 4B/5 B Encoder ........................................... ................................. ........................39
3 Magnetics Modules ................................................ ................... ................... .......42
4 PCI Comm and Register Bits ............... ................................................................56
5 PCI Status Register Bits......................................................................................57
82559 — Networking Silicon
viii Datasheet
6 B as e Addr e ss Regi ster Funct ionalitie s ....... ........................................................61
7 82559 ID Fields Program min g ............................. ...............................................62
8 Power Management Capability Register.............................................................63
9 Power Manag eme nt Control and Status Register...............................................64
10 82559 B-step Ethernet Data Register . ................................................................64
11 82559 C-step Ethernet Data Register.............. .. ....... .......... ....... ....... ....... ....... ....65
12 Power Manageme nt Control and Status Register...................................... .........67
13 Modem Status Register .......................................................................................67
14 Modem Revision Register...................................................................................68
15 Ethernet Data Register........................................................................................69
16 Power Management Driver Register.................. ....... ..... ..... ....... .. ....... ..... ....... ....75
17 General Control Register ..................... ....... ..... ....... .. .......... .. ....... ..... ....... ..... ......76
18 General Status Register......... ......... ............ ....... ....... ............ ....... ............ ....... ....76
19 L AN Fun ction Eve n t Regi ste r.............................................. ................................77
20 L AN Fun ction Eve n t Mask Regi ste r..... ..... ..... .......................... ...........................77
21 L AN Fun ction Pre s e n t State Regi ster..... .... ..... ................... .......................... ......78
22 L AN Force Event Regi ster ....... ................... ................................. .......................79
23 82558 Statistical Counters ..................................................................................79
24 Modem Function Even t Mask Regist er....... ..... ..... .......................... ....................83
25 Modem Function Pre se n t Sta te Regist e r............................................................83
26 NAND Tree Chain s ...... ..... ..... ..... ............................................................. ...........94
27 General DC Specifications.............. ............ ..... ....... ....... ....... ....... ....... ..... ....... ....97
28 PCI/CardBus Interface DC Specifications...........................................................97
29 SMB Interface DC Specifications........................................................................98
30 Flash/Modem/EEPROM Interface DC Specifications .........................................98
31 LED Voltage/Current Characteri stics .......... ..... .. ....... ..... ..... .. ..... .. ....... ..... ..... .. ....99
32 100BASE-T X Voltage/Current Characteristics................. ................................. ..99
33 10BASE-T Voltage/ Current Characteristics ......................................................100
34 AC Specifications for PCI Signaling.. ................... .............................................101
35 AC Specifications for CardBus Signaling..........................................................101
36 AC Specifications for Local Bus Signaling........................................................101
37 PCI/Car d Bus Clock Specifications..... ..... ............................................... ...........1 0 2
38 X1 Clock Speci fications............................. ........................................................10 2
39 Measure and Test Condition Parameters .......... ....... .......... .. ....... ....... .......... ....103
40 PCI/Car d Bus Ti mi n g Parameters......................................................................104
41 Flash Timing Parameters..................................................................................105
42 EEPROM Timing Parameters...........................................................................107
43 10BASE-T NLP Timing Parameters..................................................................108
44 Auto -N e gotiat ion FLP Timin g Parameter s ....... ..... .... ...................... .... ..... ..... ....108
45 100Base-TX Transmitter AC Specification. .................................... ...................109
46 Flash Timing Parameters..................................................................................109
47 82559 Pin Assignme nts .......................................................... ..........................112
Datasheet ix
Networking Silicon — 82559
Revision History
Revision
Date Revision Description
Jan. 1999 1.0 First release.
May 1999 2.0 •Preliminary 82559 C-step updates:
•Added Section 1.3, "Enhancements to the 82559 C-Step"
•Changed resistance values for RBIAS pins in Section 3.6, "PHY Sig-
nals"
•Changed signal names (Section 3.4, "System Management Bus (SMB)
Interface Signals"):
•Alert Bus Data: ALERTD (previously) to SMBD
•Alert Bus Clock: ALERTCLK (previously) to SMBCLK
•Bus Alert: BUSALRT (previously) to SMBALRT
•Changed value of PCI power management in the Capability ID Register from
01H to 02H (Section 8.1.18, "Capability ID Register")
•Changed value of bits 18:16 in the Power Management Capabilities Register
from 001b to 010b (Section 8.1.20, "Power Management Capabilities Regis-
ter")
•Changed power consumption values in Table 15. Ethernet Data Register in
Section 8.1.22, "Data Register"
•Changed name of Modem Capabilities Pointer (Modem Cap_Ptr) register in
PCI Configuration space to Modem (Section 8.2, "Function 1: Modem PCI
Configuration Space")
•Added Section 11.0, "82559 Test Port Functionality"
Mar. 2000 2.1 M odified text description fo r the Voltage Input/Out put signal in Section 3.2.3 ,
"System and Power Management Signals"
May 2001 2.2 •Updatedvalueofthe10KΩpull-up resistor to 100 KΩfor the Isolate signal
(Section 3.2.3, "System and Power Management Signals").
•Added note to Section 3.3, "Local Memory Interface Signals" to leave
unused Flash Address and Data pins floating.
•Added Revision ID for the 82559 C-step (09H) in Section 8.1.4, "PCI Revi-
sion ID Register"
•Corrected values in Table 32 “100BASE-TX Voltage/Current Characteristics”
and Table 33 “10BASE-T Voltage/Current Characteristics”for the Input Dif-
ferential Accept and Reject Peak Voltages.
82559 — Networking Silicon
x Datasheet
Note: Thi s pag e left intenti onally bl ank.
Networking Silicon — 82559
Datasheet 1
1.0 Introduction
1.1 82559 Overview
The 82559 is Intel's second generation fully integra ted 10BASE-T/100BASE-TX LAN solution.
The 8255 9 cons is ts of both the Media Access Controlle r (MAC) a nd the physic al layer (PHY)
interface combined into a single component solution. The 82559 builds on th e basic functionality
of the 82558. In addition to the 82558, the 82559 ha s ad ded new feat ures and enhancements:
•Host-side Car d Bus interface
•Enhanced power management implementation
•Enhanced Total Cost of O wnership (TCO) support
•Optim ized Flash or modem interface support
The 32- bit PCI/CardBu s contr oll er pro vi des e nhance d scatte r -ga ther b us maste ring cap abi litie s and
enabl es the 82559 to perform high speed data transfers over the PCI bus and CardBus. Its bus
maste r capabilities enable the comp onent to proces s high lev el commands and pe rform multip le
operations, which lowers CPU ut ilization by off-loa ding communication tasks fr om the CPU. Two
large trans m it and receive FIFOs of 3 Kb yte each help prevent data underruns and o verr uns while
wait ing for b us acces ses. T his ena bles t he 82559 t o tra nsmit d ata wit h mini mum inter frame spa cing
(IFS).
The 82559 can operate in either full duplex or half duplex mode. In full duplex mode the 82559
adheres wi th the IEEE 802.3x Flow Contro l spec ification. Half d uplex performance is enhanced by
a proprietary collision reduction mechanism.
The 8255 9 incl udes a simple PHY interface to the wire transform er at rates of 10BASE-T and
100BASE-TX enables reduc tion in co st , real estat e and d es ign comple xity. Its Auto-Negotiati on
capa bility f or speed, duplex, and flow control mode reduce s c ost, real estate, and design
complexity.
The 8255 9 also inclu des an interf ace to a serial (4-pin) EEPROM and a par allel inte rface to a 128
Kbyte Flash memory. The EEPROM provides power-on initial iza tion for hardware and softwa re
co n figur ation parameters. The p ar allel port ca n b e used as either a Fl ash memory in terface or an
ISA-like interface for modem.
Combined with a Total Cost of Ownersh ip (TC O ) controller, t he 82559 can help reduce the tota l
cos t of ownership in network environments. The devi ce i ncludes a Syste m Management Bus
(S M B ) interface en a bl in g th e TC O co n tr o l le r to co m mu ni c at e w it h a ma n ag em e n t age n t o n the
network.
1.2 Fea t ures, Enhancemen ts, and Changes to the 82559 from
the 825 58
•Gluele ss 32-bi t PCI bus m aster int erfac e
•Suppo rt for latchless Flash interface with up to 128 Kbyte of Flash addressing
•Glueless CardBus master interface
82559 — Netwo rking Silicon
2Datasheet
•Modem interf ac e for combination soluti on (LAN and mode m) in PCI an d CardB us des igns
•Low power consumption for LAN/modem combination designs to meet CardBus powe r
requirements
•Comp liance with Advanced Configuration and Power Interface and PCI Power Management
specifications
•Support for wake-up on interesting packets and link status change
•Sup port for remote po wer-up using Wake on LAN* (WOL) tec hnology
•Deep power-down mode support
•Sup port of Tot al Cost of Ownershi p (TCO) manage me nt int erface and Wired for Mana gement
(WfM)
•Bac kward compatible software with 82558 and 82557
•TCP/UDP checksum offload capabilities
•Support for Intel’s Adaptive Technol ogy
The follo win g is a list o f cha nges tha t wer e made from the 825 58 B-ste p F ast Ethe rnet Co ntrol ler to
the 82559 Fa st Ethernet Mult ifunct ion P CI/CardBusController.
•Use of 3.3 V power supply (82559) versus 5 V power supply
•I ndividual Addre ss, Multicast Addre s s, and ARP wake- up ev ents merged into extended
prog r a mm abl e w ake-u p packe t com mand a n d r e move d f ro m the CS M A com ma n d
•Receive collision bit in the RFD status word replaced with a TCO indication bit
•SMB port imple mented to support TCO managemen t interface
•PHY identifier in MII Register 3 modified
•External PHY support removed
•PHY-ba sed flow co ntrol removed (802.3x flow control was not remove d)
1.3 Enhancements to the 82 559 C-Step
The success of the 82559 B-step in mobile de signs has spurred the addition of several new features
to the device. Th ese enhance ments integrate new capabilities into the 82559 for both CardBus and
MiniPCI system designs:
•Reduc ing the declared Flash window requirement to 128 b ytes from 1 Mb yte.
•Adding glueless support f or PXE Flash ROM in LAN/mod em combination designs by adding
an external gating signa l
Networking Silicon — 82559
Datasheet 3
2.0 82559 Architectural Overview
Figure 1 is a high level block diagram of the 82559. It is divided into five main subsystems: a
parallel subsystem, a FIFO subsystem, the Total Cost of Ownership (TCO) subsystem, the 10/100
Mbps Ca rrier Sen se Mult ipl e Acces s with Co lli sion Dete ct (CSMA/CD) u nit, a nd the 10/ 100 Mbps
physical layer (PHY) unit.
2.1 Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI b us master interface, a
micr omachine processing unit and its corre sponding mi crocode ROM, and a PCI Tar get Control/
Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem,
pas si ng data (such as tr ansmit, re ceive, and configuration data) and command and status
parameters between these two blocks.
The dual functi on LAN and modem interfac e provi des a complete glueless connection to the PCI
bus and is compl iant with the PCI Bus Specifi cation, Revision 2.2. The 82559 pro vides 32 bits of
addressing and data, as well as the comp lete control interface to operate on a PCI bus. As a PCI
targe t, it follows the PCI con figuration form at which all ows all a ccesses to the 8 2559 to be
autom atical ly m appe d into free memory and I/O sp ace upon initializ ation of a PCI system. For
processing of t r ansmit and receive frames, the 82559 operate s as a master on the P CI b us, initi ating
zero wait state transfers for accessing these data parameters.
The 82559 Control/Status Registe r Block is part of the PCI tar get element. The Control/Status
Register block consists of the following 82559 internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPR OM Control, Modem Control and Management Data Interface
(MDI) Control .
The micromachine is an embedded processing unit contained in the 82559 th at enables Adaptive
Technol ogy. The micromachine acc esses the 82559 m icrocode ROM w orking its way through the
operation code s, opcodes (or instructions) , con tained in the ROM to pe rform its functio ns.
Parameters accessed from memory such as pointers to data buffers are also used by the
Figure 1. 82559 Block Diagram
10/100 Mbps
CSMA/CD
Data Interface Unit
(DIU)
100BASE-TX/
10BASE-T
PHY
Four Channel
Addressing Unit -
DMA
PCI Bus
Interface Unit
(BIU)
PCI Target and
Flash/Modem/EEPROM
Interface
Micro-
machine
Dual
Ported
FIFO
3Kbyte
Rx FIFO
FIFO Control
3Kbyte
Tx FIFO
SMB
Interface
Local Memory/
Modem Interface
SMB
Interface
PCI/
CardBus
Interface
TPE
Interface
82559 — Netwo rking Silicon
4Datasheet
micr om ac hine duri ng the processi ng of transmit or receive frames by the 82 559. A typical
micr om achine function is to transfer a data buffer pointer fiel d to the 82559 DMA unit for direc t
acc es s to the data buffe r. The micromachine is divide d into two units, Receive Unit and C ommand
Unit which includes transmit func tions. These two units opera te independently and concurrently.
Control is switched be tween the two units according to the micr ocode ins truction flow. The
inde pen dence of the Rec ei v e and Command uni ts in the mic romac hine al lows the 82559 to e x ecute
com mands and receiv e incoming fr ames si multaneously, with no real-time CPU interve ntion.
The 82559 contains an interfac e to an exte rnal Flash memory, an ex ternal serial EEPROM, and
mode m. The se three interface s are m ultipl ex ed, and both read and write accesse s are supporte d.
The Flash may be us ed for re mote boot functio ns, n etw ork st atis tica l and di agn ostic s func tions , and
ma nagement functions. The Flas h is mapped into hos t system me mory (an ywhere with in the 32-bi t
memory address s p ace) for softw are acce sses. It is also mapp ed into an available boot e x p ans io n
ROM loc ation during boot time of the system. More informati on on the Flash interfac e is detaile d
in S ection 4.6, “Paralle l Flash /Mode m Interface” on page 33. The EEPROM i s use d t o stor e
r elevant informati on for a L AN conne ction such as nod e addr es s, as well as board manufacturing
and conf igurat ion information. Both re ad and write accesses to the EEPROM are supported by the
82559. Information on the EEPROM interface is detailed in Se ction 4.7, “Serial EEPROM
Interface” on page 33. The modem inter face uses an ISA-like signal and is de scribed in more det ail
in S ection 6.0, “82559 Modem Functionality” on page 49.
2.2 FIF O Sub sy ste m Overv iew
The 82 559 F IFO subs ystem cons ists of a 3 Kbyt e transmit F I F O and 3 Kbyte receive FIFO. Each
FIFO is unidirectiona l and independent of the other. The FIFO subs ystem serv es as the interfac e
between the 8255 9 parallel side and the serial CSMA/CD unit. It provides a tempo r ary buff er
storage area for frames as they are either being received or transmitted by the 82559, which
improves performance:
•Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission
withi n the minimum Interfra m e Spacing (IFS).
•The storage area in the FIFO allows th e 82559 to withsta nd long PCI bus latencies without
losing incoming data or corru pting outg oing data.
•The 82559 transm it FIFO threshold allows the transmi t s tart threshold t o be tun ed to eliminat e
underruns while concurre nt transm its are being performed.
•The FIFO subsection allows extended PCI zero wait state burst accesses to or from the 82559
for both transmit and recei ve frames since the transfer is to the FIFO storage area rather than
d ir ectly to the seri al link.
•Tr ans m issions resulting in errors (collisi on detecti on or data underrun) are ret r ansmitted
directly from the 82559 FIFO, increa sing performanc e a nd eliminating the need to re-a cc es s
this data from the host system.
•Incoming runt receive frames (in other words, frames that are less than the legal minimum
f rame siz e) ca n be dis carde d autom atic ally b y th e 82559 wit hout trans ferr ing t his f aulty d ata to
the host system.
Networking Silicon — 82559
Datasheet 5
2.3 10/100 Mbps Serial CSMA/CD Unit Overview
The CSMA/CD unit of the 82559 allows it to be connected to either a 10 or 100 Mbps Ethernet
network. The CSMA/CD un it performs all of th e functions of the 802. 3 protocol such as frame
for matting, frame strip ping , colli sion hand lin g, deferral to li nk tra ff ic , etc. The CSMA/CD uni t can
also be placed in a full duplex mode which allows simul taneous tr ansmission and reception of
frames.
2.4 10/100 Mbps Ph ysical Layer Unit
The Physi ca l Layer (PHY) un it of the 825 59 allo ws con necti on to e ither a 10 or 100 Mbps Eth ernet
network. The PHY unit supports Auto-Ne goti ation for 100BASE -TX Full Duplex, 100BASE-TX
Half Dupl ex, 10B AS E-T Full Duple x, and 1 0B ASE-T Ha lf Duple x . It al so support s thre e LED pins
to indicate link sta tus, network activity, and spe ed.
82559 — Netwo rking Silicon
6Datasheet
Note: Thi s pag e left intenti onally bl ank.
Networking Silicon — 82559
Datasheet 7
3.0 Signal Descriptions
3.1 Signal Type Definitions
3.2 PCI Bus and CardBus Interface Signals
3.2.1 Address and Data Signals
Type Name Description
IN Input The input pin is a sta ndar d input only s ignal.
OUT Output The output p in is a To tem Pole O utput pin and is a standard
active driver.
T/S Tri-State The tri-state pin is a bidirectional, input/output pin.
S/T/S Sustained Tri-State
The sustained tri-state pin is an active low tri-state signal owned
and driven b y one agent at a time. The agent asserting th e S/T/
S pin lo w must dr ive it high at le ast one clock cyc le before
floating the pin. A new agent can only assert an S/T/S signal low
one cloc k cycle after it has been tri-stated b y the previous
owner.
O/ D Open Drain The open drain pin allows multiple devices to share this signal
as a wired-O R.
A/I Analog Input The analog input pin is used for analog input signals.
A/O Analog Output The analog output pin is used for analog output signals.
B Bias The bias pin is an input bias.
Symbol T ype Name and Function
AD[31:0] T/S
Address and Data. The ad dress an d data lin es are mult ipl exed on the
same PCI pins. A bus transaction consists of an address phase
followed by one or more data phases. During the address phase, the
addres s and data lines cont ain the 32-bit phy sical address. For I/O,
this is a byte addre ss; for conf igur at ion and memory, it is a Dword
address. The 82559 uses little-endian byte ordering (in other words,
AD[31: 24] contain the mo st significant by te and AD[7:0] contain the
least significant byte). During the data phases, the address and data
lines contain d ata.
C/BE[3:0]# T/S
Command and Byte Enable. The bus command and by te en able
signals are multiplexed on the same PCI pins. During the address
phase, the C/ BE# line s def ine t he bus command. Duri ng th e data
phase, the C/BE# lines are used as Byte Enables. The Byte Enables
are valid f or the entire data ph ase and d etermine which b yte lanes
car r y me anin gful data.
PAR T/S
Parity. Pa ri ty is even acr os s AD [31: 0] an d C/ BE[ 3:0 ]# li ne s . It is st ab le
and vali d one clock after the address pha se. For data phases, PAR is
stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is a sserted on a read tran saction.Once PAR is
valid, it remains valid until one clock after the completion of the current
data pha se. The master drives PAR for address and write data
pha s es; and the ta rge t, for read data ph ases .
82559 — Netwo rking Silicon
8Datasheet
3.2.2 Interface Control Signals
Symbol Type Name and Function
FRAME# S/T/S
Cycle Frame. The cycle frame signal is driven by the current master
to indicate the beginning and duration of a transaction. FRAME# is
as serted to indicate the start of a tran saction and de-asserted d uring
the fi nal data phase.
IRDY# S/T/S
Initiator Ready. The initi ator ready signa l indicates the bu s master’s
ability to complete the current data phase and is used in conjunction
with the target ready (TRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
TRDY# S/T/S
Target Ready. The target re ady signal indicates th e sele cted device’s
ability to complete the current data phase and is used in conjunction
wit h the initiato r ready (IR DY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
STOP# S/T/S
Stop. The stop signal is driven by the target to indicate to the initiator
tha t i t wi she s to st op the cur re nt tr ans ac ti on. As a bus sla v e , ST OP # is
driven by the 8255 9 to inform the b us master to s top t he cur rent
transact ion. As a b us master, STOP# is received by the 825 59 to stop
th e cu r re nt transa ction.
IDSEL IN
Initialization Device Select. The initialization device se lect signal is
us ed by the 82559 as a chip select during PCI configu ration read and
write tran sact ions. This s ignal is provided by th e host in PCI systems .
In a C ardBus s ystem, this pin should not be conn ected.
DEVSEL# S/T/S
Device Select. Th e d e vice se le ct sign al i s as se rted b y th e t arg et on ce
it has detected its address. As a bus master, the DEVSEL# is an input
signal to the 82559 indicating whether any device on the bus has been
selected. As a b us slave, the 82559 asserts DEVSEL# to indicate that
it has d ecoded its addres s as the target of the current transac tio n.
REQ# T/S Request. The request signal indica tes t o the bus arbit er that the
82559 desires use of the bus. This is a point-to-point signal and every
bus master has its own REQ#.
GNT# IN Grant. The grant signal is asserted by the bus arbiter and indicates to
the 82559 that access to the bus has been granted. This is a point-to-
p oi nt sign al and every master has it s own GN T# .
INTA# O/D Interrupt A. The interrupt A signal is used to request an interrupt by
the 82559. This is an active low, level triggered interrupt signal.
SERR# O/D System Error. The system error signal is used to report address
parity errors. When an error is detected, SERR# is driven low for a
single PCI cl ock.
PERR# S/T/S
Parity Error. T he parit y err or si g na l i s us ed to r ep ort dat a pa ri ty err ors
during all PCI transactions except a Special Cycle. The parity error pin
is asserted two clock cycles after th e error was detected by the device
receiving data. The minimum duration of PERR# is one clock for each
data phase where an error is detected. A device cannot report a parity
err or until it h as claimed the access b y asserting DEVSEL# an d
completed a data phase.
Networking Silicon — 82559
Datasheet 9
3.2.3 System and Power Management Signals
Symbol T ype Name and Function
CLK IN
Clock. The Clock signal provides the timing for all PCI transactions
and is an input si gnal to every PCI device . The 82559 requires a PC I
Clock signal (frequency greater than or equal to 16 MHz) for nominal
operation. The 82559 su pports Clock signal suspension using t he
Clockrun protocol.
CLKRUN# IN/OUT
O/D
Clockrun. The Cl oc k run si gn al is used b y t h e sy stem to pa us e o r slo w
dow n t he P CI C loc k si gna l . It is use d b y th e 825 59 t o ena bl e or d is abl e
suspension of the PCI Clock signal or restart of the PCI clock. When
the Clockrun signal is not used, this p in should be co nnected to an
external pull-down resistor.
RST# IN Reset. The PCI Reset signal is used to place PCI registers,
sequencers, and signals into a consistent state. When RST# is
ass erted, all PCI ou tput signals will be tri-st ated.
PME#
(PCI) O/D Power Management Event. The Power Management Event signal
indicates that a power management event has occurred in a PCI bus
system.
CSTSCHG
(CardBus)/
WOL (PCI) OUT
Card Status Change/Wake on LAN. Th is pin is multip lexed to
provi de Card Status Change o r Wake on LAN sign als. In a Car dBus
sys tem, it is u s ed as the Card Status Change output sign al and is an
asynchronous signal to the Clock signal. It indicates that a power
management event has occurred in a CardBus system. In a PCI
system, it is used as the WOL pin and provides a positive pulse of
approximat ely 52 ms upon de tection of an inco ming Magic Packet*.
ISOLATE# IN
Isolate. The Isolate signal is used to isolate the 82559 from the PCI
bus. When Isolate is active (low), the 82559 does not drive its PCI
output s (except PME# and CSTSCHG) or sample its PCI in puts
(incl uding CLK and RS T#). If t he 82559 is no t po wered by an auxiliary
power source, the ISOLATE# pin must be pulled high through a
100 KΩ resistor.
ALTRST# IN
Alternate Reset. The Alternate Reset signal is used to reset the
8255 9 o n p o we r-u p . In sy stem s t ha t su pp ort an au xi li ary po w er s uppl y,
ALTRST # should be conn ected to a po wer- up detection circuit.
Otherwise, ALTRST# should be tied to VCC.
VIO B
IN
Voltage Input/Output. The VIO pin is the voltage bias pin for the PCI
interface. In a 5 V or 3.3 V signaling environment, it shou ld be
connected through a 100 KΩ resistor to the 5 V or 3.3 V supply.The
resistor acts as a leakage current limiter in systems where the VIO
bi a s vol tag e may be tu r ned off .
82559 — Netwo rking Silicon
10 Datasheet
3.3 Local Memory Interface Signals
Note: Al l unus ed Flash Addre ss and Data pins must be left floatin g. Some of these pins have
undocumente d test functionality and can cause unpredictable behavior i f they are unnecessa r ily
connected to a pull-up or pull-down resistor.
Symbol Type Name and Function
FLD[7:0] T/S Flash/Modem Data Input/Output. Thes e pins are used for Flash/
Modem data interface. These pins should be left floating if the F lash
and modem are not used.
FLA[16]/
CLK25 OUT
Flash Address[16]/25 MHz Clock. T hi s mu lti pl exed pin is con tr o lle d
by the stat us of the Fl ash Address[7] (FLA[7]) pin. If F LA[7] is left
float ing, this pi n is used a s FLA[16 ]; other wis e, i f FLA[7] is conne c ted
to a pull-up resistor, this pin is used as a 25 MHz clock. This pin should
be left floating if th e Flash and CLK25 functionali ty are not used.
FLA[15]/
EESK OUT
Flash Address[15]/EEPROM Data Output. During Flash accesses,
this multiplex ed pin acts as the Flash Address [15] output signal.
During EEPROM accesses, it acts as the seri al shift clock ou tput to
the EEPRO M.
FLA[14]/
EEDO IN/OUT
Flash Address[14]/EEPROM Data Output. During Flash accesses,
this multiplex ed pin acts as the Flash Address [14] output signal.
During EEPROM accesses, it accepts serial inpu t data from the
EEPROM Data Output signal.
FLA[13]/
EEDI OUT
Flash Address[13]/EEPROM Data Input. During Fl ash a ccesses,
this multiplex ed pin acts as the Flash Address [13] output signal.
During EEPROM accesses, it provides serial output data to the
EEPRO M Data Input si gnal.
FLA[12]/
MCNTSM# OUT
O/D
Flash Address[12]/Modem Central Site Mode. This multiplexed pin
ac ts as t he Fl ash A ddres s[12] output si gnal in a non-modem card. If
modem is enabled, it is used as an output signal to the modem. It is
either floated by default or driven low by the Modem System Control
Registers. T his pin should be left floating if th e Flash and modem
functionality are not used.
FLA[11]/
MINT IN/OUT
Flash Address[11]/Modem Interrupt. This multiplexed pi n acts as
the Fl as h Add res s[ 11 ] o utp ut si gnal in a n on -mod em c ard . I f mo dem is
enabled, it is us ed a s t he Mo de m I n ter rupt i np ut s ig na l. T hi s pi n s ho uld
be left flo ati ng if the Flash and mo dem functio nality ar e not used.
FLA[10]/
MRING# IN/OUT
Flash Address[10]/Modem Ring. Th is mult iplexed pi n acts as the
Flash Address[10] output signal in a non-modem card. If modem is
enabled, it is used as the Modem R ing input signal. This pin should be
left floating if the Flash and modem functionality are not used.
FLA[9]/
MRST OUT
Flash Address[9]/Modem Reset. This multiplexed pin acts as the
Flash Address[9] output signal in a non-modem card. If m odem is
enabled, it acts a s the Modem Rese t signal with an activ e high out put .
Thi s p in sh ould be l ef t f lo atin g if the F la sh and m ode m f u ncti on al it y ar e
not us ed .
FLA[8]/
IOCHRDY IN/OUT
Flash Address[8]/ISA Input/Output Channel Ready. This
multiplexed pin acts as the Flash Address[8] output signal in a non-
modem card. If modem is enabled, it is used as the ISA IOCHRDY
input s ignal. This pin should be left floating if the Flash and modem
functionality are not used.
Networking Silicon — 82559
Datasheet 11
FLA[7]/
CLKEN T/S
Flash Address[7]/Clock Enable. This is a multiple x ed pin and acts
as the Flash Address[7] output signal during nominal operation. When
the PCI Reset signal is active, this pin acts as input control over the
FLA [16] / CLK 25 outp ut si gnal . If t he FL A[7 ]/C LKE N pi n i s co nn ec ted t o
a pull-up resist or (3.3 KΩ), a 2 5 MHz clock signal is pr ovided on th e
FLA[16]/CLK25 output; otherwise, it is used as FLA[16] output. This
pin should be left floating if th e Flash and 25 MHz clock output are not
used.
FLA[6:2] OUT
Flash Address[6:2]. These pins are used as Flash address outputs
to support 128 Kbyte Flash addressing. If the modem is enabled,
these pins carry modem ad dress bit s 6:2 . This pin should be left
float ing if the Flash and modem functi onality are not us ed.
FLA[1]/
AUXPWR T/S
Flash Address[1]/Auxiliary Power. This multiplexed pin acts as the
Flas h A d dre ss[ 1] o ut put si gn al dur in g nom in al o per at ion. I f the mo de m
is e nab le d, thi s pi n ca rri es mode m ad dres s bi t 1. Whe n RST # is ac ti v e
(low), it acts as the power supply indicator. If the 82559 is fed PCI
power, this pi n should be connec ted to th e Flash Address 1 (of the
Flash component) signal or left floating if Flash is not present. If the
82559 is fed by auxiliary power, this pin should b e connected to a pull-
up resistor.
FLA[0]/
PCIMODE# T/S
Flash Address [0]/PCI Mode. Th is mult iplexed pi n acts as the Fl ash
Addr ess[0] output s ignal during nominal operation. If t he modem is
enabled, this pin carries modem address bit 0. When RST# is active
(low), it acts as the input system type. If the 82559 is used in a
CardBus system, this pin should be c onnected to a pull -up resis tor
(3.3 KΩ); otherwise, the 82559 considers the host as a PCI system.
This pi n sho uld be le f t fl oa tin g i f the Fl as h a nd mo de m f unc tio na li ty a r e
not used.
EECS OUT EEPROM Chip Select. The EEPROM Chip Select signal is used to
ass ert chip se lect to the serial EEPROM.
FLCS#/AEN OUT
Flash Chip Select/Address Enable. The Flash Chip Select signal is
active during Flash. In modem mode, it acts as an ISA-like Address
Enable signal (modem chip select). This pin should be left floating if
the Flash and modem functionality are not used.
FLOE# OUT
Flash Output Enable. This pin provides an active low output enable
cont r ol (r ead) to th e Fl as h memo ry. If th e mo dem is enab l ed , thi s is an
active-low output enable (read) of the modem. This pin should be l eft
float ing if the Flash and modem functi onality are not us ed.
FLWE# OUT
Flash Write Enable. This pin provides an active low write enable
control to the Flash memory. If the modem is enabled, this is an active
low write-enable to the modem. This pin should be left floating if the
Flash and modem functionali ty ar e not used.
CFCS# OUT
Security ASIC Chip Select. This pin provides an active low function
enable to enable/disable Flash memory in Combo designs. This signal
is asserted high to enable Flash memory in LAN/modem designs. If
this si gn al is a sse rted l o w, the mod em devi ce is en ab led , an d lo cal b u s
signals are d efi ned f or modem. Thi s pin is controlled by setting/
clearing the Boot Enable bit in the BootROM BAR. This bit is set
fol lowing a PC I re s et en abli ng external Fl as h.
CFCLK OUT Security ASIC Clock. This pin provides a clock out to a companion
ASIC residing on the local bus. This pin should be left unconnected in
designs that do not utilize a companion A SIC on the Flash int erface.
Symbol T ype Name and Function
82559 — Netwo rking Sili con
12 Datasheet
3.4 System Managem ent B us (SMB) Inter face Si gnals
3.5 Tes tab ility Port Sign als
3.6 PH Y Si gn al s
Symbol Type Name and Function
SMBD IN
O/D
Alert Bus Data. This signal is stable when the Alert Bus Clock signal
is high. This op en dr ain signal should be pulled high to VCC in all
cases.
SMBCLK IN
O/D
Alert Bus Clock. This pin is used for the Alert Bus Clock signal. One
clock pulse is generated for each data bit transferred. It is an open
drai n signal and should be p ulled high to VCC in all cases.
SMBALRT# O/D Bus Alert. The Bus Alert pin is used as an interrupt signal for a slave
deviceon the Alert Bus. Itis an open drain signaland should be pulled
high to VCC in all cases.
Symbol Type Name and Function
TEST IN Test Port. If this input pin is high, the 82559 will enable the test port.
During nominal operation this pin should be connected to a pull-down
resistor.
TCK IN Test Port Clock. This pin is used for the Test Port Clock signal.
TI IN Test Port Data Input. This pin is used for the Test Port Data Input
signal.
TEXEC IN Test Port Execute Enable. Thi s pin is us ed for t he Test Port Execute
Enable signal.
TO OUT Test Port Data Output. This pi n is us ed for the Tes t Po r t Data Ou tpu t
signal.
Symbol Type Name and Function
X1 A/I Crystal Input One. X1 and X2 can be driven by an external 3.3 V 25
MHz cr ystal. Otherwise, X1 may be driven by an external metal-oxide
semiconductor (MOS) le v el 25 MHz oscillator when X2 is left floating.
X2 A/O Crystal Input Two. X1 and X 2 ca n be dr ive n by an exte r n a l 3.3 V 25
MHz crystal. Otherwise, X1 may be driven by an external MOS level
25 MHz oscillator wh en X2 is lef t floati ng.
TDP
TDN A/O
Analog Twisted Pair Ethernet Transmit Differential Pair. These
pins transmit the serial bit stream for transmission on the Unshielde d
Twisted Pair (UTP) cable. The current-driven differential driver can be
tw o-l e vel (1 0BA SE- T) or thr e e-l e v el ( 10 0BA SE- TX ) sign al s de pe nd ing
on the mode of operation. These signals interface directly with an
isola tion tr an sformer.
RDP
RDN A/I
Analog Twisted Pair Ethernet Receive Differential Pair. These pins
receive the serial bit stream from the isolation transformer. The bit
stream can be two-lev el (10BASE-T) or three-level (100BASE-TX)
signals depending on t he mode of operation.
Networking Silicon — 82559
Datasheet 13
ACTLED# OUT
Activity LED. The Activity LED pin indicates either transmit or receive
activity. When activity is present, the activity LED is on; when no
activity is present, the activity LED is off.
In Wake on LAN mode, the ACTLED# signal is used to indi cate that
the received frame pa ssed MAC address filtering.
LILED# OUT Link Integrity LED. The Link Integrity LED pin indicates link integrity.
If the link is valid in either 10 or 100 Mbps, th e LED is on; if l ink is
invalid, the LED is off.
SPEEDLED# OUT Speed LED. The Speed LED pin indicates the speed. The speed LED
will be on at 100 Mbps and off at 10 Mbps.
RBIAS100 B Reference Bias Resistor (100 Mbps). This pin should be connected
to a 619 Ω pull-down resistor.a
RBIAS10 B Reference Bias Resistor (10 Mbps). This pi n should be connected
to a 549 Ω pull-down resistor.b
VREF B
Voltage Reference. This pin is connected to a 1.25 V ± 1% ex ternal
v oltage reference gener ator. To use the internal voltage reference
source, this pin should be left floating. Under normal circumstances,
the in te rnal v ol t age r e fe r en ce sh ould be u sed a nd this p in wo ul d b e le ft
open.
a. 619 Ω for RBIAS 100 is only a recommended value and should be fine tuned for various designs.
b. 549 Ω for RBIAS 10 is only a recommended value and should be fine tuned for various designs.
Symbol T ype Name and Function
82559 — Netwo rking Sili con
14 Datasheet
Note: Thi s pag e left intenti onally bl ank.
Networking Silicon — 82559
Datasheet 15
4.0 82559 Media Access Control Functional Descripti on
4.1 82559 Initialization
The 8255 9 has four sources for initialization. They are listed ac cording t o their precedence:
1. ALTRST# Signal
2. PCI RST# Signal
3. Soft ware Reset (S oftware Com mand)
4. Selectiv e Reset (Software Comma nd)
4.1.1 Initialization Effects on 82559 Units
The f oll o wing ta ble s ho ws the e f fect of ea ch of t he d if fer ent i nit ia liza tio n sourc es on major porti ons
of the 82559. The init ia liza tion s ources are l isted in orde r of pr ecedence . For example , an y res ource
th at is initialize d by the Software Reset is also init iali zed by th e D3 to D0 tr ansition and ALTRST#
and PCI RST# but not neces sarily by t he selective reset.
ALTRST# PCI RST# ISOLATE# D3 to D0
Transition Software
Reset Selective
Reset
EEPROM read and
initialization XXX-- -- --
Loadable mi croc ode
decoded/reset XX-- XX--
MAC configuration reset and
multicast hash XXXXX--
M emory po int ers and
mircomachine state reset XX-- XXX
PC I Configurati on register
reset XXXX-- --
PHY configuration reset XX-- -- -- --
Power management event
reset X
Clear only
if no
auxiliary
power
present
-- -- -- --
Sta t is tic coun t e r s res et XX-- XX--
82559 — Netwo rking Sili con
16 Datasheet
4.1.2 Initialization Effects on TCO Functionality
The 82 559 has the ability to be controll ed by two masters, the host CPU on the PCI bu s and the
TCO con troller on the SMB. The 82559 may be initialized by the PCI b us du ring SMB operation.
The table below summarizes the effect of those sources:
4.2 PCI and CardBus Interface
4. 2.1 8 2559 Bus Oper ations
After conf iguration, the 82559 is ready for it s normal operation. As a Fast Ether net Contro ller, the
role of the 82559 is to access transmitted data or deposit received data. In both cases the 82559, as
a bus master dev ice , will initiate mem ory cycles via the PCI bus to fetch or deposit the require d
data.
I n or der to perform these actions, the 82559 is controlled and examined by the CPU via its c ontrol
and s tatus structures and re gisters. Some of these c ontrol and status structures reside in the 82559
and some reside in system memory. For access to the 82559’s Control/Statu s Registers (CSR), the
82559 acts as a slave (in othe r w ords , a t arget device). The 82559 serves as a slave also while the
CPU accesses its 128 Kbyte Flas h buffer or its EEPROM. When the 82559 is in modem mode, it
also acts as a sl ave. Details regarding mod em i nterface ar e described in Se ction 4. 6, “Parallel Flash/
Modem Interface” on pa ge 33.
Section 4.2.1.1, “82559 Bus Slav e Operation” describes the 82559 sla ve operation. It is follo w ed
by a de scription of the 82559 operation as a bus mast er (initiator) in Sect ion 4.2.1.2, “825 59 Bus
Master Op er at i on ” on page 22.
4.2.1.1 82559 B u s Sl ave Oper ati o n
The 82559 se rves as a ta rget device i n one of the following cases:
•CPU accesses to the 8 2559 S ystem Control Block (SCB ) Control/Status Registe rs (CSR)
Init ia lizati on Source SMB Be havior Status and Receive
Enable
ALTRST#, PCI RST#, or
ISOLATE#aThe SMB is terminat ed instantaneously.bI nitialized to inactive
D3 to D0 transition
The SMB cycl e is aborted. During SMB read
c ommands , the 82559 transfers zeros until the end of
the cycle. An SMB writ e cycle has no ef fect on the
82559. The 82559 asserts the SMBALRT# after a D3
to D0 transition. The 82559 indicates its initialization
status to the TCO controller via an active initialization
bit in the Status word.
Initialized to inact ive
Software Reset,
Selective Reset, or D3 to
D0 transition
The SMB cycl e is aborted. During SMB read
c ommands , the 82559 transfers zeros until the end of
the cycle. An SMB writ e cycle has no af fect on the
82559. After a software reset, the 82559 reports its
in itializati on in th e s ame manner as in a D3 to D0
transition.
Unaffected
a. ISOLATE# acts as reset on its trailing edge. While the 82559 is in the D3 power state, the PCI RST# initializes the 82559
on the trailing edge.
b. SMB commands in process will be terminated immediately.
Networking Silicon — 82559
Datasheet 17
•CP U ac c esses to th e EE P ROM th r o u gh it s CS R
•CPU acce sses to the 82559 PORT address via the CSR
•CPU acce ss es to t he M D I control regist er in th e CSR
•CP U accesses to th e Fl ash co n tr o l reg ist er in th e C S R
•CPU accesses to the 128 Kbyte Flash
The CSR and the 1 Mbyte Flash buffer are conside r ed by the 82559 as two totally se parated
memory spaces. The 82559 provides se para te Base Address Registers (B ARs) in the configurat ion
spa ce t o distinguish betwe en them. The size of the CSR memory space is 4 Kbyte in th e memo ry
spa ce and 64 bytes in the I/O space. The 82 559 treats acc es ses to th es e mem ory spaces diffe r ently.
4.2.1.1.1 Control/Status Register (CSR) Accesses
The 825 59 su pports zero wait state single cycle memory or I/O mapped accesses to its CSR space.
Separate BARs reque st 4 Kb ytes of memory space and 64 bytes of I/O space to ac com plish this .
Bas ed on its needs, the softwar e driver will use eit her memory or I/O mapping to ac cess these
registe r s. The 82559 provides 4 valid Kbytes of CSR spac e, which inc lude the following elements:
•System Control Block (SCB) registers
•PORT register
•Flash control register
•EEPROM control register
•MDI control register
•Flow control registers
•Car dBus re gis ters
The figures below show CSR zer o wait st ate I/O read and write cycles. I n the case of accessing the
Control/Status Re gisters, the CP U is the initia tor and the 82559 is the target of the transaction.
Figure 2. Con trol/Status Register I/O Read Cycle
SYSTEM
82559
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 56789
ADDR DATA
I/O RD BE#
STOP#
82559 — Netwo rking Sili con
18 Datasheet
Read A ccesse s: T he CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[ 3:0] and the control lines IRDY# a nd FRAME#. As a sla ve, the 82559 c ontrols
the TRDY# signal and pro vides valid data on each data access. The 82559 allows the CPU to iss ue
only one read cycle when it acc esses th e Control/S tatus Re gisters , generating a disconnect by
as serting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not
ready .
Write Accesses: The CPU, as the initia tor, dr ives the add r ess line s AD[31:0], the command and
byte enable lines C/BE#[3:0] and the contr ol lines IRDY# an d FRAME#. It also provides the
82559 with valid dat a on each data access immedia tely after asserting IRDY#. The 82559 controls
the TRDY# signal and as se rts it from the data a cc es s. The 82559 allows the CPU to issu e only one
I /O write cycle to the Control/Status Re gisters , generat ing a discon nec t by asserting the STOP#
signal. This is tr ue for both memory mappe d and I/O mapped accesses.
Figure 3. Contro l/ Status Register I/O Write Cycle
SYSTEM
82559
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 56789
ADDR DATA
I/O WR BE#
STOP#
Networking Silicon — 82559
Datasheet 19
4. 2.1.1. 2 Fl ash B u ffer Acc esse s
The CPU accesses to the Flash buff er are very slow. For this reason the 82559 issue s a target-
disc onnect at the first data acc ess. The 8255 9 asserts the STOP# signal t o indicate a target-
disconnect. The figures below illustrate memory CPU read and write acc esses to the 128 Kbyte
Flash b uffer. The longest b urs t cy cle to the Flash buf fer contains one data access only.
Read Accesses: T he CPU, as the initiator, dri ves the addres s lines AD[ 31:0], the com mand and
byte enable l ines C/BE#[3:0] and the control line s IRDY# and FRAME#. The 82559 controls the
TRDY# signal and de-ass erts it fo r a c ertain number of cloc ks until valid data can be read from the
Figure 4. Fl ash Buffer Read Cycle
SYSTEM
82559
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD ADDR DATA
MEM RD BE#
STOP#
82559 — Netwo rking Sili con
20 Datasheet
Fl as h buffer. When TRDY# is asserted, the 82559 dri ves valid da ta on the AD[31:0] lines. The
CPU can also i ns ert wait states by de-a sserting IRDY# until it is ready. Flash buffer read acce s se s
can be byte or word length.
Write Accesses: The CPU, as the initiator, driv es the address lines AD[31:0], the command and
b y te enable li n es C/BE#[3 :0] and the control lines IRDY# and FRAME#. It also provides the 82559
with valid data immediately after asserting IRDY#. The 82559 co ntrols the TRDY# signal and de-
as serts it for a ce rtain number of clocks until val id data is writ ten to the Flas h buffer. By asserting
TRDY#, the 82559 sig nals the CPU that the current data access has com pleted. Flash bu ffer wri te
acc es ses can be byte length only.
4.2.1.1.3 Retry Premature Accesses
The 82559 res ponds with a Re try to any configuration cycle ac cessing the 82 559 before the
completion of the automatic read of the EEPROM. The 82559 may continue to Retry any
configuration accesses until the EEPROM read is complete. The 82559 does not enforce the rule
that th e r et r ied ma s t er mu s t at te m p t to ac ce s s th e sa me add r ess aga in in ord er to comp let e any
del ayed tra nsacti on. An y master acces s to th e 82559 a fter the c ompletion of th e EEPR OM re ad will
be honored. Figure 6 below depicts how a Retry looks when it occ urs .
Figure 5. Flash Buffer Write Cy cle
SYSTEM
82559
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD ADDR
MEM WR BE#
STOP#
DATA
Networking Silicon — 82559
Datasheet 21
Note: T he 82559 is considered the ta rget in the abo ve diagram; thus, TRDY# is not asserted.
A Retry may also occur in the following two scenarios:
•Card Information Structure (CIS) in memory is accessed in CardBus mode.
•External modem registers are accessed and the modem does not assert IOCHRDY within 7
PCI clocks from the assertion of MDMCS#.
4.2.1.1.4 Error Handling
Data Parity Errors: The 82559 checks for data parity errors while it i s the target of the
transaction. If a n er ro r w as de tected, the 82 559 always set s the Detected Parity Error b it in the P CI
Configuration S tatus re gister, bi t 15. The 82559 al so asserts PERR#, if the Parity Error Response
bit is set (PCI Configuration Comma nd register, bit 6). The 82559 does not attempt to termina te a
cycle in which a parity error was detected. This gives the initiator the option of recovery.
Target-Disconnect: The 82559 prematurely terminate a cycle in the fol lowi ng cases:
•Af te r acces s es to th e F l ash buffer
•Af ter acces ses to it s CSR
•Af te r acces ses to th e con fi gur ati o n sp ace
System Error: The 82 559 report s pari ty erro r duri ng the addre ss phase us ing the SERR# pi n. If the
SERR# E nable bit in the PC I Configuration Command register or the Pari ty Error Respons e bit are
not set, the 82 559 only sets the Dete cted P arity Er ror bit ( PCI Conf ig uration Status re gis ter , bit 15).
If SERR# Enable and P arity Error R esponse bits are b oth set, th e 82559 sets the Sign ale d S ystem
Error bit (PCI Conf iguration S tatus re gister, bit 14) as well as the Detected Parity Error bit and
asserts SERR# for one clock.
The 82559, when detecting system error, will clai m th e cycle if it was the target of the trans ac tion
an d co n tinue the transaction as i f t h e addr ess w as co rrec t .
Note: The 82559 will report a syste m error for a ny parity error during an address pha s e, whether or not i t
is involved in the current transa ction.
Figure 6. PCI Retry Cycle
SYSTEM
82559
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
82559 — Netwo rking Sili con
22 Datasheet
4.2.1.2 82559 B u s M aste r O p er ation
As a PCI Bus Master, the 82559 initiates memory cycles to fetch data for transmission or deposit
r ec eived data and for accessing the memory resident control struct ures . The 82559 perform s zero
wait state bu r st re ad and write cy cles to the hos t ma in memory. Figure 7 and Figure 8 depict
me mory read and wr ite b urst cyc les. For bus master cycles, the 82559 is the initiator and the host
ma in memo ry ( or the PCI host bridge , de pending on th e con f iguration of the system) is the target.
The CPU provides the 82559 with action commands and pointers to the data buffers that reside in
host main memory. The 82559 independent ly manages these structures and initiates burst memo ry
cycles to transfer data to and from them. The 82559 uses the Memory Read Multipl e (MR
Multiple ) com m and for burst accesses to data buffers and the Memory Read Line (MR Line)
command for burst accesses to control structures. For all write accesses to the control structure, the
82559 uses the Memory Write (MW) command. For write acc es s es to data stru cture, the 82559
ma y use either the Memory Writ e or Memory Write and Inv alidate (MWI) comma nds .
Figure 7. Memory Read Burst Cycle
82559SYSTEM
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 5678910
ADDR DATA
MR BE# BE#
DATA DATA DATA DATA
Figu re 8. Mem or y Write Burs t C ycle
82559SYSTEM
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 5678910
ADDR DATA
MW BE# BE#
DATA DATA DATA DATA
Networking Silicon — 82559
Datasheet 23
Read Ac ce sses: The 82559 perform s block tran sfer s from host system memory i n orde r to perform
frame transmission on the serial link. In this case , the 8 2559 initiates zero wait sta te memory read
burst cycles for these accesses. The length of a burst is bounded by the system and the 82559’s
internal FIFO. The l ength of a read burst may also be bounded by the value of the T r ansmit DMA
Maxim um Byte Count in the Configure command. The T r ansmi t DMA Maxim um Byte Count
v alue indica tes the ma ximum number of transmi t DMA PCI c y cles that will be completed after an
82559 internal arbitr ation.
The 82559, as the initiator, drives the address lines AD[31:0], the command and b yte enable l ines
C/BE#[3:0 ] and the control li nes IRDY# and FRAME#. The 8 2559 as s erts IRDY# to suppor t zero
wait stat e burst c ycles. The target s ignals the 82559 that v ali d data is ready to be read b y as serting
th e TRDY# signal.
Write Accesses: The 82559 performs block transfers to hos t s ystem memory durin g fr ame
rece ption. In this case, the 82559 initiates memory write b urst cyc les to deposit the data, usually
without wait st ates. The length of a burs t is bounded by the syste m an d the 82559’s internal FIFO
thres hold. The length of a write burst ma y also be bounded by the v alue of the Receive DMA
Maxim um Byte Count in th e Conf i gure comm and. Th e Recei v e DMA Maxim um Byte Count v alu e
indicates the maximum number of receive DMA PCI transfers that will be completed before the
82559 internal arbitr ation. (Details on the Configure command are described in the 10/100Mbit
Family Software Deve loper’s Manual.)
The 82559, as the initiator, drives the address lines AD[31:0], the command and b yte enable l ines
C/BE#[3:0 ] and the control li nes IRDY# and FRAME#. The 8 2559 as s erts IRDY# to suppor t zero
wait state burst cycles. The 82 559 also drives valid data on AD[31:0] lines duri ng each data phas e
(from the first clock and on). The tar get control s the le ngth and signals completion of a data pha s e
by de-a ssertion and assert ion of TR DY#.
Cy cl e C o mpletio n : The 82559 completes (terminates) its initiated memory burst cycles in the
following cases:
•Normal Completi on: All t ransact ion data has been trans ferred to or from t he ta rget de vic e (for
example, host main memory).
•Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the
82559 by the arb iter, indicating that the 82559 has been preempted by another bu s master.
•Transmit or Receive DMA Maximum Byte Count: The 82559 burst has reached the le ngth
spe cified in the Transmit or Receive DMA Maximum By te Count field in the Conf igure
command block.
•Target Termination: The target may request to termi nate the tra nsaction with a target-
disconnect, target-retry, or target-abort. In the first two cases, the 82559 initi ates the cycle
agai n. In the case of a target-abort, the 825 59 sets the Received Target-Abort bit in the PCI
Configuration S tatus field (PCI Confi guratio n St atus register, bit 12) and does not r e-initiate
the cycle.
•Master Abort: The target o f the transaction ha s not responded to the addres s in itiated by the
82559 (in other wor ds, DEVSEL# has not been asserte d). The 82559 simply de-assert s
FRAME# and IRDY# as in the case of normal completion.
•Erro r C o nd it i o n: In the event of pari ty or any other s ys tem error detec tion, the 82559
comp letes its c urrent initiated tra nsacti on. Any further ac tion taken by the 82559 depends on
the type of error and othe r condit ions .
82559 — Netwo rking Sili con
24 Datasheet
4.2.1.2.1 Memory Write and Invalidate
The 82559 has four Direct Memory Access (DMA) channels. Of these four channels, the Receive
DMA is used to deposit the large number of data bytes received from the link into system memory.
The Rece ive DMA u ses bo th the M emory W rite (MW) and th e Memo ry Writ e and Invalidat e
( MWI) commands. In order to use MWI, the 82559 must guarantee the fol lowi ng:
1. Minimum tran sfer of one cache line
2. Active byte enable bits ( or BE#[3:0] are all low) during MWI acc es s
3. The 82 559 may cross the cache line boundary only if it intends to transfe r the next ca che line
too.
I n or der to ensure the abo ve conditio ns , the 82559 may use th e MWI comman d only if the
f ollowing conditio ns hold:
1. The Cache Line Size (CLS ) written in the CLS register during PCI configuration is 8 or 16
Dwords.
2. The accessed address is cache line aligned.
3. The 82559 has at least 8 or 16 Dwords of data in its receive FIFO.
4. Ther e are at least 8 o r 16 Dwo rd s o f dat a sp ace lef t in the s y st em memo r y buffer.
5. The MWI Enable bit in the PCI Conf iguration Command register, bit 4, should is se t to 1b.
6. The MWI Enable bit in the 82559 Configure comman d should is set to 1b .
I f any one of the abo ve conditions does not hold, the 82559 wil l us e the MW command. If a MWI
cycle has s tarted and one of the conditions is no longer v alid (for example , the data spac e in the
memory buffer is now less than CLS), then the 82559 terminates the MWI cycle at the end of the
cache line. The next cycle will be either a MW or MWI cycle depending on the conditions listed
above.
If the 82559 started a MW cycle and reached a cache line boundary, it either continues or
terminat es the cycle depe nding on the Termin ate Wri te on Cache Line configuration bit of the
82559 Confi gure command (byte 3, bi t 3). If this bit is set, the 82559 termina tes the MW cycle and
attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all of the above
listed con d itions are met. If the bit is not set, the 82559 continues the MW cycle acros s the cache
line boundary if required.
4.2.1.2.2 Read Align
The Read Align feature enhances the 82559’s performance in cache line oriented systems. In these
particular systems, starting a PCI transaction on a non-cache line aligned address may cause low
performance.
In order to resolve this performance anomaly, the 82559 attempts to terminate transmit DMA
cycles on a cache line bou ndary and start the next transa ction on a cache line aligned address. Thi s
f eature is enabled when the Read Align E nable bit is set in the 82559 Configure command (byte 3,
b it 2).
I f this bit is set, the 82559 op erates as fol lows:
•When the 82559 is al most out of resources on the transmit DMA (that is, t he transmit FIFO is
almost full), it attempts to terminate the read transaction on the nearest cache line boundary
when pos s ible.
Networking Silicon — 82559
Datasheet 25
•When the arb i tration coun t er’s feature is ena b led (in o ther words, the Tran smit DMA
Maxim um By te Count v alue is set in the Configure command), the 82559 switches t o other
pending DMAs on cache line boundary only.
Note the following:
•This feature is not re comm ended for use in non-cache line oriented systems si nce it ma y cause
short er burst s and lower performa nce .
•This fea ture should be u se d only when the CLS register in PCI Conf igura tion spac e is set to 8
or 16.
•The 8255 9 reads all control data structur es (includ ing Receive Buffer Desc riptors) from t he
first Dword (even if it is not required) in order to maintain cache line alignment.
4.2.1.2.3 Error Handling
Data Parity Errors: As an initi ator, the 82559 checks and det ects data pa rity errors tha t occur
dur ing a transa ction. If the Parity Error Response bit is set (PCI Configur ation Command re gister,
bit 6), the 82559 also as s erts PERR# and sets the Data Parity Det ected bit (PCI Conf igurati on
Status regi st er, b it 8). In addition, if the error was detec ted by the 82559 during read cycles, it sets
the Det ected Pari ty Error bit ( PCI Configu r ation Status register, bit 15).
4.2.2 PCI Mode Pin
During P CI reset the 82559 samp les the PCIMODE# (mult iplexed with FLA0) input signa l to
deter min e the natu r e o f th e ho st sys t em. If th e PCI M O D E # sig n a l is s amp led low w h en RS T# is
active , the host system bus is a PCI sy stem. If PCIMOD E # is sampled high durin g reset, the host
system is a CardBus system. In a CardBus system, the PCIMODE# pin shoul d b e connected to a
pull-up resistor; otherwise, the 82559 assumes it is a PCI system.
4.2. 3 Clo c kr un Sig nal
The CLKRUN# signal i s used to control the PCI clock as defined in the CardBus specific ation and
PCI Mobi le design gui de a nd is com pliant with both the CardBus specification and PCI Mobile
des ign guide . This sig nal is activ e in both the Card Bus and PC I b us oper ating mode s. T he Cloc krun
signal is an open drain I/O signal. It is used as a bidirectional channe l between the host and the
devices.
•The host de-asserts the CLKRUN# signal to indicate that the clock is about to be stopped or
slo w ed down to a non-operational fre quency.
•The host asserts the CLKRUN# signal when the interface clock is either running at a normal
operating fr eque ncy or about to be start ed.
•The 82559 as se rts the CLKRUN# signal to indicate tha t it needs the PCI clock to prevent the
host fro m stopping the PCI clo ck or to request that the host restore the clock if it was
previ ously stopp ed.
Prope r operation requires that t he system latency from the n omi nal PCI CLK to CLKRUN#
assertion should be less than 0.5 µs. If the system la tency is longer than 0.5 µs, the occurrence of
rece iv e ov erruns increases . For use in the se types of sy stems, th e Clockrun functionality should be
disa bled (Section 9.1.12, “General Control Regi ste r” on page 76 ). In t his c ase, t he 82559 wi ll claim
the PCI clock even during idle time. If the CLKRUN# signal is not used, it should be connected to
a pull-down resistor.
82559 — Netwo rking Sili con
26 Datasheet
4.2.4 Power Management Event and Card Status Change Signals
The 82559 supports power mana gem ent i ndications in both the PCI and CardBus mode. In
CardBus system s, the CSTSCHG pin is used for power management event indicat ion. The PME#
output pin provides an indicat ion of a power manage m ent event in PCI systems. The CSTSCHG
pin is support ed by four registers located in the Control/S tatus Register (Section 9.0, “Control/
Status Registers” on pa ge 71 de scri bes the se registers in mo re deta il):
•Event Register
•Mask Regi ster
•Present State Register
•Force Event Register
4.3 PCI Power Management
I n additi on t o the ba se fun ctiona lity of the 8255 8 B-ste p, the 8255 9 support s a lar ge r set of wake -up
packets and the capability to wake the system on a link status change from a low power state. These
added power management enhanceme nts enable the 825 59 to adhere to emerging st andards. The
82559 enables the h ost syste m to be in a sleep state and rema in virt ually connected to the network.
After a power mana gement event or link status c hange is detected, the 82559 will wake the host
system. The sec tions below describe thes e events, the 82559 po wer s tates, and e stimated power
cons um ption at eac h power state.
4.3.1 Power States
The 82559 cont ains two sets of po wer mana gement regis ters , one fo r PCI and one for CardBus , and
imp lements al l four powe r st ate s as defined in the Power Management Network Device Class
Refe rence Spe cifica tion, Revision 1.0. The four stat es , D0 through D3, vary from maximum power
cons umpti on at D0 t o the m inimum power c onsumpti on a t D3. PCI t ransa ctions a re only al lo wed in
the D0 state, e xcept for host acc es ses to th e 82559’s PCI configuration registe rs. The D1 and D2
power mana gement stat es enable intermedia te power savings while providin g the system wake-up
cap abili tie s. In the D3cold state, the 82559 ca n provide wake-up c apabilities only if auxiliary powe r
is supplied. Wake-up indications from the 82559 are provided by the Po wer Management Event
( PME#) si gnal in PCI i mplemen tatio ns and the Card S tat us Cha nge (CS TSCHG) si gnal i n CardBu s
designs.
I n addition to providing a host interface through the PCI bus, the 82559 pr ovide s TCO controller
acc ess through a dedicated S ystem Manage ment Bus (SMB). Additional information on the
supported TC O functionality at all power states is desc ribed in Section 7.0, “82559 TCO
Functionality” on page 51.
4.3.1.1 D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82559 rec eives full power and should be providing full
functionality. In the 82559 the D0 state is partitioned into two substates, D0 Uninitialized (D0u)
and D0 Active (D0a).
Networking Silicon — 82559
Datasheet 27
D0u is the 82559’s initial power s tate following a power on res et e vent and pri or to the Base
Addres s Registers (BARs) be ing access ed. Whi le i n the D0u sta te, the 82559 ha s PCI slav e
functionality to support its initi alization by the ho st and supports Wake on LAN* mode.
Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space
switches the 82559 from the D0u st ate to the D0a state.
In the D0a state, the 82559 provides its full functionality and consumes its nomi nal p ower. In
addition, the 82559 supports wake on link status change (s ee Section 4.3.2, “Wak e-up Ev ents” on
page 31). While it is active, the 82559 requires a nominal PCI clock signal (in other w ords , a cloc k
frequency gre ater than 16 MHz) for proper operation. During idle tim e, the 82559 support s a PCI
clock signal su spe ns ion using the Clockrun signal mechanism. The 82559 supports a dynamic
sta ndby mode. In this mode, the 82559 is able to save almos t as much power as i t does in the static
power-do wn s tates . The transition to or from standby is done dynamically by the 82559 and is
tr anspar ent to the software .
4.3.1.2 D1 Power State
In order for a device to meet the D1 power state requirements, as specified in the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus
tr ansmiss ion or i nte rrupts ; ho we v er , b us re cepti on is allo wed. Theref ore, device con text may be l ost
and the 82 559 does not initiate any PCI activi ty. In this state, the 82559 responds only to PCI
acc es ses to it s c onfiguration space and sy st em w ake-up events .
The 82559 retains link integrity and monitors the link for any wake-up events such as wake-up
packets or link status cha nge. Fol lowing a wake-up event, the 82559 as serts the PME# signal to
alert the PCI based system or the CSTSCHG signal for a CardBus system.
4.3.1.3 D2 Power State
The ACPI D2 power st ate is similar in func tionality to the D1 po wer stat e. If th e bus is in th e B2
state, the 82559 will consume less current than it d oes in the D1 state. In addition to D1
functionality, the 82559 can provide a lower power mode with wake-on-link status change
capa bilit y. The 82559 ma y enter this m ode if the li nk is down while the 82559 is in the D2 state . In
this sta te, t he 82559 m onitors th e link for a tr ansi tion from an invalid l ink to a v al id link . The 82 559
will not attempt to keep the link aliv e by transmitt ing idle symbols or link integrity pulses.1 The
sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the
Power Management Driver Register (PMDR).
4.3.1.4 D3 Power State
In the D3 po wer s tate , the 82559 has the same c apabi litie s and consu mes the same am ount of po we r
as it does in the D2 state. However, it enables the PCI system to be in the B3 state. If the PCI
system is in the B3 stat e (in other words , no PCI power is present), the 82559 p r ovides wake-up
capa bilit ies if it is connected to an auxi liary power source in the system. If P ME is dis abled, the
82559 does not provide wake-up capability or maintain link integrity. In this mode the 82559
consumes its minimal power.
The 8255 9 enables a syste m to be in a sub-5 watt state (low power state) and sti ll be v irtually
connected. More s pecifically, the 82559 supports full wa ke-up capa biliti es while it is in the D3cold
state . The 8255 9 can b e conne cted to an a uxilia ry p o wer sou rce (VAUX), whi ch ena ble s it to prov ide
1. For a top olog y of two 8255 9 de vices co nnec te d by a crosse d twis ted- pair E ther net cabl e, th e deep po we r-down mode s houl d be disabled. If
it is ena bl ed, th e two devices may not det ect eac h other if the ope ratin g sys t em pl ace s them into a l ow power sta te be fore bo th nodes
become active.
82559 — Netwo rking Sili con
28 Datasheet
w ake-up functionality while the PCI power is of f. The typi cal curren t consumption of the 82559 is
125 mA at 3.3 V. Thus, a du al power pla ne is not required. If conne cted to an auxiliary power
source, the 82559 recei ves al l of its power from the auxiliary sour ce in all power states. When
connected to an a uxiliary powe r supply, the 82559 is requir ed to have a status indicator of whether
or not the po w er s upply is valid (in other wor ds, auxiliary power is stable). The indication is
received at the AUXPW R pin, as described next.
4.3.1. 4.1 Auxiliary Powe r Si g n al
The 82559 senses whether it is connected to t he PCI power supply or to an aux iliary power supply
(VAUX) via th e FLA1/ AUXPWR pin. The auxil iary po wer detect ion pin (multiplexed with F LA1)
is sample d when the PCI RST# or ALTRST# signa ls are active. An external pull -up resis tor should
be connecte d to the 82559 if it is fed by VAUX; otherwise, the FLA1/AUXPWR pin should be le ft
floating. The presence of AUXPWR affects the v alue reported in the Po wer Management
Capa bilit y Register (PCI Conf iguration Space, offs et DE H) . Th e Power Manage me nt Capability
Register is desc ribed in more detail in Section 8.1.20, “Power Management Capabilities Register ”
on page 63 .
4.3.1. 4.2 Alt er n ate R eset S ign al
The 82559’s ALTRST# input pin functions as a power-on reset input. Following ALT RST# being
dr iven low, the 82559 is initialized to a known state. In systems that support auxiliary po wer, this
pin should be conn ected to the auxiliary powe r’s power sta ble signa l (powe r good) of the 82559’s
power source. In a LAN on Motherboard (LOM) solution, this signal is a va ilable on the system. In
network adapter implementations, an external analo g device connected t o the au xiliary power
supply can be used to produce this signal. In systems that do not have an auxili ary power source,
the ALTRST# signal should be tied to a pull-up resistor.
4.3.1.4.3 I solate Signal
When the 82559 is conn ected to VAUX, it may be powered on while the PCI bus is po w er ed off. In
this case, the 82559 isol ates itself from the PCI bus . The 82559 has a de dicat ed ISOLATE# pin that
should be connected to the PCI po wer source’s stable power signal (power good). Whenever the
PCI Bus is in th e B3 stat e, th e PCI power good s igna l becom es in acti v e a nd the 82559 isola tes itse lf
f rom the PCI b us. During thi s sta te, th e 82559 ignore s all PCI sig nals incl udin g the RST# and CLK
signals. It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI
power sta te (in other words, from B3 powe r st ate to B0 powe r state), the PCI po wer good signal
shifts high.
In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In
network adapter implementations, the PCI power good signal can be generate d locally us ing an
external analog device. In t hese des igns, the ISOLAT E# sign al should “envelope” th e syste m’s PCI
power good signal as shown in Figure 9.
Figu re 9. Isolate Signal Behav i or to PCI Power Go od Sign a l
PCI power good signal
Required ISOLATE#
signal behavior
Networking Silicon — 82559
Datasheet 29
In many sy stems , the PCI RST# signal is ass erted low when ever the PCI bus is inactive. In these
systems, the 82559 B-step device and later devices allow the ISOLAT E# pin to be driven from the
PCI RST# sig nal. In thi s case , the ALTRST# pin on th e 82559 shoul d be pulle d high to the PCI bus
high voltage le ve l.
4.3.1.4.4 PCI Reset Signal
The PCI RST# signal may be activ ated in one of the follow ing cases :
•Power-up
•Warm boot
•Wake -up (B3 to B0 transitio n)
•Set to power -down (B0 to B3 transition)
If PME is enable d (in the PCI po wer management registers) , the RS T# signal does not affect any
PME related circuits (in other words, the CSTSCHG registers (CardBus only), PCI power
management register s, and the wake -up packet would not be affect ed). While the RST# signal is
act ive, the 82559 ignores othe r PCI signals and floa ts its out puts. However, if AUXPWR is
as ser t ed , th e RS T # si gn a l h as no aff ec t o n any ci rcu itr y.
While the 82559 is in the D0, D1, or D2 power state, it is initialized by the RST# l ev el. When the
82559 is i n the D3 power state, the system bus may be in the B3 bus power state. I n the B3 po wer
state, the PCI RST# signa l is undefined; however, the au xiliary power source proposal for the PCI
Specification, Revision 2.2 is for the PCI RST# signal to be an active low. Therefore, the 82559
uses the PCI RS T# similarly to the ISOLATE# signal in D3 power state. Following the trailing
edge of the PCI R ST#, the 82559 is initialized while prese r ving the PME# signal and its context.
Note: Accord ing to the P CI specification, durin g th e B3 state, the RST# signal is undefi n ed .
The transition from the B3 power state to the B0 power state occurs on the trailing edge of the
RST# signal.
The initi alization signa l is generate d interna lly in the f ollowing cas es :
•Active RST# signal while the 82559 is the D0, D1, or D2 power sta te
•RST# traili ng edge while the 82559 is in the D3 power sta te
•ISOLATE# trail ing edge
The internal initialization signal resets the PCI Configuration Space, MAC configuration, and
memory structure.
82559 — Netwo rking Sili con
30 Datasheet
The behav ior of the PCI RST# signal and the internal 82559 initi alization signal are shown in the
figure below.
The tabl es below summarizes the 8255 9’s functionality and powe r consumption at the dif f erent
power states.
NOTE: All value s show n for th e D3 state as sum e the availa bility of 3. 3 V standby available to t he devic e.
Figure 10. 82559 Initialization Upon PC I RST# and ISOLATE#
PCI RST#
Internal hardware
reset
PCI RST#
Internal hardware
reset
ISOLATE#
Internal hardware
reset
D0 - D2 power state
D3 power state
Internal reset
due to ISOLATE#
640 ns
640 ns
Power State Conditions 100 Mbs 10 Mbs
D0 Maximum 175 mA 140 mA
D0 Average (5 Mbps) 125 mA 115 mA
D0 Dynamic st andby
(with n etwork load) 12 0 mA 5 5 mA
D0u Car dBus with PCI CLK < 70 mA < 70 mA
D2/D3 (link
down) PCI CLK 10 mA 10 m A
With o ut PCI CLK 3 mA 3 mA
Dx (x>0 with
PME# disabled) PCI CLK 10 mA 10 m A
With o ut PCI CLK 3 mA 3 mA
WOL Wake on LAN power down < 3 mA < 3 mA
Networking Silicon — 82559
Datasheet 31
.
4.3.2 Wake-up Events
Th er e a r e two types of wa ke-up eve n ts : “Interesting” Packets and Link Status Cha nge. These two
events are detailed below.
Note: T he wa ke-up eve nt is supported only if the PME Enab le bit in the Power Management Control/
Status (P MCS R) regist er is set. (The PMCSR is described in Section 8.1.21, “Power Management
Control/Status Register (PMCSR)” on page 64.)
4.3.2.1 “Interesting” Packet Event
In the power-down stat e, the 82559 is capable of recognizing “interesting” packets. The 82559
supports pre-d efi ned and p rogrammable packets that can be defi ned as any of the follo wing:
•ARP Pa ckets (wi th Multiple IP addresses)
•Dir ect Packets (wit h or without type qualification)
•Mag i c Pa ck et *
•Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)
•NetBIOS over TCP/IP (NBT) Query Packet (unde r IP v4)
•Internetwork Package Exchange* (IPX) Diagnostic Packet
•TCO Pack et
This allo ws the 82559 to handle v arious packet types . In general, the 82559 supports
program m able filtering of any packet in the f irst 128 bytes.
Power
State Link 82559 Functionality
D0u Don’t care •Power-up state
•PCI slave access
D0a Valid Full functionality at fu ll power and wak e on inv alid
link
Invalid Full functionality at full power and wake on valid link
D1
Valid •Wake on “interesting”packets and link invalid
•PCI configuration access
Invalid •Wake on link valid
•PCI configuration access
D2 Valid Same functionality as D1 (link valid)
Invalid Detecti on for v alid link and no link integrity
D3 ( with
power) Valid Same functionality as D1 (link valid)
Invalid Detecti on for v alid link and no link integrity
Dx (x>0
without
PME#) Don’t Care
No wake-up functionality
Note: If the TCO bit is set in the EEPROM, the
82559 will n ot disable the link function and wi ll
consume power as in the D2 state.
82559 — Netwo rking Sili con
32 Datasheet
When the 82 559 is in one of the lo w powe r st ates, it searches for a prede fine d pattern in the firs t
128 bytes of the incoming packets. The on ly exception is the Magic Packet, whic h is sc anned for
the entire fra me. Th e 82559 will classify the incoming packets as one of the f ollowing categories:
•No Match. The 82559 discard s the pack et a nd continu es to process the incoming packets .
•T C O Packet. The 82559 implements perfect filtering of TCO packets. After a TCO packet is
pr ocessed, the 82559 is ready for the next incoming packet. There are two pos s ible system
environments:
—T CO contr o lle r on the SMB. Th e entire T C O p acket is tra n sferred to the TC O contro ller.
—System without TCO controller . TCO packet s a re tre ated as any other wake-up packet
and may assert the PME# signal if configured to do so.
•Wake-up Packet. The 82559 is capable of recognizing and storing t he fir st 1 28 bytes of a
w ake-up packe t. If a wake-up packet is lar ger t han 128 byt es , its tail is disca rded b y the 82559.
Af te r th e sys t em is ful ly power ed - u p, sof t wa r e ha s th e ab i li ty to de ter mi n e th e cau s e o f the
wake-up event via the PMDR and dump the stored data to the host memory.
Magic Pa cket s are an e xcept ion. Th e magic pa cket s may cause a powe r managem ent e ven t an d
se t an in dication bit i n the PMDR; however, i t is not s tored by the 82559 for use b y the sys tem
when it is woke n up.
4.3.2.2 Link Status Change Event
The 8 2559 link status indi ca tion ci rcuit is c apable of issuing a PME on a li nk status change from a
v al id link t o a n in v a lid li nk c onditio n or vi ce v ersa. The 8 2559 report s a PME lin k status e ve nt in a ll
p ower states. The PME # signal is g ated b y the PME Enab le bit in th e PMCSR and the CSMA
Configure command.
4.4 CardBus Power Management
The CardBus Power Management Proposal diff ers from the PCI P ower Management Specification
in the following manner:
•The PME# signal is replaced by CSTSCHG which is an active high output signal.
•An auxiliary power sourc e, VAUX, is supplied on the sam e Vcc pins.
•An auxiliary power sourc e bit in the PMC register must be se t.
•The PCI clock signal and the PCI reset signal are guaranteed to be kept low in the B3 state.
I n additio n, the 82559 also meets the Car dBus requirement for current consumption less than 70
mA in the D0u state.
4.5 Wake on LAN (Pr eboot Wake-up)
When the 82559 is dra wing power from an auxil iary po wer sourc e (VAUX), it can su pport the same
pr eboot Wake on LAN (WOL) capabi liti es as the 82558 d evi ce. The 82 559 ente rs WOL mode af ter
the following events occur:
•An ALTRST# is completed.
•The 82559 reads the EEPROM and the WOL bit is set.
Networking Silicon — 82559
Datasheet 33
When the 82559 is in WOL mode:
•The 82559 scans incoming packets for a Magic Packet. When it receives a Magic packet, the
82559 asserts the PME# signal (until cleared) and the CSTS CHG signal for 52 ms.
•The Activity LED changes its functionali ty to indicates that the received fra me pas s ed
Indivi dual Address (IA) filtering or broadcast f iltering.
•The PCI Confi guratio n registers are acces sible to the host.
•Software should not attempt to access the Flash.
The 82559 switches from WOL mode to the D0a power state following a setup of the Memory or
I/O Bas e Address Reg iste rs in t he PCI Conf igura tio n spac e. Whil e the 825 59 is i n the D0u, D1, D2 ,
or D3 po wer s tate , if the 8255 9 recei v es a Magic pa cket , it iss ues a pos it iv e p ulse f or approxi mate ly
52 ms on the CSTSCHG pin. For PCI systems and in designs that support the 3-pin header
standard, the CSTSCHG pin acts as the WOL signal.
4.6 Parallel Flash/Modem Interface
The 82 559’s parallel interface is use d for F lash int erface only or modem i nterface only. The 8 2559
supports a glueless interface to an 8-bi t wide, 128 Kbyte, paral lel memory device. The paralle l
local po r t is mu l ti p lexed wi th a mod em in t er f ace in a LA N /modem co mbi n atio n car d.
The Flash (or boot PROM ) is read from or written to whenever the host CPU performs a read or a
write ope ratio n to a memo ry location that is within the Flash mapping window . All acce s ses to the
Flas h, exce pt read ac cesses, require the appropriate command s equence for the devi ce used. (Refer
to the spec if ic Fla sh dat a sheet fo r more detai ls on re ading fr om or writi ng to the Flas h de vic e.) The
acc esses to th e Flash are based on a dire ct deco de of CPU accesse s to a memory window def ined in
either the 82559 Flash Base Address Register (PCI Configuration space at offset 18H) or the
Expan sion ROM Base Addres s Re gister (PCI Configuration spa ce at offset 3 0H). T he 82559
as ser t s co n tr o l to th e Flash w he n it d ecod e s a valid acce s s.
The 825 59 support s an exte rnal F lash memory (or boot PR OM) of up to 128 Kb yte . The Expa nsion
ROM address can be separately di sabled b y se tting the correspondi ng bit in the EEPROM, word
AH.
Note: Flash access es must always be assembled or disass embled b y the 82559 whenever the acces s is
great er than a byte-wide access. Du e to slow ac ces s times to a typical Fla sh and to avoi d v i o lating
PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not
syste m initi ation cy cles), the maximum data siz e is eithe r one wo rd or one byte for a read operat ion
and one byte only for a write operation.
4.7 Serial EEPROM Interface
The serial EE P ROM stores conf igura tion da ta for the 82559 and is a seria l in/ serial out device. The
82559 supports a either a 64 register or 256 registe r size EEPROM and automatically detects th e
EEPROM’s size . A 256 word EEPR OM device is required for a Cardb us system and conta ins the
CIS i nform ation. A 256 word EEPROM device is also required for a TCO enabl ed system in order
to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz.
82559 — Netwo rking Sili con
34 Datasheet
All accesses, either read or write, are preceded by a command instruction to the device. The address
f ield is six bi ts for a 64 register E EPROM or eight bits for a 256 registe r EE PROM. The end of the
address field is in dicated by a dummy zero bit fr om the EEPROM, which indicate s the entire
address field has been transferred to the devi ce . An EEPROM read ins truction wavefo rm is shown
in the figure below.
The 82559 may also use the EEPROM for heartbeat packet transmission (systems without a TCO
controller are also supported). In these designs, the EEPROM is accessed through time windows
autonomously by the 82559 hardware. During these time windows, the 82559 wi ll respond wit h a
PC I Ret r y to bot h EE PROM an d Fl as h ac cess e s.
The 82559 performs an auto matic read of five words (0H, 1H, 2H, AH, and DH) of the EEPROM
afte r the de -asse rtion of R eset. I t may r ead six more words (B H, CH, FBH, FCH, FDH, and FE H) if
the modem bit is set in the EEPROM (word AH, bit 0).
Figure 11. 64-word EEPROM Read Instruction Waveform
A
1
A
0
EECS
EESK
EEDI
EEDO
A
5
A
4
A
2
D
15
D
0
READ OP code
A
3
A
1
A
0
Networking Silicon — 82559
Datasheet 35
The 8255 9 EEPROM format is shown belo w in F igure 12.
Note th at word AH c ont ains se v eral c onf ig uration bit s. Bits from word AH, FBH through F EH, and
cert ain bits from word DH are described as follows:
Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0H IA Byte 2 IA Byte 1
1H IA Byte 4 IA Byte 3
2H IA Byte 6 IA Byte 5
AH Sig I D 0b BD Rev ID ALT
ID DPD WOL 00b WMR STB
Ena MDM
BH Subsystem ID
CH Subsystem Vendor ID
D H 0000b HB Packet Po in ter SMB Addr ess Field/ EEPROM CIS Point er
FBH M odem Vendor ID
FCH M odem Device ID
FDH Modem Program Interface (02) Modem Revision Number (00)
FEH Modem Power Dissipation (D0-D3) Modem Power Consumption (D0-D3)
Figure 12. 8 2559 E EPROM Fo rmat
Table 1. EEPROM Words Field Descri p tions
Bits Name Description
Word
AH,
15:14
Signature The Signature field is a signature of 01b, indicating to the 82559 that there is a
v alid EEPROM presen t. If the Sign ature field is not 01b, the oth er bi ts ar e
ignore d and the def ault values are us ed.
Word
AH, 13 ID The ID bi t indi ca t es how the S ub sys tem ID an d Su bs ystem Vendor ID f ield s ar e
used as described in Section 8.1.12, “PCI Subsystem Vendor ID and
S ub sy s tem ID Re gi st er s” on page 61. Default value is 0b.
Word
AH, 12 Rese rved This bit i s reserved and should be se t to 0b.
Word
AH, 11 Boot Disable The Boot Disable bit disables the Expansion ROM Base Address Register (PCI
C on fig ura tio n sp ac e, offse t 30H) w hen it is set. Defau lt value is 0b.
Word
AH,
10:8
Revision ID These three bi ts are used as the three least significant bits of the device
revision, if bits 15, 14, and 13 equal 011b and the ID was set as described in
Section 8.1.12, “PCI Subsystem Vendor ID and Subsystem ID Registers” on
page 61. The default value depends on the silicon revision (for example, the
82559 C-Step’s Revision ID is 09h).
Word
AH, 7 82559 B-step Th is bit is re serv ed and should be set to 1b.
82559 C-step
Alternate ID This bit i s used in conjunction with the Signa ture fi eld and the ID bit to help
define the Devic e ID. When bit 7 equals 1b, the Device ID i s 1229H and the
device i s compatibl e to previous steppi ngs of the 82559. When bit 7 equa ls 0b,
the LA N fu ncti on repo rts a De v ice ID of 102 9H an d th e devi ce is not compa ti b le
wit h the 82559. De tai ls re gard ing the 82559 ID pr ogr amming are descri bed in
Section 8.1.12, “PCI Subsystem Vendor ID and Subsystem ID Registers” on
page 61.
82559 — Netwo rking Sili con
36 Datasheet
Note: The IA read from the EEPROM is used by the 82559 until an IA Setup command is issued by
software. The IA defined by the IA Setup command overrides the IA read from the EEPROM.
4.8 10/100 Mbps CSMA/CD Unit
The 82559 CSMA/CD unit im plements both the IEEE 802. 3 Ethernet 10 Mbps and IEEE 802.3u
F as t Ethernet 100 Mbps st andards. I t performs all the CSMA/CD protocol funct ions such as
tr ansmission, reception, collis ion handl ing, etc. The 82 559 CS MA/CD unit interfac es the internal
PHY unit through a standard Media Independent Interface (MII) , as sp ec ifie d by IEEE 802.3,
Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the serial
clocks run at eit her 25 or 2.5 MHz.
Word
AH, 6 Deep Power
Down This bit either enables or disab les Deep Power Down in the D2 or D3 states
when PME is disabled:
‘0’ Deep Power Down is enabled in D3 state if PME-Disabled
‘1’ Deep Power Down disabled in D3 state when PME-Disabled.
Note: When using the 82559’s A le rt capa bil it y, the D eep Po w er Do wn c apa bi l ity
should b e disabled. Alert de v ices will not be able to transmi t or receive on the
SMBus if the device is in a D eep Power Down Mode.
Word
AH, 5 Wake on LAN The WOL bit set s the 82559 i nto WOL mode . When in t his mode the 82 559
reads three add itio nal words from the EEPROM, word addres ses 0H, 1H, a nd
2H. These words are expected to hold the MAC Individual Address. After
reading these words the 82559 wakes the system by asserting PME# when a
wak e-u p pack et is received. Default value is 0b.
Word
AH, 4:3 Reserved Thes e are reserved and should be se t to 00b.
Word
AH, 2
Word
AH, 1 Standby Enable The Standby Enable bit enables the 82559 to enter standby mode. When this bit
equals 1b, the 8255 9 is abl e to recogniz e an i dle state and can enter standb y
mode (s ome internal clocks are stop ped for pow er s aving purposes). The
8255 9 do es not req ui re a P CI cl o c k sign al in st and b y mod e . If th is bit eq ua ls 0b ,
the id le re cog ni tio n c ir c uit is di sa b led an d t h e 825 59 al ways rema i ns in an a ct iv e
state . Thus, the 8255 9 will always request PCI C LK us ing the Cl ockrun
mechanism.
Word
AH, 0 Modem If this bit equals 0b, the design is a single function design (LAN function) only. If
this bit equals 1b, a modem is attached on the 82559 local parallel port.
Word
DH,
11:8
Heartbeat Packet
Pointer This field of bits contains the location of the Heartbeat packet within the
EEPROM. The pointers are expressed in a granularity of 16 words. A value of 0
is used as a null pointer .
Word,
DH, 7:0 SMB Address
Field/EEPROM
CIS Pointer
This field of bits is a multiple xed function field. In a PCI system, it acts as an
SMB ad dre ss f iel d ( 7 -bi t fiel d) . W he n thi s f i el d is u se d a s t he SMB ad dre ss f iel d,
bit 7 equals 0b.
In a CardBus system, this field is used for CIS pointers. When this field is used
as the EEPROM CIS Pointer, it contains two 4-bit pointers that point to the
location of the CIS information within the EEPROM. The pointers are expressed
in a granularity of 16 words. A value of 0 is used as a null pointer. The Ethernet
CIS pointer resides in bits 3:0 and the modem CIS pointer resides in bits 7:4.
Words
FBH -
FEH
Modem
Configuration
Parameters
These word fie lds hold the modem configuration parameters are loaded to the
PCI Configuration space. A combination LAN/modem card requires a 256-word
EEPROM.
Table 1. EEPROM Words Field Descripti ons
Bits Name Description
Networking Silicon — 82559
Datasheet 37
4.8.1 Full Duplex
When operating in full duplex mode the 82559 can transmit and receive frames simultaneously.
Transmissi on st arts regardless of the state of the inte rnal receive path. Reception starts when the
internal PHY detects a valid frame on the receive differential pair of the PHY.
The 825 59 operates in eith er half duplex mode or fu ll duple x m ode. Fo r pr oper operation, both the
82559 CSMA/CD module and the PHY uni t must be set to the same duplex mode. The CSMA
duple x mode i s set by th e 82559 Conf igu re command or forced by automa tical ly tr acking the mode
in the PHY unit.
The PHY duple x mode is set either by Auto-Neg otiation or, if Auto-Negotiation is dis abled, by
set ting the full dupl e x bit in the Managemen t Data Int erfa ce (MDI) Re gist er 0, bi t 8. By defa ult, t he
internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the
duplex setting of the CSMA unit. The CSMA configuration should m atch the resu lt of the Aut o-
Negotiation.
The selection of duplex operation (full or half) and flow control is done in two levels: MAC and
PHY. The MAC duplex se lection is done only th rough CSMA configuration mechanism (in other
words, the Configure comma nd fr om software).
4.8.2 Flow Control
The 825 59 support s IEEE 802 .3x frame ba sed flo w cont rol fra mes only in both f ull duplex and ha lf
duplex switched environment s. The 82559 flow control feature is not intended to be used in shared
media environments.
Flow control is optional in full duplex mode and can be sel ected through software conf igurat ion.
There are three modes of flow control that can be selected: frame based transmit flow control,
frame based receiv e flow control, and none.
The PHY unit’s duplex and flow con trol enable can be se lected using NWay* Au to-Neg otiation
algorithm or throu gh the Management Data I nterface .
4.8.3 Address Filtering Modifications
The 82559 can be configured to ignore one bit when checking for its Individual Address (IA) on
incom ing receive frames . T he address bit, known as the Upper/L ower ( U/L) bit, is the se cond least
significant bit of the f irst byte of the IA. This bi t ma y be used, in some case s, as a priorit y
indication bit. When configured to do so, the 82559 passes any frame that matches all other 47
address bits of its IA, regardless of the U/L bit va lue.
This confi guration only affects the 82559 specifi c IA and not multicast, multi -IA or broadcast
address filtering. The 82559 doe s not attribute any priori ty to frames with this bit set, it simpl y
passes them to memor y r egar d less of this bit.
4.8.4 VLAN Support
The 82559 supports the VLAN standard currently being defined by the I EE E 802.1 committe e. All
VLAN flows will be impl emented by s oftware. The 82559 supports the recept ion of long frames,
spe cificall y fr am es longer than 1518 bytes, including the CRC, if so ftware se ts the Long Receive
OK bit in the Configuration com m and. Otherwise, “long” frames are discarded.
82559 — Netwo rking Sili con
38 Datasheet
4.9 Media Independent Interface (MII) Management Int erface
The MII management inte rf ace allows the CPU to control the PHY unit via a control r egiste r in the
82559. This allows the so ftware driver to place the PHY in specif ic modes such as full duplex,
loopb ack, po we r down, etc., with out t he need for spe cifi c hardwa re pins to select the desire d mode.
This structure allo ws the 82559 to query the PHY unit for st atus of the link. This register is the
MDI Control Register and resides at offset 10H in the 82559 CSR. (The MDI registers are
des cribe d in detail in Section 10.0, “PHY Unit Registers” on page 85.) The CPU wri tes commands
to this regist er and the 82559 reads or writes the control/s tatus paramete rs to the PHY uni t through
the MDI register. Although the82559 foll ows the MII forma t, the MI bus is not acces s ible on
ex te rnal p ins.
Networking Silicon — 82559
Datasheet 39
5.0 82559 Physical Layer Functional Description
5.1 100BASE-TX PHY Unit
5.1.1 100BASE-TX Transmit Clock Generation
A 25 MHz crystal or a 25 MHz oscilla to r i s used to drive the PHY uni t’s X1 and X2 pins . The PHY
unit deriv es its inter nal transmit digi tal cl ocks from th is cr ystal or o sc illator in put. The in ternal
Transmit Clock signal is a derivativ e of the 25 MHz internal clock. The accuracy of the external
crys tal or oscil lator must be ± 0.005% (5 0 PPM).
5.1.2 100BASE-TX Transmit Blocks
The transmit subsecti on of the PHY unit accep ts n ibble-wide data from th e CS MA/CD unit. The
transmit subsection passes data unconditionally to the 4B/5B encoder.
The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5-
bit-wide parallel symbols . These symbols are sc ram bled and s erialized into a 125 Mbps bit stream,
converted b y th e analog transmit driver into a MLT-3 wa veform format, and transmitted onto the
Unshielded Twisted P air (UTP) or S hielde d Twisted P air (STP) wir e.
5.1.2.1 100BASE-TX 4B/5B Encoder
The 4B/ 5B encoder complies with the IEEE 802.3u 100BASE - TX standard. Four bits are encoded
acc ording to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4- bit
code.
The ta ble below illu strate s the 4B/5B enc oding scheme associa ted with t he giv en symbol.
Table 2. 4B/5B Encoder
Symb ol 5B Symbo l Code 4B Nibbl e Code
0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000
9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
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40 Datasheet
5. 1.2.2 100 BA SE- T X Scrambler an d MLT-3 Encod er
Data i s scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long
transmissions of high-frequency data codes. The scram ble r logic accepts 5 bits from the 4B/5B
encoder block and presents the scrambled data to the MLT-3 encoder. The PHY unit implements
the 11-bit s tream ciphe r scrambl er as adop ted by the ANSI XT3T 9.5 committ ee for UTP op eration.
The cipher equat ion used is:
X[n] = X[n-11] + X[n-9] (mod 2)
The encoder rece iv es the scrambled Non-Return to Zero (NRZ) data stream from the Scrambler
and e ncodes the strea m into MLT-3 for pr esenta tio n to the driver . MLT-3 is simi lar to NRZ I coding,
but three l ev els are output inst ead of two. There are three output levels: positive, ne gative and z ero.
D 11011 1101
E 11100 1110
F 11101 1111
I 11111 Inter Packet Idle Symbol
(N o 4B)
J 11000 1st Start of Packet Symbol
0101
K 10001 2nd Start of Packet Symbol
0101
T 011 01 1s t End of Pack et Symbol
R 00111 2 nd En d of Pa cket Sy m bo l
and Flow Cont rol
V 00000 INVALID
V 00001 INVALID
V 00010 INVALID
V 00011 INVALID
H 00100 INVALID
V 00101 INVALID
V 00110 INVALID
V 01000 INVALID
V 01100 INVALID
V 10000 PHY based Flow Con trol
V 11001 INVALID
Tab le 2. 4B/5B En code r
Symbol 5B Symbol Code 4B Nibble Code
Networking Silicon — 82559
Datasheet 41
When an NRZ “0” ar r ives at the input of the encoder, the last output level is mainta ined (either
posi ti ve , neg ati ve or zero). When an NRZ “1” arri ve s at the i nput of the encode r, the outpu t steps to
the next level. The order of st eps is nega tive-zero-positive-zero whic h continues periodical ly.
5.1.2.3 100BASE-TX Transmit Framing
The PHY unit does not differenti ate between the fi elds of the MAC frame cont aining pr eamble,
Star t of F r ame Delimiter, data and Cyclic Redundancy Check (CR C). The PHY un it encodes the
first byte of the preamble as the “JK” symbol, enc odes all other pieces of data according to the 4B/
5B lookup table, and adds the “TR” code after the end of t h e p acket. Th e PHY unit scr ambles and
serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives it onto the wire.
5. 1.2. 4 Transmit Dr i ver
The transmit di fferential pair line s ar e implement ed with a digital slop e controlled current driver
that meets the TP-P MD specif ic ations. Current is sink ed from the is olati on trans former b y the TDP
and TDN pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the
followi ng figure.
Figure 13. NRZ to MLT-3 Enco ding Diagram
Clock
NRZ
NRZ1
MLT-3
1100 0110
1100 0110
1100 0110
Figure 14. Co nc eptua l Transm it Differential Waveform
(VTDP -VTDN )
+1V
0V
-1V
t
82559 — Netwo rking Sili con
42 Datasheet
The magnetics module tha t is external to the PHY unit conv erts ITDP and ITDN to the 2.0 Vpp, as
required by the TP-PMD specification. The same magnetics used for 100BAS E-TX mode should
also work in 10BASE-T mode. The follo wing i s a list of current magnetics mod ules a va ilable from
several vendors:
5.1.3 100BASE-TX Receive Blocks
The rece iv e subsect ion of the PHY unit accepts 100BASE-TX MLT-3 data on the receive
differential pair. Due to the advanc ed digit al signal pr oce ssing de si gn techn iques employed, the
PHY unit will accura tely receiv e v alid da ta from Cate gory-5 ( CAT5) UTP and Type 1 STP cabl e of
length well in excess of 100 me ters.
5.1.3.1 Adaptive Equalizer
The distorted MLT-3 signa l at the end of the wire is resto r ed by the equa lizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior Data Depe ndent Jitter performance .
5.1.3.2 R ecei ve Clock an d D ata R ecover y
The cloc k recovery circuit uses ad vanced digital signal proce s sing tech nology to co mpensate for
vari ous signal jitter cau se s . The circuit recovers the 125 MHz clo ck and d ata and presents the data
to the MLT-3 de code r.
5.1.3.3 M LT-3 Deco d er, Descrambler, and R eceive D i g it al Section
The PHY unit f irst decodes the MLT-3 data; afterwards , the descrambler reproduces the 5B
symbol s o rigi nated in th e transm it ter. The desc rambli ng is ba sed o n synchr onizat ion to th e transm it
11-bit Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B
decoder. Once the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA
unit.
5.1.3.4 100BASE-TX Receive Framing
The PHY unit do es not differentiate between the fiel ds o f the MAC frame containing preamble,
start of frame delimiter, data and CRC. During 100 Mbps reception, the PHY unit differentiates
b etween the idle conditio n (“L” s ymb ols on th e wi r e) a n d th e pr ea m b le or s tar t o f f r am e deli m i ter.
When two non-conse cutive bits are 0b withi n 10 bits (125 Mbps 5B data coding) the PHY unit
im me d i at el y as se rt s ca r rie r s en se. W h en th e “JK” symb ols (“11000, 1000 1”) are fully rec ognized,
th e PHY unit provides the receiv ed data to t h e CS MA unit. If the “JK” symbol is not recognized
(“fals e ca rr i er sen s e ”), th e carrie r sens e is immediately de-asserted and a receive error is indicated.
Table 3. Magnetics Modules
Vendor Model/Type 100BASE-TX 10BASE-T
Delta LF8200A Yes Yes
Pulse Engineering PE-68515 Yes Yes
Pulse Engineering H1012 Yes Yes
Networking Silicon — 82559
Datasheet 43
5. 1.3. 5 1 00BASE- T X Re ceive Erro r Det ect i o n and Re p o rt i n g
In 100BASE-TX mode, the P HY unit can dete ct errors in receive data in a num ber of ways. Any of
the following conditions is considered an error:
•Link integrity f ails in the midd le of frame recept ion.
•The Start of Stream Delimiter (SSD) “JK” symbol is not fully dete cted after i dle.
•An invalid symbol is detected at the 4B/5B decoder.
•Idle is detected in the middle of a frame (before “TR” is dete cted).
When any of the above error conditions occurs, the PHY unit immediately asserts its receive error
indication to th e CSMA unit. The receiv e e rror indi cation is held active a s long as the receive error
conditio n persists on the receiv e pai r.
5.1.4 100BASE-TX Collision Detection
100BASE-TX collisions in ha lf duplex mode only are detected sim ilarly to 10BASE-T collision
detection, via simultaneou s transmission and reception.
5.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution
The 82559 Auto -Nego tiation functi on automati cally confi gures the devic e to the technology,
media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE
specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full
duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.
The PHY unit has two Phys ical Media Attachment (P MA) tec hnologie s with its link integrity
function, 10BASE-T a nd 100BASE-TX.
5.1.5.1 Link Integrity
In 100B ASE -TX, the link in te gri ty funct ion is d etermine d by a s tabl e sign al statu s coming fr om the
TP-PMD bl ock. Signal status is as serted when the PMD detects breaking squelch energy and the
right bit error rate accordi ng to the ANSI speci ficati on.
5.1.5.2 Auto-Negotiation
The PHY unit fully supports IEEE 802.3u, clause 28. The tec hnology, 10B A S E-T or 100B ASE-
TX, is determined by the Auto-Negot iatio n r esult.
Sp ee d and d up l ex au t o -s el ect ar e f u nc ti o n s of Auto - N egot iati o n . H owever, these pa r amet er s may
be manually configu r ed via the MII manage ment interface (MDI register s).
5.1.6 Auto 10/100 Mbps Speed Selection
The MAC may either allow th e PHY unit to au tomatically selec t its oper ating speed or force the
PHY into 10 Mbps or 100 Mbps mod e. The Manage ment Data Interface (MDI) can control the
PHY unit speed mode.
82559 — Netwo rking Sili con
44 Datasheet
The PHY unit auto-select function determines the operation speed of the media based on the link
integrity pulse s it receive s. If no Fast Link Pulses ( FLP s ) are de tected and Normal Link Puls es
( NLPs) are dete cted, the PHY unit defaults to 10 Mbps operation. If the PHY unit de tects a speed
change, it dynamical ly changes its tr ansmit clo ck and receive cloc k frequencies to the appropriate
val ue. This change takes a maximum of five millise conds.
5.2 10BASE-T Functionality
5.2.1 10BASE-T Tr ansmit Clock Generation
The 20 MHz a nd 10 MHz clocks needed for 10BASE-T a re s ynthesi ze d from the e xter nal 25 MHz
crystal or os cillator. The PHY unit provides th e transmit clock and receive clock to the internal
MAC at 2.5 MHz.
5.2.2 10BASE-T Transmit Blocks
5.2 .2. 1 1 0BASE-T Mancheste r Encoder
After the 2.5 MHz clocked data is s erializ ed in a 10 Mbps s erial stream, the 20 MHz clock
performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the
value is 1b then the transition is from low to high. If the value is 0b then the tra nsition is f r om high
to low. The boundary transi tion occurs on ly when the data changes from bit to bi t. For e xample, if
the value is 10b, then the change is from high to low; if 01 b, then the cha nge is from low to high.
5. 2.2.2 10BASE-T D r i ver an d F i l t er
Si nce 1 0BASE -T a nd 100BASE-TX hav e different filtration nee ds, both filters are imple mented
inside the chip. This allows the two technologies to share the same magnetics. The PHY unit
supports bot h technologies throu gh one pa ir of TD pins and by externally shari ng the same
magnetics.
I n 10 Mbps mode, the PHY unit be gins transmi tting the s erial Manches ter bit stream within 3 bit
tim es (300 na nos econds) after the MA C asserts TXEN. In 10 Mbps mode the line drivers use a pre-
distortion algorithm to impro ve jitter tolerance. The line drive rs reduce their drive level during the
seco nd half of “wide” (100 ns) Manc hester pul ses and maintain a full dri ve l ev el during all narrow
(50 ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide
p ulses, a ma jor source of jitte r.
5.2.3 10BASE-T Receive Blocks
5.2 .3. 1 1 0BASE-T Mancheste r Decoder
The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The
Manchester-e ncoded data stre am is d ecoded from th e RD pair to separate Receiv e Clock and
Receive Data f r om the diff er ential signal. This data is transferred to the CS MA un it at 2.5 MHz /
nibble. The high-performance circuitry of the PHY unit exceeds the IEEE 802.3 jitter
requirements.
Networking Silicon — 82559
Datasheet 45
5.2.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter
In 10 Mbps mode, data is expected to be received on the receive differential pair after passing
through isolation tran sformers. The filter is implement ed inside the PHY unit for s upporting si ngle
magn etics that are shared with the 100BASE-TX side. The input d ifferential voltage range for the
Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive
bu ffer distinguishes v alid rece iv e data, link tes t pulses, and the idle co ndition, accor ding to the
requirements of the 10BASE-T standard.
The following line activity is determined to be inactive and is rejected:
•Differential pulses of peak magnitude less than 300 mV
•Continuous sinusoids with a dif f eren tial am plitud e less than 6.2 VPP and fre quency less than 2
MHz
•Sin e wa ve s of a single cycle duration sta r ting wit h 0 or 180° p h ase t h at have a differential
ampl itude les s than 6.2 VPP and a fr equen cy of at least 2 M H z an d not mor e than 16 MHz .
These single-cycle sine waves are dis carded only if they are preceded by 4 bit time s (400
nanos ec onds) of silence.
All othe r acti vi ty is determine d to be eithe r data, link tes t pulses, Au to-Neg oti ation fa st lin k pulses,
or the idle condition. Whe n activity is detect ed, the carrier sens e signal is asser ted to the MAC.
5.2.3.3 10BASE-T Error Detection and Repor ting
In 10 Mbps mode, the PHY unit can detect errors in the rece ive data. The following condition is
con si d er e d an er r o r:
The r e cei v e pa ir ’s vo ltage lev el drop s t o the idle st ate dur ing rece ption be fore the e nd-of- frame
bit is d etected (250 nanoseco nds without mid-bit transitions ).
5.2.4 10BASE-T Collision Detection
Collision detecti on in 10 Mbps mode is indicate d by simult aneous tra nsmissi on and recept ion. If
the PHY unit detects this condition, it asserts a collision indication to the CSMA/CD unit.
5.2.5 10BASE-T Link Integrity
The link inte grity in 10 Mbps works with l ink pul se s. The P HY unit senses and differentiates those
link pulses fr om fast link pulses and from 100BASE - TX idles. The 10 Mbps link pulses or normal
link pulses are drive n in the t ransmit differential pair lin e but are 100 ns wide and ha ve levels fr om
0 V to 5 V. The link beat pu lse is also used to determine if the recei ve pair polarity is reversed. If it
is, the polarity is corrected internally.
5.2.6 10BASE-T Jabber Control Function
The PHY unit contains a jabber cont rol functi on that inhibits transmission after a specified ti me
window when ena bled. In 10 Mbps mode, t he jabber tim er is set to a va lue between 26.2 m s and 39
ms. If the PHY unit detect s conti nuous tr ansmis sion th at is great er than thi s time per iod, it prev ent s
further transmissions from onto the wire until it detects that the MAC transmit enable signal has
been inactive for at least 314 ms.
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46 Datasheet
5.2.7 10BASE-T Full Duplex
The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test,
and the car r ier sens e tr ansmit function. This allows the PHY unit to tra nsmit and receive
si multa neously, ac hie ving up to 20 Mbps of n et work b andwidth . The c onfi gura tion ca n be ac hie v ed
through Auto-Ne goti ation. Ful l duplex s hould only be used i n point-to - point connections (no
shar ed medi a) .
5.3 Auto- Negotiati on Functiona lity
The PHY unit supports Auto-Negotiation. Auto- N egotiation is an automatic confi guration sc heme
d es igned to manage in terope r ability in multifunctional LAN environments. I t all ows two stat ions
with “N” different modes of commu nication to establish a common mode of operation . At power-
up, Auto-Negotiation automatically establishes a link that takes advantage of an Auto-Negotiation
capable device. An Auto-Negotia tion capable device can detect and autom atically configure its
port to take ma xim um advantage of common modes of operation wi thout user i ntervention or prior
knowledge by ei ther station. The possibl e comm on modes of op eration are: 100BASE-TX,
100BASE-TX Ful l Duplex, 10BAS E-T, and 10BASE-T Full Duplex.
5.3.1 Description
Auto-Nego tiation s elects the f as test operating mode (in other w ords, the hig hest common
denominat or) available to hardware at both ends of the cable. A PHY’s capability is encoded by
bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange
and handshak e during link initializa tion ti me . Once the link is establis hed by this handshake, th e
native link pulse scheme re su mes (that is, 10BASE-T or 100BASE-TX link pulses). A rese t or
ma nagement rene gotia te command (through the MDI interface ) will restart th e proc es s. To enable
Auto-Nego tiation, bit 12 of the MDI Control Registe r must be se t. If the PHY unit cannot perform
Auto-Negotiation, it will set this bit to a 0 and determine the speed using Parallel Detection.
The P HY unit supports four technol ogies: 100BASE-Tx F ull and Half Duplex and 10BASE-T Full
and Half Duplex. Since only one technology can be used at a time (after every re-negotiate
com mand), a prioritization sche me must be use d to ens ure that the h ighest common denominator
abi lit y is chose n. Each bit in thi s tabl e is set accordi ng to what the PHY is capa ble of sup porting. In
the case of the 82559’s PHY unit, bits 0, 1, 2, 3, and 5 (10BASE-T, 10BASE-T full duplex,
100BASE-TX, 100BASE-TX full duplex and pause [frame based flow contro l], respectively) are
set.
To detect the co rrect technology, the two register fields , t ec hnology a bilit y and t ec hnology priority,
should be ANDed toge ther to obtain the hig hes t common denominator. This value should then be
u se d to map into a priority resolution table used b y the MAC driver to use the appropriate
technology.
5.3.2 Parallel Detect and Auto-Negotiation
The PHY unit automatically determine s the speed of the link eithe r by using Parallel Detect or
Auto-Nego tiation. Upon a reset, a link s tatus fail, or a Negotiate/ Re-negotiate command, the PHY
unit inserts a long delay during which no link pulses are trans mi tted. Thi s pe riod, kno wn as
For ce _Fa il , in s u r es that th e PHY u nit ‘s link part ner has gone into a Li nk F ail state before Auto-
Negoti ation or Parallel Detection be gins. Thus, b oth sides (PHY unit and PHY unit’s link partner)
Networking Silicon — 82559
Datasheet 47
will perform Auto-Negotia tion or Pa rallel Detection with no dat a packet s be ing transmitted.
Connection is then esta blished ei ther by FLP exchange or Paralle l Detection. The PHY unit wil l
look for both FLPs and link integrity pulses. The follo wing dia gram illustrat es this process .
5.4 LED Desc ription
The PHY unit support s three LED pins to ind ica te li nk s tatus, network activity and network speed.
Each pin can source 10 mA.
•Link: This LED is off until a va lid link has been detected. After a va lid l ink ha s been detected,
the LED will remain on (active-low).
•Activity: This LED blinks o n and off when activi ty is detected on the wire.
•Speed: This LED will be on if a 100 BASE -TX link is detected and of f if a 10BASE-T link is
dete ct ed. I f t he link fa il s wh ile in Auto- Ne goti ation , t his L ED will k e ep t he last v alid lin k sta te .
If 100B ASE -TX link is forc ed this LED will be on, rega rdl ess of the link statu s. This LE D will
be of if the 10BASE-T link is forced, regardless of the link status.
MDI register 27 in Secti on 10.3.12, “Register 27: PHY Unit Special Control Bit Definitions” on
page 92 details the infor ma tion for LED funct ion mapping and support enhancem ents.
Figure 15. Auto-Neg otiation and Parallel Detect
Force_Fail
Ability detect either by
parallel detect or auto-
negotiation.
10Base-T or
100Base-TX Link
Ready FLP capable
LINK PASS
Parallel Detection Auto-Negotiation
Look at Link Pulse;
Auto-Negotiation capable = 0 Auto-Negotiation capable = 1
Ability Match
Auto-Negotiation Complete bit set
Networking Silicon — 82559
Datasheet 49
6.0 82559 Modem Functionality
The local port mimics the standard 8-bit interface of a modem to the host system a nd emulates a
16550 Un iv ersal Asynchronous Recei ver /Transceiver (UART ) mo dem interf ace. The modem
inter f a c e in c lud e s th e fo llow in g :
•8-bit data bus: FLD[7:0]
•Control si gnal s: AEN (FLCS#), MCNTSM# (FLA[12]), MINT (FLA[11]), MRING#
(FLA[10]), MRST (FLA[9]), RD# (FLOE#), and WR# (FLWE#)
•4 addres s lines
6.1 PCI Address Mappin g to the Modem
The modem can be acce ssed by the PCI bus through eit her I/O or m emory mapping.
6.2 Modem Read and Write Cycles
Bas i c r ead /w r i te cycl es to th e m od e m device ar e sh ow n in th e figur e bel ow.
6.3 Modem and Preboot eXtension Environment Coexistence
The 82559 C-Step local bus interface supports either a Flash device or modem without external
support. In addit ion, the 82559 can also supp ort both de vices conc urrentl y on the bus. Supp ort is
provided through the use of the Security ASIC Chip Select (CFCS#) pin by usi ng it in conjunct ion
with the Flas h Chip Select (FL CS#) signal to en able the target devic e.
6.3.1 Programming Details
For d esigns that use bo th F lash and modem device s, the 82559 C-ste p supports the coexistence of
BootROM access es (for Preboot eXtension Environment [PXE] code) and modem:
1. Set th e EEP ROM ’s MDM bit.
Figure 17. M o dem Read /Write Cycles
Modem AEN (CS#)
Modem Addrsess
Modem Data In / Out
Modem WE# / RD#
Modem IOCHRDY
82559 — Netwo rking Sili con
50 Datasheet
2. C lear the BD bit in the EEP ROM.
This enabl es both the modem and boot RO M. This allows th e Boot Enable bi t in the Expansion
BAR to select which external device (modem or F lash) is activ e on th e local bu s through the use of
the CFCS# pin. Afte r initialization, the 82559 C-step enables the Flash on th e local bus (in other
w ords, the Boot Enable bit in the BAR equa ls 1b) and the modem is di sabled. F ollowing the
execution of the boot code from the Flash devic e, the ena ble bit is cl eared, and th e mod em is
enabled. The clearing o f the Boot Enable bit causes the CFCS# pin to be d e-asserted, enablin g th e
mode m, Fu nction 1 (Modem) Configuration space, to be a vailable regardless of the stat e of the
Boot Enable bi t or CFCS#.
6.3.2 Suppor t Circuitry
An e xampl e of sup port cir cuitry i s s how n in F igure 18. When CF CS# is l o w, th e mode m is ena ble d;
CFCS# is high, the Flash device is enabled.
Figure 18. Support Circuitry Example
MODEM_CS#
FLASH_CS#
CFCS#
(Modem_Mode#)
FLCS#
Networking Silicon — 82559
Datasheet 51
7.0 82559 TCO Functio nality
The 82 559 supports management communicati on to reduce Total Co st of Ownership (TCO). It has
a Syste m Manage ment Bus (SMB) on which the 82559 is a slave device. The SMB is used as an
interface between the 82559 and a TCO “entity”. The TCO entity ma y be a dedica ted TCO
controller, or it may be direct connection to a future integrated host controller. In the case of a
direct connection to an integr ated host controller, a larger EEPROM of 256 words would be
requir ed i f the h eartbe at co mmand is use d. The secti ons be lo w descri be the 8255 9’s f un ctiona lity i n
the a sys tem with a TCO con troller and a sys tem without a TCO control ler.
7.1 System Functionality with a TCO Controller
When a TCO controller accesses the 82559 through the SMB, the bus operates as a half duplex
channel. Therefore, once the TCO controller starts a transmit command or another execution
comman d, it must complet e it before responding to the SMB Aler t (SMBAL RT) cause and vis e
versa. T he 82559 functionality available th rough the SMB is lis ted in the table below .
D0 Nominal Ope ration:
In the D0 power sta te, the 82559 can transfer TCO packets to the TCO controller. This feature is
enabled by the set receive enable command from the TCO controller. The TCO packets are
transferred to the 82559’s memo r y str u ct u r e, R eceive Fr ame A r ea (R FA); th er e f o re , th i s fe at u re
requires software to be loaded and av ailable receiv e resources. The 82559 s uspends transmit and
re cei ve processes and sets the TCO request bit in the TCO State re gis ter. Afterwards, it transfers
the TC O packet back to the TCO cont roller through the SMB and recl aims r eceive memor y
str uctures tha t ar e occupied by the TCO packe t, elimin ating the n eed fo r softwar e interventio n in
the process. Fina lly, the 82559 in crements the receiv e TCO statistic counter, cle ars the TCO
request bit and res um es norm al operation. The 82559 always increments th e receive TCO counter
followi ng the recept ion of a T CO pac ket.
Note: Traf fic betwe en the 82559 and the TCO co ntroller is lim ited by the SMB speed and the TCO
controller latency. For ex ample, for a syste m wit h a 100 KHz clock on the SMB, the ban dwidth
may be as low as 50 Kbps, which is a reception rate of approximately 100 packets per second for
64- byte packets.
Transm i t Command during Nomi nal Operation
Power State TCO Controller Functionality
D0 Nominal
•Transmit
•Set receive TCO packets
•Receive TCO packets
•Read 82559 status
•Force TCO mode
Dx (x > 0) •D0 functionality
•Read PHY registers
Force TCO Mode
•Dx functionality
•Configure commands (configuration, individual
address, multicast, load microcode)
•Read/Write PHY registers
82559 — Netwo rking Sili con
52 Datasheet
The 82559 completes the following process for the during nominal operation of the
tr ansmit comma nd in TCO mode .
1. The 82559 completes the current transmit DMA.
2. The 82559 sets the TCO request bit in the TCO State register.
3. The 82559 responds to the TCO controller’s transmit request.
4. Upon completion of the TCO transmit DMA, the 82559 increments the transmit TCO
statistic counter.
5. Upon completion of the transmit operation, the 82559 increments the nominal
transmit statistic counters and clears the TCO request bit in the TCO State register.
6. The 82559 resumes its normal transmit flow.
During the this t ime, th e receiv e flow is no t affected.
Receive TCO Packets
The 82559 supports receive flow towards the TCO controller. The 82559 can transfer
either TCO packets or packets that pass MAC address filtering according to its
confi guratio n and mode of operation. If the 82559 is configured to trans f er only TCO
packets, it supports Ethernet Type II packe ts with opti onal VLAN tagg ing.
Read 82559 Status (Power Management and Link State)
The TCO controller is capable of reading the 82559’s power state and link status.
Following a status change the 82559 issues an SMB alert and the TC O entity reads the
new power state.
Set Force T C O Mo d e
The TCO controller ca n set the 82559 int o the Force TCO m ode. The 82559 is s et back to
the nominal operation following a PCI RST# or ALTRST#. After the transition from
normal operation to TCO mode, the 82559 aborts transmit and receive operations and
clears its memory structures. The TCO may configure the 82559 before it starts transmit
and receive operations if required.
Caution: The Force TCO is a destructive command. It causes the 82559 to lose its
memory structure s. Also, in Fo rce TCO mode , the 8255 9 ignor es PCI cyc les. The refore, it
is highly recommen ded to use this comm and by the TCO controller at system emergency
only.
Dx (x>0):
When the 82 559 is in a low po wer state (D1, D2, or D3) , it may receive TCO p ac kets dire ctly
t o th e TCO cont rol le r. TCO pa ck et rec ep tio n is en abl ed b y s etti ng th e re cei v e ena ble com mand
f r om th e TCO controller. Alth ough TCO packets can mat ch other wake-up filters, once it is
identified as a TCO packet, no further matching is performed. When TCO reception is
disabled , a TCO pack et may cause a power manage me nt ev ent if configured to so b y the load
wake-up packet command.
Force TCO Mode:
When the 82 559 is in the force TCO mode, it may rec eive packets dir ectly to the TCO controller.
TCO p acket re ception and filtering is cont r olled by the set receive enable command fro m the TCO
controller. After rec eiving a TCO packet, the 82 559 increments its nominal receive statistic
counters as well as the receive TCO counter.
Configuration Commands
While the 82559 is in the force TCO mode it supports the Configure CSMA, Individual
Addr ess Setu p, Multi cast Se tup, Lo ad Microc ode commands and all ows read/writ e acces s
to the PHY registers.
Networking Silicon — 82559
Datasheet 53
7.2 Sys tem Fu nctio n ali ty wit ho ut a TCO Cont ro lle r
This section des cribes the 82559 functi onality when it is connected on the SMB directly to an
integrated host control ler.
Re ceive Functionali ty - In the power -up state , the 82559 transfers TC O pac kets to the host as any
other packet. These packets include a new status indication bit in the 82559’s Receive Fra m e
Descriptor (RF D ) stat us and have a s pecific port number indicating TCO packe t recognition. In the
power - down state, the TCO packe ts are treated as a wake-u p packets. The 8255 9 asserts the PME#
signal and deliv ers the first 120 bytes of the pa cket to the ho st.
Transmit Funct ional ity - The 82 559 supp orts t he Hear tbeat (HB) trans miss ion co mmand from th e
SMB in terface. Th e se n d HB pac k et command includ es a system health stat us issued by t h e
integrated system controlle r. The 82559 com putes a matched checksum and CRC and will
transmit the HB packet from its serial EEPROM. The HB packet size and structure are not limited
as lon g as it fits wi th i n th e EE PROM s i ze . In th is cas e , th e E E P ROM size is 2 5 6 wo r d s to enab l e
the s torage of the HB packe t (the f irs t 64 words are used for driver specific data) .
Note: On the SMB, the send heartbeat packet command is not normally used in the D0 power state. The
one excepti on in which it is used in t he D0 state is when the sys tem is hung. In norm al operatin g
mo d e, th e he ar t b eat pa ck et s are tr an sm i tt ed th r o u gh th e 8 2 55 9 ’s softw are si milar to other packets.
7.3 TCO Interface
Support for a TCO controller is thro ugh a dedicat ed SMB interf ac e. The 82559 acts as a sl ave on
the SMB and supports data (SMB D), cl ock (SMBCLK), and alert (SMB ALRT#) signals. The
82559 me ets the 100 KHz SMB requirements ac cording to the specification. It is also functional
with an increased clock freq uency of up to 1 MHz and still meets all required SMB tim ings. A
basic SMB wave form diagram is shown in Figure 19.
7.3.1 SMB Alert Signal (SMBALRT#)
The 82 559 operates in slave mode on the SMB during both read and wri te cycl es . When the 82559
tr ans mits data on the SMB (rec eive packet), it iss ues the SMBALRT# signal. In respons e to the
SMBALRT# activ ation, the host proces ses th e interrupt. It acce sses all SMB de vic es
simultaneously by an Alert Response Address (ARA) cycle. The device(s) that issued the
SMBA LRT# signal acknowledges the cycle. If more than one device issued the SMBALRT#, the
highest priority (lowest address) device will win comm unication. Only the winning device ca n de-
asserts its SMBALRT# signal.
As a slave device, the 82559 signals the external TCO Controller using SMBALRT#. The
SM BA LRT# si g nal is act ivated f or th e fo ll ow in g events:
Figure 19. SMB Session
SMBCLK
SMBD
MSB R/W#ADDR ACK ACK ACKACK
CMD BC DATA
start stop
82559 — Netwo rking Sili con
54 Datasheet
•TCO packet received
•Low power st at e ch an g e
•PHY read
7.3.2 Alert Response Address (ARA) Cycle
I f a slav e device needs to initiate a session, it should assert the SMBALRT signal as follo w:
I f the 82559 is not ready, it indicates this in one of two ways:
1. If the 82559’s PHY unit is in a low power st ate, the 82559 will not produce the acknowledge
bit afte r its address appears on the bus. This forc es the TCO controller to stop the se s sion and
r estart it.
2. I f the 82559’s PHY unit is in nominal mode , the 82559 wi ll pull-down the SMBCLK until it is
r ea dy. If the 82559 forces the SMBCLK for more the n 25 ms, t he TCO controller s hould stop
the transmission and restart it.
Figure 20. Slave Request for Data Transfer
SMBCLK
SMBD ACKMSB ACK1
start stop
SMBALRT# The SMBALRT# will rise only if an address match exists.
MSB 1
Networking Silicon — 82559
Datasheet 55
8.0 PCI and CardBus Configuration Registers
The 82559 acts as both a master and a slave on the PCI bus. As a master, the 82559 interacts with
the system main memory to access data for transmission or deposit received data. As a slave, some
82559 control structures are ac cessed by the host CPU to read or write i nformation to the on-chi p
reg iste rs. T he CPU also pro vi des th e 825 59 with the necess ary comm ands a nd pointe rs tha t allow it
to process receive and transmit data.
8.1 Function 0: LAN (Ethern et) PCI Conf iguration Space
The 82559 PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Heade r, as defined in the PCI Specif ication, Revision 2.1. A smal l section is also configured
acc ording to its device specifi c conf iguration space. The confi guratio n spa ce h eader is dep icted
below in Figure 21.
8.1.1 PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82559 are both read onl y w ord entities. Their values are:
Vendor ID: 8086H
Device ID: 1229H
Device ID Vendor ID 00H
Status Command 04H
Class Code Revision ID 08H
BIST Header Type Latency Timer Cache Line Size 0CH
CSR Memory Mapped Base Address Register 10H
CSR I/O Mapped Base Address Regis ter 14H
Flash Memory Mapped Base Address Reg ister 18H
Reserved Base Address Register 1CH
Reserved Base Address Register 20H
Reserved Base Address Register 24H
Reserved (PCI)/CIS P ointer (CardBus) 28H
Subsystem ID Subsystem Vendor ID 2CH
Expansion ROM Base Address Register 30H
Reserved Cap_Ptr 34H
Reserved 38H
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3CH
Power Management Capabilities Next Item Ptr Capability ID DCH
Reserved Data Power Management CSR E0H
Figure 21. P CI Configuration Reg isters
82559 — Netwo rking Sili con
56 Datasheet
8.1.2 PCI Command Register
The 82559 Command register at word a ddress 04H in the PCI c onfiguration spa ce pr ovide s contro l
ove r the 8 2559’s ability to generate an d respond to PCI cycles. If a 0His writt en to thi s regi ster, the
82559 is logica lly disconnected from the PCI bus for all acces s es except configuration accesses.
Th e f ormat of th is r egi s t er is sh ow n in th e figu r e bel ow.
Note th at bi ts three, fiv e, sev en, and nin e are se t to 0b . The table bel o w descr ibes the bit s of the PCI
Command register.
Figure 22. PCI Command Register
Reserved
SERR# Enable
Parity Error Respons e
Memory Write and Invalidat e Enable
Bus Master Enable
Memor y Sp a ce
IO space
0000
1015 01234567
89
Table 4. PCI Command Register Bits
Bits Name Description
15:10 Reserved These bi ts ar e res erve d and should be set to 000000b.
8 SERR# Enable
This bit controls a device’s ability to enable the SERR# driver. A value of 0b
disabl es the SE RR# dr iver. A value of 1b enables th e SERR# driver. This
bit must be set to report address parity errors. In the 82559, this bit is
c onfi gur able and has a default value of 0b.
6 Parity Error Control
This bit controls a device’s response to pa rity errors. A value of 0b cau s es
the device to ignore any parity err ors that it de tect s and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82559, this bit is configurable and has a default value of 0 b.
4Memory Write and
Invalidate Enable
This bit controls a device’s abili ty to use th e Memory Write and Inv alidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write an d Invalidate com m and. In th e 82559, this bit is
c onfi gur able and has a default value of 0b.
2Bus Master
This bit controls a device’s ab il i ty to a ct as a ma ste r on the P CI b us . A v a lue
of 0b disables the device from generating PCI accesses. A value of 1b
allows the devic e to be have as a b us maste r. In the 82559, this bit is
c onfi gur able and has a default value of 0b.
1 Mem ory S pa ce
This bit controls a device’s response to the memory space accesses. A
v al ue of 0b di sa b le s the device re sp on se. A val ue of 1b al l ows th e d ev ic e t o
respond to memory space accesses. In the 82559, this bit is configurable
and its default value of 0b.
0 I/O Spac e
Thi s bi t contr ol s a de v ice’s response to the I/O space accesses.A value of
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82559, this bit is configurable and
the defaul t value of 0 b.
Networking Silicon — 82559
Datasheet 57
8.1.3 PCI Status Register
The 8255 9 Status regis ter is used to record s tatus informa tion for PCI bus re lated e vents. The
for mat of this regi ster is sho wn in the f igure below.
Note that bits 21, 22, 26 , and 27 are set to 0 b and bits 20, 23, and 25 are se t to 1b. The PCI Status
re gister bits are des cribed in the table below.
Figure 23. P CI Status Register
0
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Parity Error Detected
Fast Back To Back (target)
Capabilities List
Reserved011000 10
31 30 29 28 27 26 25 24 23 22 21 20 19 16
Table 5. PCI Status Register Bits
Bits Name Description
31 Detected Parity Error
This bit indicates whether a parity error is detected. This bit must be
asserted by the device when it de tect s a par ity e rror, ev en if parit y error
handling is disabled (as controlled by the Parity Error Response bit in the
PCI Command register, bit 6). In the 82559, the initial value of the Detected
Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
30 Signaled System Error This bi t ind icates w hen t he device has as serted SERR#. In the 82559, the
initial value of the Si gnaled Syst em Error bit is 0b. This bit is set un til
cleared by wri tin g a 1b.
29 Received Master
Abort
This bit indicates whether or not a master abort has occurred. This bit must
be set by the master de vice when its transaction is terminated with a
master abort. In the 82 559, the initial value of th e Receive d Master Abort
bit is 0b. This bit is set until cleared by writing a 1b.
28 Received Target Abort
This bit indicates that the master has received the target abort. This bit
must be set by the master device when its transaction is terminated by a
target abort. In the 82559, the initial value of the Received Target Abort bit
is 0b. This bit is set until cleared by writing a 1b.
27 Signaled Target Abort This bi t ind icat es wheth er a transaction was t erminated by a target abort.
This bit must be set b y the target de vice when i t terminat es a transac tion
with target abort. In the 82559, this bit is always set to 0b .
26:25 DEVSEL # Tim ing
These two bits indicate the timing of DEVSEL#:
00b - Fast
01b - Med ium
10b - Slow
11b - Reserved
In the 82559, these bits are always set to 01b, medium.
82559 — Netwo rking Sili con
58 Datasheet
8.1.4 PCI Revision ID Register
The Rev is ion ID is an 8-bit read only register with a default value of 08H for t he 82559 B- step and
09H for the 82559 C-step. The three least significant bits of the Revision ID can be overridden by
the ID and Revision ID fields in the EEPROM (Section 4.7, “Serial EEPROM Interface” on
page 33).
8.1.5 PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, sp ecific r egister level programm ing interface. The re gister is broken into three byte
size fields. The upper byte is a base class code and s pecifie s the 82559 as a network controll er, 2H.
The middle by te is a subcl ass cod e and spec if ies the 82559 a s an Ethe rnet con trolle r , 0H. The lo we r
byt e ident if ies a spe cif ic re giste r le ve l prog ramming int erfa ce and the 82559 al ways returns a 0H in
this field.
8.1.6 PCI Cache Line Siz e Register
I n order for the 82559 to support the Memory Writ e and Invalidate (MWI) command, the 82559
must also support the Cache Line Size (CLS) register in PCI Configuration space. The register
supports onl y cac he line sizes of 8 and 16 Dwords. Any v alue other than 8 or 16 that is written to
the regis ter is ignored a nd the 82 559 does not use the MWI co mmand. If a value other t han 8 or 16
is written into the CLS regist er, t he 82559 returns all zeroe s when the CLS regist er is rea d. The
figure below illustrates the format of this register.
24 Parity Error Detected
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
which the error occurred.
3. The Parity Error Response bit in the command register (bit 6) is set.
In th e 82559, the i niti al va lue of the Parity Error Detected bit is 0b. This bit
is set until cleared by writing a 1b.
23 Fa st Back- to-Back
This bit indicates a device’s ability to accept fast back-to-back transactions
when the tran sact ions are not to the same agent. A val ue of 0b disables
fast back-to-bac k ability. A value of 1b enables fast b ack-to-back ab ility. In
the 82559, th is bit is rea d only and is set to 1b.
20 Capabilities List
This bit indicate s whether the 82559 implements a list of new capab ilities
such as PCI Power Management. A value of 0b means that this function
does not implement the Capabilities List. If this bit is set to 1b, the Cap_Ptr
regi ster provides an offset into t he 82559 PCI C onfiguration space pointing
to the location of the first item in the Capabilities List. This bit is set only if
the power management bit in the EEPROM is set.
19:16 Reserved These bi ts are reserved and should be set to 0000b.
Table 5. PCI Status Register Bits
Bits Name Description
76543210
000RWRW000
Figure 24. Cache Line Size Register
Networking Silicon — 82559
Datasheet 59
Note: Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b
only if the value of 00010000b (16H) is written to this register. All other bits are rea d only a nd will
return a valu e of 0b on read.
This register is e xpected to be written by the BIOS and the 82559 driver sho uld not write to it.
8.1.7 PCI Latency Timer
The Late ncy Timer register is a byt e wide register. When the 82559 is acting as a bus master, this
registe r defin es the amount of ti me , in PCI clock cycles, that it may own the bus .
8.1.8 PCI Header Type
The Heade r Type regist er is a byte read only register. It is equal t o 00H for a single function
Ethe rnet card and 80H for a combin ation Ethe rnet and mode m card. The v alu e of the hea der type i s
set by the EEPROM (Secti on 4.7, “Se rial EEPR OM Interface” on page 33). In a dual func tio n card,
the OS will read the next conf igurat ion reg is ters bank at offset 100 H.
8.1.9 PCI Base Address Registers
One of the most imp ortant fun ctions for enabling superior configurability and ease of use is th e
ability to relocate PCI devic es in address sp aces. The 8255 9 contains three types of Base Addre ss
Registers (BARs). Two are used for memory mapped re so urces, and one is used for I/O mapping.
Each register is 32 bits wide. The least sign ificant bit in the BAR determ ines whether it represents
a memory or I/O space. The f igures below show the layout of a BAR for both memory and I/O
mapping. After determini ng this information, power-up software can map the memory and I/O
controllers into available locations and proceed with system boot. In order to do this mapping in a
device independent manner, t he base registe r s for this mapping a r e place d in the pr edefined header
por tion of conf i gurati on spa ce. Devi ce drivers c an the n acc ess t his c onf igurat ion space to d etermine
the mapping of a partic ular de vice.
Figure 25. Base Address Register for Memor y Mappi ng
Base Address 0
0
31 4321
Prefetchable
The prefetchable bit is set to ‘0’ in 8255 9 devi ce s
Type
00 - locate anywhere in 32-bit address space
01 - locate below 1 Mbyte
10 - locate anywhere in 64-bit address space
11 - reserved
Memory space indicator
82559 — Netwo rking Sili con
60 Datasheet
Note: B it 0 in all base re giste rs is rea d only and us ed to det ermine whet her the re gis ter maps into memor y
or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that
map to I/ O s pa c e m u s t r etu rn 1b in bi t 0.
Base re gi ster s that map into I/O space are alw ays 32 bits wi de with bit 0 hard-wir ed to a 1b, bit 1 is
r eserved and mus t return 0b on reads, and the other bits are use d to map the device into I/ O space.
The numbe r of u pper bits tha t a device actually imple ments depends on how much of the address
spa ce the device will respond to. For example, a dev ice that wants a 1 Mbyte memory addres s
spa ce w ould set the most signific ant 12 bit s of the bas e address re gister to be configurable, setting
the other bits to 0b.
The 82559 contains BARs for the Control/S tatus Register (CSR), Flash, and Expansion ROM.
8.1.9.1 C SR M emo r y Map p ed Ba se A ddr ess Reg i ster
The 82559 requires one BAR for memory mapping. Software determi nes which BAR, memory or
I /O, is used to access the 82559 CSR registers.
The me mory space for the 82559 CSR Memory Mapped B AR is 4 Kbytes. The space is marked as
not prefetchable and is mapped anywhere in the 32-bit memory add r es s spa ce.
8.1.9.2 C SR I /O M ap p ed Ba se A ddr ess Register
The 82559 req uires one B AR for I/ O mappi ng. Softw are de te rmines which BAR , memory or I/ O, i s
use d to access th e 82559 CSR reg is ters. The I/O s pace for the 82559 CSR I/O BA R is 64 bytes.
8.1.9.3 F la sh M emo r y Map p ed Ba se Add r ess Reg i ster
The Flas h Mem ory BAR is a Dword register. The 82559 physica lly supports a 128 Kbyte Flash
de vi ce. In a CardB us system , the upper s ectio n of the memory mapped windo w (abov e the phys ical
Fl ash dev ice) is used for CIS info rmation. The 825 59 claim s a window of 128 Kb ytes in CardBus
mode and al ways cl aims a Fl ash memory window, r egardless of whethe r or not a Flash de vice is
connected.
8.1.9.4 Exp an si o n RO M Ba se A ddr ess Register
The Expansio n ROM has a memory s pace of 1 Mb yte a nd its BAR is a Dw ord re gis ter th at support s
a 128 Kb yte memory via the 82559 loc al bu s. Th e Expan sion R O M BAR c an be dis able d b y sett ing
the Boot Disab le bit of the EEPROM (word AH, bit 11). If the Boo t Dis able bit is se t, the 82559
returns a 0b for all bits in this address register, avoiding request of memory allocation for this
spa ce. In LAN/modem combinati on designs using Flash , this bit controls the state of the CFCS #
signal (pin L 7) and is cleared after the initial acces s of the ex pans ion R OM area. Th erefore, in a
Figure 26. Base Address Register for I/O Mapping
Base Address 00
31 21
Reserved
I/O sp ac e in dica t o r
1
Networking Silicon — 82559
Datasheet 61
LAN/mo dem comb ination design, t he CFCS # signal will be de-ass erted (high) when the Boot
Disable bit is not se t in the EEPROM and the ROM enable bi t is set in t he Expansion R O M Base
Address Register. After the initial access to the Expansion ROM BAR, the Boot Disable bit is
cleared and CFCS# is asserted (l ow) ena bling the mode m to use the local bus.
8.1.10 Base Address Registry Summary
The preceding description of the Base Address Registers’ f u n ctions a r e summarized in the
following table:
8.1.11 CardBus Card Information Structure (CIS) Pointer
The Card Informat ion Structure (CIS) pointer is a Dword hard coded read only registe r. It is
meaningful only i n a Ca rdBus system (in a PCI s ystem it is zero). The CIS pointe r defi nes where
th e CIS st ruct u r e is mapped in the Flash addr ess space.
8.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers
The Subsystem Vendor ID fie ld identifies the ven dor of an 82559-based solution. The Subsyst em
Vendor ID values are ba se d upon the v endor’s PCI Vendor ID and is controlled by the PCI Special
Interest Group (SIG).
The Subs ystem ID f ield identif ies the 8255 9-based specific solution implemented by the vendor
indicated in the Subsystem Vendor ID field.
The 8255 9 p rov ides suppo rt for conf igur abl e Subsyste m Vendor ID and Subsyst em ID fields . After
hardware reset is de-asserted, the 8 2559 automatically reads addresses AH through CH of the
EEPROM. The first of these 16-bit values is used for controlling various 82559 functions. The
second is the Subsystem ID va lue, and the third is the Subsystem Vendor ID value. Again, the
default values for the Subsystem ID and Subs ys tem Vendor ID are 0H and 0H, respective ly.
Table 6. Base Address Reg ister Functional ities
Register
Name PCI Function PCI Window CardBus Function CardBus Window
BAR0 Memory CSR 4 Kby te Memory CSR 4 Kbyte
B AR1 I/O CSR 4 Kbyt e I/O CSR 4 Kbyte
BAR2 Fl ash 12 8 Kbyte CIS at o ffs et + 64 K byt e 128 K byt e
Expansion
BARaBootROM 1 Mbyte N/A
(Disabled by EEPROM) 1 Mbyte
a. The Expansion BAR can be disabled by setting the Boot Disable bit in the EEPROM.
Bits R/W Default Description
31:4 R 1000H Ethernet CIS Pointer (above the physical Flash window)
3:0 R 3H CIS in the Flash window
82559 — Netwo rking Sili con
62 Datasheet
The 82559 che cks bit numbers 15, 14, and 13 in the EEPROM, wo rd AH and funct ions according
to Table 7 below.
The above table implies that if the 82559 detects the presence of an EEPROM (as indicated by a
value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the
EEP ROM, words BH and CH, will be loaded into the Subsystem ID (word BH) and Subsystem
Vendor ID (word CH) fields. If bits 15 and 14 equal 01b and bit 13 equals 1b, the three least
significant bits of the Revis ion ID field are program m ed by bits 8-10 of the first EEPROM word,
word AH.
Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82559
does not respond to an y P CI conf igurati on cycles. If the 82558 happens to be accessed during this
time, it will Retr y the acce ss . More information on Retry is provided in Section 4.2.1.1.3, “Retry
Premature Accesses” on page 20.
8.1.13 Capability Pointer
The Capability Pointer is a hard coded byte register with a value of DCH. It provides an offset
within the Configuration Space for the location of the Power Management registers.
8.1.14 Interrupt Line Register
The Inte r r u pt L ine re gister ide n tifies which system inte r r upt request line on the int er rupt contr oller
the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.
8.1.15 Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
I NTA# through INTD#, a PCI device is connected to . The 82559 is connected the INTA# pin.
8.1.16 Minimum Grant Register
The Minimum Grant (Min_ Gnt) register is an optional re ad only regi st er for b us mast ers and is not
applicable to non-mas ter devices. It defines the amount of time the b us master w ants to retain PCI
bus ownership when it initi ates a trans ac tion. The default valu e of this reg is ter for the 82559 is
08H.
Table 7. 82559 ID Fields Pr ogramming
Signature
(B its 15:1 4) ID
(Bit 13) AltID
(Bit 7) Device
ID Vendor
ID
Revision IDaSubsystem
ID Subsystem
Vendor ID
B-step C-step
11bb, 10 b,
00b X X 1229H 8086H 08H 09H 0000H 0000H
01b 1b X 122 9H 8086H Word AH ,
bits 10:8 Word AH,
bits 10:8 Word BH Word CH
01b 0b 1b 1229H 8086H 08H 09H Word BH Word CH
01b 0b 0b 1029H 8086H 08H 09H Word BH Word CH
a. The Revision ID is subject to change according to the silicon stepping.
b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
Networking Silicon — 82559
Datasheet 63
8.1.17 Maximum Latency Register
The Maxim um Latency (Ma x_Lat) register is an optional rea d only reg is ter for bus masters and is
not applicabl e to non-master devi ces. This register defi nes how ofte n a device nee ds to access the
PCI bus. The default value of this register fo r the 82559 is 18 H.
8.1.18 Capability ID Register
The Capabili ty ID is a byte registe r. It signifi es whether the current item in the linked list is the
register defin ed for PCI power management. PCI po wer m ana gement has been assigned the value
of 02H. The 82559 is fully compl iant with the P CI Power Mana gem ent Specif ication, Revision 2.2.
8.1.19 Next Item Pointer
The Next Item Pointe r is a byte registe r. It descr ibes the location of the ne xt item in the 82559’s
capability lis t. Since power management is the last item in the li st, this re gister is set to 0b.
8.1.20 Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the c apabi lit ies of the 82559 relate d to power managem ent. T he 82559 re ports a val ue of FE21H
if it is connected to an aux iliary power source and 7E21H otherwise. It indicates that the 82559
supports wak e-up in the D3 state i f power is supplied, either Vcc or VAUX.
Ta ble 8. P ow er Mana geme nt Capabi l it y Regis t er
Bits Default Read/Write Description
31:27 00011b
(no VAUX)
11111b
(VAUX)
Read Only PME Support. Th is five bit field indicates the power state s in which
the 82559 may assert PME#. The 82559 supports wake-up in all
power states if it is fed by an auxiliary power supply (V AUX) an d D0,
D1, D2, and D3hot if it is fed by PCI power .
26 1b Read Only D2 Support. If this bit is set, the 8255 9 supports the D2 power state .
25 1b Read Only D1 Support. If this bit is set, the 8255 9 supports the D1 power state .
24: 22 0 00 b Read O nl y Auxiliary Current. This field reports whether the 82559 implements
the Data registers. The au xiliary power consump tio n is the same as
the current co nsumption reported in the D 3 state in the Data register.
21 1b Read Only Device Specific Initialization (DSI). The DSI bit indi cate s whether
special initialization of this function is required (beyond the standard
PCI configuration header) before the generic class device driver is
able to use it. DSI is required for the 82559 after D3-to-D0 reset.
20 0b ( PC I)
1b
(CardBus)
Read Only Reserved (PCI)/Auxiliary Power Source (CardBus). When this bit
is set to ‘1’, it indicates that the 82559 requires auxiliary power
supplied by the system for wake-up from the D3cold sta te.
19 0b Read Only PME Clock. The 82 55 9 do es no t re qu ire a clo c k to gen era t e a power
management event.
18: 16 0 10 b Read O nl y Version. A value of 010b i ndicates that the 82559 complies with of
the PCI Power Management Specifica tion, Revision 2. 2.
82559 — Netwo rking Sili con
64 Datasheet
8.1.21 Power Management Control/Status Register (PMCSR)
The Po wer Managemen t Control/ S tatus is a word re gister. It is used to det erm ine and change the
current power state of the 8 2559 and control the power man agement interrupts in a standard
manner.
8.1.22 Data Register
The data register is an 8-bi t read only registe r that provides a mechanism for the 82559 to report
state depende nt maximum po wer consumption and heat dis sipation. The value reported in this
r egiste r depends on the val ue written to the Data Sele ct fi eld in the PMCSR register. The po wer
me asurements defined in this register have a dynamic ra nge of 0 to 2.55 W with 0.01 W res olution
acc ording to th e Data Scale. The value in this re gister is hard coded in the silicon. The struc ture of
the data re gister differs betwe en the 82559 B-step and C-step. The are pres ented below in Table 10
and Table 11, resp ectively.
Table 9. Power Management Control and Status Register
Bits Default Read/Write Description
15 0b Read/Clear PME Status. This bit is set up on a wake-up ev ent. It is independent of
the state of the PME Enable bit. If 1b is written to this bit, the bit will be
cleared. It also de-asserts the PME# signal and clears the PME status
bit in the Power Management Dr iver Regis ter. When the PME# signal
is enabled, the PME# signal reflects the state of the PME status bit.
In a C ardBus system, writing a 1b to this bit clears the GWAKE bit in
the Fu nct ion E v en t r eg is ter. Th e Fu nct i on Ev en t reg is te r i s d es cri bed in
Section 9.1.14.1, “LAN Function Event Register” on page 77.
14:13 00b Re ad Only Data Scale. This field indicates the data register scaling factor. It
equals 10b for registers zero through eight and 00b for registers nine
t hro ugh fifteen.
12:9 0000b Read Only Data Select. T hi s f ield is us ed to se le ct w hic h dat a is re ported thr oug h
the Data register and Data Scale field.
8 0b Read Clear PME Enable. This bit enables the 82559 t o assert PME#.
7:5 0 00b Read Only Reserved. These bits are reserv ed and should be set t o 000b.
4 0b Read Only Dynamic Data. The 82559 does not supp ort the ability to monitor the
po wer co ns u mp t io n dy na m ic ally.
3:2 0 0b Read Only Reserved. These bits are reserved and should be set to 00b.
1:0 00b Read/Write Power State. Th is 2- bit field i s used to determ ine t he cur re nt power
state of the 82559 and to set the 82559 into a new power state. The
definition of the field v alues is as follows.
00 - D0
01 - D1
10 - D2
11 - D3
Table 10. 82559 B-step Ethernet Data Register
Data Select Data Scale Data Reported
0 2 D0 Power Consumption = 58 (580 mW)
1 2 D1 Power Consumption = 40 (400 mW)
2 2 D2 Power Consumption = 40 (400 mW)
Networking Silicon — 82559
Datasheet 65
3 2 D3 Power C onsumpt ion = 40 (400 m W)
4 2 D0 Power Dissipated = 58 (580 mW)
5 2 D1 Power Dissipated = 40 (400 mW)
6 2 D2 Power Dissipated = 40 (400 mW)
7 2 D3 Power Dissipated = 40 (400 mW)
8 2 Common Function Power Dissipated = 00
9-15 0 Reserved (00H)
Table 11. 82559 C-step Ethernet Data Register
Dat a Se lect Data Scale Dat a Report ed
0 2 D0 Power C onsumpt ion = 60 (600 m W)
1 2 D1 Power C onsumpt ion = 42 (420 m W)
2 2 D2 Power C onsumpt ion = 42 (420 m W)
3 2 D3 Power C onsumpt ion = 42 (420 m W)
4 2 D0 Power Dissipated = 60 (600 mW)
5 2 D1 Power Dissipated = 42 (420 mW)
6 2 D2 Power Dissipated = 42 (420 mW)
7 2 D3 Power Dissipated = 42 (420 mW)
8 2 Common Function Power Dissipated = 00
9-15 0 Reserved (00H)
Table 10. 82559 B-step Ethernet Data Register
Dat a Se lect Data Scale Dat a Report ed
82559 — Netwo rking Sili con
66 Datasheet
8.2 F unction 1: Modem PCI Configuration Space
I n PCI systems and CardBus systems, the 82559 sup ports a dual function de vice: L AN/modem.
The LAN is defined as f unction zero , and the m odem is d efin ed as function one. The mode m
f unction is active depending on the EEPROM setup.
The modem co nfiguration regis ters define the res ources required by the modem function. It is
meaningful in a multifunction card design only. Some of the modem configuration registers are a
r eflectio n of thei r matched Ethernet regis ters. The registe rs ’ values are pre-defined by hardware,
initialized by the EEPROM, or configurable through software. The shaded fields are des cribed in
detail in the following subsections.
8.2.1 Modem Configuration ID Register
The Modem Configuration ID field is a Dword register com posed of the Device ID and Vendor ID.
It is a re ad only regis t er an d its value is lo a d ed fro m th e EE PROM .
Modem Configuration ID 00H
M odem Status Modem Command 04H
Modem Revi sion ID 08H
BIST Mode m Header Type Latenc y Time r Cache Line Siz e 0CH
Modem I /O Mapped Base Address Register 10H
Modem Memory Mapped Base Address Register 14H
Reserved Base Address Register 18H
Reserved Base Address Register 1CH
Reserved Base Address Register 20H
Reserved Base Address Register 24H
Reserved (PCI)/Modem CIS Pointer (CardBus) 28H
Modem Subsyst em ID Modem Subsystem Vendor ID 2CH
Expansion ROM Base Address Register 30H
Reserved Cap_Ptr 34H
Reserved 38H
Max_Lat Min_Gnt Modem I nterrupt 3CH
Modem Power Management Capa bilities Next Item Ptr Capability ID DCH
Reserved Modem Data Modem Power Management CSR E0H
Figu re 27 . Modem PC I Conf i gurat i on Re g ist ers
Networking Silicon — 82559
Datasheet 67
8.2.2 Modem Command Register
The Modem Comm and field is a 16 bit word registe r and provides basic control ov er the modem’s
abil ity to r espond to PCI /CardBus acc esse s. T he Comman d regi ste r’s structure is shown in the table
below.
8.2.3 Modem Status Register
The Modem Status field is a 16 bi t word re gister. It provides basic track of CardBus relate d events .
All bits are cleared by PCI R ST#.
Table 12. Po wer Management Control and Status Register
Bits Default Read/Write Description
15: 10 0 00 00 0b Rea d O nly Reserved. Thes e bits are reserved and s hould be set to 0000 00b.
9 0 b Rea d O nl y Fast Back-to-Back.
8 0b Read/Write System Error Enable.
7 0 b Rea d O nl y Wait Cycle Enable.
6 0b Read/Write Parity Error Enable.
5 0 b Rea d O nl y VGA (define).
4 0 b Rea d O nl y Memory Write and Invalidate.
3 0 b Rea d O nl y Special Cycle.
2 0 b Rea d O nl y Master Enable.
1 0b Read/Write Memory Access Enable.
0 0b Read/Write I/O Access Enable.
Table 13. Modem Status Register
Bits Default Read/Write Description
15 0 Read/Write Parity Error.
14 0 Read/Write System Error Enable.
13: 11 0 00 Rea d O nl y Signaled/Received Target Abort.
10:9 01 Read Only Device Select Timing.
80 Read OnlyData Parity Detect.
70 Read OnlyFast Back-to-Back Capable.
6:5 0 0 R ea d O nl y Reserved. These bits are reserved and s hould be set to 00b.
41 Read OnlyNew Capability.
3:0 0 00 0 R ea d O nl y Reserved. Th ese bits are reserved and should be set to 0000b.
82559 — Netwo rking Sili con
68 Datasheet
8.2.4 Modem Revision ID Register
The Modem Revision ID r egister is a Dword, read only field. It is com pos ed of the Revision ID
byte and a 24-bit Class Code register. Its value is loaded from the EEPROM. The Class Code
identi fies the function as a modem. The Class Code and Revis ion ID are listed in the table bel ow.
8.2.5 Modem Header Type Register
The Modem Header Type field is a byte wide, read only register. It indi ca tes that this is a
multifunction card and a value of 80H is hard coded in the si licon.
8.2.6 Modem I/O Base Address Register
The Modem I/O BAR is a Dword register that specifies the I/O base address for accessing the
82559’s modem. The required I/O space is 8 bytes.
8. 2.7 Modem Mem ory Base Add ress Reg ister
The Modem Mem ory BAR is a Dword register that specifies the memory base address for
acc essing the 82559’s modem port. The re quired me mory space is 5 12 bytes. T he memory s pace is
use d for both control regist ers and CIS mapping.
8.2.8 Modem CardBus CIS Pointer
The CI S poi nter is a Dword, h ard c oded, read only register. The CIS pointer indicates whether or
not the CIS structure is located in the memory address space. The physical location of the CIS
structure is in the serial EEPROM. The EEPROM format is described in S ection 4.7, “Serial
EEPROM Inte rface” on page 33.
8. 2.9 Modem Subsystem Ven dor ID Regis ter
The Modem Subsystem Vendor ID is a 16 bit read only register. Its value is loaded from the
EEPROM and is a reflection of register 2CH in Function 0, LAN (Ethernet) function.
Table 14. Modem Revision Register
Bits Default Read/Write Description
31:24 07H Read Only Base Class. This indicates that the 82559 is a co mmunica tio n device.
23:16 00H Read Only Subclass. This indicates the serial controller equals 00H.
15:8 02H Read Only Program Interface. This indicates that the 82559 is 16550 UART
co mpat ible and initialized by EEPROM word FEH.
7:0 XXH Read Only Revision Number. Thi s i nd icat es the r evi si on numb er an d is i n it ial iz ed
by EEPROM word FEH.
Bits R/W Default Description
31:4 R 0010H Modem CIS Pointer (above the control registers)
3:0 R 2H CIS in the Memory Base Address Register
Networking Silicon — 82559
Datasheet 69
8.2.10 Modem Subsystem ID Register
The Mo dem S ubsystem ID is a 16 bit re ad only register. It s val ue is loaded from the EEPROM and
is a reflection of register 2EH in Function 0, LAN (Ethernet) function.
8.2.11 Modem Capabilities Pointer
The Modem Ca pability Pointer is a hard coded, by te registe r that contains the value DCH. It
provides an of fset within the Configuration Space for the loca tion of the power mana gement
registers.
8.2.12 Modem Interrupt Register
The Modem Interrupt register spe cifies whether or not the mode m requires an interrupt. Thi s
register is hard coded identically to register 3CH in Function 0, LAN (Ethernet). It indicates that
the mo dem r equires int errupt support.
Note: T he modem and Ethernet f unctions share the same I NTA# pin.
8.2.13 Modem Power Management Capabilities Register
The Mo dem Po wer Manageme nt Capa bilit ie s re gist er is a Dword f ie ld tha t i ndicat es i f th is func tion
has po wer m anageme nt capabil ity, as wel l as ide ntifyi ng whic h power manage ment capa bilit ie s are
supported. The 82559 reports a value of FE31H if i t is conne cted to an auxiliary power sourc e and
7E21H othe rwise.
8.2.14 Modem Power Management Contro l/Status Register
The Mod em Po wer Mana gement Con trol /Statu s Re gist er i s a wor d regi ster. It is used to manag e the
modem’s power management state. It also enables and monitors power management events. The
Modem Power Management Control/Status Register structure is identical to register E0H in
Function 0, LAN (Ether net) function.
8.2.15 Modem Data Register
The Modem Data re gister h as similar functionality to re gister E2H in Function 0, LAN (Ethe rnet).
The register at locat ion E2H r eports power consumption of the modem functio n. Th e value of
power consumption and power di ssipation are loaded from the EEPROM.
Table 15. Ethernet Data Regist er
Dat a Se lect Data Scale Dat a Report ed
0 - 3 2 D0 to D 3 P o we r Co nsu mp tion (lo ade d f rom
EEPROM)
4 - 7 2 D0 to D3 Power Dissipated (loaded from
EEPROM)
8 - 15 0 Reserved (00H)
82559 — Netwo rking Sili con
70 Datasheet
8.2.16 Modem Support in PCI Mode
The 82559 C-step su pports modem int erface in PCI mode. The Modem Ena ble (MDM) bit in the
EE PROM ca n be activat ed in PCI systems without the loss of BootROM support. In addition ,
BootROM support has been simplified. The 82559 C-step suppor ts the co-existenc e of a BootRom
Fl as h dev ice and a modem device (using CFCS# with e xternal glue logic). This is don e by setting
the MDM bit a nd cle aring th e Bo ot Disable (BD) b it i n the E EPR OM. Wit h thi s conf i gurati on, both
the modem function and BootRom BAR a re ac tive. The selecti on between the two functions is
done through the Boot Enable bit (th e least signif ican t bit of BootRom BAR i n the L AN PCI
Configuration space). The 82559 will not support a LAN/modem design if add itiona l companion
ASIC s ar e operating on the Fl as h/modem interface. This li mi tati on does not affect companion
ASIC s th at re side on the SMB interface of the 82559.
Networking Silicon — 82559
Datasheet 71
9.0 Control /Status Registers
9.1 LAN (Ethernet) Control/Status Reg isters
The 8255 9’s Control/Status Register (CSR) is illustrated in th e figu re below.
NOTE: In Figure 28 above , SCB is def ined as the Sy stem Control Block of th e 82559, and PM DR is defined as
the Power Management Driver Register.
SCB Status Word: The 82559 places the s tatus of its Command and Receive units and
inter r u p t in d icati on s in th i s reg iste r f o r th e CP U to re ad .
SCB Command Word: The CPU pla ces commands for the Comm and and Receive units in
this register. Interrup ts are also acknowledged in this r egiste r.
SCB General Pointer: The SCB Genera l P ointer register points to various data structure s
in main me mo ry depending on the current SCB Com mand word.
PORT Interface: The PORT interface allows the CPU to reset the 82559, force the
82559 to dum p informati on to main memory, or pe rform an inte rna l
self test.
Flash Control Register: The Flash Control register allows the CPU to enable writes to an
external Flash.
EEPROM Control Register: The EEPROM Control registe r allows the CPU to read a nd write to
an ext er nal EEP RO M .
D31 Upper Word D16 D15 Lower Word D0 Offset
SCB Command Word SCB Status Word 00H
System Control Block General Pointer 04H
PORT 08H
EEPROM Control Register Flash Control Register 0CH
Management Data Int erface (MDI) Control Register 10H
Re ceive Direct Memory Access Byte Count 14H
PMDR Flow Control Register Early Receive Int 18H
Re se rved Ge neral S ta t us Gen er a l Co nt r ol 1 C H
Reserved 20H
Reserved 24H
Reserved 28H
Reserved 2CH
Funct ion Event Register 30H
Function Eve nt Ma sk Register 34H
Function Present State Register 38H
Force E vent Register 3CH
Figure 28. 82559 Control/Status Register
82559 — Netwo rking Sili con
72 Datasheet
MDI Control Register: The MDI Control register al lows the CPU to read and write
information from the PHY unit (or an external PHY component)
through the Management Data Interface.
Receive DMA Byte Count: Th e Re c e ive D M A Byte Co unt reg is ter kee p s tr a c k of how m a ny
bytes of receive dat a have been pass ed into host mem ory via DMA.
Flow Control Register: This register holds the flow control threshold value and indicates
the flow control commands to the 82559.
PMDR: The Power Manageme nt Driver Register provides an indication in
memory and I/O space that a wake-up interrupt has occurred. The
PMDR is described in further detail in Section 9.1.11, “Power
Management Driver Register ” on page 75.
General Control: The General Control register allows the 82559 to enter the deep
power-do wn st ate and provides the ability to disable the Clockrun
functionality. The General Control register is described in further
detail in Section 9.1.12, “General Control Regis ter” on page 76.
G ener al Status : The General Status register describes the status of the 82559’s
duplex mode, spe ed, and link. The Genera l S tatus re gister is
detail ed in Section 9.1.13, “General Status Register” on page 76.
Function Even t: The Function Event Register is used for CardBus power
managem ent applications and s pecifies the event that changed the
status . Th e Function Ev ent register is furthe r defi ned i n Section
9.1.14.1, “LAN Function Event Register” on page 77.
Function Event Mask: The Function Event Mask register masks the CSTSCHG signal
assertion for specified ev ents. The Function Event Mask register is
further def ined in Section 9.1.14.2, “LAN Funct ion Event Mask
Register” on pag e 77.
Func t io n Present S tat e : The Function Present State register reflects the current state of each
condition th at may cause a status change or int errupt. The Fun ction
Present State register is fu r ther defin ed in Sec tion 9.1.14.3, “LAN
Function Present State Register” on page 78.
Force Event: The Force Event register simulates the status change events for
troubleshooting purposes. The Force Event register is further
defined in S ection 9.1.14.4, “LAN Force Even t Register” on
page 79.
Networking Silicon — 82559
Datasheet 73
9.1.1 System Control Block Status Word
The System Control Block (SCB ) St atus Word contain s sta tus information relat ing to the 82559’s
Command and Receive units.
9.1.2 System Control Block Command Word
Commands for the 82559 ’s Command and Receive units are placed in this register by the CPU.
Bits Name Description
15 CX Command Unit (CU) Executed. The CX bit indicates t hat the CU has
completed executing a command with its interrupt bit s et.
14 FR Frame Received. The FR bit indicates that the Receive Unit (RU) has
finished receiving a frame.
13 CNA CU Not Active. The CNA b it is set w h en the CU is no longer a ctive and in
either an idle or suspended state.
12 RNR Receive Not Ready. The RNR bit is set when the RU is not in the ready
st at e. This may be cau se d by an RU Abo r t com m an d, a no reso ur c es
situation, or set suspend bit due to a filled Receive Frame Descriptor.
11 MDI
Management Data Interrupt. The MDI bit is set when a Management Data
Int erface re ad o r writ e cycl e h as comp le t ed. T he mana ge ment da ta in te rru pt
is enabled th rough the interru pt enable b it (bit 2 9 in th e Management Data
Interface Control register in the CSR).
10 SWI Software Interrupt. The SWI bit is set when software generates an
interrupt.
9ER Early Receive. The ER bit i s used for early recei ve interrupts.
8FCP Flow Control Pause. The FCP bit is used as the flow control pause bit.
7:6 CUS Command Unit Status. The CUS field contains the status of the Command
Unit.
5:2 RUS Receive Unit Status. The RUS field contains the status of the Receiv e Unit.
1:0 R eserved The se bit s are reserved and should be se t to 00b.
Bits Name Description
31:26 Specific
Interrupt Mask
Specific Interrupt Mask. Setting this bit to 1b causes the 82559 to stop
generating an interrupt (in other w ords, d e-assert the INTA# signal) on the
corresponding event.
25 SI Software Generated Interrupt. Setting this bit to 1b causes the 82559 to
gener ate an interrupt. Writing a 0b to this bit has no effect.
24 M Interrupt Mask. If the Interrupt Mask bit is set to 1b , the 82559 will not
assert its INTA# pin. The M bit has higher precedence that the Specific
Inte rr u pt Mask bits and the SI bit.
23:20 CUC Command Unit Command. This fiel d contains th e CU comman d.
19 Reserved This bit is reserved and should be set to 0b.
18:16 RUC Receive Unit Command. Th is fi eld contains the RU command.
82559 — Netwo rking Sili con
74 Datasheet
9.1.3 System Control Block General Pointer
The System Control Block (SCB) General Pointer is a 32-bit f ield that points to various data
structure s de pending on the command in the CU Command or RU Command f ield.
9.1.4 PORT
The POR T interf ace a llo ws s oftw are to p erform cert ain co ntrol func ti ons on t he 82559. This fie ld i s
32 bits wi d e :
•Address and Data (bits 32:4)
•PORT Function Select ion (bits 3:0)
The 82559 supports four PORT commands: Software Reset, Self-test, Selective Reset, and
Dump.
9.1.5 Flash Control Register
The Flash Control Register is a 32-bit field that allows access to an external Flash device.
9.1.6 EEPROM Control Register
The EEPR OM Control Register is a 32-bit field that enables a read from and a write to the external
EEPROM.
9.1.7 Management Data Interface Control Register
The Management Data Interface ( MDI) Control re gis ter is a 32-bi t fie ld and is used to read and
write bits from the MDI.
9.1.8 Receive Direct Memory Access Byte Count
The Rece ive DMA Byte Count register keeps track of how many bytes of receive data have been
pas sed into hos t m em ory via DMA.
Bits Description
31:30 These bits are res erved and shou ld be set to 00b.
29 Interrupt Enable. When this bit is set to 1b by software, the 82559 asserts an interrupt to
indicate the end of an MDI cycle.
28 Ready. This bit is set to 1b by the 82559 at the end of an MDI transaction. It should be reset to
0b by software at the same time the command is written.
27:26 Opcode. These bits define the opcode: 01 for MDI write an d 10 for M DI read. All other value s
(00 an d 11) are reserved.
25:21 PHY Address. Th is field of b its contains the PHY address.
20:16 PHY Register Address. This field of bits contains the PHY Register Address.
15:0 Data. In a write command, soft ware places the data bits in this field, and the 82559 trans fers
the da ta to th e PH Y uni t. D urin g a rea d co mma nd , the 82 55 9 rea ds the se bit s se rial l y fro m t he
PHY unit, and software reads the data from this location.
Networking Silicon — 82559
Datasheet 75
9.1.9 Early Receive Interrupt
The Early Receive Interrupt register allows the 82559 to generate an early interrupt depending on
th e length of t h e f r ame. An early inter rupt is indicated by t h e ER bit in t he SCB Sta tus Word and
the assertion of the INTA# signal.
9.1.10 Flow Control Register
The Flow Cont rol Register contains the following fields :
•Flow Control Command
The Flow Control Command field describes the ac tion of the flow control process (for
exa mple, pause, on, or off).
•Flow Control Threshold
The Flow Control Threshold fie ld contains the thres hold value (in oth er words, the number of
fr ee byt es in th e Receive F I F O ) .
9.1.11 Power Management Driver Register
The 82559 provides an ind icati on in memory and I/O spac e that a wake- up e vent has occurred. It is
located in the Po wer Management Driver (PMDR). The PMDR is us ed for CardBus mode only.
Note: T he PMDR i s initializ ed at ALTRS T# reset only.
Table 16. Po wer Management Driver Register
Bits Default Read/Write Description
31 0b Read/Clear Link Status Change Indication. The link st atus change bi t is set
following a change in link status and is cleared by writing a 1b to it.
30 0b Read/Clear Magic Packet. This bit is set when a Magic Packet is received
regardless of the Magic Packet wake-up disable bit in the configuration
c ommand and the PME Enable bit in the Power Management Control/
Status Regist er. This bit is cleared by writing 1b t o it.
29 0b Read/Clear Interesting Packet. This bit is set when an “interesting” packet is
recei ved. Int eres ting packets are defined by the 82559 packet filters.
This bit is cleared by wri ting 1b to it .
28: 26 0 00 b Read O nl y Reserved. Thes e bit s are rese rved and should be se t to 000b.
25 0b Read/Clear TCO Request. This bit is set to 1b when the 82559 is busy with TCO
activity.
24 0b Read/Clear PME Status. This bit is a r eflection of the PME Status bit in the Power
Management Control/S tat us Register (PMCSR). It is se t upon a wake-
up event and is inde pendent of the PME Ena ble bit.
This bit is cleared by writing 1b to it. This also clears the PME Status
bit in the PMCSR and de-asserts the PME signal. In a CardBus
s ystem, if 1b is writt en to this field, the General Wake -up (GWAKE) bi t
in th e Fun c tion E ven t register is cleared.
82559 — Netwo rking Sili con
76 Datasheet
9.1.12 General Control Register
The General Control regi ster is a b yte re giste r and is describe d belo w. The General Control re giste r
is used in CardBus mode only.
9.1.13 General Status Register
The General Status registe r is us ed i n CardBus mode only and is a byte register which indicates the
link statu s of the 82559.
9.1.14 Ethernet Card Status Change Registers
The PME si gnal used in PCI systems is replaced by the Card Status Change (CSTS CHG) s ignal in
CardBus systems. The CardBus specif ication requires the use of control/status registers related to
C ST SCHG. There are four event relat ed reg is t ers.
•Function Event Register: Specifies the ev ent tha t change d stat us
•Function Event Mask Register: Masks C STSC H G sign a l assertio n for spe cified events
•Fu ncti on Pr esent St ate Reg ist er: Reflect s the curren t sta te of e ach c onditi on t hat may c ause a
st atus change or int errupt
•Force Even t Regist er: Simu lates sta tus change ev ents for troubleshooti ng purposes
These CardBus registers are used by software to determine which event has occurred, manage the
ev ent, and cont rol the CSTSCHG signal.
Table 17. General Control Register
Bits Default Read/Write Description
7:2 0 00000b Read Only Reserved. These bits are reserved and should be set to 000000b.
1 0b Read/Write Deep Power-Down on Link Down Enable. If a 1b is written to this
field, the 82559 may enter a deep power-down state (sub-3 mA) in t he
D2 and D3 power states while the l ink is do wn.
In this state, the 82559 does not keep link integrity. This state is not
supported for point-to-point co nnection of two end st ati ons.
0 0b Read/Write Clockrun Signal Disable. If this bit is set to 1b, then the 82559 will
always request the PCI clock signal. This mode can be used to
ove rc om e potential rec e ive over r uns ca us ed by Cl ock run si gnal
la tencie s over 5 µs.
Tab le 18. Gene ral S ta tus Register
Bits Default Read/Write Description
7:3 0 0000b Read Only Reserved. These bits are reserved and should be set to 00000b.
2 -- Read Only Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)
or half duplex (0b).
1 -- Read Only Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps
(0b).
0 0b Read Only Link Status Indication. This bit indicates the status of the link: valid
(1b) or invali d (0b ).
Networking Silicon — 82559
Datasheet 77
The 8255 9 supports onl y the interrupt and general wake-up ev ent bits i n the c ard status change
register s. These registers c ompl im ent the PCI Power Management registers in a non- ACPI
comp liant OS. They are initialized by a power-up re se t on the ALTRST# pin.
The l ocation of the se registe r s shoul d be spec ified within t he configura tion space pointing to offse t
address 30H of the CSR.
Note: Ac cess to the CSTSCHG re gisters in P CI mo de is forbidden.
9.1.14.1 LAN Function Event Register
The Function Event r egister specified the event that changed the status.
9.1.14.2 LAN Function Event Mask Register
The Function Event Mask register masks CSTSCHG and INTA# assertion.
Tabl e 19. LAN Function Event R e gi st er
Bits Function Default Description
31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.
15 INTR 0b
This bit is used for as the interrupt bit. It is set when the Ethernet
int erru pt sou rce is se t, r eg ardl ess of th e mask v a lu e. I t is cl ea red when
the O S wri tes 1b to this fiel d and the interrupt source has been
serviced. Writin g 0b to this field has no ef fect.
14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification.
4 GWAKE 0b
This bit is used for general wake-up. It is set when the Ethernet wake-
up source is set, regardless of the mask value. Writing 1b to this field
clears this bit and the PME Status bit in the PMCSR. Writing 0b to this
field has no effect. Note that writing 1b to the PME Status bit in the
PMCSR has the same effec t.
3 Reserved 0b Bit 3 is reserved in the CardBus Specification.
2 BVD RDY 0b Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
1 BVD WP 0b Bit 1 is used as the BVD Write Protect (WP) bit.
0 Reserved 0b Bit 0 is reserved in the CardBus Specification.
Table 20. LAN Function Event Mask Register
Bits Function Default Description
31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.
15 INTR 0b
This bit is the interrupt mask. When this bit equals 0b, it masks the
Ethernet function INTA# line but has no effect on the LAN Function
Event reg ist er. The Ethernet funct ion can assert the INTA# signal only
when both fields are enabled: the interrupt bit and the “M” bit in the
System Control Block (SCB) register within the CSR space. The
interrupt mask bit affects the INTA# masking.
14 WKUP 0b This bit is the wake-up mask. When this bit equals 0b, it masks the
Ethernet function CSTSCHG signal but has no effect on the LAN
Functi on Event regi ster. This bit is dependent on bit 4 of t his r egister.
13:7 Reserved 0 Bits [13:7] are reserved in the CardBus Specification.
6:5 PWM
BAM 0These bits are used for Pulse Width Modulation Binary Audio Enable
(PWM BAM).
82559 — Netwo rking Sili con
78 Datasheet
9.1 .14.3 LAN Function Present State Register
The Function Present State re giste r reflects the current state of the LAN function that ma y cause a
st atus change or int errupt.
4 GWAKE 0b
Thi s bi t is th e ge ne ral wa k e- up ma sk. When th is bi t equ al s 0b, it masks
the Ether ne t func ti on wak e -up e v e nt s towar d s the CST SCHG si gnal . It
has no ef fect on the L AN Fun c tio n Ev ent regi ster. The 82559 can
assert the CSTSCHG si gnal in the follow ing configuration of mask ed
bits: wake-up bit AND general wake- up bit, or PME Enable bit in the
PMCSR register only.
3 Reserved 0b Bit 3 is reserved in the CardBus Specificat ion.
2 BV D RDY 0b Bit 2 is used as the Battery Vol tage Detect Ready (BVD RDY) bit.
1 BVD WP 0b Bit 1 is used a s the BVD Write Protect (WP) bit.
0 Reserved 0b Bit 0 is reserved in the CardBus Specificat ion.
Table 20. LAN Function Event Mask Register
Bits Function Default Description
Table 21. LAN Fu nction Present State Register
Bits Function Default Description
31:16 Reserved 0 Bits [31: 16] a re reserved in the CardBus Specification.
15 INTR 0
This bit is used for interrupts. It reflects the current state of the
Ethernet source of the interrupt regardless of the mask value. It is set
when the Ethernet function has a pending inter rup t and c lear ed when
the software driver acknowledges all active int errupts through the SC B
Command Word.
14:5 Reserved 0 Bits [14:5] are re serve d in t he CardBus Specification.
4 GWAKE 0
This bit is used for general wake-up. It reflects the current state of the
Ethernet source of CSTSCHG. It is a logical OR result of the gated
three most significan t bit s in th e PMDR : Li nk Status Change, Magic
Pa cket , and Int eres ting Packet . The Link Status change bit is gated b y
the Link Status Change Wake Ena ble bit in the Confi gur ation
comma nd . The M ag ic P ac k e t bit is ga t ed b y t h e M agic Pac k e t Wa k e- up
disable bit in the Configuration command. The Intere sting Packet bit is
gated by the programmable filter command.
3 Reserved 0b Bit 3 is reserved in the CardBus Specificat ion.
2 BV D RDY 0b Bit 2 is used as the Battery Vol tage Detect Ready (BVD RDY) bit.
1 BVD WP 0b Bit 1 is used a s the BVD Write Protect (WP) bit.
0 Reserved 0b Bit 0 is reserved in the CardBus Specificat ion.
Networking Silicon — 82559
Datasheet 79
9.1.14.4 LAN Force Event Register
The For ce Event re gi ster simula te s status change e vent s for trouble shooti ng purpose s. This regi ste r
provid es the abilit y to simulate ev ents by f or cing values into the Function Event registe r.
9. 2 Sta tis tic al C oun ters
The 82 559 pro vides in form ation for netw ork manage ment st atis tics by pr ovidi ng on- chi p statis tica l
counters tha t count a variety of events associat ed with both tr ans mit and receive. The counte r s are
updated by the 82559 when it com pletes the process ing of a frame (that is, when it has completed
tr ansmittin g a f r ame on the link or when it has comp leted re ceiving a f r ame). The Statistical
Counters are reported to th e s oftware on demand by iss uing the Dump Stat istical Counters
comman d or Dump and Re set Statis tica l Co unters command i n the SCB Command Uni t Command
(CUC) field.
Table 22. LAN Force Event Register
Bits Function Default Description
31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.
15 INTR 0 This bit is used for interrupts. Writing 1b in this field will set the interrupt
bit in the LAN Function Event register. If the INTA# pin is not masked,
then it will also be activated. Writing 0b ha s no ef fect.
14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification.
4 GWAKE 0 This bit is used for general wake-up. Writing 1b in this field will set the
CSTS CH G bi t in t he LAN F unc tio n E v ent re gist er. If th e CS TSC HG pi n
is not masked, then it will also be activated. Writing 0b has no effect.
3:0 Reserved 0 Bits [3:0] are reserved in the CardBus Specification.
Table 23. 82558 Statistical Counters
ID Counter Description
0 Transmit Good Frames This counter conta ins t he number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory as is do ne f or the Transmit
Command Block status.
4 Transmit Maximu m Collisions
(MA XCOL) Errors This co unte r con tai ns the number of fr ames that were not
transmitted because they encountered the configured
maximum number of collisions.
8 Tra nsmit Late Coll isio ns ( LAT ECOL)
Errors This counter c onta ins t he number of frames that were not
tra ns mi t te d si nc e t hey enc ou n t ere d a colli s ion lat e r than the
confi gured slot time .
12 Transmit Underrun Errors A transmit underrun occurs because the system bus cannot
keep up with the transmission. This counter contains the
number of frames that were either not transmitted or
retransmitted due to a transmit DMA underrun. If the 82559 is
confi gured to retransmit on underrun, this count er may be
updat ed multiple time s for a single frame.
16 Transmi t Lost Carrier Sense (CR S) This counter c ontains the number of frames that were
transmitted by the 82559 despite the fact that it detected the
de-assertion of CRS during the transmission.
20 Trans mit Def er red This cou nte r contai ns the nu mber of frame s th at were def err ed
before transmission due to activity on the link.
82559 — Netwo rking Sili con
80 Datasheet
24 Transmi t Single Col lisions Thi s counter contai ns the number of tran smit ted frames that
encountered one collision.
28 Transmi t Multiple Collisions This counter contai ns the number of t ransmitted frames that
encountered more than one coll ision.
32 Transmi t Total C ollisions This counter cont ains the total number of coll isions that were
encountered while attempting to transmit. This count includes
late c ollisions and fram es that encou nte red MAXCOL.
36 Receiv e G ood Frames This counter contains the number of frames that were
received properly from the link. It is updated only after the
ac tua l recept ion from t he link is compl ete d and all the data
bytes ar e stored in memory.
40 Receive CRC Errors This counter contains the number of aligned frames discarded
because of a CRC error. This counter is updated, if needed,
regardless of the Receive Unit state. The Receive CRC Errors
counter is mutually exclusive of the Receive Alignment Errors
and Receive Short Frame Errors counters.
44 Receiv e Al ignment Errors This coun ter cont ains the number of frames that are both
misaligned (for example, CRS de-asserts on a non-octal
boundary) and contain a CRC error . The counter is updated, if
needed, regardless of the Receive Unit state. The Receive
Alig nment Er rors counter is mutually e x clusi ve of the Receiv e
CRC Errors and Receive Short Frame Errors counters.
48 Receiv e Resource Errors This counter contains the number of good fr ames disc arded
due to unavailability of resources. Frames intended for a host
whose Receive Unit is in the No Resources state fall into this
c ategory. If the 8255 9 is configur ed t o Sa ve Bad Frames and
the st atu s of the rec eived frame indicates tha t it is a bad
frame, the Receive Resource Errors counter is not updated.
52 Receiv e O verrun Er rors This counter contains the number of f ram es known to be lost
because the local system bus was not available. If the traffic
problem persists for more than one frame, the frames that
follow the first are also lost; howeve r, because there is no lost
frame indicator, they are not counted.
56 Receiv e Collision Detect (CDT) Thi s counter contains the n umber of f ram es tha t encountered
c olli s ions during frame recept ion.
60 Receiv e Short Frame Errors This c ounter contains the number of received frames that are
sh orte r th an the mini mum fr am e le ngth. Th e R ec ei ve S ho r t
Frame Errors co unte r is m utua lly exclusive to the Receive
Alignment Errors and Receive CRC Errors counters. A short
frame will always increment only the Receive Sho rt Fr ame
Errors counter.
64 Flow Control Transmit Pause This counter contai ns the number of Flow Control frames
transmitted by the 82559. This count includes both the Xoff
frames transmitted and Xon (PAUSE(0)) frames transmitted.
68 Flow Control R eceiv e Pause This count er co ntai ns the number of Flow Control frames
received by the 82559. This count includes both the Xoff
fram es rec e i ved an d Xon (PAUSE(0) ) f ram es re c eive d.
Table 23. 82558 Statistical Counters
ID Counter Description
Networking Silicon — 82559
Datasheet 81
The Statistical Counters are initially set to zero by the 82559 after reset. They cannot be preset to
anything other than zero. The 82559 incre ments the cou nters by internal ly reading the m,
increment ing them and writ ing them back . Thi s process is invisible to the CPU and PCI bus. In
addition, the counters adhere to the f ollowing rules :
•The counters are wra p-around counters. After reaching FFFFFFFFH the c ounters wrap around
to 0.
•The 82559 updates the required counters for each frame. It is possible for more than one
counter to be updat ed as mu ltiple errors can occur in a sin gle frame.
•The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 8255 9 supports all mandatory and rec ommend statistics functions through the
sta tus of the receive header and d irectly through the se Statistic al Counters.
The CPU can acc es s the counters by i ssuing a Dump Statistical Counters SCB comm and. This
provides a “snapshot”, in main me m ory, of the internal 82559 stat istica l counters. The 82559
supports 21 counters. The du mp could c onsist of the eith er 16, 19, or all 21 counter s, depending on
the status of the Extended Statistics Counters and TCO Statistics configuration bits in the
Configuration command (described in the 82559 Soft ware Developer’s Manual).
9.3 Mode m Control/S tatus Registers
Acce ss to mo dem based memory or I/O ports are mapp ed to a cycle to the modem wit h the lowes t
16 addre sses of the PCI address spa ce mappe d to the addr ess b us of t he mod em, which is co nnected
to FLA[3:0].
9.3.1 Modem Base Memory Addressing
The modem base memory addressin g is an 8-byte address space. The r e are three types of address
spaces:
•Modem chipset address space: 0H to FH
•Modem fun ction address space: 80H to FFH (implemented in 82559)
72 Fl ow Contr ol Receive Unsuppo rted This counter contains t he number of MAC Control frames
received by the 82559 that are not Flow Control Pause frames.
These f ra mes ar e vali d MAC control frame s tha t have t he
predefined MAC control Type v alue and a valid address but
has an un supported op code.
76 Rece ive TCO Frame s This cou nt e r cont a ins th e n umb er of TCO pa c k et s rec ei v ed by
th e 82 55 9.
78 Transmit TCO Frames This counter contains the number of TCO packets transmitted.
Table 23. 82558 Statistical Counters
ID Counter Description
82559 — Netwo rking Sili con
82 Datasheet
•Modem CIS address space: 100H to 1FFH (loaded from EEPROM)
9.3.2 Modem Base I/O Addressing
The modem base I/O addressing is an 8-byte address spac e. Dur ing I/O cycle s, accesses to the
mode m po rt are byte accesses. FLA3 is kept low while FLA[2:0] are mappe d according to the PCI
byt e add ress offs et.
9. 3.3 Modem Car d Bus CST CHG Regist er s
The modem CardBus CSTCH G registers are used in CardBus mode only. There are four event
r ela ted registers. The CardBus software us es the regis ters to det ermine which event has occurre d
and manage the e ven t and to control the CSTSCHG signal. The 82559 supports on ly the interrupt
and general wa ke-up event bits in the CSTSCHG registers . These register s com pliment the PCI
Po wer Man agement regis ters for the use wit h non- ACPI compli ant OS . It is initi aliz ed by power -up
re set dr iven o n the ALTRS T# p i n .
9.3.3.1 Modem Function Event Register
The Modem F unction Ev ent regi ster speci fies the event that c h anged its st atus. I t is identical to the
Eth ernet Funct ion Eve nt regis ter desc ribed in Secti on 9.1.14. 1, “LAN Function Event Register” on
page 77.
Byte Offset Register Description
0H: 7H Modem controll er mimic port, ISA address spac e 0: 7
0H:3FH Modem chipset address space (external modem ports)
8H:FH Mod em controller Resource Management Port (RMP), ISA
address space 8:15
10H:3FH General purpose address space
80H:83H Modem Control Register: Reset[0], Ce ntral Site M ode[1]
E0H:E3H Reserved
F0H :F 3H Modem Function Event Register
F4H :F7H Modem Function Mask Register
F8H:FBH Modem Fun c tio n Present Reg ister
FCH:FFH Modem Force Function Event Register
100H:1FFH CIS Area (loaded from the EEPROM)
Byte Offset Register Description
0H:7H Ven us MIMIC po rt, ISA address sp ace 0:7
Networking Silicon — 82559
Datasheet 83
9.3.3.2 Modem Function Event Mask R egister
The Modem Function Event Mask regist er masks CSTSCHG and INTA# assertion as sh own in
Table 24 below.
9.3.3.3 Modem Function Present State Register
The Modem Function Present State regi st er specifies the current state of an event’s sources as
shown in Table 25 below.
Table 24. Modem Function Event Ma sk Register
Bits Function Default Description
31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.
15 INTR 0b
This bit is the interrupt mask. When this bit equals 0b, it masks the
modem function IN TA# line but ha s no ef fect on the Mode m Function
Ev ent register. The modem function can assert the INTA# signal only
when both fields are enabled: the interrupt bit and the modem control
bit in the System Control Bloc k (SCB) registe r w ith in t he CSR space.
The interrupt mask bit affects the INT A# masking only after the OS has
set this register . Thus, on legacy systems that do not access the status
change registers, the modem INTA# signal is not mas ked by the
interrupt.
14 WKUP 0b This bit is the wake-up mask. When this bit equals 0b, it masks the
modem function CSTSCHG signal but has no effect on the Function
Ev ent register. This bit is dependent on bit 4 of this register.
13:7 Reserved 0 Bits [13:7] are reserved in the CardBus Specification.
6:5 PWM
BAM 0These bits are used for Pulse Width Modulation Binary Audio Enable.
(PWM BAM).
4 GWAKE 0b
This bit is the general wake-up mask. When this bit equals 0b, it masks
the mode m function wak e-up events towards th e CSTSCHG signal. It
has no ef fect on the Modem Funct ion Event r egister. The 82559 can
assert the CSTSCHG signal in the following configuration of masked
bit s : wa ke-u p bit AND ge ne r al wake- u p bi t, or P ME Enable bit in t he
PMC SR register only.
3 Reserved 0b Bit 3 is reserved in the CardBus Specification.
2 BVD RDY 0b Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
1 BVD WP 0b Bit 1 is used as the BVD Write Protect (WP) bit.
0 Reserved 0b Bit 0 is reserved in the CardBus Specification.
Table 25. Modem Fun ction Presen t State Register
Bits Function Default Description
31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification.
15 INTR 0 This bit is used f or interrupts. It reflects the current state of the Modem
Interrupt (MINT) input pin from the modem.
14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification.
4 GWAKE 0 This bi t is us ed f or gene r a l wa k e-u p . It r efl ec ts th e cu rre nt invers e st at e
of the Modem Ring (MRING#) input pin from the modem.
3 Reserved 0b Bit 3 is reserved in the CardBus Specification.
82559 — Netwo rking Sili con
84 Datasheet
9.3.3.4 M o d em F orce Event Re g i ster
The Modem Force Event register simulate s status change ev ents for troubleshooting purposes. It is
identical to the Ethernet Force Event register described in Section 9.1.14.4, “LAN Force Event
Register” on page 79.
2 BVD RDY 0b Bit 2 is used as the Batter Voltage Detect (BVD RDY) bit.
1 BVD WP 0b Bit 1 is used a s the BVD Write Protect (WP) bit.
0 Reserved 0b Bit 0 is reserved in the CardBus Specificat ion.
Table 25. Modem Function Present State Register
Bits Function Default Description
Networking Silicon — 82559
Datasheet 85
10.0 PHY Unit Registers
The 82559 provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms menti oned in the registers are defin ed as follo w s :
SC: Self cleared.
RO : Re ad only.
E: EEPROM setting affects content.
LL: Latch low.
LH: Latch high.
10.1 MDI Registers 0 - 7
10.1.1 Register 0: Control Register Bit Definitions
Bit(s) Name Description Default R/W
15 Reset This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
ac cepts a read or wri te transaction.
1 = PHY Reset
0RW
SC
14 Loopbac k This bit enables loopback of transmit dat a nibbles from
the TXD[3:0] signals to the receive data path. The PHY
unit’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
No t e als o t h at t he l oop bac k c onfi g ura ti o n b it t ak e s pri orit y
ov er the Loopback MDI bit.
1 = Loopba ck enabled
0 = Loopback disabled (Normal opera tion)
0RW
13 Speed Selection This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disab led.
1 = 100 Mbps
0 = 10 Mbps
1RW
12 Auto-Negotiation
Enable This bit enables Auto-Negoti ation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Au to-Negotiation i s enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
1RW
11 Power-Down This bit sets the PHY unit into a low power mode. In low
power mode, the PHY unit consumes no more than 30
mA.
1 = Power-Down enabled
0 = Power-Down disabled (Normal oper ation)
0RW
10 Reserved This bit is reserved and should be set to 0b. 0 RW
82559 — Netwo rking Sili con
86 Datasheet
10.1.2 Register 1: Status Register Bit Definitions
9 Res ta r t Auto-
Negotiation This bit rest arts the Auto-Negotiation process and is s elf-
clearing.
1 = Restart Auto-Negotiation process
0RW
SC
8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation
is disabled. If the PHY reports that it is only able to
opera te in one duplex mode, the value of th is bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit,
bit 8.
1 = Full Duplex
0 = Half Duplex
0RW
7 Collision Test This bit will force a collision in response to the assertion
of the transmit enabl e signal.
1 = Force COL
0 = Do not force COL
0RW
6:0 Reserved These bits are reserved and should be set to 0000000b. 0 RW
Bit(s) Name Description Default R/W
15 Reserved This bit is reserved and should be set to 0b. 0 RO
E
14 100BASE-TX Full
Duplex 1 = PHY able to perform full duple x 100BASE-TX 1 RO
13 100 Mbps Ha lf
Duplex 1 = PHY able to perform half duplex 100BASE-TX 1 R O
12 10 Mbps Ful l
Duplex 1 = PHY able to operate at 10Mb ps in full duplex
mode 1RO
11 10 Mbps Half
Duplex 1 = PHY able t o operate at 10 Mbp s in half duplex
mode 1RO
10:7 Reserved These bits are reserved and should be set to 0000b. 0 RO
6 Management
F ra mes Pr eamble
Suppression
0 = PHY will not accept management frames with
p rea m bl e su pp r es s ed 0RO
5 Auto-Negotiation
Complete 1 = Auto-Negotiatio n proc ess completed
0 = Auto-Negotiation process has not completed 0RO
4 Remote Fault 0 = No remote fa ult c ondition de tected 0 RO
3 Auto-Negotiation
Ability 1 = PHY is able to perform Auto-Negotiation 1 R O
2 Link Status 1 = Valid link has been established
0 = Invali d lin k dete cted 0RO
LL
1 Jabber Detect 1 = Jabber condition detected
0 = No jabber condition detected 0RO
LH
0 Extended
Capability 1 = Extend ed register capabilities en abled 1 RO
Bit(s) Name Description Default R/W
Networking Silicon — 82559
Datasheet 87
10.1.3 Register 2: PHY Identifier Register Bit Definitions
10.1.4 Register 3: PHY Identifier Register Bit Definitions
10.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions
10.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit
Definitions
Bit(s) Name Description Default R/W
15:0 PHY ID (high
byte) Value: 02A8H -- RO
Bit(s) Name Description Default R/W
15:0 PHY ID (low byte) Value: 0154H -- RO
Bit(s) Name Description Default R/W
15 Next Page Constant 0 = Transmitting primary capability data
page 0RO
14 Reserved This bit i s reserved and should be set to 0b. 0 RO
13 Remote Fault 1 = Indicate link partner’s rem o te faul t
0 = No remote fault 0RW
12:5 Technology Ability
Field Technology Ability Field is an 8-bit field containing
information indicating supported technologies specific
to the selector field value.
00101111 RW
4: 0 Sele ct or Fie ld The S ele ct or Fi el d is a 5-b it fi el d id en tif yi ng the t ype o f
mes s age to be sent via Auto-Negot iation. This field is
read on ly in the 82559 and cont ains a v alue of
00001b, IEEE Standar d 802.3.
00001 RO
Bit(s) Name Description Default R/W
15 Ne xt Page This bit reflects the PHY’s link partner’s Auto-
Negotiati on ability. -- RO
14 Acknowledge This bit is used to indicate that the 82559’s PHY un it
has successfull y received its link partner’s Aut o-
Negotiati on adv ertis ing ability.
-- RO
13 Remote Fault This bit reflects the PHY’s link partner’s Aut o-
Negotiati on ability. -- RO
12:5 Technology Ability
Field This bi t refle c ts the PH Y’s link partner’s Auto-
Negotiati on ability. -- RO
4:0 Selector Field This bit reflects the PHY’s link partner’s Auto-
Negotiati on ability. -- RO
82559 — Netwo rking Sili con
88 Datasheet
10.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
10.2 MDI Registers 8 - 15
Regist ers eight through fifteen are reserved for IEEE.
10.3 MDI Register 16 - 31
10.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions
Bit(s) Name Description Default R/W
15:5 Reserved These bits are reserved and should be set to 0b. 0 RO
4 P ar al le l De te cti on
Fault 1 = Fault dete cted via parallel det ection (multiple lin k
fault occurred)
0 = No fault detected via parallel detection
This bit will self-clear on read
0RO
SC
LH
3Link Partner Next
page Ab le 1 = Link Partner is Next Page able
0 = Link Partner is not Next Page able 0RO
2 Next Page Able 1 = Loca l drive is Next Page able
0 = Local drive is not Next Page able 0RO
1 Page Received 1 = New Page received
0 = New Page not receiv ed
This bit will self-clear on read.
0RO
SC
LH
0 Link Partner Auto-
Negotiat ion A ble 1 = Link Partner is Auto-Negotiati on able
0 = Link Partner is not Auto-Negotiation able 0RO
Bit(s) Name Description Default R/W
15:14 Reserve d These bits are reserved and should be set to 00b 00 RW
13 Carrier Sense
Disconnect
Control
This bit enables the disconnect function.
1 = Disconnect function enabled
0 = Disconnect function disabled
0RW
12 Transmit Flow
Co ntrol D is abl e This bit enables Transmit Flow Control
1 = Transmit Flow Control enabled
0 = Transmit Flow Control disabled
0RW
11 Receive De-
Serializer In-Sync
Indication
This bit indicates status of the 100B ASE-TX Receive
De-Serializer In-Sync. -- RO
10 100BASE-TX
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = P ower-Down
0 = Normal operat ion
1RO
Networking Silicon — 82559
Datasheet 89
10.3.2 Register 17: PHY Unit Special Control Bit Definitions
9 10BASE-T
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = P ower-Down
0 = Nor m al operation
1RO
8 Polarity This bit indicates 10BASE-T polarity.
1 = Reverse polarity
0 = Nor m al pola rity
-- RO
7:2 Reserved These bits are reserved and should be set to 0B. 000000 RO
1 Speed This bit indicates the Auto-Negotiation result.
1 = 100 Mbps
0 = 10 Mbps
-- RO
0 Duplex Mode This bit indicates the Auto-Negotiation result.
1 = Full Duplex
0 = Half Duplex
-- RO
Bit(s) Name Description Default R/W
15 Scrambler By-
pass 1 = By-pass Scrambler
0 = Nor m al operations 0RW
14 By-pass 4B/5B 1 = 4 bit to 5 bit by-pass
0 = Nor m al operation 0RW
13 Force Tran smit H-
Pattern 1 = Force transmit H-pattern
0 = Nor m al operation 0RW
12 Force 34 T ransmit
Pattern 1 = F orce 34 transmit pa tte rn
0 = Nor m al operation 0RW
11 Good Link 1 = 100BASE-TX link good
0 = Nor m al operation 0RW
10 Reserved This bit i s reserved and should be set to 0b. 0 RW
9 Transmit Carrier
Sense Disable 1 = Transmit Carrier Sense disabled
0 = Transmit Carrier Sense enabled 0RW
8 Disable Dynamic
Power-Down 1 = Dynamic P ower-Down disabled
0 = Dynamic Power-Down enabled (normal) 0RW
7 Auto-Negotiation
Loopback 1 = Aut o-Negotiation loop back
0 = Auto-Nego tiation no rmal mode 0RW
6 MDI Tri-State 1 = MDI Tri-state (transmit driver tri-states)
0 = Nor m al operation 0RW
5 Filter By-pass 1 = By-pass filter
0 = Normal filter operation 0RW
4Auto Polarity
Disable 1 = Auto Polarity disabled
0 = Nor m al pola rity oper ation 0RW
3 Squelch Disable 1 = 10BASE-T squelch test disable
0 = Nor m al squelch operation 0RW
Bit(s) Name Description Default R/W
82559 — Netwo rking Sili con
90 Datasheet
10.3.3 Register 18: PHY Address Register
10.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
10 .3.5 Re gister 20 : 100B ASE-T X Receive D iscon nect Coun ter Bit D efiniti ons
10.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
2 Extended
Squelch 1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled 0RW
1 Link Integrity
Disable 1 = Link disabled
0 = Normal Link Int egrity operation 0RW
0 Jabber Function
Disable 1 = Jabber di sable d
0 = Normal Jabber operation 0RW
Bit(s) Name Description Default R/W
15:5 Reserved These bits are reserved and should be set to a
constant ‘0’0RO
4:0 PH Y Address These bits are set to t he PHY’s address, 00001b. 1 RO
Bit(s) Name Description Default R/W
15:0 Rec eive False
Carrier These bits are used for the false carrier counter. -- RO
SC
Bit(s) Name Description Default R/W
15:0 Disconnect Event This field contains a 16-bit counter that increments for
each disconnect ev ent . The counter freezes wh en fu ll
and self -cl ear s on read
-- RO
SC
Bit(s) Name Description Default R/W
15:0 Receive Error
Frame This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a sy mb ol er ror or prema ture end of f ram e) in that
frame. The counter freezes when full and self-clears
on read .
-- RO
SC
Bit(s) Name Description Default R/W
Networking Silicon — 82559
Datasheet 91
10.3.7 Register 22: Receive Symbol Error Counter Bit Definitions
10.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions
10.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit
Definitions
10.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Definitions
10.3.11 Register 26: Equalizer Control and Status Bit Definitions
Bit(s) Name Description Default R/W
15:0 Symbol Error
Counter This field contains a 16-bit counter that increments for
eac h symbol error. The counter freezes when ful l and
se lf- c le ar s on rea d.
In a fra me wit h a ba d sy mbo l, ea ch se qu ent ia l si x bad
symbols count as one.
-- RO
SC
Bit(s) Name Description Default R/W
15:0 Premature End of
Frame This field contains a 16-bit counter that increments for
eac h pre mature end of frame event. The count er
freezes when full and se lf-c lears on read.
-- RO
SC
Bit(s) Name Description Default R/W
15:0 End of Frame
Counter Thi s is a 16-bi t co unter th at inc r e m en ts for eac h end
of frame error event. The counter freezes when full
and self -cl ears on re ad.
-- RO
SC
Bit(s) Name Description Default R/W
15: 0 Ja bb er Det e c t
Counter Thi s is a 16-bi t co unter th at inc r e m en ts for eac h
jabber detection event. The counter freezes when full
and self -cl ears on re ad.
-- RO
SC
Bit(s) Name Description Default R/W
15:0 RFU Reserved for Future Use -- RW
82559 — Netwo rking Sili con
92 Datasheet
10.3.12 Register 27: PHY Unit Special Control Bit Definitions
Bit(s) Name Description Default R/W
15:3 Reserved These bits are reserved and should be set to 0b. 0 RW
2:0 LED Switch
Control Value
000
001
010
011
100
101
110
111
ACTLED
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED
Link
Collision
Link
Collision
Off
On
Off
On
000 RW
Networking Silicon — 82559
Datasheet 93
11.0 82559 Test Port Functi onality
11.1 Introduction
The 8255 9’s NAND T ree Test Access Port (TAP) is the access point f or tes t data to and from the
device. The port provides the ability to per f orm bas ic production leve l testing. The port pro vides
tw o functio ns:
•The synchronous IC validation mode is used in the production of the device. This mode gives
the s ignals the ir names (for ex ample, Testabilit y Port Clock [TCK]).
•The 82559 al so support s asynchronous testing modes. These test modes s upport the validation
of connections at the board leve l.
11.2 Asynchronous Test Mode
F our as ynchrono us tes t m odes are support ed for s ystem level design use. The modes are s elected
through the use of the test port input pin in static combi nation s. The test port pins are Test Port
(TEST), Test Port Data Input (TI), Test Port Execute Enable (TEXEC) and Test Port Clock (TCK).
During normal operati on the TES T pin must be pulled down t hrough a r es is tor (pulling T EST high
enabl es the test mode ). All other port inputs may ha ve a pull-do w n at the designers discret ion.
11.3 Test Function Description
The 82559 TAP mo de supports sev eral tests tha t can be used in board le v el desi gn. These te sts hel p
verify basic functi onalit y as well as test the inte grity of solder connec tion on the board. The tests
ar e described in the follow ing subsect ions.
11.3.1 Tristate
The tris tate command s ets all 82559 input and output pins into a tristate (high-Z) mo de (all int ernal
pull-ups and pull-do wns are disabled). This mode is ent ered b y setti ng the following test pin
combination and resetting the de vic e:
TE ST = 1 TEX EC = 0
TCK = 0 TI = 1
11.3.2 NAND Tree
The NAND Tree test mode is the most useful of the asynchronous test modes. I t ena bles the
placement of the 82559 to be validated at board test. The NAND Tree was chosen for its speed
advantages. Modern au tomated tes t equipmen t ca n perform a complete periphera l sc an without
support at the board level. This command connects all outputs of the input buffers in the device
periphery in to a NAND Tree scheme. All the output driv ers of the output buffers, except the Te st
Port Data Output (TO) pin, are put into hi gh-Z mode. These pins are driven to affect the output of
the tree. There are two separate chains and associated outputs for speed. Any hard strapped pins
will prevent the tester from sca nning correctly. This mode is entered b y placing the te st pins in the
following combination:
82559 — Netwo rking Sili con
94 Datasheet
TEST = 1 TEXEC = 1
TCK = 0 TI = 1
The r e are two NAND Tree chains with t wo separate outputs assigned to FLOE# (Ch ain 1) and
FLWE# (Chain 2).
Table 26. NAND Tree Chains
Cha in Order
(NAND Tree Output) Chain 1
(FLOE#) Cha in 2
(FLWE#)
1 RST# LILED
2 IDSEL ACTLED#
3 REQ# SPEEDLED
4 AD23 SMBALRT#
5 SERR# SMBCLK
6AD22SMBD
7AD21ISOLATE#
8 AD20 ALTRST#
9 AD19 CLKRUN#
10 AD18 AD31
11 AD17 AD30
12 C/BE2# AD29
13 FRAME# AD28
14 IRDY# AD27
15 TRDY# PME#
16 CLK CSTSCHG
17 DEVSEL# AD26
18 INTA# AD25
19 STOP# C/BE3#
20 GNT# AD24
21 PERR# FLD0
22 PAR FLD1
23 AD16 FLD2
24 C/BE1# FLD3
25 AD15 FLD4
26 AD14 FLD5
27 AD13 FLD6
28 AD12 FLD7
29 AD11 FLA0
30 AD10 FLA1
31 AD9 FLA2
32 AD8 FLA3
33 C/BE0# FLA4
Networking Silicon — 82559
Datasheet 95
34 AD7 FLA5
35 AD6 FLA6
36 AD5 FLA7
37 AD4 FLA8
37 AD3 FLA9
39 AD2 FLA10
40 AD1 FLA11
41 AD0 FLA12
42 EECS FLA13/EEDI
43 FLA14/EEDO
44 FLA15/EESK
45 FLA16
46 FLCS#
47 CFCLK
48 CFCS#
Table 26. NAND Tree Chains
Chain Order
(NAND Tree Output) Chain 1
(FLOE#) Chain 2
(FLWE#)
82559 — Netwo rking Sili con
96 Datasheet
Note: Thi s pag e left intenti onally bl ank.
Networking Silicon — 82559
Datasheet 97
12.0 Electrical and Timing Specificatio ns
12 .1 Abso lu te Ma ximum Rating s
Maximum ratings are listed below:
Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C
Sto r age Temper ature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 140 C
Outputs and Supply Voltages (except PCI and SMB) . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.0 V
PCI and SMB Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 5.25 V
Transmit Data Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 8.0 V
Input Voltages (except PCI and SMB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 V to 5.0 V
PCI and SMB Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V 6.0 V
Stresses abo ve the lis ted absolute maximum ratings may cau se permanent damage to the 82559
device. This is a stres s ra ting only and functio nal operations of the device at thes e or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolu te maximu m rat ing condit ions for ext ended peri ods may af fe ct de vice relia bilit y.
12.2 DC Specifications
NOTES:
1. VIO should be 5 V ± 5% in a ny PCI environment (ei the r 5 V or 3.3 V signaling). In CardBus, VIO must be
identical to VCC.
2. Typical current consumption is in nominal operating conditions (VCC = 3.3 V) and average l ink activity.
Maximu m current co nsumption is in ma ximu m VCC and maximum link activity.
The 82559 supports both the PCI and CardBus interface standards. In the PCI mode, the 82559 is
f iv e vo lts tolera nt and supports both 5 V an d 3.3 V signaling environments.
Table 27. General DC Specificati ons
Symbol Parameter Condition Min Typical Max Units Notes
VCC Supply Vo ltage 3.0 3.3 3.5 V
VIO Periphery Clamp
Voltage PCI 4.75 5.0 5.25 V 1
CardBus 3.0 3.3 3.6 V 1
ICC Power Supply 125 195 mA 2
Table 28. PCI/CardBus Interface DC Specifications
Symbol Parameter Condition Min Max Units Notes
VIHP Input High Voltage 0.475VCC VIO + 0.5 V
VILP Input Low V o ltage -0.5 0.325VCC V
VIPUP Input Pull-up Voltage 0.7VCC V1
VIPDP Input Pull-down Voltage 0.2VCC V1
IILP Inp ut Lea kage Current 0 < Vin < VCC ±10 µA2
82559 — Netwo rking Sili con
98 Datasheet
NOTES:
1. These values are only applicable in 3.3 V signaling environments (PCI or CardBus). Outside of this limit the
input buffer must consume its minimum current.
2. Input leak age curr ents include high-Z ou tput leakage for all bi directional b uffer s with tristate ou tputs.
3. Si gnals without pull-up resis tors have 3 mA low output current; and sign als r equi ring pull-up resi stors, 6 mA.
The si gnals requiri ng pul l-up resist ors include: FRAME#, TRDY#, IRDY #, DEVSEL#, STOP#, SERR# and
PERR#.
4. This value is characterized but not tested.
NOTE: SMB outputs (SMBALRT#, SMBD, and SMBCLK) are open drain.
NOTE:
1. This value is characterized but not tested.
VOHP Output High Vol tage Iout = -2 mA
Iout = -500 µA
Iout = -150 µA
2.4
0.9VCC
0.9VCC
V
V
V
PCI
CardBus
VOLP Ou tput Low Volta ge Iout = 3 mA , 6 mA
Iout = 1500 µA
Iout = 700 µA
0.55
0.1VCC
0.1VCC
V
V
V
3, PCI
CardBus
CINP Input Pin Capacitance 10 pF 4
CCLKP CLK Pin Capacitance 5 12 pF 4
CIDSEL IDSEL Pin Capacitance 8 pF 4
LPINP Pin Inductance 12 nH 4
Table 28. PCI/Card Bus Interface DC Specifica tions
Table 29. SMB Interface DC Sp ecifications
Symbol Parameter Condition Min Max Units Notes
VIHS Input High Voltage 1.4 VIO + 0.5 V
VILS Input Low Voltage -0.5 0.6 V
IILS I nput Low Leakag e
Current 0 < Vin < VCC ±1.0 µA
VOLS Ou tput Low Volta ge IPULLUP = 100 µA0.4V
Tab le 30. Flash/Mo de m/EEPROM Interface DC Speci fications
Symbol Parameter Condition Min Max Units Notes
VIHL Input High Voltage 2.0 VCC + 0.5 V
VILL Input Low Voltage -0.5 0.8 V
IILL I nput Low Leakag e
Current 0 < Vin < VCC ±20 µA
VOHL Output High Vol tage Iout = -1 m A 2.4 V
VOLL Ou tput Low Volta ge Iout = 2mA 0.4 V
CINL Input Pin Capacitance 10 pF 1
Networking Silicon — 82559
Datasheet 99
NOTES:
1. Current is mea s ure d on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
the load resistance value.
Table 31. LED Voltage/Curren t Characteri stics
Symbol Parameter Condition Min Typical Max Units Notes
VOHLED Output High Voltage Iout = -10 mA 2.4 V
VOLLED Output Low Voltage Iout = 10 mA 0.7 V
Table 32. 100BASE-TX Voltage/Current Char acteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID100 Input Differential
Impedance DC 10 KΩ
VIDA100 Input Differential
Accept Peak Voltage ±500 mV
VIDR100 Input Differential
Reject Peak Voltage ±100 mV
VICM100 Input Common Mode
Voltage VCC/2 V
VOD100 Output Differential
Peak Voltage 0.95 1.00 1.05 V
ICCT100 Line Dri ver Sup ply
Peak Current RBIAS100 = 619 Ω20 mA 1
Figure 29. RBIAS100 Resistance Versus Transmitter Current
Rbias100
585 0hm
619 Ohm
650 Ohm
Icct100
19mA 20 mA 21mA
82559 — Netwo rking Sili con
100 Datasheet
NOTES:
1. Current is measured on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is a ttained by divi ding the measu red maximum d iffer ent ial o utpu t peak voltage by
the lo ad resist ance value .
Table 33. 10BASE-T Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID10 Input Differential
Impedance 10 MHz 10 KΩ
VIDA10 Input Differential
Accept Peak Voltage 5 MHz ≤ f ≤ 10
MHz ±585 ±3100 mV
VIDR10 Input Diff erential
Reject Peak Voltage 5 MHz ≤ f ≤ 10
MHz ±300 mV
VICM10 Input Common Mode
Voltage VCC/2 V
VOD10 Output Differ ent ial
Peak Voltage RL = 100 Ω2.2 2.8 V
ICCT10 Line Driver Supply
Peak Current RBI AS10 = 549 Ω48 mA 1
Figure 30. RBIAS10 Resistance Versus Tran smitter Current
Rbias10
621.5 0hm
549 Ohm
576 Ohm
Icct10
19mA 20 mA 21mA
Networking Silicon — 82559
Datasheet 101
12.3 AC Spec ifications
NOTES:
1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain
outputs.
2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point).
Equation s defi ning these maximums (A and B) ar e provided. To fa cilitate component testing, a max imum
current test point is defined for each side of the output driver.
3. This parameter is also applic able to Car dBus environment.
Table 34. AC Specifications for PCI Signaling
Symbol Parameter Condition Min Max Units Notes
IOH(AC)
Switching
Current High
0 < Vout ≤ 1.4 -44 mA 1
1. 4 < Vout < 0.9VCC -17.1(VCC - Vout)mA1
0.7VCC < Vout < VCC Eqn A mA 2
(Test Point) Vout = 0.7VCC -32VCC mA 2
IOL(AC)
Switching
Cur re nt Low
Vout ≥ 2.2 95 mA 1
2. 2 > Vout > 0.1VCC Vout/0.023 mA 1
0.18VCC > Vout > 0 Eq n B mA 2
(Test Point) Vout = 0.18VCC 38VCC mA 2
ICL Low Clamp
Current -3 < Vin ≤ -1 -25 + (Vin + 1)/
0.015 mA 3
ICH High Clamp
Current VCC +4 > Vin ≥ VCC
+1 25 + (Vin-VCC-1)/
0.015 mA 3
slewRP PCI Output Rise
Slew Rate 0.4 V to 2.4 V 1 4 V/ns
slewFP PCI Output Fall
Slew Rate 2.4 V to 0.4 V 1 4 V/ns
Equa tion A. IOH = (98/VCC)*(Vout - VCC)*(Vout + 0.4VCC), for VCC > Vout > 0.7VCC
Equation B. IOL = (256/VCC)*(Vout)*(VCC - V out), for 0 < Vout < 0.1 8VCC
Table 35. AC Specifications for CardBus Sign aling
Symbol Parameter Condition Min Max Units Notes
tRP CardBus Output
Rise Time 0.2VCC to 0.6VCC 0.25 1.0 V/ns
tFP CardBus Output
Fall Time 0.6VCC to 0.2VCC 0.25 1.0 V/ns
Table 36. AC Specifications for Local Bus Signaling
Symbol Parameter Condition Min Max Units Notes
IOH Current Output High 1 mA
IOL Current Output Low 2 mA
82559 — Netwo rking Sili con
102 Datasheet
12.4 Timing Specifications
12.4.1 Clocks Specifications
12.4.1.1 PCI/CardBus Clock Specifications
The 82559 uses the PCI Clock signal directly. Figure 31 shows the clock waveform and requi red
me asurement poi nts for the PCI Clock signal . Table 37 summarizes the PCI Clock specifications.
NOTES:
1. The 82559 will work with a ny PCI clock frequency up to 33 MH z.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the
minimum peak-to-peak portion of the clock waveform as shown in Fi gu re 31.
12.4.1.2 X1 Specifications
X1 serves as a signal input from an external crystal or oscillator. Table 38 defines the 82559
r equirements from t his signal.
Figure 31. PCI/CardBus Clock Waveform
0.6VCC
0.475VCC
0.4VCC
0.325VCC
0.2VCC
0.4VCC p-to-p
(minimum)
T_high T_low
T_cyc
Table 37. PCI/Card Bus Clock Specifications
Symbol Parameter Min Max Units Notes
T1 Tcyc C LK Cycle Time 30 ns 1
T2 Thigh C LK High Tim e 11 ns
T3 Tlow C LK Low Tim e 11 n s
T4 Tslew CLK Slew Rate 1 4 V/ns 2
Table 38. X1 Clock Specifications
Symbol Parameter Min Typical Max Units Notes
T8 Tx1_dc X1 Duty Cycle 40% 60%
T9 Tx1_pr X1 Period 40 ns ±50PPM
Networking Silicon — 82559
Datasheet 103
12.4.2 Timing Parameters
12.4.2.1 Me asurement and Test Conditions
Figure 32, Figure 33, an d Table 3 9 define the conditions under which timing measurements are
don e. The component test g uar ante es that all ti mings are met with minimum clock slew ra te
(slowes t edge) and voltage swing. Th e design must guarantee that minimum tim ings are also met
with maximum clock slew rate (fast es t edge) and voltage swing. In addit ion, the design m us t
guarantee prope r input oper ation for input voltage swings and slew rates that e xceed the spec ified
test conditions.
Figure 32. Output Timing Measurement Conditions
T_off
T_on
T_val
V_step
V_test V_test
V_test
V_th
V_tl
CLK
OUTPUT
DELAY
Tri-State
OUTPUT
Figure 33. I nput Tim ing Measur ement Con ditions
CLK
INPUT
V_test V_test
V_test
V_th
V_tl
V_th
V_tl
T_h
T_su
inputs
valid V_max
Table 39. Measur e and Test Con dition Para m eters
Symbol PCI Level Car dBus Level Units Notes
Vth 0.6VCC 0.6VCC V
Vtl 0.2VCC 0.2VCC V
82559 — Netwo rking Sili con
104 Datasheet
NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the ma ximum peak-to-peak waveform allowe d
for testing input timing.
12.4.2.2 PCI/CardBus Timings
NOTES:
1. Timing measurement conditions are illustrated in Fi gu r e 32 .
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
4.2.3.2.
3. CardBus minimum times are specified with a 0 pF equivalent load. Maximum times are specified with a 30 pF
equivalent load. Actual test loads may vary but must be correlated to these loads.
4. n a P CI envi ronm ent, REQ# and GNT# are point- to-point signals and have differ ent outp ut valid delay times
an d inp ut set u p tim es than bus sed si gnal s. All other signals are buss ed.
5. Timing measurement conditions are illustrated in Fi gu r e 33 .
6. RST# is asserted and de-asserted asyn chronously with respect to the C LK signal.
7. Al l PCI a nd CardBus in terface output driv er s are floa ted when RS T# is active.
Vtest 0.4VCC 0.4VCC V
Vstep (risi ng edge) 0.285VCC 0.325VCC VMin Delay
0.475VCC VMax Delay
Vstep (fal ling edge) 0.61 5VCC 0.475VCC VMin Delay
0.325VCC VMax Delay
Vmax 0.4VCC 0.4VCC V
Input Signal Edge
Rate 11V/ns
Table 39. Measure and Test Condition Parameters
Tabl e 4 0. PCI / C ardB us Ti m i ng Param e te rs
Symbol Parameter Min Max Units Notes
T14 tval PCI CLK to S ignal Vali d Delay 2 11 ns 1, 2, 4
CardBus CLK to Signal Valid Dela y 2 18 ns 1, 3
T15 tval(ptp) PCI CLK to Sig n al Valid Del ay (point-
to-point) 2 12 ns 1, 2, 4
T16 ton Float to Active Delay 2 ns 1
T17 toff Active to Float Delay 28 ns 1
T18 tsu Input Setup Time to CLK 7 ns 4, 5
T19 tsu(ptp) PCI Input Setup Time to CLK (point-to-
point) 10 ns 4, 5
T20 thInput Hold Time from CLK 0 n s 6
T21 trst Reset Active Time After Po wer Stable 1 ms 6
T22 Trst-clk
PCI Reset Activ e Time After CLK
Stable 100 µs6
CardBus Reset Active Time After CLK
Stable 100 clocks 6
T23 Trst-off Reset Active to Output Float Delay 4 0 ns 6, 7
Networking Silicon — 82559
Datasheet 105
12.4.2.3 Flash/Modem Interface Timings
The 8255 9 is designed to support up to 150 nan oseconds of Fl ash access ti me. The VPP signal in
the F lash implementation should be connect ed permanen tly to 12 V. Thus , writing to the Flash is
controlled only by the FLWE# pin.
Table 41 provi des the timin g par ameters fo r th e Flas h i nterfac e signals. The timing parameters ar e
illust r ated in Figure 34 and Figure 35.
Modem is supported t hrough the Flash i nterf ace when the following conditions appl y:
•FLA[6:0], FLD[7:0], FLCS#, FLOE#, and FLWE# have the same funct ions for F lash and
modem.
•FLA[8] acts as IOCHRDY asynchronous input in modem mode.
Table 41. Flash Timing Parameters
Symbol Parameter Min Max Units Notes
T35 tflrwc Flash Read/Write Cycle Time 150 ns 1, Flash tAVAV
= 150 ns
T36 tflacc F LA to Rea d FLD Setup Tim e 15 0 ns 1, Flash tAVQV
= 150 ns
T37 tflce FLCS# to Read FLD Setup Time 150 ns 1, Flash tELQV
= 150 ns
T38 tfloe FLOE # Ac tive to Read FLD Setup Time 120 ns 1, Flash tGLQV
= 55 ns
T39 tfldf FLOE# Inactive to FLD Driven Delay
Time 50 ns 1, Flash tGHQZ
= 35 ns
T40 tflas FLA Setup Time before FLWE# 5 ns 2, Flash tAVWL
= 0 ns
T41 tflah FLA Hold Time after FLWE# 200 ns 2, Flash tWLAX
= 60 ns
T42 tflcs FLCS# Hold Time before FLWE# 30 ns 2, Flash tELWL
= 20 ns
T43 tflch FLCS# Hold Time after FLWE# 30 ns 2, Flash tWHEH
= 0 ns
T44 tflds FLD Setup Tim e 150 ns 2, Flash tDVWH
= 50 ns
T45 tfldh FLD Hold Time 10 ns 2, Flash tWHDX
= 10 ns
T46 tflwp Write Pul s e Width 120 ns 2, F lash tWLWH
= 60 ns
T47 tflwph Write Pulse Width H igh 25 ns 2, Flash tWHWL
= 20 ns
T48 tMioha IOCHRDY Hold Time after FLWE# or
FL OE# Active 25 ns
T49 tMiohi IOCHRDY Hold Time after FLWE# or
FLOE# Inactive 0ns
82559 — Netwo rking Sili con
106 Datasheet
NOTES:
1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150
timings.
2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150
timings.
Figure 34. Flash/Mo dem Tim ings for a Read Cy cle
FLADDR
FLCS#
FLOE#
FLDATA-R
IOCHRDY
Address Stable
Data In
T35
T37
T38 T39
T48T49
T36
Figure 35. Flash/Mo dem Ti mings for a Write Cycle
FLADDR
FLCS#
FLWE#
FLDATA-W
IOCHRDY
Address Stable
Data Out
T35
T40 T41
T42 T46 T43
T47 T44 T45
T48T49
Networking Silicon — 82559
Datasheet 107
12.4.2.4 EEP ROM Interface Timings
The 8255 9 is des igned to support a standard 64x16 or 256x16 ser ial EEPR OM. Table 42 provides
th e timing par ameters fo r the EEPROM interface s ignals. The timing param eters are illustr ated in
Figure 36.
Table 42. EEPROM Timing Parameters
Symbol Parameter Min Max Units Notes
T50 tEFSK Serial Cloc k Frequency 1 Mhz EEPROM fsk =
1 MHz
T51 tECSS De lay from EECS High to E ESK Hig h 30 0 ns EEPROM tcss
= 50 ns
T52 tECSH De lay from EESK Low to EECS Low 30 ns EEPROM tcsh
= 0 ns
T53 tEDIS Setup Time of EEDI to EESK 300 ns EEPROM tdis
= 150 ns
T54 tEDIH Hold Time of EEDI after EESK 300 ns EEPROM tdih
= 150 ms
T55 tECS EECS Low Time 750 ns EEPROM tcs =
250 ns
Figure 36. EEPROM Timings
EECS
FLA15EESK
FLA13EEDI
T51 T52
T54T53
82559 — Netwo rking Sili con
108 Datasheet
12.4.2 .5 PHY Timings
Table 43. 10BASE-T NLP Timing Parameters
Symbol Parameter Condition Min Typ Max Units
T56 Tnlp_wid NLP Width 10 Mbps 100 ns
T57 Tnlp_per NLP Period 10 Mbps 8 24 ms
Figu re 37 . 10BAS E -T N LP Ti m in gs
Normal Link Pulse
T57
T56
Tabl e 4 4. Auto-N egoti a tio n FLP Tim i ng Para me te rs
Symbol Parameter Min Typ Max Units
T58 Tflp_wid FLP Width (cl ock/ data) 100 ns
T59 Tflp_clk_clk Clock Pulse to Clock Pulse Period 111 125 139 µs
T60 Tflp_clk_dat Clock Pulse to Data Pulse Period 55.5 62.5 69.5 µs
T61 Tflp_bur_num Number of Pulses in one burst 17 33
T62 Tflp_bur_wid FLP Burst Width 2 ms
T63 Tflp_bur_per FLP Burst Period 8 24 ms
Figu re 38 . Auto- N egotiation FLP Timi ngs
Fast Link Pulse
T60
T58
T59
Clock Pulse Data Pulse Clock Pulse
FLP Bursts T62 T63
Networking Silicon — 82559
Datasheet 109
12.4.2 .6 SMB Interface Timings
Table 45. 100Base-TX Tran smitter AC Spec ification
Symbol Parameter Condition Min Typ Max Units
T64 Tjit TDP/TDN Diff ere ntial
Ou tput Peak Jit ter HLS Data 1400 p s
Table 46. Flash Timing Parameters
Symbol Parameter Min Max Units Notes
fsmb SMB Operating Frequency 1 MHz
T84 tdhs Data Hold Time 300 ns
T85 tdsus Data Setup Time 250 ns
82559 — Netwo rking Sili con
110 Datasheet
Note: Thi s pag e left intenti onally bl ank.
Networking Silicon — 82559
Datasheet 111
13.0 Package and Pinout Information
13.1 Package Information
The 82559 is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure
39. More information on Intel device packagi ng is av ailable i n the Intel P ackaging Handbook,
wh ich is availa b le fr o m th e I n tel L i te r a t ur e Cent er o r y ou r lo cal I n te l s al e s offic e.
Figure 39. Di mension Diagram for the 82559 196-pin BGA
82559 — Netwo rking Sili con
112 Datasheet
13.2 Pinout Information
13.2.1 8 2559 Pin Assignm ents
Table 47. 82559 Pin Assignments
Pin Name Pin Name Pin Name
A1 NC A2 SERR# A3 VCC
A4IDSELA5AD25A6PME#
A7VCCA8AD30A9ALTRST#
A10 SMBCLK A11 VCC A12 LILED
A13 TEST A14 NC
B1 AD22 B2 AD23 B3 VSSPP
B4 AD24 B5 AD26 B6 AD27
B7 VSSPP B8 AD31 B9 ISOLATE#
B10 SMBALRT# B11 SPEEDLED B12 TO
B13 RBIAS100 B14 RBIAS10
C1 AD21 C2 RST# C3 REQ#
C4 C/BE3# C5 CSTSCHG C6 AD28
C7 AD29 C8 CLKRUN# C9 SMBD
C10 VSSPT C11 ACTLED C12 VREF
C13 TDP C14 TDN
D1 AD18 D2 AD19 D3 AD20
D4 VSS D5 VSS D6 VSS
D7 VSS D8 VSS D9 NC
D10 NC D11 VSS D12 TI
D13 TEXEC D14 TCK
E1 VCC E2 VSSPP E3 AD17
E4 VSS E5 VSS E6 VSS
E7 VSS E8 VSS E9 VSS
E10 VSS E11 VSS E12 VCC
E13 RDP E14 RDN
F1 IRDY# F2FRAME#F3 C/BE2#
F4 VSS F5 VSS F6 VSS
F7 VSS F8 VSS F9 VSS
F10 VSS F11 VSS F12 FLD2
F13 FLD1 F14 FLD0
G1 CLK G2 VIO G3 TRDY#
G4 NC G5 VCC G6 VCC
G7 VSS G8 VSS G9 VSS
G10 VSS G11 VSS G12 FLD3
Networking Silicon — 82559
Datasheet 113
G13 VCC G14 VSSPL
H1 STOP# H2 INTA# H3 DEVSEL#
H4 NC H5 VCC H6 VCC
H7 VCC H8 VCC H9 VSS
H10 VSS H11 VSS H12 FLD6
H13 FLD5 H14 FLD4
J1 PAR J2 PERR# J3 GNT#
J4 NC J5 VCC J6 VCC
J7 VCC J8 VCC J9 VCC
J10 VCC J11 VCC J12 FLA1
J13 FLA0 J14 FLD7
K1 AD16 K2 VSSPP K3 VCC
K4 VCC K5 VCC K6 VCC
K7 VCC K8 VCC K9 VCC
K10 VCC K11 VCC K12 VSSPL
K13 VCC K14 FLA2
L1 AD14 L2 AD15 L3 C/BE#1
L4 VCC L5 VCC L6 VSS
L7 CFCS# L8 CFCLK L9 VCC
L10 VCC L11 VSS L12 FLA5
L13FLA4L14FLA3
M1 AD11 M2 AD12 M3 AD13
M4 C/BE0# M5 AD5 M6 VSSPP
M7 AD1 M8 FLOE# M9 FLWE#
M10 FLA15/EESK M11 FLA12 M12 FLA11
M13FLA7M14FLA6
N1 VSSPP N2 AD10 N3 AD9
N4 AD7 N5 AD4 N6 VCC
N7 AD0 N8 VCC N9 FLCS#
N10 FLA14/EEDO N11 X1 N12 VSSPL
N13 FLA10 N14 FLA8/IOCHRDY
P1 NC P2 VCC P3 AD8
P4 AD6 P5 AD3 P6 AD2
P7 EECS P8 VSSPL P9 FLA16
P10 FLA13/EEDI P11 X2 P12 VCC
P13FLA9P14 NC
Table 47. 82559 Pin Assign m ents
PinNamePinNamePinName
82559 — Netwo rking Sili con
114 Datasheet
13.2.2 82559 Ball Grid Array Diagram
Figure 40. 82559 Ball Grid Array Diagram
NCFLA9VCCPLX2
FLA13/
EEDI
FLA16VSSPLEECSAD2AD3AD6AD8VCCPPNC
FLA8FLA10VSSPLX1
FLA14/
EEDO
FLCS#VCCPLAD0VCCPPAD4AD7AD9AD10VSSPP
FLA6FLA7FLA11FLA12
FLA15/
EESK
FLWE#FLOE#AD1VSSPPAD5CBE0#AD13AD12AD11
FLA3FLA4FLA5VSSVCCVCCCFCLKCFCSVSSVCCVCCCBE1#AD15AD14
FLA2VCCPLVSSPLVCCVCCVCCVCCVCCVCCVCCVCCVCCPPVSSPPAD16
FLD7FLA0FLA1VCCVCCVCCVCCVCCVCCVCCNCGNT#PERR#PAR
FLD4FLD5FLD6VSSVSSVSSVCCVCCVCCVCCNC
DEVSEL
#
INTA#STOP#
VSSPLVCCPLFLD3VSSVSSVSSVSSVSSVCCVCCNCTRDY#VIOCLK
FLD0FLD1FLD2VSSVSSVSSVSSVSSVSSVSSVSSCBE2#FRAME#IRDY#
RDNRDPVCCVSSVSSVSSVSSVSSVSSVSSVSSAD17VSSPPVCCPP
TCKTEXECTIVSSNCNCVSSVSSVSSVSSVSSAD20AD19AD18
TDNTDPVREFACTLEDVSSPTSMBD
CLKRU
N#
AD29AD28
CSTSC
HG
CBE3#REQ#RST#AD21
RBIAS1
0
RBIAS1
00
TO
SPEEDL
ED
SMBAL
RT#
ISOLAT
E#
AD31VSSPPAD27AD26AD24VSSPPAD23AD22
NCTESTLILEDVCCPT
SMBCL
K
ALTRST
#
AD30VCCPPPME#AD25IDSELVCCPPSERR#NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
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82559 Ballout BGA196 15mmx15mm
(top view) 4 May 98
