FUJITSU SEMICONDUCTOR DATA SHEET DS07-13722-8E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90480/485 Series MB90F481/F482/487B/488B/483C MB90F488B/F489B/V480/V485B DESCRIPTION The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C*2 interface, DTP/ external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is the abbreviation for FUJITSU Flexible Microcontroller. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C standard a Specification as defined by Philips. FEATURES * Clock Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied x 4 (25 MHz internal operating frequency/3.3 V 0.3 V) 62.5 ns/4 MHz base frequency multiplied x 4 (16 MHz internal operating frequency/3.0 V 0.3 V) PLL clock multiplier * Maximum memory space: 16 Mbytes (Continued) Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright(c)2002-2006 FUJITSU LIMITED All rights reserved MB90480/485 Series (Continued) * Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word) Typical addressing modes (23 types) 32-bit accumulator for enhanced high-precision calculation Enhanced signed multiplication/division instruction and RETI instruction functions * Instruction set designed for high-level programming language (C) and multi-task operations System stack pointer adopted Instruction set symmetry and barrel shift instructions * Non-multiplex bus/multiplex bus compatible * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts * Data transfer function (DMAC) Up to 16 channels * Embedded ROM Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes * Embedded RAM Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes * General purpose ports Up to 84 ports (Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings) * A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 s conversion time (at 25 MHz) ) * I2C interface (MB90485 series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch) Do not apply high voltage in excess of recommended operating ranges to the N-ch open drain pin (with P-ch) in MB90V485B. * PG (MB90485 series only) : 1 channel * UART : 1 channel * Extended I/O serial interface (SIO) : 2 channels * 8/16-bit PPG : 3 channels (with 8-bit x 6 channel/16-bit x 3 channel mode switching function) * 8/16-bit up/down counter/timer: 1 channel (with 8-bit x 2 channels/16-bit x 1-channel mode switching function) * PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three) * 3 V/5 V I/F pin (MB90485 series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77 * 16-bit reload timer : 1 channel * 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free run timer * On chip dual clock generator system * Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode * Packages : QFP 100/LQFP 100 * Process : CMOS technology * Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485 series) 2 MB90480/485 Series PRODUCT LINEUP * MB90480 series Part number Item Classification ROM size RAM size MB90F481 MB90F482 MB90V480 Flash memory product Evaluation product 192 Kbytes 256 Kbytes 4 Kbytes 6 Kbytes 16 Kbytes Number of instructions : 351 Instruction bit length : 8-bit, 16-bit CPU function Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock) General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) Ports General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output) UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit x 6 channels/16-bit x 3 channels 8/16-bit up/down Event input pins : 6, 8-bit up/down counters : 2 counter/timer 8-bit reload/compare registers : 2 Number of channels : 1 16-bit free run timer Overflow interrupt 16-bit Output compare Number of channels : 6 I/O timers (OCU) Pin input factor : A match signal of compare register Input capture Number of channels : 2 (ICU) Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt pin channels : 8 (edge or level detection) Extended I/O serial interface Embedded 2 channels 18-bit counter Timebase timer Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, A/D converter programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms Watchdog timer (minimum value, at 4 MHz base oscillator) Low-power consumption Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, (standby) modes timebase timer mode Process CMOS User pin*1, Type Not included security function 3 V/5 V versions Included Emulator power supply*2 *1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77 *2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. Note : Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, -5%) . 3 MB90480/485 Series * MB90485 series Part number Item Classification MB90487B MB90488B MB90F488B MB90V485B MB90F489B MASK ROM product MB90483C Flash memory product Evaluation product Flash memory product MASK ROM product ROM size 192 Kbytes 256 Kbytes 256 Kbytes 384 Kbytes 256 Kbytes RAM size 10 Kbytes 10 Kbytes 10 Kbytes 16 Kbytes 24 Kbytes 16 Kbytes Number of instructions : 351 Instruction bit length : 8-bit, 16-bit Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bit, 16-bit Minimum instruction execution time : 40 ns (25 MHz machine clock) CPU function Ports General-purpose I/O ports : up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain output) UART 1 channel, start-stop synchronized 8/16-bit PPG 8-bit x 6 channels/16-bit x 3 channels 8/16-bit up/down counter/timer Event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 16-bit free run Number of channels : 1 timer Overflow interrupt 16-bit I/O timers Output compare (OCU) Number of channels : 6 Pin input factor: A match signal of compare register Input capture (ICU) Number of channels : 2 Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt pin channels: 8 (edge or level detection) Extended I/O serial interface Embedded 2 channels I2C interface*2 1 channel PG 1 channel PWC 3 channels Timebase timer 18-bit counter Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) A/D converter Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) (Continued) 4 MB90480/485 Series (Continued) Part number Item MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Low-power consumption (standby) modes Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode Process CMOS Type Emulator power supply*3 3 V/5 V power supply*1 3 V/5 V power supply*1 3 V/5 V power supply*1 Included security function 3 V/5 V power supply*1 3 V/5 V power supply*1 Included security function 3 V/5 V power supply*1 Included *1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and P70 to P77. *2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. However, MB90V485B uses the N-ch open drain pin (with P-ch) . *3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. Notes : * As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/PG/I2C become CMOS input. * Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, - 5%) . 5 MB90480/485 Series PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS (TOP VIEW) (FPT-100P-M06) * : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/A11, P44/A12, P45/A13, P75 to P77. Note : MB90485 series only * I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. * As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/PG/I2C become CMOS input. 6 MB90480/485 Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 (FPT-100P-M05) * : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/ A11, P44/A12, P45/A13, P75 to P77. Note : MB90485 series only * I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. * As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ PG/I2C become CMOS input. 7 MB90480/485 Series PIN DESCRIPTIONS Pin No. Pin name I/O circuit type*3 Function QFP*1 LQFP*2 82 80 X0 A Clock (oscillator) input pin 83 81 X1 A Clock (oscillator) output pin 80 78 X0A A Clock (32 kHz oscillator) input pin 79 77 X1A A Clock (32 kHz oscillator) output pin 77 75 RST B Reset input pin This is a general purpose I/O port. A setting in the port 0 input resistance register (RDR0) can be used to apply pull-up resistance (RD00-RD07 = "1") . (Disabled when pin is set for output.) P00 to P07 85 to 92 83 to 90 93 to 100 1 to 4 91 to 98 99, 100, 1, 2 AD00 to AD07 C (CMOS) D00 to D07 In non-multiplex mode, these pins function as the external data bus low output pins. P10 to P17 This is a general purpose I/O port. A setting in the port 1 input resistance register (RDR1) can be used to apply pull-up resistance (RD10-RD17 = "1") . (Disabled when pin is set for output.) AD08 to AD15 C (CMOS) 3 to 6 In non-multiplex mode, these pins function as the external data bus high output pins. P20 to P23 This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. When the bits of external address output control register (HACR) are (CMOS/H) set to "0" in multiplex mode, these pins function as address high output pins (A16-A19). A16 to A19 When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A16-A19). E This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high E output pins (A20-A23). A20 to A23 (CMOS/H) When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A20-A23). PPG0 to PPG3 Output pins for PPG. This is a general purpose I/O port. P30 9 7 In multiplex mode, these pins function as the external address/data bus high I/O pins. D08 to D15 P24 to P27 5 to 8 In multiplex mode, these pins function as the external address/data bus low I/O pins. A00 AIN0 E (CMOS/H) In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.0) . (Continued) 8 MB90480/485 Series Pin No. QFP*1 LQFP*2 Pin name I/O circuit type*3 P31 10 8 A01 This is a general purpose I/O port. E (CMOS/H) BIN0 10 A02 This is a general purpose I/O port. E (CMOS/H) ZIN0 11 A03 This is a general purpose I/O port. E (CMOS/H) AIN1 12 A04 This is a general purpose I/O port. E (CMOS/H) BIN1 13 A05 This is a general purpose I/O port. E (CMOS/H) ZIN1 P36, P37 A06, A07 16, 17 14, 15 D (CMOS) E 19 17 A08 This is a general purpose I/O port. G (CMOS/H) In non-multiplex mode, this pin functions as an external address pin. SIN2 Extended I/O serial interface input pin. P41 This is a general purpose I/O port. A09 F (CMOS) In non-multiplex mode, this pin functions as an external address pin. Extended I/O serial interface output pin. P42 18 In non-multiplex mode, this pin functions as an external This is a PWC input pin. SOT2 20 address pin. MB90485 address pin. (CMOS/H) series P40 16 This is a general purpose I/O port. MB90480 series In non-multiplex mode, this pin functions as an external This is a general purpose I/O port. PWC0, PWC1*4 18 In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) P36, P37 A06, A07 In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) . P35 15 In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.1) . P34 14 In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.0) P33 13 In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (ch.0) . P32 12 Function A10 SCK2 This is a general purpose I/O port. G (CMOS/H) In non-multiplex mode, this pin functions as an external address pin. Extended I/O serial interface clock input/output pin. (Continued) 9 MB90480/485 Series Pin No. QFP*1 LQFP*2 Pin name I/O circuit type*3 Function P43, P44 This is a general purpose I/O port. F (CMOS) MB90480 In non-multiplex mode, this pin functions as an external series A11, A12 address pin. 21, 22 19, 20 P43, P44 This is a general purpose I/O port. A11, A12 In non-multiplex mode, this pin functions as an external F (CMOS) MB90485 address pin. series MT00, MT01 P45 A13 24 22 25, 26 23, 24 This is a general purpose I/O port. A13 G MB90485 In non-multiplex mode, this pin functions as an external (CMOS/H) series address pin. EXTC*4 PG input pin. P46, P47 This is a general purpose I/O port. A14, A15 P50 68 ALE P51 71 69 RD P52 72 73 This is a general purpose I/O port. F MB90480 In non-multiplex mode, this pin functions as an external series (CMOS) address pin. P45 OUT4/ OUT5 70 PG output pin. F In non-multiplex mode, this pin functions as an external address pin. (CMOS) Output compare event output pins. This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin. D (CMOS) In external bus mode, this pin functions as the address load enable (ALE) signal pin. This is a general purpose I/O port. In external bus mode, this pin functions as the RD pin. D (CMOS) In external bus mode, this pin functions as the read strobe output (RD) signal pin. This is a general purpose I/O port. In external bus mode, when the WRE bit in the EPCR register is set to "1", this pin functions as the WRL pin. WRL D (CMOS) In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. P53 This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to "1", this pin functions as the WRH pin. 70 71 WRH D (CMOS) In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. (Continued) 10 MB90480/485 Series Pin No. QFP*1 LQFP*2 Pin name I/O circuit type*3 This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to "1", this pin functions as the HRQ pin. P54 74 72 HRQ D (CMOS) In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to "1", this pin functions as the HAK pin. P55 75 73 HAK D (CMOS) In external bus mode, this pin functions as the hold acknowledge output (HAK) pin. When the HDE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the RYE bit in the EPCR register is set to "1", this pin functions as the RDY pin. P56 76 74 RDY D (CMOS) In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the CKE bit in the EPCR register is set to "1", this pin functions as the CLK pin. P57 78 76 CLK 38 to 41 36 to 39 43 to 46 41 to 44 27 25 28 26 29 27 30 28 31 29 P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P70 SIN0 P71 SOT0 P72 SCK0 P73 TIN0 P74 TOT0 Function D (CMOS) In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. These are general purpose I/O ports. H (CMOS) These are the analog input pins for A/D converter. These are general purpose I/O ports. H (CMOS) These are the analog input pins for A/D converter. This is a general purpose I/O port. G (CMOS/H) This is the UART serial data input pin. This is a general purpose I/O port. F (CMOS) This is the UART serial data output pin. This is a general purpose I/O port. G (CMOS/H) This is the UART serial communication clock I/O pin. G This is a general purpose I/O port. (CMOS/H) This is the 16-bit reload timer event input pin. This is a general purpose I/O port. F (CMOS) This is the 16-bit reload timer output pin. (Continued) 11 MB90480/485 Series Pin No. QFP*1 LQFP*2 Pin name 30 P75 PWC2* 4 31 G MB90485 This is a general purpose I/O port. (CMOS/H) series This is a PWC input pin. F (CMOS) P76 33 Function F MB90480 series This is a general purpose I/O port. (CMOS) P75 32 I/O circuit type*3 P76 MB90480 series This is a general purpose I/O port. This is a general purpose I/O port. SCL*4 I MB90485 Serves as the I2C interface data I/O pin. During opera(NMOS/H) series tion of the I2C interface, leave the port output in a high impedance state. F (CMOS) P77 34 32 P77 MB90480 series This is a general purpose I/O port. This is a general purpose I/O port. 4 SDA* I MB90485 Serves as the I2C interface data I/O pin. During opera(NMOS/H) series tion of the I2C interface, leave the port output in a high impedance state. 47, 48 45, 46 52 to 57 50 to 55 P80, P81 IRQ0, IRQ1 P82 to P87 These are general purpose I/O ports. E (CMOS/H) External interrupt input pins. E IRQ2 to IRQ7 (CMOS/H) External interrupt input pins. This is a general purpose I/O port. P90 58 56 SIN1 E (CMOS/H) CS0 P91 59 57 SOT1 CS1 58 SCK1 This is a general purpose I/O port. D Extended I/O serial interface data output pin. (CMOS) Chip select 1. Extended I/O serial interface clock input/output pin. P93 This is a general purpose I/O port. 59 CS3 60 (CMOS/H) Chip select 2. ADTG 62 This is a general purpose I/O port. E CS2 FRCK 61 Extended I/O serial interface data input pin. Chip select 0. P92 60 These are general purpose I/O ports. P94 PPG4 When the free run timer is in use, this pin functions as the external clock input pin. E (CMOS/H) When the A/D converter is in use, this pin functions as the external trigger input pin. Chip select 3. This is a general purpose I/O port. D (CMOS) PPG timer output pin. (Continued) 12 MB90480/485 Series (Continued) Pin No. QFP*1 LQFP*2 63 61 64 62 65 63 66 to 69 64 to 67 Pin name P95 PPG5 P96 IN0 P97 IN1 PA0 to PA3 I/O circuit type*3 D (CMOS) Function This is a general purpose I/O port. PPG timer output pin. This is a general purpose I/O port. E (CMOS/H) Input capture ch.0 trigger input pin. E This is a general purpose I/O port. (CMOS/H) Input capture ch.1 trigger input pin. OUT0 to OUT3 D (CMOS) These are general purpose I/O ports. Output compare event output pins. 35 33 AVCC A/D converter analog power supply input pin. 36 34 AVRH A/D converter reference voltage input pin. 37 35 AVSS A/D converter GND pin. 49 to 51 47 to 49 84 82 MD0 to MD2 VCC3 J Operating mode selection input pins. (CMOS/H) 3.3 V 0.3 V power supply pins (VCC3) . MB90480 3.3 V 0.3 V power supply pin. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply. 23 21 VCC5 11, 42, 81 9, 40, 79 VSS 3 V/5 V power supply pin. 5 V power supply pin when P20 to P27, P30 to P37, MB90485 P40 to P47, P70 to P77 are used as 5 V I/F pins. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . GND pins. *1 : QFP : FPT-100P-M06 *2 : LQFP : FPT-100P-M05 *3 : For the I/O circuit type, refer to " I/O CIRCUIT TYPES". *4 : As for MB90V485B, input pins become CMOS input. 13 MB90480/485 Series I/O CIRCUIT TYPES Type Circuit Remarks * Feedback resistance X1, X0 : approx. 1 M X1A, X0A : approx. 10 M * With standby control X1, X1A X0, X0A A Standby control signal Hysteresis input with pull-up resistance B Hysteresis input * With input pull-up resistance control * CMOS level input/output CTL P-ch C P-ch N-ch CMOS CMOS level input/output P-ch N-ch D CMOS * Hysteresis input * CMOS level output P-ch E N-ch CMOS (Continued) 14 MB90480/485 Series (Continued) Type Circuit P-ch F N-ch Remarks Open drain control signal * CMOS level input/output * With open drain control CMOS P-ch G Open drain control signal * CMOS level output * Hysteresis input * With open drain control N-ch Hysteresis input * CMOS level input/output * Analog input P-ch N-ch H CMOS Analog input N-ch Digital output * Hysteresis input * N-ch open drain output I (Flash memory product) * CMOS level input * With high voltage control for flash testing (Flash memory product) Control signal J Mode input Diffusion resistance (MASK ROM product) Hysteresis input (MASK ROM product) Hysteresis input 15 MB90480/485 Series HANDLING DEVICES 1. Be careful never to exceed maximum rated voltages (preventing latch-up) In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS pins exceeds the rated voltage level. When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) . 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. Treatment of Power Supply Pins (VCC/VSS) When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC/VSS pins of this device with as low impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 F be placed between the VCC and VSS lines as close to this device as possible. 4. Crystal Oscillator Circuits Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. 5. Precautions when turning the power supply on In order to prevent abnormal operation in the chip's internal step-down circuits, a voltage rise time during poweron of 50 s (0.2 V to 2.7 V) or greater should be assured. 6. Supply Voltage Stabilization Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50 MHz to 60 MHz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off. 7. Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. 16 MB90480/485 Series 8. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 9. Notes on Using Power Supply Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies. 10. Notes on Using External Clock Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. X0 OPEN X1 11. Treatment of NC pins NC (internally connected) pins should always be left open. 12. Notes on during operation of PLL clock mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs. 13. When the MB90480/485 series microcontroller is used as a single system When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open. 14. Writing to Flash memory For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V. 17 MB90480/485 Series BLOCK DIAGRAM X0, X1, RST X0A, X1A MD2, MD1, MD0 8 CPU F2MC16LX series core Clock control Circuit RAM Interrupt controller ROM 8/16-bit PPG PPG0, PPG1 PPG2, PPG3 PPG4, PPG5 8/16-bit up/down counter/timer AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 DMAC Communication prescaler SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7 F2MC-16LX Bus 2 SIN0 SOT0 SCK0 UART Extended I/O serial interface x 2 channels EXTC MT00 MT01 PG Chip select CS0, CS1, CS2, CS3 Input/output timer 16-bit input capture x IN0, IN1 2 channels A/D converter ( 10-bit ) 16-bit output compare x 6 channels 16-bit free-run timer OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 16-bit reload timer TIN0 TOT0 I2C interface SCL SDA PWC0 PWC1 PWC x 3 channels PWC2 External interrupt 8 IRQ0 to IRQ7 I/O port 8 8 8 8 8 8 8 8 8 8 4 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 to to to to to to to to to to PA0 to P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3 : Only MB90485 series P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P77 (8 pins) : with an input pull-up resistance setting register. : with an input pull-up resistance setting register. : with an open drain setting register. : with an open drain setting register. MB90485 series only * I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin. * As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ PG/I2C become CMOS input. Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. 18 MB90480/485 Series MEMORY MAP * MB90F481/F482/487B/488B/483C/F488B/V480/V485B/F489B Internal ROM Single chip external bus External ROM external bus FFFFFFH ROM area ROM area ROM area FF bank image ROM area FF bank image Address #1 010000H Address #2 Address #3 RAM Register RAM Register RAM Register 000100H 0000D0H Peripheral Peripheral Peripheral 000000H : Internal : External : Access inhibited * : In models where address #3 overlaps with address #2, this external area does not exist. Model MB90F481 MB90F482 MB90487B MB90488B MB90F488B MB90V480 MB90V485B MB90483C MB90F489B Address #1 FC0000H *1 FC0000H FD0000H FC0000H FC0000H (FC0000H) (FC0000H) FB0000H*4 F90000H *2 Address #2 004000H or 008000H, selected by the MS bit in the ROMM register 0080000H fixed Address #3 001100H 001900H 002900H 002900H 002900H 004000H 004000H 004000H 006100H*3 *1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank are the same, enabling reference to tables in ROM without using the for specification in the pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to "0", the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only. (Continued) 19 MB90480/485 Series (Continued) *2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM external-bus mode. *3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area that is larger than 004000H by the emulation memory area setting on the tool side. *4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internalROM external-bus mode. 20 MB90480/485 Series * MB90F489B Single chip Internal ROM external bus ROM (FF bank) ROM (FF bank) ROM (FE bank) ROM (FE bank) ROM (FD bank) ROM (FD bank) ROM (FB bank) ROM (FB bank) ROM (FA bank) ROM (FA bank) ROM (F9 bank) ROM (F9 bank) ROM area FF bank image ROM area FF bank image External ROM external bus FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H F7FFFFH 010000H 00FFFFH 008000H 007FFFH 006100H 0060FFH RAM Register RAM Register RAM Register 000100H 0000FFH 0000D0H 0000CFH Peripheral Peripheral : Internal : External Peripheral 000000H : Access inhibited 21 MB90480/485 Series * MB90483C Single chip Internal ROM external bus ROM (FF bank) ROM (FF bank) ROM (FE bank) ROM (FE bank) ROM (FD bank) ROM (FD bank) ROM (FB bank) ROM (FB bank) ROM area FF bank image ROM area FF bank image External ROM external bus FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H F7FFFFH 010000H 00FFFFH 004000H or 008000H 004000H 003FFFH RAM Register RAM Register RAM Register 000100H 0000FFH 0000D0H 0000CFH Peripheral Peripheral : Internal : External Peripheral 000000H 22 : Access inhibited MB90480/485 Series F2MC-16L CPU PROGRAMMING MODEL *Dedicated registers AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8-bit 16-bit 32-bit *General purpose registers MSB LSB 16-bit 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 *Processor status 13 12 15 PS ILM 8 7 RP 0 CCR 23 MB90480/485 Series I/O MAP Address Register name Abbreviated Read/ register name Write Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (MB90480 series) 11XXXXXXB (MB90485 series) XXXXXXXXB XXXXXXXXB ----XXXXB 00H 01H 02H 03H 04H 05H 06H Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 07H Port 7 data register PDR7 R/W Port 7 08H 09H 0AH Port 8 data register Port 9 data register Port A data register PDR8 PDR9 PDRA R/W R/W R/W 0BH Up/down timer input enable register UDRE R/W Port 8 Port 9 Port A Up/down timer input control 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H Interrupt/DTP enable register Interrupt/DTP source register Request level setting register Request level setting register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register ENIR EIRR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 17H Port 7 direction register DDR7 R/W 18H 19H 1AH Port 8 direction register Port 9 direction register Port A direction register DDR8 DDR9 DDRA R/W R/W R/W 1BH Port 4 output pin register ODR4 R/W 1CH Port 0 input resistance register RDR0 R/W 1DH Port 1 input resistance register RDR1 R/W 1EH Port 7 output pin register ODR7 R/W 1FH Analog input enable register ADER R/W ELVR XX000000B 00000000B XXXXXXXXB DTP/external interrupts 00000000B 00000000B Port 0 00000000B Port 1 00000000B Port 2 00000000B Port 3 00000000B Port 4 00000000B Port 5 00000000B Port 6 00000000B 00000000B (MB90480 series) Port 7 XX000000B (MB90485 series) Port 8 00000000B Port 9 00000000B Port A ----0000B Port 4 00000000B (Open-drain control) Port 0 00000000B (resistance control) Port 1 00000000B (resistance control) 00000000B (MB90480 series) Port 7 (Open-drain control) XX000000B (MB90485 series) Port 6, A/D 11111111B (Continued) 24 MB90480/485 Series Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H Register name Serial mode register Serial control register Serial input/output register Serial status register Read/ Write SMR R/W SCR W, R/W SIDR/SODR R/W SSR R, R/W (Reserved area) Abbreviated register name Communication prescaler control register CDCR R/W Serial mode control status register 0 SMCS0 R/W SDR0 R/W Communication prescaler control register 0 SDCR0 R/W Serial mode control status register 1 SMCS1 R/W SDR1 R/W SDCR1 R/W Serial data register 0 Serial data register 1 Communication prescaler control register 1 Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload resister H (ch.1) Reload register L (ch.2) Reload register H (ch.2) Reload register L (ch.3) Reload register H (ch.3) Reload register L (ch.4) Reload register H (ch.4) Reload register L (ch.5) Reload register H (ch.5) PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register PPG4 operating mode control register PPG5 operating mode control register PPG0, PPG1 output control register PPG2, PPG3 output control register PPLL0 R/W PPLH0 R/W PPLL1 R/W PPLH1 R/W PPLL2 R/W PPLH2 R/W PPLL3 R/W PPLH3 R/W PPLL4 R/W PPLH4 R/W PPLL5 R/W PPLH5 R/W PPGC0 R/W PPGC1 R/W PPGC2 R/W PPGC3 R/W PPGC4 R/W PPGC5 R/W PPG01 R/W (Reserved area) PPG23 R/W (Reserved area) Resource name Initial value UART 00000X00B 00000100B XXXXXXXXB 00001000B Communication prescaler (UART) 00--0000B SIO1 (ch.0) ----0000B 00000010B XXXXXXXXB Communication prescaler SIO1 (ch.0) 0---0000B SIO2 (ch.1) ----0000B 00000010B XXXXXXXXB Communication prescaler SIO2 (ch.1) 0---0000B 8/16-bit PPG XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0X000XX1B 0X000001B 0X000XX1B 0X000001B 0X000XX1B 0X000001B 00000000B 8/16-bit PPG 00000000B 8/16-bit PPG (ch.0 to ch.5) (Continued) 25 MB90480/485 Series Address 44H Register name PPG4, PPG5 output control register 45H 46H 47H 48H 49H Abbreviated register name Read/ Write PPG45 R/W (Reserved area) Control status register Data register 4AH Output compare register (ch.0) lower digits 4BH Output compare register (ch.0) upper digits 4CH Output compare register (ch.1) lower digits 4DH Output compare register (ch.1) upper digits 4EH Output compare register (ch.2) lower digits 4FH Output compare register (ch.2) upper digits 50H Output compare register (ch.3) lower digits ADCS1 R/W ADCS2 W, R/W ADCR1 R ADCR2 W, R OCCP0 R/W OCCP1 R/W OCCP2 R/W OCCP3 R/W OCCP4 R/W OCCP5 R/W Resource name Initial value 8/16-bit PPG 00000000B 00000000B A/D converter 00000000B XXXXXXXXB 00000XXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 16-bit input/output timer output compare (ch.0 to ch.5) 51H Output compare register (ch.3) upper digits 52H Output compare register (ch.4) lower digits 00000000B 53H Output compare register (ch.4) upper digits 54H Output compare register (ch.5) lower digits 55H Output compare register (ch.5) upper digits 56H Output control register (ch.0) OCS0 R/W 0000--00B 57H Output control register (ch.1) OCS1 R/W ---00000B 58H Output control register (ch.2) OCS2 R/W 0000--00B 00000000B 00000000B 00000000B 00000000B 59H Output control register (ch.3) OCS3 R/W ---00000B 5AH Output control register (ch.4) OCS4 R/W 0000--00B 5BH Output control register (ch.5) OCS5 R/W ---00000B 5CH Input capture data register (ch.0) lower digits R XXXXXXXXB 5DH Input capture data register (ch.0) upper digits 5EH Input capture data register (ch.1) lower digits 5FH Input capture data register (ch.1) upper digits 60H Input capture control status register 61H IPCP0 R R IPCP1 R ICS01 R/W 16-bit input/output timer input capture (ch.0, ch.1) XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B (Reserved area) (Continued) 26 MB90480/485 Series Address Register name 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH Timer counter data register lower digits Timer counter data register upper digits Timer control status register Timer control status register Compare clear register lower digits Compare clear register upper digits Up/down count register (ch.0) Up/down count register (ch.1) Reload/compare register (ch.0) Reload/compare register (ch.1) Counter control register (ch.0) lower digits Counter control register (ch.0) upper digits 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H* 77H* 78H* 79H* 7AH* 7BH* 7CH* 7DH* 7EH* 7FH* 80H* 81H* 82H* 83H 84H* 85H 86H* 87H Abbreviated register name Read/ Write TCDT TCDT TCCS TCCS R/W R/W R/W R/W CPCLR R/W UDCR0 UDCR1 RCR0 RCR1 R R W W CCRL0 W, R/W 0X00X000B CCRH0 R/W 00000000B Resource name 16-bit input/output timer free run timer 8/16-bit up/down Initial value 00000000B 00000000B 00000000B 0--00000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B (Reserved area) ROM mirror function select register Counter control register (ch.1) lower digits Counter control register (ch.1) upper digits Counter status register (ch.0) Counter status register (ch.1) PWC control/status register ROMM R/W CCRL1 W, R/W CCRH1 R/W CSR0 R, R/W (Reserved area) CSR1 R, R/W (Reserved area) PWCSR0 R, R/W PWCR0 R/W PWCSR1 R, R/W PWCR1 R/W PWCSR2 R, R/W PWC data buffer register PWCR2 R/W Dividing ratio control register DIVR0 R/W (Reserved area) DIVR1 R/W (Reserved area) DIVR2 R/W (Reserved area) ROM mirroring function 0X00X000B 8/16-bit up/down PWC control/status register 8/16-bit UDC PWC control/status register PWC (ch.0) PWC (ch.1) ------00B PWC (ch.2) ------00B PWC (ch.2) Dividing ratio control register Dividing ratio control register 00000000B 00000000B 0000000XB 00000000B 00000000B 00000000B 0000000XB 00000000B 00000000B 00000000B 0000000XB 00000000B 00000000B ------00B PWC (ch.1) PWC data buffer register -0000000B 00000000B PWC (ch.0) PWC data buffer register ------+1B (Continued) 27 MB90480/485 Series Address Register name Abbreviated register name Read/ Write Resource name Initial value 88H* Bus status register IBSR R 00000000B 89H* Bus control register IBCR R/W 00000000B 8AH* Clock control register ICCR R/W 8BH* Address register IADR R/W -XXXXXXXB 8CH* Data register IDAR R/W XXXXXXXXB 8DH 8EH* I2C --0XXXXXB (Reserved area) PG control status register 8FH to 9BH PGCSR R/W PG 00000---B (Disabled) 9CH DMAC status register lower digits DSRL R/W DMAC 00000000B 9DH DMAC status register upper digits DSRH R/W DMAC 00000000B 9EH Program address detection control status resister PACSR R/W Address match detection function 00000000B 9FH Delayed interrupt source general/ cancel register DIRR R/W Delayed interrupt generator module -------0B A0H Low-power consumption mode control register LPMCR W, R/W Low-power consumption 00011000B A1H Clock select register CKSCR R, R/W Low-power consumption 11111100B A2H, A3H (Reserved area) A4H DMAC stop status register DSSR R/W DMAC 00000000B A5H Automatic ready function select register ARSR W External pins 0011 - -00B A6H External address output control register HACR W External pins ********B A7H Bus control signal select register EPCR W External pins 1000*10 -B A8H Watchdog timer control register WDTC R, W Watchdog timer XXXXX111B A9H Timebase timer control register TBTC W, R/W Timebase timer 1XX00100B AAH Watch timer control register WTC R, R/W Watch timer 10001000B ABH (Reserved area) ACH DMAC enable register lower digits DERL R/W DMAC 00000000B ADH DMAC enable register upper digits DERH R/W DMAC 00000000B AEH Flash memory control status register FMCS W, R/W Flash memory interface 000X0000B AFH (Disabled) B0H Interrupt control register 00 ICR00 W, R/W XXXX0111B B1H Interrupt control register 01 ICR01 W, R/W XXXX0111B B2H Interrupt control register 02 ICR02 W, R/W XXXX0111B B3H Interrupt control register 03 ICR03 W, R/W XXXX0111B B4H Interrupt control register 04 ICR04 W, R/W Interrupt controller XXXX0111B B5H Interrupt control register 05 ICR05 W, R/W XXXX0111B B6H Interrupt control register 06 ICR06 W, R/W XXXX0111B B7H Interrupt control register 07 ICR07 W, R/W XXXX0111B B8H Interrupt control register 08 ICR08 W, R/W XXXX0111B (Continued) 28 MB90480/485 Series (Continued) Address Register name Abbreviated register name Read/ Write Resource name Initial value B9H Interrupt control register 09 ICR09 W, R/W XXXX0111B BAH Interrupt control register 10 ICR10 W, R/W XXXX0111B BBH Interrupt control register 11 ICR11 W, R/W XXXX0111B BCH Interrupt control register 12 ICR12 W, R/W BDH Interrupt control register 13 ICR13 W, R/W XXXX0111B BEH Interrupt control register 14 ICR14 W, R/W XXXX0111B BFH Interrupt control register 15 ICR15 W, R/W XXXX0111B C0H Chip select area mask register 0 CMR0 R/W 00001111B C1H Chip select area register 0 CAR0 R/W 11111111B C2H Chip select area mask register 1 CMR1 R/W 00001111B C3H Chip select area register 1 CAR1 R/W 11111111B C4H Chip select area mask register 2 CMR2 R/W C5H Chip select area register 2 CAR2 R/W C6H Chip select area mask register 3 CMR3 R/W 00001111B C7H Chip select area register 3 CAR3 R/W 11111111B C8H Chip select control register CSCR R/W ----000*B C9H Chip select active level register CALR R/W CAH CBH CCH CDH Timer control status register 16-bit timer register/ 16-bit reload register CEH CFH TMCSR Interrupt controller Chip select function 00001111B 11111111B ----0000B 00000000B R/W 16-bit reload timer TMR/TMRLR XXXX0111B R/W ----0000B XXXXXXXXB (Reserved area) PLL output control register D0H to FFH PLLOS W Low-power consumption ------X0B (External area) 100H to #H (RAM area) 1FF0H Program address detection register 0 (Low order address) 1FF1H Program address detection register 0 (Middle order address) 1FF2H Program address detection register 0 (High order address) 1FF3H Program address detection register 1 (Low order address) 1FF4H Program address detection register 1 (Middle order address) 1FF5H Program address detection register 1 (High order address) PADR0 R/W Address match detection function XXXXXXXXB PADR1 R/W Address match detection function XXXXXXXXB * : These registers are only for MB90485 series. They are used as the reserved area on MB90480 series. (Continued) 29 MB90480/485 Series (Continued) Descriptions for read/write R/W : Readable and writable R : Read only W : Write only Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is "1" or "0". The value depends on the mode pin (MD2, MD1 and MD0) . + : The initial value of this bit is "1" or "0". The value depends on the RAM area of device. 30 MB90480/485 Series INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Clear of EI2OS DMAC channel number Number Address Number Address Reset x #08 FFFFDCH INT9 instruction x #09 FFFFD8H Exception x #10 FFFFD4H INT0 (IRQ0) 0 #11 FFFFD0H INT1 (IRQ1) x #12 FFFFCCH ICR00 0000B0H INT2 (IRQ2) x #13 FFFFC8H INT3 (IRQ3) x #14 FFFFC4H ICR01 0000B1H INT4 (IRQ4) x #15 FFFFC0H INT5 (IRQ5) x #16 FFFFBCH ICR02 0000B2H INT6 (IRQ6) x #17 FFFFB8H INT7 (IRQ7) x #18 FFFFB4H ICR03 0000B3H PWC1 (MB90485 series only) x #19 FFFFB0H PWC2 (MB90485 series only) x #20 FFFFACH ICR04 0000B4H PWC0 (MB90485 series only) 1 #21 FFFFA8H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH Interrupt source Interrupt vector PPG0/PPG1 counter borrow x x #22 FFFFA4H PPG2/PPG3 counter borrow x x #23 FFFFA0H PPG4/PPG5 counter borrow x x #24 FFFF9CH 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/up/down inversion x #25 FFFF98H Input capture (ch.0) load 5 #26 FFFF94H Input capture (ch.1) load 6 #27 FFFF90H Output compare (ch.0) match 8 #28 FFFF8CH Output compare (ch.1) match 9 #29 FFFF88H Output compare (ch.2) match 10 #30 FFFF84H Output compare (ch.3) match x #31 FFFF80H Output compare (ch.4) match x #32 FFFF7CH Output compare (ch.5) match x #33 FFFF78H UART sending completed 11 #34 FFFF74H 16-bit free run timer overflow, 16-bit reload timer underflow*2 12 #35 FFFF70H UART receiving completed 7 #36 FFFF6CH SIO1 (ch.0) 13 #37 FFFF68H SIO2 (ch.1) 14 #38 FFFF64H Interrupt control register (Continued) 31 MB90480/485 Series (Continued) Interrupt source I2C interface (MB90485 series only) Clear of EI2OS DMAC channel number Number Address x x #39 FFFF60H 15 #40 FFFF5CH x #41 FFFF58H A/D conversion Flash write/erase, timebase timer, watch timer *1 x Delay interrupt generator module x x Interrupt vector #42 Interrupt control register Number Address ICR14 0000BEH ICR15 0000BFH FFFF54H x : Interrupt request flag is not cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time. *2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable (TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111B) , then set the INTE bit to 0. Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request flags at the EI2OS/DMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/ DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to "0" and interrupt requests from that resource should be handled by software polling. 32 MB90480/485 Series PERIPHERAL RESOURCES 1. I/O Ports The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port data register (PDR) . The input/ output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each I/ O port. The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A. (1) Port Data Registers PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H 7 6 5 4 3 2 1 0 Initial value Access P07 P06 P05 P04 P03 P02 P01 P00 Undefined R/W*1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Undefined R/W*1 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 PDRA 7 6 5 4 3 2 1 0 Address : 00000AH PA3 PA2 PA1 PA0 Undefined*2 R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 *1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following operations. * Input mode Read : Reads the corresponding signal pin level. Write : Writes to the output latch. * Output mode Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin. *2 : The initial value of this bit is "11XXXXXXB" on MB90485 series. 33 MB90480/485 Series (2) Port Direction Registers DDR0 7 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH 6 5 4 3 2 1 0 Initial value Access D07 D06 D05 D04 D03 D02 D01 D00 00000000B R/W 7 6 5 4 3 2 1 0 D17 D16 D15 D14 D13 D12 D11 D10 00000000B R/W 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B*2 R/W 00000000B R/W 00000000B R/W ----0000B R/W 7 6 5 4 3 2 1 0 D37 D36 D35 D34 D33 D32 D31 D30 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 7 6 5 4 3 2 1 0 D57 D56 D55 D54 D53 D52 D51 D50 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D63 D62 D61 D60 7 6 5 4 3 2 1 0 D75 D74 D73 D72 D71 D70 D77*1 D76* 1 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 7 6 5 4 3 2 1 0 D97 D96 D95 D94 D93 D92 D91 D90 7 6 5 4 3 2 1 0 DA3 DA2 DA1 DA0 *1 : The value is set to "" on MB90485 series only. *2 : The initial value of this bit is "XX000000B" on MB90485 series only. * When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : Input mode. 1 : Output mode. Reset to "0". Notes : * When any of these registers are accessed using a read-modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output. * P76, P77 (MB90485 series only) This port has no DDR. To use P77 and P76 as I2C pins, set the PDR value to "1" so that port data remains enabled (to use P77 and P76 for general purposes, disable I2C) . The port is an open drain output (with no P-ch) . To use it as an input port, therefore, set the PDR to "1" to turn off the output transistor and add a pull-up resistor to the external output. 34 MB90480/485 Series (3) Port Input Resistance Registers RDR0 7 6 Address : 00001CH 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 7 6 5 4 3 2 1 0 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RDR1 Address : 00001DH 5 Initial value Access 00000000B R/W 00000000B R/W These registers control the use of pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : With pull-up resistance in input mode. In output mode, these registers have no function (no pull-up resistance) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . Using of this function is prohibited when an external bus is used. Do not write to these registers. (4) Port Output Pin Registers ODR7 7 6 Address : 00001EH OD77*1 OD76*1 ODR4 Address : 00001BH 5 4 3 2 1 Initial value 0 OD75 OD74 OD73 OD72 OD71 OD70 7 6 5 4 3 2 1 0 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 B 2 Access 00000000 * R/W 00000000B R/W *1 : The value is set to "" on MB90485 series only. *2 : The initial value of this bit is "XX000000B" on MB90485 series only. These registers control open drain settings in output mode. 0 : Standard output port functions in output mode. 1 : Open drain output port in output mode. In input mode, these registers have no function (Hi-Z output) . Input/output mode settings are controlled by the setting of port direction (DDR) registers. Using of this function is prohibited when an external bus is used. Do not write to these registers. (5) Analog Input Enable Register ADER 7 6 Address : 00001FH ADE7 ADE6 Initial value Access 5 4 3 2 1 0 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111B R/W This register controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The default value at reset is all "1". (6) Up/down Timer Input Enable Register UDER 7 6 5 Address : 00000BH UDE5 4 3 2 1 0 UDE4 UDE3 UDE2 UDE1 UDE0 Initial value Access XX000000B R/W This register controls the port 3 pins as follows. 0 : Port input mode. 1 : Up/down timer input mode.The default value at reset is "0". 35 MB90480/485 Series 2. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK synchronized communication. * Full duplex double buffer * Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) . * Multi-processor mode supported. * Embedded proprietary baud rate generator Asynchronous : 76923/38461/19230/9615/500 k/250 kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 kbps * External clock setting available, allows use of any desired baud rate. * Can use internal clock feed from PPG1. * Data length : 7-bit (asynchronous normal mode only) or 8-bit. * Master/slave type communication functions (in multi-processor mode) . * Error detection functions (parity, framing, overrun) * Transfer signals are NRZ encoded. * DMAC supported (for receiving/sending) 36 MB90480/485 Series (1) Register List 8 7 15 0 CDCR SCR SMR SSR SIDR (R)/SODR (W) 8 bits 8 bits Serial mode register (SMR) 000020H 7 6 5 4 3 2 1 0 MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W X Initial value Serial control register (SCR) 000021H 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 1 R/W 0 R/W 0 Initial value Serial I/O register (SIDR/SODR) 000022H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Initial value Serial status register (SSR) 000023H 15 14 13 12 11 10 9 8 PE ORE FRE RDRF TDRE BDS RIE TIE R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 0 R/W 0 Initial value Communication prescaler control register (CDCR) 000025H 15 14 13 12 11 10 9 8 MD SRST DIV3 DIV2 DIV1 DIV0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Initial value 37 MB90480/485 Series (2) Block Diagram Control signal Receiving interrupt (to CPU) Proprietary baud rate generator PPG1 (internal connection) SCK0 Clock select circuit Sending clock Receiving clock Sending interrupt (to CPU) External clock SIN0 Receiving control circuit Start bit detect circuit Sending control circuit Send start circuit Receive bit counter Send bit counter Receiving parity counter Send parity counter SOT0 Receiving status decision circuit Receiving shifter Sending shifter Receiving control circuit DMAC receiving error generation circuit (to CPU) Sending start SIDR SODR F2MC-16LX BUS SMR MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR PEN P SBL CL A/D REC RXE TXE SSR PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 38 MB90480/485 Series 3. Expanded I/O Serial Interface The expanded I/O serial interface is an 8-bit x 1-channel serial I/O interface for clock synchronized data transfer. A selection of LSB-first or MSB-first data transfer is provided. There are two serial I/O operation modes. * Internal shift clock mode : Data transfer is synchronized with the internal clock signal. * External shift clock mode : Data transfer is synchronized with a clock signal input from the external clock signal pin (SCK) . In this mode the general-purpose port that shares the external clock signal pin (SCK) can be used for transfer according to CPU instructions. (1) Register List Serial mode control status register 0/1 (SMCS0, SMCS1) Address : 000027H 00002BH Address : 000026H 00002AH 15 14 13 12 11 10 9 8 Initial value SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT 00000010B R/W R/W R/W R/W R/W R R/W R/W 7 6 5 4 3 2 1 0 MODE BDS SOE SCOE R/W R/W R/W R/W ----0000B Serial data register 0/1 (SDR0, SDR1) Address : 000028H 00002CH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB Communication prescaler control register 0/1 (SDCR0, SDCR1) Address : 000029H 00002DH 15 14 13 12 11 10 9 8 MD DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W 0---0000B 39 MB90480/485 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Transfer direction selection Initial value SIN1, SIN2 SDR (Serial Data Register) Read Write SOT1, SOT2 SCK1, SCK2 Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus 40 SOE SCOE MB90480/485 Series 4. 8/10-bit A/D Converter The A/D converter converts analog input voltage to digital values, and provides the following features. * Conversion time : minimum 3.68 s per channel (92 machine cycles at 25 MHz machine clock, including sampling time) * Sampling time : minimum 1.92 s per channel (48 machine cycles at 25 MHz machine clock) * RC sequential comparison conversion method, with sample & hold circuit. * 8-bit or 10-bit resolution * Analog input selection of 8 channels Single conversion mode : Conversion from one selected channel. Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to 8 channels. Continuous conversion mode : Repeated conversion of specified channels. Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to synchronize with conversion start. * At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU. The interrupt can be used activate the DMAC in order to transfer the results of A/D conversion to memory for efficient continuous processing. * The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status register) ADCS1 7 6 5 Address : 000046H MD1 MD0 ANS2 ADCS2 Address : 000047H 3 2 1 0 ANS1 ANS0 ANE2 ANE1 ANE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 0 R/W 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 X R X R X R X R X R X R X R X R 15 14 13 12 11 10 9 8 S10 ST1 ST0 CT1 CT0 D9 D8 0 W 0 W 0 W 0 W 0 W X R X R X R ADCR2, ADCR1 (Data register) ADCR1 7 Address : 000048H D7 ADCR2 Address : 000049H 4 Initial value Bit attributes Initial value Bit attributes Initial value Bit attributes Initial value Bit attributes 41 MB90480/485 Series (2) Block Diagram AVCC AVRH AVSS D/A converter MP Input circuit Sequential comparison register Comparator Data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Decoder Sample & hold circuit Data registers ADCR1, ADCR2 A/D control register 1 A/D control register 2 ADTG Trigger activation Timer (PPG1 output) 42 Timer activation ADCS1, ADCS2 Operation clock Prescaler MB90480/485 Series 5. 8/16-bit PPG The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer operation. Hardware resources include 6 x 8-bit down counters, 12 x 8-bit reload timers, 3 x 16-bit control registers, 6 x external pulse output pins, and 6 x interrupt outputs. Note that MB90480/485 series has six channels for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate as a three-channel 16-bit PPG. The following is a summary of functions. * 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels. * 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5. * 8 + 8-bit PPG output operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/ PPG5) to provide to 8-bit PPG output at any desired period length. * PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also be used with external circuits as a D/A converter. (1) Register List PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register) 00003AH 00003CH 00003EH 7 6 5 4 3 2 1 0 PEN0 PE00 PIE0 PUF0 Reserved R/W 0 X R/W 0 R/W 0 R/W 0 X 1 X Read/write Initial value PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register) 00003BH 00003DH 00003FH 15 14 13 12 11 10 9 8 PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved R/W 0 X R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 1 0 Read/write Initial value PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register) 000040H 000042H 000044H 7 6 5 4 3 PCS2 PCS1 PCS0 PCM2 PCM1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 D04 D03 D02 D01 D00 R/W X R/W X R/W X R/W X R/W X PPLL0 to PPLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H R/W R/W R/W 000034H X X X 000036H 000038H PPLH0 to PPLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H R/W R/W R/W 000035H X X X 000037H 000039H 2 PCM0 Reserved Reserved 12 11 10 9 8 D12 D11 D10 D09 D08 R/W X R/W X R/W X R/W X R/W X Read/write Initial value Read/write Initial value Read/write Initial value 43 MB90480/485 Series (2) Block Diagram * 8-bit PPG ch.0/2/4 block Diagram Peripheral clock x 16 Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG0/2/4 output enable PPG0/2/4 A/D converter PPG0/2/4 output latch PEN0 S R Q PCNT (down counter) Count clock select IRQ ch.1/3/5 borrow "L"/"H" selector Timebase counter output main clock x 512 PUF0 PIE0 "L"/"H" select PRLL PRLBH PPGC0 (operation mode control) PRLL "L" data bus "H" data bus 44 MB90480/485 Series * 8-bit PPG ch.1/3/5 Block Diagram Peripheral clock x 16 Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG1/3/5 output enable PPG1/3/5 UART0 PPG1/3/5 output latch PEN1 S R Q PCNT (down counter) IRQ Count clock select "L"/"H" selector Timebase counter output main clock x 512 PUF1 PIE1 "L"/"H" select PRLL PRLBH PPGC1 (operation mode control) PRLL "L" data bus "H" data bus 45 MB90480/485 Series 6. 8/16-bit up/down Counter/Timer 8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits. (1) Principal Functions * 8-bit count register enables counting in the range 0 to 256. (In 16-bit x 1 mode, counting is enabled in the range 0 to 65535) * Count clock selection provides four count modes. Count modes Timer mode Up/down count mode Phase differential down count mode ( x 2) Phase differential down count mode ( x 8) * In timer mode, there is a choice of two internal count clock signals. Count clock 125 ns (8 MHz : x 2) (at 16 MHz operation) 0.5 s (2 MHz : x 8) * In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins. Edge detection Falling edge detection Rising edge detection Both rising/falling edge detection Edge detection disabled * In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc. * The ZIN pin provides a selection of two functions. ZIN pin Counter clear function Gate functions * A compare function and reload function are provided, each for use separately or in combination. Both functions can be activated together for up/down counting in any desired bandwidth. Compare/reload function Compare function (output interrupt at compare events) Compare function (output interrupt and clear counter at compare events) Reload function (output interrupt and reload at underflow events) Compare/reload function (output interrupt and clear counter at compare events, output interrupt and reload at underflow events) Compare/reload disabled * Individual control over interrupts at compare, reload (underflow) and overflow events. * Count direction flag enables identification of the last previous count direction. * Interrupt generated when count direction changes. 46 MB90480/485 Series (2) Register List 8 7 15 0 UDCR1 UDCR0 RCR1 RCR0 Reserved area CSR0 CCRH0 CCRL0 Reserved area CSR1 CCRH1 CCRL1 8-bit 8-bit CCRH0 (Counter Control Register High ch.0) Address : 00006DH 15 14 13 12 11 10 9 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B CCRH1 (Counter Control Register High ch.1) Address : 000071H 15 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W Initial value -0000000B CCRL0/1 (Counter Control Register Low ch.0/ch.1) Address : 00006CH Address : 000070H 7 6 5 4 3 2 1 0 UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W W R/W R/W W R/W R/W R/W Initial value 0X00X000B CSR0/1 (Counter Status Register ch.0/ch.1) Address : 000072H Address : 000074H 7 6 5 4 3 2 1 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 R/W R/W R/W R/W R/W R/W R R Initial value 00000000B UDCR0/1 (Up Down Count Register ch.0/ch.1) Address : 000069H Address : 000068H 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 R R R R R R R R 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 R R R R R R R R Initial value 00000000B Initial value 00000000B RCR0/1 (Reload/Compare Register ch.0/ch.1) Address : 00006BH Address : 00006AH 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 W W W W W W W W 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 W W W W W W W W Initial value 00000000B Initial value 00000000B 47 MB90480/485 Series (3) Block Diagram Data bus 8-bit CGE1 CGE0 CGSC ZIN0 Edge/level detection RCR0 (Reload/ compare register 0) CTUT Reload control RLDE UCRE Counter clear UDCC 8-bit UDCR0 (Up/down count register 0) Carry CES1 CES0 CMS1 CMS0 UDFF OVFF Count clock UDMS AIN0 BIN0 Up/down count clock selection Prescaler CLKS 48 UDF1 UDF0 CDCF CFIE CSTR Interrupt output CITE UDIE CMPF MB90480/485 Series 7. DTP/External Interrupt The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the extended intelligent DMAC or interrupt processing. (1) Detailed Register Descriptions Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register) ENIR 7 6 5 4 3 2 1 Address : 00000CH EN7 EN6 EN5 EN4 EN3 EN2 EN1 R/W R/W R/W R/W R/W R/W 0 EN0 R/W R/W Interrupt/DTP Source Register (EIRR : External Interrupt Request Register) EIRR 15 14 13 12 11 10 9 Address : 00000DH ER7 ER6 ER5 ER4 ER3 ER2 ER1 R/W R/W R/W R/W R/W Initial value 00000000B 8 ER0 R/W R/W R/W Initial value XXXXXXXXB Interrupt Level Setting Register (ELVR : External Level Register) Address : 00000EH Address : 00000FH 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B Initial value 00000000B (2) Block Diagram F2MC-16 bus 4 4 4 8 Interrupt/DTP enable register Gate Source F/F Edge detection circuit 4 Request input Interrupt/DTP source register Interrupt level setting register 49 MB90480/485 Series 8. 16-bit Input/Output Timer The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input capture modules. These functions can be used to output six independent waveforms based on the 16-bit free run timer, enabling input pulse width measurement and external clock frequency measurement. * Register List * 16-bit free run timer 15 0 Compare-clear register 000066/67H CPCLR 000062/63H TCDT Timer counter data register 000064/65H TCCS Control status register * 16-bit output compare 15 0 00004A, 4C, 4E, 50, 52, 54H 00004B, 4D, 4F, 51, 53, 55H 000056, 58, 5AH 000057, 59, 5BH Output compare register OCCP0 to OCCP5 OCS1/3/5 Output compare control registers OCS0/2/4 * 16-bit input capture 15 00005C, 5EH 00005D, 5FH 000060H 50 0 Input capture data register IPCP0, IPCP1 ICS01 Input capture control status register MB90480/485 Series * Block Diagram Control logic To each block Interrupt 16-bit free run timer 16-bit timer Bus Clear Output compare 0 Compare register 0 TQ OUT0 Output compare 1 Compare register 1 TQ OUT1 Output compare 2 Compare register 2 TQ OUT2 Output compare 3 Compare register 3 TQ OUT3 Output compare 4 Compare register 4 TQ OUT4 Output compare 5 Compare register 5 TQ OUT5 Input capture 0 Capture data register 0 Edge selection IN0 Input capture 1 Capture data register 1 Edge selection IN1 51 MB90480/485 Series (1) 16-bit Free Run Timer The 16-bit free run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare. * The counter operation provides a choice of eight clock types. * A counter overflow interrupt can be produced. * A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register. * Register List Compare clear register (CPCLR) 000067H 000066H 15 14 13 12 11 10 9 8 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB Initial value XXXXXXXXB Timer counter data register (TCDT) 000063H 000062H 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 R/W R/W R/W R/W R/W R/W R/W R/W 13 12 11 10 9 8 Initial value 00000000B Initial value 00000000B Timer control status register (TCCS) 15 000065H 000064H 52 14 ECKE MSI2 MSI1 MSI0 ICLR ICRE R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0--00000B Initial value 00000000B MB90480/485 Series * Block Diagram Interrupt request IVF Prescaler IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Bus Clock 16-bit free run timer Count value output T15 to T00 16-bit compare clear register Compare circuit MSI2 to MSI0 ICLR ICRE Interrupt request A/D activation 53 MB90480/485 Series (2) Output Compare The output compare module is composed of a 16-bit compare register, compare output pin unit, and control register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output levels can be inverted and an interrupt generated. * There are six compare registers in all, each operating independently. A setting is available to allow two compare registers to be used to control output. * Interrupts can be set in terms of compare match events. * Register List Output compare registers (OCCP0 to OCCP5) 00004BH 00004DH 00004FH 000051H 000053H 000055H 00004AH 00004CH 00004EH 000050H 000052H 000054H 15 14 13 12 11 10 9 8 C15 C14 C13 C12 C11 C10 C09 C08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B Initial value 00000000B Output control registers (OCS1/OCS3/OCS5) 000057H 000059H 00005BH 15 14 13 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W R/W R/W R/W R/W Initial value ---00000B Output control registers (OCS0/OCS2/OCS4) 000056H 000058H 00005AH 54 7 6 5 4 3 2 1 0 ICPIC ICP0 ICE1 ICE0 CST1 CST0 R/W R/W R/W R/W R/W R/W Initial values 0000--00B MB90480/485 Series * Block Diagram 16-bit timer counter value (T15 to T00) Compare control TQ OTE0 OUT0 (2) (4) OTE1 OUT1 (3) (5) Compare register 0 (2, 4) CMOD Bus 16-bit timer counter value (T15 to T00) Compare control TQ Compare register 1 (3, 5) ICP1 Control unit Individual control blocks ICP0 ICE0 ICE0 Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt 55 MB90480/485 Series (3) Input Capture The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An interrupt can also be generated at the instant of edge detection. The input capture module consists of input capture registers and a control register. Each input capture module has its own external input pin. * Selection of three types of valid edge for external input signals. Rising edge, falling edge, both edges. * An interrupt can be generated when a valid edge is detected in the external input signal. * Register List Input capture data register (IPCP0, IPCP1) 00005DH 00005FH 00005CH 00005EH 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R R R R R R R 7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R R R R R R R R Initial value XXXXXXXXB Initial value XXXXXXXXB Input capture control status register (ICS01) 000060H 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W R/W R/W R/W R/W * Block Diagram Bus Capture data register 0 Edge detection 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Capture data register 1 ICP1 Edge detection ICP0 IN0 ICE1 IN1 ICE0 Interrupt Interrupt 56 Initial value 00000000B MB90480/485 Series 9. I2C Interface (MB90485 series only) The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus. The I2C interface has the following functions. * Master/slave transmit/receive * Arbitration function * Clock synchronization * Slave address/general call address detection function * Forwarding direction detection function * Start condition repeated generation and detection * Bus error detection function (1) Register List Bus Status Register (IBSR) 7 6 5 BB RSC AL R R R 000088H 4 3 2 1 0 Initial value 00000000B LRB TRX AAS GCA FBT R R R R R Bus control register (IBCR) 000089H 15 14 13 12 11 10 9 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W R/W R/W R/W R/W Initial value 8 R/W 00000000B Clock control register (ICCR) 7 00008AH 6 5 4 3 2 1 0 EN CS4 CS3 CS2 CS1 CS0 R/W R/W R/W R/W R/W R/W Initial value --0XXXXXB Address register (IADR) 00008BH 15 14 13 12 11 10 9 8 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W Initial value -XXXXXXXB Data register (IDAR) 00008CH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB 57 MB90480/485 Series (2) Block Diagram ICCR I2C enable EN Clock dividing 1 5 F2MC-16LX Bus ICCR CS4 6 7 Peripheral clock 8 Clock selection 1 CS3 Clock dividing 2 CS2 2 4 8 16 32 64 128 256 CS1 CS0 Sync Shift clock generation Clock selection 2 Change timing of shift clock edge IBSR BB RSC Bus busy Repeat start Last Bit LRB Start/stop condition detection Transmission/ Reception Error TRX First Byte FBT Arbitration lost detection AL IBCR SCL BER BEIE Interrupt request INTE INT IBCR SCC MSS ACK End Start Master ACK enable Start/stop condition detection GC-ACK enable GCAA IDAR IBSR AAS GCA Slave Global call Slave address comparison IADR 58 IRQ SDA MB90480/485 Series 10. 16-bit Reload Timer The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of internal clock, as well as an event count mode that counts down at specified edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in count value from 0000H to FFFFH. Thus an underflow will occur when counting from the value "reload register setting value + 1". The choice of counting operations includes reload mode, in which the count setting values is reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible. (1) Register List * TMCSR (Timer control status register) Timer control status register (high) (TMCSR) 0000CBH 15 14 13 12 11 10 9 8 CSL1 CSL0 MOD2 MOD1 R/W 0 R/W 0 R/W 0 R/W 0 Read/Write Initial value Timer control status register (low) (TMCSR) 0000CAH 7 6 5 4 3 2 1 0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Read/Write Initial value * 16-bit timer register/16-bit reload register TMR/TMRLR (high) 0000CDH 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Read/Write Initial value TMR/TMRLR (low) 0000CCH 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Read/Write Initial value 59 MB90480/485 Series (2) Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal Reload control circuit TMR 16-bit timer register (down counter) UF CLK Count clock generator circuit Machine clock 3 Prescaler Gate input Valid clock detection circuit Clear Wait signal CLK To A/D converter Output signal generation circuit Inverted Pin (TIN0) Input control circuit Clock selector EN External clock Function selection OUTL 3 Select signal Pin (TOT0) Output signal generation circuit 2 RELD Operation control circuit OUTE Timer control status register (TMCSR) 60 MB90480/485 Series 11. PG Timer (MB90485 series only) The PG timer performs pulse output in response to the external input. (1) Register List PG control status register (PGCSR) Initial value 00008EH 7 6 5 4 3 PEN0 PE1 PE0 PMT1 PMT0 R/W R/W R/W R/W R/W 2 1 0 00000---B (2) Block Diagram MT00 MT01 MT00 Output latch Control circuit MT01 Output latch Output enable EXTC 61 MB90480/485 Series 12. PWC Timer (MB90485 series only) The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal. A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. These components provide the following functions. Timer function : * Capable of generating an interrupt request at fixed intervals specified. * The internal clock used as the reference clock can be selected from among three types. Pulse width measurement function : * Measures the time between arbitrary events based on external pulse inputs. * The internal clock used as the reference clock can be selected from among three types. * Measurement modes - "H" pulse width ( to ) /"L" pulse width ( to ) - Rising cycle ( to ) /Falling cycle ( to ) - Measurement between edges ( or to or ) * The 8-bit input divider can be used for division measurement by dividing the input pulse by 22 x n (n = 1, 2, 3, 4) . * An interrupt can be generated upon completion of measurement. * One-time measurement or fast measurement can be selected. 62 MB90480/485 Series (1) Register list PWC control/status register (PWCSR0 to PWCSR2) 000077H 00007BH 00007FH 15 14 13 12 11 10 9 STRT STOP EDIR EDIE OVIR OVIE R/W R/W R R/W R/W R/W R 2 1 8 Initial value 0000000XB ERR Reserved PWC control/status register (PWCSR0 to PWCSR2) 000076H 00007AH 00007EH 7 6 5 4 3 0 CKS1 CKS0 PIS1 PIS0 S/C R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B MOD2 MOD1 MOD0 PWC data buffer register (PWCR0 to PWCR2) 000079H 00007DH 000081H 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W 3 2 1 0 Initial value 00000000B PWC data buffer register (PWCR0 to PWCR2) 000078H 00007CH 000080H 7 6 5 4 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 3 2 1 0 DIV1 DIV0 R/W R/W Initial value 00000000B Dividing ratio control register (DIVR0 to DIVR2) 000082H 000084H 000086H 7 6 5 4 Initial value ------00B 63 MB90480/485 Series (2) Block Diagram PWCR read Error detection ERR Internal clock (machine clock/4) PWCR 16 Reload Data transfer 16 22 Clock Overflow 16-bit up count timer Clock divider 23 F2MC-16 Bus Timer clear Count enable Control bit output Flag set etc. Control circuit Start edge selection Completion edge selection Start of measurement edge CKS1/CKS0 Dividing ON/OFF Input waveform comparator Edge detection Completion of measurement edge PIS0/PIS1 Completion of measurement interrupt request Overflow interrupt request PWCSR ERR 8-bit divider CKS0/ CKS1 Dividing ratio selection 15 2 64 Divider clear DIVR PWC0 PWC1 MB90480/485 Series 13. Watch Timer The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer. (1) Register List Watch timer control register (WTC) 0000AAH 7 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W 1 R 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 Read/write Initial value (2) Block Diagram Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clear 28 29 Sub clock Watch counter 210 211 Interval selector Interrupt generator circuit Watch timer interrupt 212 213 210 213 214 215 214 To watchdog timer 65 MB90480/485 Series 14. Watchdog timer The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated. (1) Register List Watchdog timer control register (WDTC) 0000A8H 7 6 5 4 3 2 1 0 PONR Reserved WRST ERST SRST WTE WT1 WT0 R X X R X R X R X W 1 W 1 W 1 Read/write Initial value (2) Block Diagram Watchdog timer control register (WDTC) Re- PONR served WRST ERST SRST WTE WT1 WT0 2 Watch mode start Timebase timer mode start Sleep mode start Hold status start CLR and start Watchdog timer Stop mode start Counter clear control circuit Count clock selector 2-bit counter CLR Watch timer control register (WTO) WDCS bit Clock select register (CKSCR) SCM bit CLR Watchdog reset generator circuit 4 4 Clear Time-base counter HCLK x 2 SCLK x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK : Oscillator clock SCLK : Sub clock 66 Internal reset generator circuit MB90480/485 Series 15. Timebase Timer The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the internal count clock signal (base oscillator x 2) , and functions as an interval timer with a choice of four types of time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait period, and operating clock signal feed for other timer circuits such as the watchdog timer. (1) Register List Timebase timer control register (TBTC) 0000A9H 15 14 13 12 11 10 9 8 RESV TBIE TBOF TBR TBC1 TBC0 R/W 1 X X R/W 0 R/W 0 W 1 R/W 0 R/W 0 Read/write Initial value (2) Block Diagram To PPG timer To watchdog timer Timebase timer counter HCLK x 2 x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 Power-on reset Stop mode start Hold status start CKSCR : MCS = 10*1 CKSCR : SCS = 01*2 OF OF OF OF To clock control module oscillator stabilization wait time selector Counter clear control circuit Interval timer selector TBOF set TBOF clear Timebase timer control register (TBTC) RESV TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 : Overflow : Oscillator clock : Switch machine clock from main clock or sub clock to PLL clock. : Switch machine clock from sub clock to main clock. 67 MB90480/485 Series 16. Clock The clock generator module controls the operation of the internal clock circuits that serve as the operating clock for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle is referred to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from the PLL oscillator are called the PLL clock. (1) Register List Clock select register (CKSCR) 0000A1H 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 0 Read/write Initial value PLL output select register (PLLOS) 0000CFH 68 15 14 13 12 11 10 9 8 PLL2 W X W 0 Read/write Initial value MB90480/485 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin high-impedance control Pin high-impedance control circuit RST Internal reset generator circuit pin CPU intermittent operation selector Internal reset Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Peripheral clock Oscillator stabilization wait release Clock generator module PLL output select register (PLLOS) Clock selector Oscillator stabilization wait period selector PLL2 2 SCLK x4 2 PLL multiplier circuit Sub clock generator circuit X0A pin X1A pin SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) System clock generator circuit x2 HCLK X0 CPU clock pin X1 pin x 1024 x2 x4 x4 x4 x2 MCLK Timebase timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock To watchdog timer 69 MB90480/485 Series (3) Clock Feed Map 4 Peripheral functions Watchdog timer 4 Clock generator module X0A pin Sub clock generator circuit X1A pin Watch timer Timebase timer 8/16-bit PPG timer 1 PPG2, PPG3 8/16-bit PPG timer 2 PPG4, PPG5 1 2 x4 pin X1 pin 3 4 PLL multiplier circuit SCLK X0 System clock x2 generator HCLK MCLK circuit PPG0, PPG1 8/16-bit PPG timer 0 pins pins TIN0 16-bit reload timer 0 PCLK Clock selector pins pin TOT0 pin SCK0, SIN0 pins UART0 SOT0 pin CPU, DMAC SCK1, SCK2 SIN1, SIN2 Extended I/O serial interface, 2 channels 8/16-bit up/down counter pins SOT1, SOT2 pins AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 pins CS0, CS1, CS2, CS3 Chip select 16-bit output compare 16-bit free run timer 16-bit input capture 10-bit A/D converter pins OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 pins FRCK pin IN0, IN1 pins AN0 to AN7, ADTG pins IRQ0 to IRQ7 HCLK MCLK SCLK PCLK 70 : Oscillator clock : Main clock : Sub clock : PLL clock : Machine clock External interrupt 3 Oscillator stabilization wait control pin MB90480/485 Series 17. Low-power Consumption Mode The MB90480/485 series uses operating clock selection and clock operation controls to provide the following CPU operating modes : * Clock modes (PLL clock mode, main clock mode, sub clock mode) * CPU intermittent operating modes (PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode) * Standby modes (Sleep mode, timebase timer mode, stop mode, watch mode) (1) Register List Low-power consumption mode control register (LPMCR) 0000A0H 7 6 5 4 3 2 1 0 STP SLP SPL RST TMD CG1 CG0 Reserved W 0 W 0 R/W 0 W 1 R/W 1 R/W 0 R/W 0 R/W 0 Read/write Initial value 71 MB90480/485 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) Re- STP SLP SPL RST TMD CG1 CG0 served RST Pin high-impedance control circuit Pin high-impedance control Internal reset generator circuit pin CPU intermittent operating selector Internal reset Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release CPU clock Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Oscillator stabilization wait release Clock generator module PLL output select register (PLLOS) Clock selector Oscillator stabilization wait period selector PLL2 2 SCLK x4 2 PLL multiplier circuit Sub clock generator circuit X0A X1A Peripheral clock SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) System clock generator circuit pin x2 pin HCLK X0 pin X1 pin x 1024 x2 x4 x4 x4 MCLK Timebase timer To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock 72 x2 MB90480/485 Series (3) Status Transition Chart External reset, watchdog timer reset, software reset Power-on Reset SCS = 0 Power-on reset SCS = 1 Main clock mode Oscillator stabilization wait ends SLP = 1 MCS = 0 PLL clock mode MCS = 1 Interrupt SLP = 1 Interrupt Main timebase timer mode STP = 1 Interrupt TMD = 0 Interrupt PLL timebase timer mode STP = 1 Main stop mode Interrupt Oscillator stabilization wait ends Sub clock mode SCS = 1 SLP = 1 PLL sleep mode Main sleep mode TMD = 0 SCS = 0 Interrupt Sub sleep mode TMD = 0 Interrupt Watch mode STP = 1 PLL stop mode Interrupt Oscillator stabilization wait ends Sub stop mode Interrupt Oscillator stabilization wait ends Main clock oscillator Main clock oscillator Sub clock oscillator stabilization wait stabilization wait stabilization wait 73 MB90480/485 Series 18. External Bus Pin Control Circuit The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List * Auto ready function select register (ARSR) Address : 0000A5H 15 14 13 12 11 10 9 8 IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 W W W W W W Initial value 0011--00B * External address output control register (HACR) Address : 0000A6H 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 W W W W W W W W Initial value ********B * Bus control signal select register (EPCR) Address : 0000A7H W - * 15 14 13 12 11 10 9 8 CKE RYE HDE IOBS HMBS WRE LMBS W W W W W W W Initial value 1000*10-B : Write only : Not used : May be either "1" or "0" (2) Block Diagram P5 P0 P0 data P0 direction RB Data control Address control Access control 74 Access control P1 P2 P3 P4 P5 P0 MB90480/485 Series 19. Chip Select Function Description The chip select module generates a chip select signals, which are used to facilitate connections to external memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding external address is detected. * Chip select function features The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to detect memory areas in 64 Kbytes units by specifying the upper 8-bit of the address for match detection. The other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match detection. Note that during external bus holds, the CS output is set to high impedance. (1) Register List 8 7 15 0 CAR0 CMR0 R/W CAR1 CMR1 R/W CAR2 CMR2 R/W CAR3 CMR3 R/W CALR CSCR R/W Chip select area mask register (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H 7 6 5 4 3 2 1 0 M7 M6 M5 M4 M3 M2 M1 M0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 Read/write Initial value Chip select area register (CARx) 0000C1H 0000C3H 0000C5H 0000C7H 15 14 13 12 11 10 9 8 A7 A6 A5 A4 A3 A2 A1 A0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Read/write Initial value Chip select control register (CSCR) 0000C8H 7 6 5 4 3 2 1 0 OPL3 OPL2 OPL1 OPL0 R/W 0 R/W 0 R/W 0 R/W * Read/write Initial value Chip select active level register (CALR) 0000C9H 15 14 13 12 11 10 9 8 ACTL3 ACTL2 ACTL1 ACTL0 R/W 0 R/W 0 R/W 0 R/W 0 Read/write Initial value * : The initial value of this bit is "1" or "0". The value depends on the mode pin (MD2, MD1 and MD0) . 75 MB90480/485 Series F2MC-16LX Bus (2) Block Diagram CMRx CARx Chip select output pins A23 to A16 76 MB90480/485 Series 20. ROM Mirror Function Select Module The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. (1) Register List * ROM mirror function select register (ROMM) Address : 00006FH 15 14 13 12 11 10 9 8 MS MI R/W R/W (+) Initial value ------+1B ( + ) : MB90F489B : Read only, fixed at "1" Other : Selectable, Initial value 0 - : Not used (2) Block Diagram F2MC-16LX bus ROM mirror function select Address area 00 bank FF bank ROM Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000H to 00FFFFH (008000H to 00FFFFH) . 77 MB90480/485 Series 21. Interrupt Controller The interrupt control register is built in interrupt controller, and is supported for all I/O of interrupt function. This register sets corresponding peripheral interrupt level. (1) Register List Interrupt control registers Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H 0000B5H 0000B7H 0000B9H 0000BBH 0000BDH 0000BFH Read/write Initial value 15 14 13 12 11 10 Reserved W X W X W X W X R/W 0 9 8 IL2 IL1 IL0 R/W 1 R/W 1 R/W 1 ICR01, 03, 05, 07, 09, 11, 13, 15 Interrupt control registers Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH Read/write Initial value 7 6 5 4 3 Reserved W X W X W X W X R/W 0 2 1 0 IL2 IL1 IL0 R/W 1 R/W 1 R/W 1 ICR00, 02, 04, 06, 08, 10, 12, 14 Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be avoided. 78 MB90480/485 Series (2) Block Diagram F2MC-16LX Bus 3 IL2 IL1 IL0 3 32 Interrupt requests (Peripheral resources) 3 (CPU) Interrupt level Interrupt priority setting 79 MB90480/485 Series 22. DMAC The DMAC is a simplified DMA module with functions equivalent to EI2OS. The DMAC has 16 DMA data transfer channels, and provides the following functions. * Automatic data transfer between peripheral resources (I/O) and memory. * CPU program execution stops during DMA operation. * Incremental addressing for transfer source and destination can be turned on/off. * DMA transfer control from the DMAC enable register, DMAC stop status register, DMAC status register, and descriptor. * Stop requests from resources can stop DMA transfer. * When DMA transfer is completed, the DMAC status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a completion interrupt to the interrupt controller. (1) Register List DMAC enable register DERH : 0000ADH 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DE15 DE14 DE13 DE12 DE11 DE10 DE9 DE8 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B DMAC enable register DERL : 0000ACH Initial value 00000000B DMAC stop status register DSSR : 0000A4H Initial value 00000000B DMAC status register DSRH : 00009DH Initial value 00000000B DMAC status register DSRL : 00009CH 80 Initial value 00000000B MB90480/485 Series (2) Block Diagram Memory space IOA I/O register DMA transfer request If transfer not ended DMAC descriptor Read by DER DMA controller If transfer is ended BAP Transfer Buffer DCT CPU IOA BAP DER DCT Peripheral function (I/O) F2MC-16LX Bus I/O register Interrupt controller : I/O address pointer : Buffer address pointer : DMAC enable register (ENx selection) : Data counter 81 MB90480/485 Series 23. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register List * Program address detection register 0 (PADR0) Address 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W PADR0 (Low order address) : 001FF0H Address PADR0 (Middle order address) : 001FF1H Address PADR0 (High order address) : 001FF2H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B * Program address detection register 1 (PADR1) Address 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 3 2 1 0 AD0E RESV R/W R/W PADR1 (Low order address) : 001FF3H Address PADR1 (Middle order address) : 001FF4H Address PADR1 (High order address) : 001FF5H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B * Program address detection control status register (PACSR) Address 7 00009EH RESV R/W R/W : Readable and writable X : Undefined RESV : Reserved bit 82 6 5 RESV RESV R/W R/W 4 RESV AD1E RESV R/W R/W R/W Initial value 00000000 B MB90480/485 Series Internal data bus Address latch Address detection register Enable bit Compare (2) Block Diagram INT9 instruction F2MC-16LX CPU core 83 MB90480/485 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC3 VSS - 0.3 VSS + 4.0 V VCC5 VSS - 0.3 VSS + 7.0 V AVCC VSS - 0.3 VSS + 4.0 V *2 AVRH VSS - 0.3 VSS + 4.0 V *2 VSS - 0.3 VSS + 4.0 V *3 VSS - 0.3 VSS + 7.0 V *3, *8, *9 VSS - 0.3 VSS + 4.0 V *3 VSS - 0.3 VSS + 7.0 V *3, *8, *9 ICLAMP -2.0 +2.0 mA *7 ICLAMP 20 mA *7 IOL 10 mA *4 "L" level average output current IOLAV 3 mA *5 "L" level maximum total output current IOL 60 mA "L" level total average output current IOLAV 30 mA *6 IOH -10 mA *4 "H" level average output current IOHAV -3 mA *5 "H" level maximum total output current IOH -60 mA "H" level total average output current IOHAV -30 mA Power consumption PD 320 mW Operating temperature TA -40 +85 C Tstg -55 +150 C Power supply voltage*1 Input voltage*1 VI Output voltage*1 VO Maximum clamp current Total maximum clamp current "L" level maximum output current "H" level maximum output current Storage temperature *6 *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : VI and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value for one of the corresponding pins. *5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (Continued) 84 MB90480/485 Series (Continued) * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: * Input/Output Equivalent circuits Protective diode +B input (0 V to 16 V) VCC Limiting resistance P-ch N-ch R *8 : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. P76 and P77 is N-ch open drain pin. *9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 85 MB90480/485 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol Value Unit Max 2.7 3.6 V During normal operation 1.8 3.6 V To maintain RAM state in stop mode 2.7 5.5 V During normal operation* 1.8 5.5 V To maintain RAM state in stop mode* VIH 0.7 VCC VCC + 0.3 V All pins other than VIH2, VIHS, VIHM and VIHX VIH2 0.7 VCC VSS + 5.8 V MB90485 series only P76, P77 pins (N-ch open drain pins) VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins VIHM VCC - 0.3 VCC + 0.3 V MD pin input VIHX 0.8 VCC VCC + 0.3 V X0A pin, X1A pin VIL VSS - 0.3 0.3 VCC V All pins other than VILS, VILM and VILX VILS VSS - 0.3 0.2 VCC V Hysteresis input pins VILM VSS - 0.3 VSS + 0.3 V MD pin input VILX VSS - 0.3 0.1 V X0A pin, X1A pin TA -40 +85 C VCC3 Power supply voltage VCC5 "H" level input voltage "L" level input voltage Operating temperature Remarks Min * : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 86 MB90480/485 Series 3. DC Characteristics (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name "H" level output voltage VOH "L" level output voltage VOL Input leakage current Pull-up resistance Open drain output current IIL All output pins All output pins All input pins RPULL Ileak P40 to P47, P70 to P77 ICC ICCS ICCL ICCT ICCH CIN Other than AVCC, AVSS, VCC, VSS Power supply current Input capacitance Condition VCC = 2.7 V, IOH = -1.6 mA VCC = 4.5 V, IOH = -4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, VSS < VI < VCC VCC = 3.0 V, at TA = +25 C At VCC = 3.3 V, internal 25 MHz operation, normal operation At VCC = 3.3 V, internal 25 MHz operation, Flash programming At VCC = 3.3 V, internal 25 MHz operation, sleep mode At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, sub clock operation (TA = +25 C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, watch mode (TA = +25 C) TA = +25 C, stop mode, At VCC = 3.3 V Min Value Typ Max Unit VCC3 - 0.3 V VCC5 - 0.5 V 0.4 V 0.4 V -10 +10 A 20 53 200 k 0.1 10 A 45 60 mA 55 70 mA 17 35 mA 15 140 A 1.8 40 A 0.8 40 A 5 15 pF Remarks At using 5 V power supply At using 5 V power supply Notes :* MB90485 series only * P40 to P47 and P70 to P77 are N-ch open drain pins with control, which are usually used as CMOS. * P76 and P77 are open drain pins without P-ch. * For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. * When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins. 87 MB90480/485 Series 4. AC Characteristics (1) Clock Timing (VSS = 0.0 V, TA = -40 C to +85 C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time SymPin name bol FCH X0, X1 Min Typ Max 3 25 External crystal oscillator 3 50 External clock input 4 25 1 multiplied PLL 3 12.5 3 6.66 MHz 2 multiplied PLL 3 multiplied PLL 3 6.25 4 multiplied PLL 3 4.16 6 multiplied PLL 3 3.12 8 multiplied PLL Unit Remarks FCL X0A, X1A 32.768 kHz tC X0, X1 20 333 ns tCL X0A, X1A 30.5 s PWH PWL X0 5 ns PWLH PWLL X0A 15.2 s *2 tcr tcf X0 5 ns With external clock fCP 1.5 25 MHz *1 fCPL 8.192 kHz tCP 40.0 666 ns tCPL 122.1 s *1 : Be careful of the operating voltage. *2 : Duty ratio should be 50 % 3 %. 88 Value Condition *1 *1 MB90480/485 Series * X0, X1 clock timing tC 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr * X0A, X1A clock timing tCL 0.8 VCC X0A 0.2 VCC PWLH PWLL tcf tcr 89 MB90480/485 Series * Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage Power supply voltage VCC (V) 3.6 Range of warranted PLL operation 3.0 2.7 Normal operating range 1.5 16 4 25 Internal clock fCP (MHz) Notes: * For A/D operating frequency, refer to "5. A/D Converter Electrical Characteristics" * Only at 1 multiplied PLL, use with more than fCP = 4 MHz. Base oscillator frequency vs. Internal operating clock frequency Internal clock fCP (MHz) 25 24 8 x *3 6 x *3 20 18 16 No multiplied 3 x *1 2 x *1,*2 1 x *1 4x *1,*2 12 9 8 6 4 1.5 3 4 5 6 8 10 12.5 16 20 25 32 40 50 Base oscillator clock FCH (MHz) *1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP 25 MHz, set the PLLOS register to "DIV2 bit = 1" and "PLL2 bit = 1". [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "0" PLLOS register : PLL2 bit = "1" [Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "0" PLLOS register : PLL2 bit = "1" *2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP 25 MHz, the following setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "0" PLLOS register : PLL2 bit = "1" 4 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "1" PLLOS register : PLL2 bit = "1" *3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to "DIV2 bit = 0" and "PLL2 bit = 1". [Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "0" PLLOS register : PLL2 bit = "1" [Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "1" PLLOS register : PLL2 bit = "1" 90 MB90480/485 Series AC standards are set at the following measurement voltage values. * Input signal waveform Hysteresis input pins * Output signal waveform Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V * Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC 91 MB90480/485 Series (2) Clock Output Timing (VSS = 0.0 V, TA = -40 C to +85 C) Parameter Cycle time CLKCLK Symbol Pin name tCYC tCHCL Conditions CLK CLK Value Min Max tCP* ns ns at fCP = 25 MHz VCC = 2.7 V to 3.3 V tCP* / 2 - 20 tCP* / 2 + 20 ns at fCP = 16 MHz VCC = 2.7 V to 3.3 V tCP* / 2 - 64 tCP* / 2 + 64 ns at fCP = 5 MHz tCYC tCHCL 2.4 V 92 Remarks VCC = 3.0 V to 3.6 V tCP* / 2 - 15 tCP* / 2 + 15 * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". CLK Unit 2.4 V 0.8 V MB90480/485 Series (3) Reset Input Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Reset input time Symbol Pin name tRSTL Value Conditions RST Unit Remarks ns Normal operation ms Stop mode Min Max 16 tCP*1 Oscillator oscillation time*2 + 4 tCP*1 *1 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". *2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. * In stop mode tRSTL RST 0.2 Vcc X0 0.2 Vcc 90 % of amplitude Internal operating clock Oscillator oscillation time 4 tCP Oscillator stabilization wait time Instruction execution Internal reset * Condition for measurement of AC standards CL : Load capacitance applied to pins during testing CLK, ALE : CL = 30 pF AD15 to AD00 (address data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF Pin CL 93 MB90480/485 Series (4) Power-on Reset Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Power rise time Power down time Pin name Conditions tR VCC tOFF VCC Value Unit Remarks Min Max 0.05 30 ms * 1 ms In repeated operation * : Power rise time requires VCC < 0.2 V. Notes: * The above standards are for the application of a power-on reset. * Within the device, the power-on reset should be applied by switching the power supply off and on again. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Note : Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied. Main power supply voltage VCC Sub power supply voltage VSS 94 RAM data maintenance The slope of voltage increase should be kept within 50 mV/ms. MB90480/485 Series (5) Bus Read Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Parameter ALE pulse width Symbol Pin name tLHLL ALE Conditions Value Unit Remarks Min Max tCP* / 2 - 15 ns 16 MHz < fCP 25 MHz tCP* / 2 - 20 ns 8 MHz < fCP 16 MHz tCP* / 2 - 35 ns fCP 8 MHz tCP* / 2 - 17 ns tCP* / 2 - 40 ns Valid address ALEtime tAVLL Address, ALE ALE address valid time tLLAX ALE, Address tCP* / 2 - 15 ns Valid address RDtime tAVRL RD, address tCP* - 25 ns Valid address valid data input tAVDV Address, Data 5 tCP* / 2 - 55 ns 5 tCP* / 2 - 80 ns fCP 8 MHz 3 tCP* / 2 - 25 ns 16 MHz < fCP 25 MHz 3 tCP* / 2 - 20 ns 8 MHz < fCP 16 MHz 3 tCP* / 2 - 55 ns 3 tCP* / 2 - 80 ns RD pulse width tRLRH RD RD valid data input tRLDV RD, Data RDdata hold time tRHDX RD, Data 0 ns RDALEtime tRHLH RD, ALE tCP* / 2 - 15 ns RD address valid time tRHAX Address, RD tCP* / 2 - 10 ns Valid address CLKtime tAVCH Address, CLK tCP* / 2 - 17 ns RDCLKtime tRLCH RD, CLK tCP* / 2 - 17 ns ALERDtime tLLRL RD, ALE tCP* / 2 - 15 ns fCP 8 MHz fCP 8 MHz * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". 95 MB90480/485 Series tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V 2.4 V ALE tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL In multiplexed mode tAVRL A23 to A16 tRLDV 2.4 V 2.4 V 0.8 V 0.8 V tAVDV 2.4 V 2.4 V tRHDX 0.7 VCC 0.8 V 0.7 VCC Read data Address AD15 to AD00 0.8 V 0.3 VCC 0.3 VCC tRHAX In non-multiplexed mode A23 to A00 tRHAX 2.4 V 2.4 V 0.8 V 0.8 V tRLDV tRHDX tAVDV 0.7 VCC 0.3 VCC 96 0.7 VCC Read data D15 to D00 0.3 VCC MB90480/485 Series (6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Parameter Valid addressWRtime WR pulse width Pin name Condition Min Max tAVWL Address, WR tCP* - 15 ns 3 tCP* / 2 - 25 ns 16 MHz < fCP 25 MHz 3 tCP* / 2 - 20 ns 8 MHz < fCP 16 MHz 3 tCP* / 2 - 15 ns 10 ns 16 MHz < fCP 25 MHz 20 ns 8 MHz < fCP 16 MHz 30 ns fCP 8 MHz tWLWH Valid data output WRtime tDVWH WRdata hold time Value Symbol tWHDX Unit WRL, WRH Data, WR WR, Data WRaddress valid time tWHAX WR, Address tCP* / 2 - 10 ns WRALEtime tWHLH WR, ALE tCP* / 2 - 15 ns WRCLKtime tWLCH WR, CLK tCP* / 2 - 17 ns Remarks * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". 97 MB90480/485 Series tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH 2.4 V WR (WRL, WRH) 0.8 V In multiplexed mode tAVWL A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH 2.4 V Address AD15 to AD00 0.8 V 2.4 V 0.8 V 2.4 V Write data 0.8 V In non-multiplexed mode A23 to A00 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH D15 to D00 98 tWHDX 2.4 V 0.8 V Write data tWHDX 2.4 V 0.8 V MB90480/485 Series (7) Ready Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Parameter Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name Conditions RDY Value Unit Min Max 35 ns 70 ns 0 ns 2.4 V Remarks at fCP = 8 MHz 2.4 V CLK ALE RD/WR tRYHS tRYHH RDY wait not inserted RDY wait inserted (1 cycle) 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tRYHS 99 MB90480/485 Series (8) Hold Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = - 40 C to +85 C) Parameter Symbol Pin name Pin floatingHAKtime tXHAL HAK HAKpin valid time tHAHV HAK Value Conditions Unit Min Max 30 tCP* ns tCP* 2 tCP* ns Remarks * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes. HAK 2.4 V 0.8 V tXHAL High-Z 2.4 V Pins tHAHV 2.4 V 0.8 V 0.8 V (9) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Serial clock cycle time tSCYC SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX tSHSL Serial clock "L" pulse width tSLSH SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX Parameter Serial clock "H" pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL External shift clock mode output pins : CL*1 = 80 pF + 1 TTL 100 Unit Min Max 8 tCP*2 ns -80 +80 ns -120 +120 ns 100 ns 200 ns tCP*2 ns CP 2 ns CP 2 4t * ns 150 ns 200 ns 60 ns 120 ns 60 ns 120 ns 4t * *1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". Note : The above rating is in CLK synchronous mode. Value Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz MB90480/485 Series * Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 101 MB90480/485 Series (10) Extended I/O Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Serial clock cycle time tSCYC SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX tSHSL Serial clock "L" pulse width tSLSH SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX Parameter Serial clock "H" pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL External shift clock mode output pins : CL*1 = 80 pF + 1 TTL *2 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". Notes : * The above rating is in CLK synchronous mode. * Values on this table are target values. Unit Min Max 8 tCP*2 ns -80 + 80 ns -120 + 120 ns 100 ns 200 ns tCP*2 ns CP 2 ns CP 2 4t * ns 150 ns 200 ns 60 ns 120 ns 60 ns 120 ns 4t * *1 : CL is the load capacitance applied to pins for testing. 102 Value Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz MB90480/485 Series * Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 103 MB90480/485 Series (11) Timer Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol Pin name Conditions tTIWH tTIWL TIN0, IN0, IN1, PWC0 to PWC2 Value Min Max 4 tCP* Unit Remarks ns * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". 0.8 VCC TIN0 IN0, IN1 PWC0 to PWC2 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (12) Timer Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Conditions CLKChange time PPG0 to PPG5 change time OUT0 to OUT5 change time tTO TOT0, PPG0 to PPG5, OUT0 to OUT5 Load conditions 80 pF CLK TOT0 PPG0 to PPG5 OUT0 to OUT5 0.7 VCC 0.7 VCC 0.3 VCC tTO 104 Value Min Max 30 Unit Remarks ns MB90480/485 Series (13) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter SCL clock frequency Hold time (repeated) START condition SDASCL Symbol tHDSTA tLOW "H" width of the SCL clock tHIGH Set-up time (repeated) START condition SCLSDA tSUSTA Data hold time SCLSDA tHDDAT Set-up time for STOP condition SCLSDA Bus free time between a STOP and START condition tSUDAT tSUSTO tBUS Standard-mode Unit Min Max 0 100 kHz 4.0 s 4.7 s 4.0 s 4.7 s 0 3.45*3 s When power supply voltage of external pull-up resistance is 5.5 V fCP*1 20 MHz, R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 20 MHz, R = 1.6 k, C = 50 pF*2 250*4 ns When power supply voltage of external pull-up resistance is 5.5 V fCP*1 > 20 MHz, R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 > 20 MHz, R = 1.6 k, C = 50 pF*2 200*4 ns 4.0 s 4.7 s fSCL "L" width of the SCL clock Data set-up time SDASCL Condition When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 k, C = 50 pF*2 *1 : fCP is internal operation clock frequency. Refer to " (1) Clock Timing". *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *4 : Refer to "* Note of SDA and SCL set-up time". Note : VCC = VCC3 = VCC5 105 MB90480/485 Series * Note of SDA and SCL set-up time SDA Input data set-up time SCL 6 tcp Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. * Timing definition SDA tBUS tLOW tHDSTA tSUDAT SCL tHDSTA 106 tHIGH tHDDAT fSCL tSUSTA tSUSTO MB90480/485 Series (14) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol Pin name Conditions tTRGH tTRGL ADTG, IRQ0 to IRQ7 Value Unit Remarks ns Normal operation s Stop mode Min Max 5 tCP* 1 * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH 0.2 VCC tTRGL (15) Up-down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Conditions Value Min Max Unit AIN input "H" pulse width tAHL 8 tCP* ns AIN input "L" pulse width tALL 8 tCP* ns BIN input "H" pulse width tBHL 8 tCP* ns BIN input "L" pulse width tBLL 8 tCP* ns AINBIN time tAUBU 4 tCP* ns BINAIN time tBUAD 4 tCP* ns 4 tCP* ns 4 tCP* ns AIN0, AIN1, BIN0, BIN1 Load conditions 80 pF AINBIN time tADBD BINAIN time tBDAU BINAIN time tBUAU 4 tCP* ns AINBIN time tAUBD 4 tCP* ns BINAIN time tBDAD 4 tCP* ns AINBIN time tADBU 4 tCP* ns ZIN input "H" pulse width tZHL 4 tCP* ns ZIN input "L" pulse width tZLL 4 tCP* ns ZIN0, ZIN1 Remarks * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". 107 MB90480/485 Series tAHL 0.8 VCC tALL 0.8 VCC AIN 0.2 VCC tAUBU tBUAD tADBD 0.8 VCC 0.2 VCC tBDAU 0.8 VCC BIN 0.2 VCC tBHL 0.8 VCC 0.2 VCC tBLL 0.8 VCC BIN 0.2 VCC tBUAU tAUBD tBDAD 0.2 VCC tADBU 0.8 VCC AIN 0.2 VCC 0.8 VCC ZIN 0.8 VCC tZHL tZLL 0.2 VCC 108 0.2 VCC MB90480/485 Series (16) Chip Select Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Conditions Min Max Chip select output valid time RD tSVRL CS0 to CS3, RD tCP* / 2 - 7 ns Chip select output valid timeWR tSVWL CS0 to CS3, WRH, WRL tCP* / 2 - 7 ns RDchip select output valid time tRHSV RD, CS0 to CS3 tCP* / 2 - 17 ns WRchip select output valid time tWHSV WRH, WRL, CS0 to CS3 tCP* / 2 - 17 ns Parameter Unit Remarks * : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". tSVRL 2.4 V RD 0.8 V tRHSV A23 to A16 CS0 to CS3 2.4 V 0.8 V 2.4 V D15 to D00 Read data 0.8 V tSVWL tWHSV 2.4 V WRH, WRL 0.8 V D15 to D00 Undefined Write data Note : Due to the configuration of the internal bus, the chip select output signals are changed simultaneously and therefore may cause the bus conflict conditions. AC cannot be warranted between the ALE output signal and the chip select output signal. 109 MB90480/485 Series 5. A/D Converter Electrical Characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V AVRH, TA = -40 C to +85 C) Parameter Value SymPin name bol Min Typ Max Unit Remarks Resolution 10 bit Total error 3.0 LSB Linear error 2.5 LSB Differential linearity error 1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Full scale transition voltage VFST AN0 to AN7 AVRH - 3.5 LSB AVRH - 1.5 LSB AVRH + 0.5 LSB mV Conversion time 3.68 *1 s Analog port input current IAIN AN0 to AN7 0.1 10 A Analog input voltage VAIN AN0 to AN7 AVSS AVRH V AVRH AVSS + 2.2 AVCC V IA AVCC 1.4 3.5 mA IAH AVCC 5 *2 A IR AVRH 94 150 A 2 A Reference voltage Power supply current Reference voltage supply current IRH AVRH 5* Offset between channels AN0 to AN7 4 LSB *1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) . 110 MB90480/485 Series * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input equivalent circuit R Analog input Comparator C During sampling : ON R C MB90487B 2.5 k (Max) 31.0 pF (Max) MB90F481/F482 1.9 k (Max) 25.0 pF (Max) MB90F488B/F489B 1.9 k (Max) 25.0 pF (Max) Note: The values are reference values. * To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k) (External impedance = 0 k to 20 k) MB90F481/F482 MB90F488B/F489B MB90487B MB90F481/F482 MB90F488B/F489B MB90487B 20 90 External impedance [k] External impedance [k] 100 80 70 60 50 40 30 20 10 0 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 Minimum sampling time [s] 35 0 1 2 3 4 5 6 7 8 Minimum sampling time [s] * If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About errors As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. Note : Concerning sampling time, and compare time when 3.6 V AVCC 2.7 V, then Sampling time : 1.92 s, compare time : 1.1 s Settings should ensure that actual values do not go below these values due to operating frequency changes. 111 MB90480/485 Series *Flash Memory Program/Erase Characteristics Parameter Conditions Sector erase time TA = + 25 C, VCC = 3.0 V Chip erase time Word (16-bit) programming time Value Unit Remarks Min Typ Max 1 15 s Excludes 00H programming prior erasure 7 s Excludes 00H programming prior erasure 16 3600 s Excludes system-level overhead Program/Erase cycle 10000 cycle Flash Memory Data hold time Average TA = + 85 C 10 year * * : The value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) . * Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator X1 Pull-up resistance 1 X0 X0A Damping resistance 1 C2 X1A Internal damping resistance 0 Damping resistance 2 C1 C3 C4 In normal use : Internal damping resistance 0 : Typ 600 Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4 * Sample use with external clock input X0 OPEN 112 X1 MB90480/485 series MB90480/485 Series EXAMPLE CHARACTERISTICS * MB90F482 VOH - IOH 1800 3.5 VCC = 3.9 V 1600 3.0 VCC = 3.6 V 1400 VCC = 3.3 V 1200 VCC = 3.0 V 2.0 VCC = 2.7 V VOL (mV) 4.0 2.5 VOH (V) VOL - IOL TA = + 25 C 1.5 VCC = 2.4 V 1000 800 600 1.0 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V 400 0.5 200 0 0.0 -1 -2 -3 -4 -5 1 2 3 4 5 IOL (mA) IOH (mA) CMOS input characteristics TA = + 25 C Hysteresis input characteristics TA = + 25 C 2.4 2.4 2.2 2.2 2.0 2.0 VIHS VIH Hysteresis input (V) 1.8 CMOS input (V) TA = + 25 C 1.6 1.4 VIL 1.2 1.0 1.8 1.6 1.4 1.2 1.0 VILS 0.8 0.8 0.6 0.6 0.4 0.4 2.4 2.7 3.0 VCC (V) 3.3 3.6 2.4 2.7 3.0 3.3 3.6 VCC (V) (Continued) 113 MB90480/485 Series ICC - VCC 60 f = 25 MHz 50 f = 20 MHz ICC (mA) 40 f = 16 MHz 30 f = 10 MHz 20 f = 4 MHz f = 2 MHz f = 1 MHz 10 0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCH - VCC 1.4 1.2 ICCH (A) 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCT - VCC 2.0 1.8 1.6 ICCT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) (Continued) 114 MB90480/485 Series IA - VCC 2.0 1.8 1.6 IA (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) R - VCC R (k) 1000 100 10 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) (Continued) 115 MB90480/485 Series (Continued) ICCS - VCC 20 18 f = 25 MHz 16 ICCS (mA) 14 f = 20 MHz 12 f = 16 MHz 10 8 f = 10 MHz 6 4 f = 4 MHz f = 2 MHz f = 1 MHz 2 0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCL - VCC 20 18 16 ICCL (A) 14 12 10 8 6 4 2 0 2.4 2.7 3.0 3.3 3.6 3.9 3.3 3.6 3.9 VCC (V) IR - VCC 250 200 IR (A) 150 100 50 0 2.4 2.7 3.0 VCC (V) 116 MB90480/485 Series ORDERING INFORMATION Part number Package MB90F481PF MB90F482PF MB90487BPF MB90488BPF MB90F488BPF MB90483CPF MB90F489BPF 100-pin plastic QFP (FPT-100P-M06) MB90F481PFV MB90F482PFV MB90487BPFV MB90488BPFV MB90F488BPFV MB90483CPFV MB90F489BPFV 100-pin plastic LQFP (FPT-100P-M05) Remarks 117 MB90480/485 Series PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch 0.50 mm Package width x package length 14.0 x 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65g Code (Reference) P-LFQFP100-14x14-0.50 (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.000.20(.630.008)SQ * 14.000.10(.551.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 0.200.05 (.008.002) 0.08(.003) M 0.100.10 (.004.004) (Stand off) 0~8 "A" 0.50(.020) +.008 1.50 -0.10 .059 -.004 (Mounting height) INDEX 0.1450.055 (.0057.0022) 2003 FUJITSU LIMITED F100007S-c-4-6 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 118 MB90480/485 Series (Continued) 100-pin plastic QFP Lead pitch 0.65 mm Package width x package length 14.00 x 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14x20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.900.40(.941.016) * 20.000.20(.787.008) 80 51 81 50 0.10(.004) 17.900.40 (.705.016) *14.000.20 (.551.008) INDEX Details of "A" part 100 1 30 0.65(.026) 0.320.05 (.013.002) 0.13(.005) M "A" C 0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 31 2002 FUJITSU LIMITED F100008S-c-5-5 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 119 MB90480/485 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0611