DS07-13722-8E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90480/485 Series
MB90F481/F482/487B/488B/483C
MB90F488B/F489B/V480/V485B
■DESCRIPTION
The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in
consumer devices and other applications requiring high-speed real-time processing.
The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instruc-
tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete
bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.
The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial
interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C*2 interface, DTP/
external interrupt, chip select, and 16-bit reload timer.
*1 : F2MC is the abbreviation for FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C standard a Specification as defined
by Philips.
■FEATURES
•Clock
Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating
frequency/3.3 V ± 0.3 V)
62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating
frequency/3.0 V ± 0.3 V) PLL clock multiplier
• Maximum memory space: 16 Mbytes
(Continued)
MB90480/485 Series
2
(Continued)
• Instruction set optimized for controller applications
Supported data types (bit, byte, word, or long word)
Typical addressing modes (23 types)
32-bit accumulator for enhanced high-precision calculation
Enhanced signed multiplication/division instruction and RETI instruction functions
• Instruction set designed for high-level programming language (C) and multi-task operations
System stack pointer adopted
Instruction set symmetry and barrel shift instructions
• Non-multiplex bus/multiplex bus compatible
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt functions
8 levels setting with programmable priority, 8 external interrupts
• Data transfer function (µDMAC)
Up to 16 channels
• Embedded ROM
Flash versions : 192 Kbytes, 256 Kbytes, 384 Kbytes, MASK versions : 192 Kbytes, 256 Kbytes
• Embedded RAM
Flash versions : 4 Kbytes, 6 Kbytes, 10 Kbytes, 24 Kbytes, MASK versions : 10 Kbytes, 16 Kbytes
• General purpose ports
Up to 84 ports
(Includes 16 ports with input pull-up resistance settings, 16 ports with output open-drain settings)
• A/D converter
8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) )
•I
2C interface (MB90485 series only) : 1channel, P76/P77 N-ch open drain pin (without P-ch)
Do not apply high voltage in excess of recommended operating ranges
to the N-ch open drain pin (with P-ch) in MB90V485B.
•µPG (MB90485 series only) : 1 channel
• UART : 1 channel
• Extended I/O serial interface (SIO) : 2 channels
• 8/16-bit PPG : 3 channels (with 8-bit × 6 channel/16-bit × 3 channel mode switching function)
• 8/16-bit up/down counter/timer: 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function)
• PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three)
• 3 V/5 V I/F pin (MB90485 series only)
P20 to P27, P30 to P37, P40 to P47, P70 to P77
• 16-bit reload timer : 1 channel
• 16-bit I/O timer : 2 channels input capture, 6 channels output compare, 1 channel free run timer
• On chip dual clock generator system
• Low-power consumption mode
With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode
• Packages : QFP 100/LQFP 100
• Process : CMOS technology
• Power supply voltage : 3 V, single power supply (some ports can be operated by 5 V power supply at MB90485
series)
MB90480/485 Series
3
■PRODUCT LINEUP
• MB90480 series
*1 : User pin : P20 to P27, P30 to P37, P40 to P47, P70 to P77
*2 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
switching) about details.
Note : Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, −5%) .
MB90F481 MB90F482 MB90V480
Classification Flash memory product Evaluation product
ROM size 192 Kbytes 256 Kbytes ⎯
RAM size 4 Kbytes 6 Kbytes 16 Kbytes
CPU function
Number of instructions : 351
Instruction bit length : 8-bit, 16-bit
Instruction length : 1 byte to 7 bytes
Data bit length : 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 40 ns (25 MHz machine clock)
Ports
General-purpose I/O ports: up to 84
General-purpose I/O ports (CMOS output)
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain output)
UART 1 channel, start-stop synchronized
8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels
8/16-bit up/down
counter/timer
Event input pins : 6, 8-bit up/down counters : 2
8-bit reload/compare registers : 2
16-bit
I/O timers
16-bit free run timer Number of channels : 1
Overflow interrupt
Output compare
(OCU)
Number of channels : 6
Pin input factor : A match signal of compare register
Input capture
(ICU)
Number of channels : 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt circuit Number of external interrupt pin channels : 8 (edge or level detection)
Extended I/O serial interface Embedded 2 channels
Timebase timer 18-bit counter
Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
A/D converter
Conversion resolution : 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
Watchdog timer Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Low-power consumption
(standby) modes
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode,
timebase timer mode
Process CMOS
Type Not included security function User pin*1,
3 V/5 V versions
Emulator power supply*2⎯Included
Part number
Item
MB90480/485 Series
4
• MB90485 series
(Continued)
MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C
Classification MASK ROM product
Flash
memory
product
Evaluation
product
Flash
memory
product
MASK ROM
product
ROM size 192 Kbytes 256 Kbytes 256 Kbytes ⎯384 Kbytes 256 Kbytes
RAM size 10 Kbytes 10 Kbytes 10 Kbytes 16 Kbytes 24 Kbytes 16 Kbytes
CPU function
Number of instructions : 351
Instruction bit length : 8-bit, 16-bit
Instruction length : 1 byte to 7 bytes
Data bit length : 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 40 ns (25 MHz machine clock)
Ports
General-purpose I/O ports : up to 84
General-purpose I/O ports (CMOS output)
General-purpose I/O ports (with pull-up resistance)
General-purpose I/O ports (N-ch open drain output)
UART 1 channel, start-stop synchronized
8/16-bit PPG 8-bit × 6 channels/16-bit × 3 channels
8/16-bit up/down
counter/timer
Event input pins : 6, 8-bit up/down counters : 2
8-bit reload/compare registers : 2
16-bit
I/O
timers
16-bit free run
timer
Number of channels : 1
Overflow interrupt
Output
compare
(OCU)
Number of channels : 6
Pin input factor: A match signal of compare register
Input capture
(ICU)
Number of channels : 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt
circuit Number of external interrupt pin channels: 8 (edge or level detection)
Extended I/O serial
interface Embedded 2 channels
I2C interface*21 channel
µPG 1 channel
PWC 3 channels
Timebase timer 18-bit counter
Interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)
A/D converter
Conversion resolution : 8/10-bit, switchable
One-shot conversion mode (converts selected channel 1 time only)
Scan conversion mode (conversion of multiple consecutive channels,
programmable up to 8 channels)
Continuous conversion mode (repeated conversion of selected channels)
Stop conversion mode (conversion of selected channels with repeated pause)
Part number
Item
MB90480/485 Series
5
(Continued)
*1 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and
P70 to P77.
*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. However, MB90V485B uses the N-ch open
drain pin (with P-ch) .
*3 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
Notes : •As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/µPG/I2C
become CMOS input.
•Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, − 5%) .
MB90487B MB90488B MB90F488B MB90V485B MB90F489B MB90483C
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(minimum value, at 4 MHz base oscillator)
Low-power
consumption (standby)
modes
Stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase
timer mode
Process CMOS
Type
3 V/5 V
power
supply*1
3 V/5 V
power
supply*1
3 V/5 V power
supply*1
Included
security
function
3 V/5 V
power
supply*1
3 V/5 V power
supply*1
Included
security
function
3 V/5 V
power
supply*1
Emulator power
supply*3⎯⎯ ⎯Included ⎯⎯
Part number
Item
MB90480/485 Series
6
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-100P-M06)
1P20/A16
P21/A17
P22/A18
P23/A19
P24/A20/PPG0
P25/A21/PPG1
P26/A22/PPG2
P27/A23/PPG3
P30/A00/AIN0
P31/A01/BIN0
V
SS
P32/A02/ZIN0
P33/A03/AIN1
P34/A04/BIN1
P35/A05/ZIN1
P36/A06/PWC0*
P37/A07/PWC1*
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2
P43/A11/MT00*
P44/A12/MT01*
V
CC
5
P45/A13/EXTC*
P46/A14/OUT4
P47/A15/OUT5
P70/SIN0
P71/SOT0
P72/SCK0
P73/TIN0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
X0A
X1A
P57/CLK
RST
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/PPG5
P94/PPG4
P93/FRCK/ADTG/CS3
P92/SCK1/CS2
P91/SOT1/CS1
P90/SIN1/CS0
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
MD2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31P74/TOT0
P75/PWC2*
P76/SCL*
P77/SDA*
AVCC
AVRH
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
P01/AD01/D01
P00/AD00/D00
VCC3
X1
X0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07,
P43/A11, P44/A12, P45/A13, P75 to P77.
Note : MB90485 series only
• I
2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
•As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for
PWC/µPG/I2C become CMOS input.
MB90480/485 Series
7
(TOP VIEW)
(FPT-100P-M05)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RST
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/PPG5
P94/PPG4
P93/FRCK/ADTG/CS3
P92/SCK1/CS2
P91/SOT1/CS1
P90/SIN1/CS0
P87/IRQ7
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P22/A18
P23/A19
P24/A20/PPG0
P25/A21/PPG1
P26/A22/PPG2
P27/A23/PPG3
P30/A00/AIN0
P31/A01/BIN0
VSS
P32/A02/ZIN0
P33/A03/AIN1
P34/A04/BIN1
P35/A05/ZIN1
P36/A06/PWC0*
P37/A07/PWC1*
P40/A08/SIN2
P41/A09/SOT2
P42/A10/SCK2
P43/A11/MT00*
P44/A12/MT01*
VCC5
P45/A13/EXTC*
P46/A14/OUT4
P47/A15/OUT5
P70/SIN0
P71/SOT0
P72/SCK0
P73/TIN0
P74/TOT0
P75/PWC2*
P76/SCL*
P77/SDA*
AVCC
AVRH
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P80/IRQ0
P81/IRQ1
MD0
MD1
MD2
P82/IRQ2
P21/A17
P20/A16
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
P01/AD01/D01
P00/AD00/D00
VCC3
X1
X0
VSS
X0A
X1A
P57/CLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
* : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/
A11, P44/A12, P45/A13, P75 to P77.
Note : MB90485 series only
• I
2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
•As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
µPG/I2C become CMOS input.
MB90480/485 Series
8
■PIN DESCRIPTIONS
(Continued)
Pin No.
Pin name
I/O
circuit
type*3
Function
QFP*1LQFP*2
82 80 X0 A Clock (oscillator) input pin
83 81 X1 A Clock (oscillator) output pin
80 78 X0A A Clock (32 kHz oscillator) input pin
79 77 X1A A Clock (32 kHz oscillator) output pin
77 75 RST B Reset input pin
85 to 92 83 to 90
P00 to P07
C
(CMOS)
This is a general purpose I/O port. A setting in the port 0 input
resistance register (RDR0) can be used to apply pull-up resistance
(RD00-RD07 = “1”) . (Disabled when pin is set for output.)
AD00 to
AD07
In multiplex mode, these pins function as the external address/data
bus low I/O pins.
D00 to D07 In non-multiplex mode, these pins function as the external data bus
low output pins.
93 to
100 91 to 98
P10 to P17
C
(CMOS)
This is a general purpose I/O port. A setting in the port 1 input
resistance register (RDR1) can be used to apply pull-up resistance
(RD10-RD17 = “1”) . (Disabled when pin is set for output.)
AD08 to
AD15
In multiplex mode, these pins function as the external address/data
bus high I/O pins.
D08 to D15 In non-multiplex mode, these pins function as the external data bus
high output pins.
1 to 4 99, 100,
1, 2
P20 to P23
E
(CMOS/H)
This is a general purpose I/O port. When the bits of external address
output control register (HACR) are set to "1" in external bus mode,
these pins function as general purpose I/O ports.
A16 to A19
When the bits of external address output control register (HACR) are
set to "0" in multiplex mode, these pins function as address high
output pins (A16-A19).
When the bits of external address output control register (HACR) are
set to "0" in non-multiplex mode, these pins function as address high
output pins (A16-A19).
5 to 8 3 to 6
P24 to P27
E
(CMOS/H)
This is a general purpose I/O port. When the bits of external address
output control register (HACR) are set to "1" in external bus mode,
these pins function as general purpose I/O ports.
A20 to A23
When the bits of external address output control register (HACR) are
set to "0" in multiplex mode, these pins function as address high
output pins (A20-A23).
When the bits of external address output control register (HACR) are
set to "0" in non-multiplex mode, these pins function as address high
output pins (A20-A23).
PPG0 to
PPG3 Output pins for PPG.
97
P30
E
(CMOS/H)
This is a general purpose I/O port.
A00 In non-multiplex mode, this pin functions as an external address pin.
AIN0 8/16-bit up/down timer input pin (ch.0) .
MB90480/485 Series
9
(Continued)
Pin No. Pin
name
I/O
circuit
type*3
Function
QFP*1LQFP*2
10 8
P31
E
( CMOS/H)
This is a general purpose I/O port.
A01 In non-multiplex mode, this pin functions as an external address pin.
BIN0 8/16-bit up/down timer input pin (ch.0) .
12 10
P32
E
( CMOS/H)
This is a general purpose I/O port.
A02 In non-multiplex mode, this pin functions as an external address pin.
ZIN0 8/16-bit up/down timer input pin (ch.0)
13 11
P33
E
( CMOS/H)
This is a general purpose I/O port.
A03 In non-multiplex mode, this pin functions as an external address pin.
AIN1 8/16-bit up/down timer input pin (ch.1) .
14 12
P34
E
( CMOS/H)
This is a general purpose I/O port.
A04 In non-multiplex mode, this pin functions as an external address pin.
BIN1 8/16-bit up/down timer input pin (ch.1) .
15 13
P35
E
( CMOS/H)
This is a general purpose I/O port.
A05 In non-multiplex mode, this pin functions as an external address pin.
ZIN1 8/16-bit up/down timer input pin (ch.1)
16, 17 14, 15
P36, P37 D
(CMOS)
MB90480
series
This is a general purpose I/O port.
A06, A07 In non-multiplex mode, this pin functions as an external
address pin.
P36, P37
E
( CMOS/H)
MB90485
series
This is a general purpose I/O port.
A06, A07 In non-multiplex mode, this pin functions as an external
address pin.
PWC0,
PWC1*4This is a PWC input pin.
18 16
P40
G
( CMOS/H)
This is a general purpose I/O port.
A08 In non-multiplex mode, this pin functions as an external address pin.
SIN2 Extended I/O serial interface input pin.
19 17
P41
F (CMOS)
This is a general purpose I/O port.
A09 In non-multiplex mode, this pin functions as an external address pin.
SOT2 Extended I/O serial interface output pin.
20 18
P42
G
( CMOS/H)
This is a general purpose I/O port.
A10 In non-multiplex mode, this pin functions as an external address pin.
SCK2 Extended I/O serial interface clock input/output pin.
MB90480/485 Series
10
(Continued)
Pin No.
Pin name
I/O
circuit
type*3
Function
QFP*1LQFP*2
21, 22 19, 20
P43, P44
F (CMOS) MB90480
series
This is a general purpose I/O port.
A11, A12 In non-multiplex mode, this pin functions as an external
address pin.
P43, P44
F (CMOS) MB90485
series
This is a general purpose I/O port.
A11, A12 In non-multiplex mode, this pin functions as an external
address pin.
MT00,
MT01 µPG output pin.
24 22
P45 F
(CMOS)
MB90480
series
This is a general purpose I/O port.
A13 In non-multiplex mode, this pin functions as an external
address pin.
P45
G
( CMOS/H)
MB90485
series
This is a general purpose I/O port.
A13 In non-multiplex mode, this pin functions as an external
address pin.
EXTC*4µPG input pin.
25, 26 23, 24
P46, P47
F
(CMOS)
This is a general purpose I/O port.
A14, A15 In non-multiplex mode, this pin functions as an external address pin.
OUT4/
OUT5 Output compare event output pins.
70 68
P50 D
(CMOS)
This is a general purpose I/O port. In external bus mode, this pin
functions as the ALE pin.
ALE In external bus mode, this pin functions as the address load enable
(ALE) signal pin.
71 69
P51 D
(CMOS)
This is a general purpose I/O port. In external bus mode, this pin
functions as the RD pin.
RD In external bus mode, this pin functions as the read strobe output (RD)
signal pin.
72 70
P52
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the WRE
bit in the EPCR register is set to “1”, this pin functions as the WRL pin.
WRL
In external bus mode, this pin functions as the lower data write strobe
output (WRL) pin. When the WRE bit in the EPCR register is set to “0”,
this pin functions as a general purpose I/O port.
73 71
P53
D
(CMOS)
This is a general purpose I/O port. In external bus mode with 16-bit bus
width, when the WRE bit in the EPCR register is set to “1”, this pin
functions as the WRH pin.
WRH
In external bus mode with 16-bit bus width, this pin functions as the
upper data write strobe output (WRH) pin. When the WRE bit in the
EPCR register is set to “0”, this pin functions as a general purpose I/O
port.
MB90480/485 Series
11
(Continued)
Pin No.
Pin name
I/O
circuit
type*3
Function
QFP*1LQFP*2
74 72
P54
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
HDE bit in the EPCR register is set to “1”, this pin functions as the
HRQ pin.
HRQ
In external bus mode, this pin functions as the hold request input
(HRQ) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
75 73
P55
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
HDE bit in the EPCR register is set to “1”, this pin functions as the HAK
pin.
HAK
In external bus mode, this pin functions as the hold acknowledge out-
put (HAK) pin. When the HDE bit in the EPCR register is set to “0”, this
pin functions as a general purpose I/O port.
76 74
P56
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
RYE bit in the EPCR register is set to “1”, this pin functions as the RDY
pin.
RDY
In external bus mode, this pin functions as the external ready (RDY)
input pin. When the RYE bit in the EPCR register is set to “0”, this pin
functions as a general purpose I/O port.
78 76
P57
D
(CMOS)
This is a general purpose I/O port. In external bus mode, when the
CKE bit in the EPCR register is set to “1”, this pin functions as the CLK
pin.
CLK
In external bus mode, this pin functions as the machine cycle clock
(CLK) output pin. When the CKE bit in the EPCR register is set to
“0”, this pin functions as a general purpose I/O port.
38 to
41 36 to 39 P60 to P63 H
(CMOS)
These are general purpose I/O ports.
AN0 to AN3 These are the analog input pins for A/D converter.
43 to
46 41 to 44 P64 to P67 H
(CMOS)
These are general purpose I/O ports.
AN4 to AN7 These are the analog input pins for A/D converter.
27 25 P70 G
( CMOS/H)
This is a general purpose I/O port.
SIN0 This is the UART serial data input pin.
28 26 P71 F
(CMOS)
This is a general purpose I/O port.
SOT0 This is the UART serial data output pin.
29 27 P72 G
( CMOS/H)
This is a general purpose I/O port.
SCK0 This is the UART serial communication clock I/O pin.
30 28 P73 G
( CMOS/H)
This is a general purpose I/O port.
TIN0 This is the 16-bit reload timer event input pin.
31 29 P74 F
(CMOS)
This is a general purpose I/O port.
TOT0 This is the 16-bit reload timer output pin.
MB90480/485 Series
12
(Continued)
Pin No.
Pin name
I/O
circuit
type*3
Function
QFP*1LQFP*2
32 30
P75 F
(CMOS)
MB90480
series This is a general purpose I/O port.
P75 G
( CMOS/H)
MB90485
series
This is a general purpose I/O port.
PWC2*4This is a PWC input pin.
33 31
P76 F
(CMOS)
MB90480
series This is a general purpose I/O port.
P76
I
(NMOS/H)
MB90485
series
This is a general purpose I/O port.
SCL*4
Serves as the I2C interface data I/O pin. During opera-
tion of the I2C interface, leave the port output in a high
impedance state.
34 32
P77 F
(CMOS)
MB90480
series This is a general purpose I/O port.
P77
I
(NMOS/H)
MB90485
series
This is a general purpose I/O port.
SDA*4
Serves as the I2C interface data I/O pin. During opera-
tion of the I2C interface, leave the port output in a high
impedance state.
47, 48 45, 46 P80, P81 E
( CMOS/H)
These are general purpose I/O ports.
IRQ0, IRQ1 External interrupt input pins.
52 to 57 50 to 55 P82 to P87 E
( CMOS/H)
These are general purpose I/O ports.
IRQ2 to IRQ7 External interrupt input pins.
58 56
P90
E
( CMOS/H)
This is a general purpose I/O port.
SIN1 Extended I/O serial interface data input pin.
CS0 Chip select 0.
59 57
P91
D
(CMOS)
This is a general purpose I/O port.
SOT1 Extended I/O serial interface data output pin.
CS1 Chip select 1.
60 58
P92
E
( CMOS/H)
This is a general purpose I/O port.
SCK1 Extended I/O serial interface clock input/output pin.
CS2 Chip select 2.
61 59
P93
E
( CMOS/H)
This is a general purpose I/O port.
FRCK When the free run timer is in use, this pin functions as the external
clock input pin.
ADTG When the A/D converter is in use, this pin functions as the external
trigger input pin.
CS3 Chip select 3.
62 60 P94 D
(CMOS)
This is a general purpose I/O port.
PPG4 PPG timer output pin.
MB90480/485 Series
13
(Continued)
*1 : QFP : FPT-100P-M06
*2 : LQFP : FPT-100P-M05
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
*4 : As for MB90V485B, input pins become CMOS input.
Pin No.
Pin name
I/O
circuit
type*3
Function
QFP*1LQFP*2
63 61 P95 D
(CMOS)
This is a general purpose I/O port.
PPG5 PPG timer output pin.
64 62 P96 E
(CMOS/H)
This is a general purpose I/O port.
IN0 Input capture ch.0 trigger input pin.
65 63 P97 E
(CMOS/H)
This is a general purpose I/O port.
IN1 Input capture ch.1 trigger input pin.
66 to 69 64 to 67 PA0 to PA3 D
(CMOS)
These are general purpose I/O ports.
OUT0 to OUT3 Output compare event output pins.
35 33 AVCC ⎯A/D converter analog power supply input pin.
36 34 AVRH ⎯A/D converter reference voltage input pin.
37 35 AVSS ⎯A/D converter GND pin.
49 to 51 47 to 49 MD0 to MD2 J
(CMOS/H) Operating mode selection input pins.
84 82 VCC3⎯3.3 V ± 0.3 V power supply pins (VCC3) .
23 21 VCC5⎯
MB90480
series
3.3 V ± 0.3 V power supply pin.
Usually, use VCC = VCC3 = VCC5 as a 3 V power supply.
MB90485
series
3 V/5 V power supply pin.
5 V power supply pin when P20 to P27, P30 to P37,
P40 to P47, P70 to P77 are used as 5 V I/F pins.
Usually, use VCC = VCC3 = VCC5 as a 3 V power supply
(when the 3 V power supply is used alone) .
11, 42,
81
9, 40,
79 VSS ⎯GND pins.
MB90480/485 Series
14
■I/O CIRCUIT TYPES
(Continued)
Type Circuit Remarks
A
• Feedback resistance
X1, X0 : approx. 1 MΩ
X1A, X0A : approx. 10 MΩ
• With standby control
B
Hysteresis input with pull-up resistance
C
• With input pull-up resistance
control
• CMOS level input/output
D
CMOS level input/output
E
• Hysteresis input
• CMOS level output
X1, X1A
X0, X0A
Standby
control signal
Hysteresis input
CTL
CMOS
P-ch P-ch
N-ch
CMOS
P-ch
N-ch
CMOS
P-ch
N-ch
MB90480/485 Series
15
(Continued)
Type Circuit Remarks
F
• CMOS level input/output
• With open drain control
G
• CMOS level output
• Hysteresis input
• With open drain control
H
• CMOS level input/output
• Analog input
I
• Hysteresis input
• N-ch open drain output
J
(Flash memory product)
• CMOS level input
• With high voltage control for flash
testing
(MASK ROM product)
Hysteresis input
CMOS
P-ch
N-ch
Open drain
control signal
P-ch
N-ch
Open drain
control signal
Hysteresis input
CMOS
P-ch
N-ch
Analog input
N-ch
Digital output
Control signal
Mode input
Diffusion resistance
(Flash memory product)
Hysteresis input
(MASK ROM product)
MB90480/485 Series
16
■HANDLING DEVICES
1. Be careful never to exceed maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and
VSS pins exceeds the rated voltage level.
When latch-up occurs, the power supply current increases rapidly causing the possibility of thermal damage to
circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply
voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins.
3. Treatment of Power Supply Pins (VCC/VSS)
When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted
electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with
total output current ratings require that all power supply pins must be externally connected to power supply or
ground.
Consideration should be given to connecting power supply sources to the VCC/VSS pins of this device with as low
impedance as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed
between the VCC and VSS lines as close to this device as possible.
4. Crystal Oscillator Circuits
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable
operation it is strongly recommended that printed circuit board artwork places ground bypass capacitors as close
as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not
cross the lines of other circuits.
5. Precautions when turning the power supply on
In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during power-
on of 50 µs (0.2 V to 2.7 V) or greater should be assured.
6. Supply Voltage Stabilization
Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation.
As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at
commercial supply frequency (50 MHz to 60 MHz) be 10 % or less of VCC, and that the transient voltage fluctuation
be no more than 0.1 V/ms or less when the power supply is turned on or off.
7. Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power
supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut
off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even
when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed
AVCC.
MB90480/485 Series
17
8. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC,
and AVSS = VSS.
9. Notes on Using Power Supply
Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V
power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be interfaced as 5 V power supplies
separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for
the A/D converter can be used only as 3 V power supplies.
10. Notes on Using External Clock
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
11. Treatment of NC pins
NC (internally connected) pins should always be left open.
12. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operation if such failure occurs.
13. When the MB90480/485 series microcontroller is used as a single system
When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS,
and X1A = Open.
14. Writing to Flash memory
For writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.
X0
X1
OPEN
MB90480/485 Series
18
■BLOCK DIAGRAM
RAM
ROM
µDMAC
8
2
X0, X1, RST
X0A, X1A
MD2, MD1, MD0
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT 2
SCK1, SCK2
AVCC
AVRH
AVSS
ADTG
AN0
to
AN7
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
888888888
P00
P07
P10
P17
P20
P27
P30
P37
P40
P47
P50
P57
P60
P67
P70
P77
P80
P87
8
P90
P97
4
PA0
PA3
IN0, IN1
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
CS0, CS1,
CS2, CS3
TIN0
TOT0
IRQ0
to
IRQ7
8
SCL
SDA
EXTC
MT00
MT01
PWC0
PWC1
PWC2
Clock control
Circuit
CPU
F
2
MC16LX series core
Interrupt controller
8/16-bit PPG
8/16-bit
up/down
counter/timer
µPG
Chip select
Input/output timer
16-bit input capture ×
2 channels
16-bit output compare
×
6 channels
16-bit free-run timer
16-bit reload timer
I
2
C interface
External interrupt
UART
Extended I/O serial
interface × 2 channels
A/D converter
( 10-bit )
PWC × 3 channels
I/O port
to to to to to to to to to to to
Communication
prescaler
F2MC-16LX Bus
: Only MB90485 series
P00 to P07 (8 pins) : with an input pull-up resistance setting register.
P10 to P17 (8 pins) : with an input pull-up resistance setting register.
P40 to P47 (8 pins) : with an open drain setting register.
P70 to P77 (8 pins) : with an open drain setting register.
MB90485 series only
• I
2C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses
the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 are also used as 3 V/5 V I/F pin.
•As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/
µPG/I2C become CMOS input.
Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a
set of pins is used with an internal module, it cannot also be used as an I/O port.
MB90480/485 Series
19
■MEMORY MAP
• MB90F481/F482/487B/488B/483C/F488B/V480/V485B/F489B
*1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH.
The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small
model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00
bank are the same, enabling reference to tables in ROM without using the for specification in the pointer
declaration.
For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed.
If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is
not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH
is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only.
(Continued)
Model Address #1 Address #2 Address #3
MB90F481 FC0000H *1
004000H or 008000H,
selected by the MS bit in
the ROMM register
001100H
MB90F482 FC0000H001900H
MB90487B FD0000H002900H
MB90488B FC0000H002900H
MB90F488B FC0000H002900H
MB90V480 (FC0000H) 004000H
MB90V485B (FC0000H) 004000H
MB90483C FB0000H*4004000H
MB90F489B F90000H *20080000H fixed 006100H*3
FFFFFF
H
010000
H
000100
H
0000D0
H
000000
H
RAM
✽
RAM RAM
ROM areaROM area
ROM area
FF bank image
ROM area
FF bank image
Peripheral Peripheral Peripheral
Single chip
Internal ROM
external bus
External ROM
external bus
Address #1
Address #3
Register
: Internal : External : Access inhibited
Address #2
* : In models where address #3 overlaps with address #2, this external area does not exist.
Register Register
MB90480/485 Series
20
(Continued)
*2 : In MB90F489B, there is no access to F8 bank and FC bank on the single-chip mode or the internal-ROM
external-bus mode.
*3 : Because installed-RAM area is larger than MB90V485B, MB90F489B should execute emulation in an area
that is larger than 004000H by the emulation memory area setting on the tool side.
*4 : In MB90483C, there is no access to F8 bank to FA bank and FC bank on the single-chip mode or the internal-
ROM external-bus mode.
MB90480/485 Series
21
• MB90F489B
RAM
FFFFFF
H
FF0000
H
FEFFFF
H
FDFFFF
H
FE0000
H
FCFFFF
H
FD0000
H
FBFFFF
H
FC0000
H
FB0000
H
FAFFFF
H
F9FFFF
H
FA0000
H
F90000
H
F8FFFF
H
F80000
H
F7FFFF
H
010000
H
00FFFF
H
008000
H
007FFF
H
006100
H
0060FF
H
000100
H
0000FF
H
0000D0
H
0000CF
H
000000
H
RAMRAM
Peripheral Peripheral Peripheral
Register
Register
Register
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
Single chip
Internal ROM
external bus
External ROM
external bus
ROM area
FF bank image
ROM area
FF bank image
ROM (FE bank)
ROM (FF bank)
ROM (FD bank)
ROM (FE bank)
ROM (FF bank)
ROM (FD bank)
: Internal : External : Access inhibited
MB90480/485 Series
22
• MB90483C
RAM
FFFFFF
H
FF0000
H
FEFFFF
H
FDFFFF
H
FE0000
H
FCFFFF
H
FD0000
H
FBFFFF
H
FC0000
H
FB0000
H
FAFFFF
H
F9FFFF
H
FA0000
H
F90000
H
F8FFFF
H
F80000
H
F7FFFF
H
010000
H
00FFFF
H
004000
H
003FFF
H
000100
H
0000FF
H
0000D0
H
0000CF
H
000000
H
RAMRAM
004000
H
008000
H
or
Single chip
Internal ROM
external bus
External ROM
external bus
ROM (FF bank) ROM (FF bank)
Register
Peripheral
Peripheral Peripheral
: Internal : External : Access inhibited
RegisterRegister
ROM area
FF bank image
ROM area
FF bank image
ROM (FE bank) ROM (FE bank)
ROM (FD bank) ROM (FD bank)
ROM (FB bank) ROM (FB bank)
MB90480/485 Series
23
■F2MC-16L CPU PROGRAMMING MODEL
•Dedicated registers
•General purpose registers
•Processor status
AH AL
DPR
PCB
DTB
USB
SSB
ADB
8-bit
16-bit
32-bit
USP
SSP
PS
PC
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
R1 R0
R3 R2
R5 R4
R7 R6
RW0
RW1
RW2
RW3
16-bit
000180H + RP × 10H
RW4
RW5
RW6
RW7
RL0
RL1
RL2
RL3
MSB LSB
ILM
15 13
PS RP CCR
12 8 70
MB90480/485 Series
24
■I/O MAP
(Continued)
Address Register name Abbreviated
register name
Read/
Write Resource name Initial value
00HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 data register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 data register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 data register PDR7 R/W Port 7
XXXXXXXXB
(MB90480 series)
11XXXXXXB
(MB90485 series)
08HPort 8 data register PDR8 R/W Port 8 XXXXXXXXB
09HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AHPort A data register PDRA R/W Port A ----XXXXB
0BHUp/down timer input enable register UDRE R/W Up/down timer
input control XX000000B
0CHInterrupt/DTP enable register ENIR R/W
DTP/external interrupts
00000000B
0DHInterrupt/DTP source register EIRR R/W XXXXXXXXB
0EHRequest level setting register ELVR R/W 00000000B
0FHRequest level setting register R/W 00000000B
10HPort 0 direction register DDR0 R/W Port 0 00000000B
11HPort 1 direction register DDR1 R/W Port 1 00000000B
12HPort 2 direction register DDR2 R/W Port 2 00000000B
13HPort 3 direction register DDR3 R/W Port 3 00000000B
14HPort 4 direction register DDR4 R/W Port 4 00000000B
15HPort 5 direction register DDR5 R/W Port 5 00000000B
16HPort 6 direction register DDR6 R/W Port 6 00000000B
17HPort 7 direction register DDR7 R/W Port 7
00000000B
(MB90480 series)
XX000000B
(MB90485 series)
18HPort 8 direction register DDR8 R/W Port 8 00000000B
19HPort 9 direction register DDR9 R/W Port 9 00000000B
1AHPort A direction register DDRA R/W Port A ----0000B
1BHPort 4 output pin register ODR4 R/W Port 4
(Open-drain control) 00000000B
1CHPort 0 input resistance register RDR0 R/W Port 0
(resistance control) 00000000B
1DHPort 1 input resistance register RDR1 R/W Port 1
(resistance control) 00000000B
1EHPort 7 output pin register ODR7 R/W Port 7
(Open-drain control)
00000000B
(MB90480 series)
XX000000B
(MB90485 series)
1FHAnalog input enable register ADER R/W Port 6, A/D 11111111B
MB90480/485 Series
25
(Continued)
Address Register name Abbreviated
register name
Read/
Write Resource name Initial value
20HSerial mode register SMR R/W
UART
00000X00B
21HSerial control register SCR W, R/W 00000100B
22HSerial input/output register SIDR/SODR R/W XXXXXXXXB
23HSerial status register SSR R, R/W 00001000B
24H (Reserved area)
25HCommunication prescaler control
register CDCR R/W Communication
prescaler (UART) 00--0000B
26HSerial mode control status register 0 SMCS0 R/W SIO1 (ch.0)
----0000B
27H00000010B
28HSerial data register 0 SDR0 R/W XXXXXXXXB
29HCommunication prescaler control
register 0 SDCR0 R/W
Communication
prescaler
SIO1 (ch.0)
0---0000B
2AHSerial mode control status register 1 SMCS1 R/W SIO2 (ch.1)
----0000B
2BH00000010B
2CHSerial data register 1 SDR1 R/W XXXXXXXXB
2DHCommunication prescaler control
register 1 SDCR1 R/W
Communication
prescaler
SIO2 (ch.1)
0---0000B
2EHReload register L (ch.0) PPLL0 R/W
8/16-bit PPG
(ch.0 to ch.5)
XXXXXXXXB
2FHReload register H (ch.0) PPLH0 R/W XXXXXXXXB
30HReload register L (ch.1) PPLL1 R/W XXXXXXXXB
31HReload resister H (ch.1) PPLH1 R/W XXXXXXXXB
32HReload register L (ch.2) PPLL2 R/W XXXXXXXXB
33HReload register H (ch.2) PPLH2 R/W XXXXXXXXB
34HReload register L (ch.3) PPLL3 R/W XXXXXXXXB
35HReload register H (ch.3) PPLH3 R/W XXXXXXXXB
36HReload register L (ch.4) PPLL4 R/W XXXXXXXXB
37HReload register H (ch.4) PPLH4 R/W XXXXXXXXB
38HReload register L (ch.5) PPLL5 R/W XXXXXXXXB
39HReload register H (ch.5) PPLH5 R/W XXXXXXXXB
3AHPPG0 operating mode control register PPGC0 R/W 0X000XX1B
3BHPPG1 operating mode control register PPGC1 R/W 0X000001B
3CHPPG2 operating mode control register PPGC2 R/W 0X000XX1B
3DHPPG3 operating mode control register PPGC3 R/W 0X000001B
3EHPPG4 operating mode control register PPGC4 R/W 0X000XX1B
3FHPPG5 operating mode control register PPGC5 R/W 0X000001B
40HPPG0, PPG1 output control register PPG01 R/W 8/16-bit PPG 00000000B
41H (Reserved area)
42HPPG2, PPG3 output control register PPG23 R/W 8/16-bit PPG 00000000B
43H (Reserved area)
MB90480/485 Series
26
(Continued)
Address Register name
Abbre-
viated
register
name
Read/
Write Resource name Initial value
44HPPG4, PPG5 output control register PPG45 R/W 8/16-bit PPG 00000000B
45H (Reserved area)
46HControl status register ADCS1 R/W
A/D converter
00000000B
47HADCS2 W, R/W 00000000B
48HData register ADCR1 R XXXXXXXXB
49HADCR2 W, R 00000XXXB
4AHOutput compare register (ch.0) lower digits OCCP0 R/W
16-bit
input/output
timer output
compare
(ch.0 to ch.5)
00000000B
4BHOutput compare register (ch.0) upper digits 00000000B
4CHOutput compare register (ch.1) lower digits OCCP1 R/W 00000000B
4DHOutput compare register (ch.1) upper digits 00000000B
4EHOutput compare register (ch.2) lower digits OCCP2 R/W 00000000B
4FHOutput compare register (ch.2) upper digits 00000000B
50HOutput compare register (ch.3) lower digits OCCP3 R/W 00000000B
51HOutput compare register (ch.3) upper digits 00000000B
52HOutput compare register (ch.4) lower digits OCCP4 R/W 00000000B
53HOutput compare register (ch.4) upper digits 00000000B
54HOutput compare register (ch.5) lower digits OCCP5 R/W 00000000B
55HOutput compare register (ch.5) upper digits 00000000B
56HOutput control register (ch.0) OCS0 R/W 0000--00B
57HOutput control register (ch.1) OCS1 R/W ---00000B
58HOutput control register (ch.2) OCS2 R/W 0000--00B
59HOutput control register (ch.3) OCS3 R/W ---00000B
5AHOutput control register (ch.4) OCS4 R/W 0000--00B
5BHOutput control register (ch.5) OCS5 R/W ---00000B
5CHInput capture data register (ch.0) lower
digits IPCP0
R
16-bit
input/output
timer input
capture
(ch.0, ch.1)
XXXXXXXXB
5DHInput capture data register (ch.0) upper
digits R XXXXXXXXB
5EHInput capture data register (ch.1) lower
digits IPCP1
R XXXXXXXXB
5FHInput capture data register (ch.1) upper
digits R XXXXXXXXB
60HInput capture control status register ICS01 R/W 00000000B
61H (Reserved area)
MB90480/485 Series
27
(Continued)
Address Register name Abbreviated
register
name
Read/
Write Resource name Initial value
62HTimer counter data register lower digits TCDT R/W
16-bit input/output
timer free run timer
00000000B
63HTimer counter data register upper digits TCDT R/W 00000000B
64HTimer control status register TCCS R/W 00000000B
65HTimer control status register TCCS R/W 0--00000B
66HCompare clear register lower digits CPCLR R/W XXXXXXXXB
67HCompare clear register upper digits XXXXXXXXB
68HUp/down count register (ch.0) UDCR0 R
8/16-bit up/down
00000000B
69HUp/down count register (ch.1) UDCR1 R 00000000B
6AHReload/compare register (ch.0) RCR0 W 00000000B
6BHReload/compare register (ch.1) RCR1 W 00000000B
6CHCounter control register (ch.0)
lower digits CCRL0 W, R/W 0X00X000B
6DHCounter control register (ch.0)
upper digits CCRH0 R/W 00000000B
6EH (Reserved area)
6FHROM mirror function select register ROMM R/W ROM mirroring
function ------+1B
70HCounter control register (ch.1)
lower digits CCRL1 W, R/W
8/16-bit up/down
0X00X000B
71HCounter control register (ch.1)
upper digits CCRH1 R/W -0000000B
72HCounter status register (ch.0) CSR0 R, R/W 00000000B
73H (Reserved area)
74HCounter status register (ch.1) CSR1 R, R/W 8/16-bit UDC 00000000B
75H (Reserved area)
76H*PWC control/status register PWCSR0 R, R/W
PWC (ch.0)
00000000B
77H*0000000XB
78H*PWC data buffer register PWCR0 R/W 00000000B
79H* 00000000B
7AH*PWC control/status register PWCSR1 R, R/W
PWC (ch.1)
00000000B
7BH*0000000XB
7CH*PWC data buffer register PWCR1 R/W 00000000B
7DH* 00000000B
7EH*PWC control/status register PWCSR2 R, R/W
PWC (ch.2)
00000000B
7FH*0000000XB
80H*PWC data buffer register PWCR2 R/W 00000000B
81H* 00000000B
82H* Dividing ratio control register DIVR0 R/W PWC (ch.0) ------00B
83H (Reserved area)
84H* Dividing ratio control register DIVR1 R/W PWC (ch.1) ------00B
85H (Reserved area)
86H* Dividing ratio control register DIVR2 R/W PWC (ch.2) ------00B
87H (Reserved area)
MB90480/485 Series
28
(Continued)
Address Register name Abbreviated
register
name
Read/
Write Resource name Initial value
88H* Bus status register IBSR R
I2C
00000000B
89H* Bus control register IBCR R/W 00000000B
8AH* Clock control register ICCR R/W --0XXXXXB
8BH* Address register IADR R/W -XXXXXXXB
8CH* Data register IDAR R/W XXXXXXXXB
8DH (Reserved area)
8EH*µPG control status register PGCSR R/W µPG 00000---B
8FH to 9BH (Disabled)
9CHµDMAC status register lower digits DSRL R/W µDMAC 00000000B
9DHµDMAC status register upper digits DSRH R/W µDMAC 00000000B
9EHProgram address detection control
status resister PACSR R/W Address match
detection function 00000000B
9FHDelayed interrupt source general/
cancel register DIRR R/W Delayed interrupt
generator module -------0B
A0HLow-power consumption mode control
register LPMCR W, R/W Low-power
consumption 00011000B
A1HClock select register CKSCR R, R/W Low-power
consumption 11111100B
A2H, A3H (Reserved area)
A4HµDMAC stop status register DSSR R/W µDMAC 00000000B
A5HAutomatic ready function select register ARSR W External pins 0011 - -00B
A6HExternal address output control register HACR W External pins ********B
A7HBus control signal select register EPCR W External pins 1000*10 -B
A8HWatchdog timer control register WDTC R, W Watchdog timer XXXXX111B
A9HTimebase timer control register TBTC W, R/W Timebase timer 1XX00100B
AAHWatch timer control register WTC R, R/W Watch timer 10001000B
ABH (Reserved area)
ACHµDMAC enable register lower digits DERL R/W µDMAC 00000000B
ADHµDMAC enable register upper digits DERH R/W µDMAC 00000000B
AEHFlash memory control status register FMCS W, R/W Flash memory
interface 000X0000B
AFH (Disabled)
B0HInterrupt control register 00 ICR00 W, R/W
Interrupt controller
XXXX0111B
B1HInterrupt control register 01 ICR01 W, R/W XXXX0111B
B2HInterrupt control register 02 ICR02 W, R/W XXXX0111B
B3HInterrupt control register 03 ICR03 W, R/W XXXX0111B
B4HInterrupt control register 04 ICR04 W, R/W XXXX0111B
B5HInterrupt control register 05 ICR05 W, R/W XXXX0111B
B6HInterrupt control register 06 ICR06 W, R/W XXXX0111B
B7HInterrupt control register 07 ICR07 W, R/W XXXX0111B
B8HInterrupt control register 08 ICR08 W, R/W XXXX0111B
MB90480/485 Series
29
(Continued)
* : These registers are only for MB90485 series.
They are used as the reserved area on MB90480 series.
(Continued)
Address Register name Abbreviated
register
name
Read/
Write Resource name Initial value
B9HInterrupt control register 09 ICR09 W, R/W
Interrupt controller
XXXX0111B
BAHInterrupt control register 10 ICR10 W, R/W XXXX0111B
BBHInterrupt control register 11 ICR11 W, R/W XXXX0111B
BCHInterrupt control register 12 ICR12 W, R/W XXXX0111B
BDHInterrupt control register 13 ICR13 W, R/W XXXX0111B
BEHInterrupt control register 14 ICR14 W, R/W XXXX0111B
BFHInterrupt control register 15 ICR15 W, R/W XXXX0111B
C0HChip select area mask register 0 CMR0 R/W
Chip select
function
00001111B
C1HChip select area register 0 CAR0 R/W 11111111B
C2HChip select area mask register 1 CMR1 R/W 00001111B
C3HChip select area register 1 CAR1 R/W 11111111B
C4HChip select area mask register 2 CMR2 R/W 00001111B
C5HChip select area register 2 CAR2 R/W 11111111B
C6HChip select area mask register 3 CMR3 R/W 00001111B
C7HChip select area register 3 CAR3 R/W 11111111B
C8HChip select control register CSCR R/W ----000*B
C9HChip select active level register CALR R/W ----0000B
CAHTimer control status register TMCSR R/W
16-bit reload timer
00000000B
CBH----0000B
CCH16-bit timer register/
16-bit reload register TMR/TMRLR R/W XXXXXXXXB
CDH
CEH (Reserved area)
CFHPLL output control register PLLOS W Low-power
consumption ------X0B
D0H to FFH (External area)
100H to #H (RAM area)
1FF0HProgram address detection register 0
(Low order address)
PADR0 R/W Address match
detection function XXXXXXXXB1FF1HProgram address detection register 0
(Middle order address)
1FF2HProgram address detection register 0
(High order address)
1FF3HProgram address detection register 1
(Low order address)
PADR1 R/W Address match
detection function XXXXXXXXB1FF4HProgram address detection register 1
(Middle order address)
1FF5HProgram address detection register 1
(High order address)
MB90480/485 Series
30
(Continued)
Descriptions for read/write
Descriptions for initial value
R/W : Readable and writable
R : Read only
W : Write only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
- : This bit is not used.
* : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
+ : The initial value of this bit is “1” or “0”.
The value depends on the RAM area of device.
MB90480/485 Series
31
■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
(Continued)
Interrupt source Clear of
EI2OS
µDMAC
channel
number
Interrupt vector Interrupt control register
Number Address Number Address
Reset × ⎯#08 FFFFDCH⎯⎯
INT9 instruction × ⎯#09 FFFFD8H⎯⎯
Exception × ⎯#10 FFFFD4H⎯⎯
INT0 (IRQ0) 0 #11 FFFFD0HICR00 0000B0H
INT1 (IRQ1) × #12 FFFFCCH
INT2 (IRQ2) × #13 FFFFC8HICR01 0000B1H
INT3 (IRQ3) × #14 FFFFC4H
INT4 (IRQ4) × #15 FFFFC0HICR02 0000B2H
INT5 (IRQ5) × #16 FFFFBCH
INT6 (IRQ6) × #17 FFFFB8HICR03 0000B3H
INT7 (IRQ7) × #18 FFFFB4H
PWC1 (MB90485 series only) × #19 FFFFB0HICR04 0000B4H
PWC2 (MB90485 series only) × #20 FFFFACH
PWC0 (MB90485 series only) 1 #21 FFFFA8HICR05 0000B5H
PPG0/PPG1 counter borrow × × #22 FFFFA4H
PPG2/PPG3 counter borrow × × #23 FFFFA0HICR06 0000B6H
PPG4/PPG5 counter borrow × × #24 FFFF9CH
8/16-bit up/down counter/
timer (ch.0, ch.1) compare/
underflow/overflow/up/down
inversion
× #25 FFFF98HICR07 0000B7H
Input capture (ch.0) load 5 #26 FFFF94H
Input capture (ch.1) load 6 #27 FFFF90HICR08 0000B8H
Output compare (ch.0) match 8 #28 FFFF8CH
Output compare (ch.1) match 9 #29 FFFF88HICR09 0000B9H
Output compare (ch.2) match 10 #30 FFFF84H
Output compare (ch.3) match × #31 FFFF80HICR10 0000BAH
Output compare (ch.4) match × #32 FFFF7CH
Output compare (ch.5) match × #33 FFFF78HICR11 0000BBH
UART sending completed 11 #34 FFFF74H
16-bit free run timer overflow,
16-bit reload timer underflow*212 #35 FFFF70HICR12 0000BCH
UART receiving completed 7 #36 FFFF6CH
SIO1 (ch.0) 13 #37 FFFF68HICR13 0000BDH
SIO2 (ch.1) 14 #38 FFFF64H
MB90480/485 Series
32
(Continued)
× : Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.
*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable
(TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111B) , then set
the INTE bit to 0.
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI2OS/µDMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/
µDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corre-
sponding resource should be set to “0” and interrupt requests from that resource should be handled by
software polling.
Interrupt source Clear of
EI2OS
µDMAC
channel
number
Interrupt vector Interrupt control register
Number Address Number Address
I2C interface
(MB90485 series only) × × #39 FFFF60HICR14 0000BEH
A/D conversion 15 #40 FFFF5CH
Flash write/erase,
timebase timer, watch timer *1 × × #41 FFFF58H
ICR15 0000BFH
Delay interrupt generator
module × × #42 FFFF54H
MB90480/485 Series
33
■PERIPHERAL RESOURCES
1. I/O Ports
The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information
from the I/O into the CPU, according to the setting of the corresponding port data register (PDR) . The input/
output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each I/
O port.
The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A.
(1) Port Data Registers
*1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following
operations.
• Input mode
Read : Reads the corresponding signal pin level.
Write : Writes to the output latch.
• Output mode
Read : Reads the value from the data register latch.
Write : Outputs the value to the corresponding signal pin.
*2 : The initial value of this bit is “11XXXXXXB” on MB90485 series.
PDR0 Initial value Access
Address : 000000HUndefined R/W*1
PDR1
Address : 000001HUndefined R/W*1
PDR2
Address : 000002HUndefined R/W*1
PDR3
Address : 000003HUndefined R/W*1
PDR4
Address : 000004HUndefined R/W*1
PDR5
Address : 000005HUndefined R/W*1
PDR6
Address : 000006HUndefined R/W*1
PDR7
Address : 000007HUndefined*2R/W*1
PDR8
Address : 000008HUndefined R/W*1
PDR9
Address : 000009HUndefined R/W*1
PDRA
Address : 00000AHUndefined R/W*1
7654 3210
P06P07 P05 P04 P03 P02 P01 P00
7654 3210
P16P17 P15 P14 P13 P12 P11 P10
7654 3210
P26P27 P25 P24 P23 P22 P21 P20
P36P37 P35 P34 P33 P32 P31 P30
7654 3210
7654 3210
P46P47 P45 P44 P43 P42 P41 P40
P56P57 P55 P54 P53 P52 P51 P50
7654 3210
7654 3210
P66P67 P65 P64 P63 P62 P61 P60
P76P77 P75 P74 P73 P72 P71 P70
7654 3210
7654 3210
P86P87 P85 P84 P83 P82 P81 P80
P96P97 P95 P94 P93 P92 P91 P90
7654 3210
7654 3210
⎯⎯⎯⎯PA3 PA2 PA1 PA0
MB90480/485 Series
34
(2) Port Direction Registers
*1 : The value is set to “⎯” on MB90485 series only.
*2 : The initial value of this bit is “XX000000B” on MB90485 series only.
• When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows.
0 : Input mode.
1 : Output mode. Reset to “0”.
Notes : •When any of these registers are accessed using a read-modify-write type instruction (such as a bit set
instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents
of output registers corresponding to any other bits having input settings will be rewritten to the input values
of those pins at that time.
For this reason, when changing any pin that has been used for input to output, first write the desired value
to the PDR register before setting the DDR register for output.
•P76, P77 (MB90485 series only)
This port has no DDR. To use P77 and P76 as I2C pins, set the PDR value to “1” so that port data remains
enabled (to use P77 and P76 for general purposes, disable I2C) . The port is an open drain output (with
no P-ch) .
To use it as an input port, therefore, set the PDR to “1” to turn off the output transistor and add a pull-up
resistor to the external output.
DDR0 Initial value Access
Address : 000010H00000000BR/W
DDR1
Address : 000011H00000000BR/W
DDR2
Address : 000012H00000000BR/W
DDR3
Address : 000013H00000000BR/W
DDR4
Address : 000014H00000000BR/W
DDR5
Address : 000015H00000000BR/W
DDR6
Address : 000016H00000000BR/W
DDR7
Address : 000017H00000000B*2R/W
DDR8
Address : 000018H00000000BR/W
DDR9
Address : 000019H00000000BR/W
DDRA
Address : 00001AH----0000BR/W
7654321 0
D06D07 D05 D04 D03D02 D01 D00
D16D17 D15 D14 D13 D12 D11 D10
76543210
76543210
D26D27 D25 D24 D23 D22 D21 D20
76543210
D36D37 D35 D34 D33 D32 D31 D30
76543210
D46D47 D45 D44 D43 D42 D41 D40
76543210
D56D57 D55 D54 D53 D52 D51 D50
76543210
D66D67 D65 D64 D63 D62 D61 D60
76543210
D75 D74 D73 D72 D71 D70
D77*1D76*1
76543210
D86D87 D85 D84 D83 D82 D81 D80
76543210
D96D97 D95 D94 D93 D92 D91 D90
76543210
⎯⎯⎯⎯DA3 DA2 DA1 DA0
MB90480/485 Series
35
(3) Port Input Resistance Registers
These registers control the use of pull-up resistance in input mode.
0 : No pull-up resistance in input mode.
1 : With pull-up resistance in input mode.
In output mode, these registers have no function (no pull-up resistance) . Input/output mode settings are
controlled by the setting of port direction (DDR) registers.
In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . Using of this function is prohibited
when an external bus is used. Do not write to these registers.
(4) Port Output Pin Registers
*1 : The value is set to “⎯” on MB90485 series only.
*2 : The initial value of this bit is “XX000000B” on MB90485 series only.
These registers control open drain settings in output mode.
0 : Standard output port functions in output mode.
1 : Open drain output port in output mode.
In input mode, these registers have no function (Hi-Z output) . Input/output mode settings are controlled by the
setting of port direction (DDR) registers. Using of this function is prohibited when an external bus is used. Do
not write to these registers.
(5) Analog Input Enable Register
This register controls the port 6 pins as follows.
0 : Port input/output mode.
1 : Analog input mode. The default value at reset is all “1”.
(6) Up/down Timer Input Enable Register
This register controls the port 3 pins as follows.
0 : Port input mode.
1 : Up/down timer input mode.The default value at reset is “0”.
RDR0 Initial value Access
Address : 00001CH00000000BR/W
RDR1
Address : 00001DH00000000BR/W
76543210
RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00
76543210
RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10
ODR7 Initial value Access
Address : 00001EH00000000B*2R/W
ODR4
Address : 00001BH00000000BR/W
76543210
OD75 OD74 OD73 OD72 OD71 OD70
OD76*1
OD77*1
76543210
OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40
ADER Initial value Access
Address : 00001FH11111111BR/W
76543210
ADE6ADE7 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
UDER Initial value Access
Address : 00000BHXX000000BR/W
76543210
⎯⎯ UDE5 UDE4 UDE3 UDE2 UDE1 UDE0
MB90480/485 Series
36
2. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK
synchronized communication.
• Full duplex double buffer
• Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) .
• Multi-processor mode supported.
• Embedded proprietary baud rate generator
Asynchronous : 76923/38461/19230/9615/500 k/250 kbps
CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 kbps
• External clock setting available, allows use of any desired baud rate.
• Can use internal clock feed from PPG1.
• Data length : 7-bit (asynchronous normal mode only) or 8-bit.
• Master/slave type communication functions (in multi-processor mode) .
• Error detection functions (parity, framing, overrun)
• Transfer signals are NRZ encoded.
•µDMAC supported (for receiving/sending)
MB90480/485 Series
37
(1) Register List
Serial mode register (SMR)
Serial control register (SCR)
Serial I/O register (SIDR/SODR)
Serial status register (SSR)
Communication prescaler control register (CDCR)
000020H
Initial value
000021H
Initial value
000022H
Initial value
000023H
Initial value
000025H
Initial value
SMR
⎯CDCR
SCR
15 0
SIDR (R)/SODR (W)SSR
87
8 bits 8 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
X
R/W
0
R/W
0
76543210
MD0
R/W
0
MD1 CS2 CS1 CS0 SCKE SOE
Reserved
R/W
0
R/W
0
R/W
0
R/W
0
W
1
R/W
0
R/W
0
15 14 13 12 11 10 9 8
P
R/W
0
PEN SBL CL A/D REC RXE TXE
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
76543210
D6
R/W
X
D7 D5 D4 D3 D2 D1 D0
R
0
R
0
R
0
R
1
R/W
0
R/W
0
R/W
0
15 14 13 12 11 10 9 8
ORE
R
0
PE FRE RDRF TDRE BDS RIE TIE
R/W
0
⎯
⎯⎯
⎯R/W
0
R/W
0
R/W
0
R/W
0
15 14 13 12 11 10 9 8
SRST
R/W
0
MD ⎯⎯DIV3 DIV2 DIV1 DIV0
MB90480/485 Series
38
(2) Block Diagram
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
F2MC-16LX BUS
SIDR SODR
SOT0
SCK0
SIN0
Control
signal
PPG1 (internal
connection)
External clock
Clock select
circuit
Receiving status
decision circuit
µDMAC receiving
error generation
circuit (to CPU)
Receiving clock
Receiving control
circuit
Start bit detect
circuit
Receive bit
counter
Receiving parity
counter
Receiving shifter
Receiving
control
circuit
Sending clock
Receiving interrupt
(to CPU)
Sending interrupt
(to CPU)
Sending control
circuit
Send start
circuit
Send bit
counter
Send parity
counter
Sending shifter
Sending
start
SMR
Control signal
SCR SSR
Proprietary baud
rate generator
MB90480/485 Series
39
3. Expanded I/O Serial Interface
The expanded I/O serial interface is an 8-bit × 1-channel serial I/O interface for clock synchronized data
transfer. A selection of LSB-first or MSB-first data transfer is provided.
There are two serial I/O operation modes.
(1) Register List
• Internal shift clock mode : Data transfer is synchronized with the internal clock signal.
• External shift clock mode : Data transfer is synchronized with a clock signal input from the external clock
signal pin (SCK) . In this mode the general-purpose port that shares the external
clock signal pin (SCK) can be used for transfer according to CPU instructions.
Serial mode control status register 0/1 (SMCS0, SMCS1)
Serial data register 0/1 (SDR0, SDR1)
Communication prescaler control register 0/1 (SDCR0, SDCR1)
Initial value
Address : 000027H
00002BH00000010B
Address : 000026H
00002AH----0000B
Address : 000028H
00002CHXXXXXXXXB
Address : 000029H
00002DH0---0000B
15 14 13 12 11 10 9 8
SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT
R/WR/W R/W R/W R/W R R/W R/W
7654321 0
⎯⎯⎯⎯MODE BDSSOE SCOE
R/W R/W R/W R/W
⎯⎯⎯⎯
76543210
D6D7 D5 D4 D3 D2 D1 D0
R/WR/W R/W R/W R/W R/W R/W R/W
⎯⎯⎯R/W R/W R/W R/W
15 14 13 12 11 10 9 8
⎯
R/W
MD ⎯⎯DIV3 DIV2 DIV1 DIV0
MB90480/485 Series
40
(2) Block Diagram
SIN1, SIN2
SOT1, SOT2
SCK1, SCK2
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
21 0
SOE SCOE
(MSB first) D0 to D7 D7 to D0 (LSB first)
SDR (Serial Data Register)
Internal clock
Internal data bus
Transfer direction selection
Read
Write
Control circuit Shift clock
counter
Interrupt
request
Internal data bus
Initial value
MB90480/485 Series
41
4. 8/10-bit A/D Converter
The A/D converter converts analog input voltage to digital values, and provides the following features.
• Conversion time : minimum 3.68 µs per channel
(92 machine cycles at 25 MHz machine clock, including sampling time)
• Sampling time : minimum 1.92 µs per channel
(48 machine cycles at 25 MHz machine clock)
• RC sequential comparison conversion method, with sample & hold circuit.
• 8-bit or 10-bit resolution
• Analog input selection of 8 channels
Single conversion mode : Conversion from one selected channel.
Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to
8 channels.
Continuous conversion mode : Repeated conversion of specified channels.
Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to
synchronize with conversion start.
• At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU.
The interrupt can be used activate the µDMAC in order to transfer the results of A/D conversion to memory
for efficient continuous processing.
• The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising
edge) .
(1) Register List
ADCS2, ADCS1 (Control status register)
ADCR2, ADCR1 (Data register)
ADCS1
Address : 000046H
←Initial value
←Bit attributes
ADCS2
Address : 000047H
←Initial value
←Bit attributes
ADCR1
Address : 000048H
←Initial value
←Bit attributes
ADCR2
Address : 000049H
←Initial value
←Bit attributes
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
76543210
MD0
0
R/W
MD1 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
15 14 13 12 11 10 9 8
INT
0
R/W
BUSY INTE PAUS STS1 STS0 STRT Reserved
X
R
X
R
X
R
X
R
X
R
X
R
X
R
76543210
D6
X
R
D7 D5 D4 D3 D2 D1 D0
0
W
0
W
0
W
0
W
X
R
X
R
X
R
15 14 13 12 11 10 9 8
ST1
0
W
S10 ST0 CT1 CT0 ⎯D9 D8
MB90480/485 Series
42
(2) Block Diagram
φ
MP
ADTG
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADCR1, ADCR2
ADCS1, ADCS2
AVCC
AVRH
AVSS
Input
circuit
D/A converter
Sequential
comparison register
Data registers
A/D control register 1
A/D control register 2
Prescaler
Operation clock
Trigger activation
Timer activation
Decoder
Comparator
Sample & hold
circuit
Timer
(PPG1 output)
Data bus
MB90480/485 Series
43
5. 8/16-bit PPG
The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer
operation. Hardware resources include 6 × 8-bit down counters, 12 × 8-bit reload timers, 3 × 16-bit control
registers, 6 × external pulse output pins, and 6 × interrupt outputs. Note that MB90480/485 series has six channels
for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate
as a three-channel 16-bit PPG. The following is a summary of functions.
• 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels.
• 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels
are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5.
•8 + 8-bit PPG output operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/
PPG5) to provide to 8-bit PPG output at any desired period length.
• PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also
be used with external circuits as a D/A converter.
(1) Register List
PPGC0/PPGC2/PPGC4 (PPG0/PPG2/PPG4 operation mode control register)
PPGC1/PPGC3/PPGC5 (PPG1/PPG3/PPG5 operation mode control register)
PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register)
PPLL0 to PPLL5 (Reload register L)
PPLH0 to PPLH5 (Reload register H)
00003AH
00003CH
00003EHRead/write
Initial value
00003BH
00003DH
00003FHRead/write
Initial value
000040H
000042H
000044HRead/write
Initial value
00002EH
000030H
000032H
000034H
000036H
000038H
Read/write
Initial value
00002FH
000031H
000033H
000035H
000037H
000039H
Read/write
Initial value
⎯
X
R/W
0
R/W
0
R/W
0
⎯
X
⎯
X
⎯
1
76543210
⎯
R/W
0
PEN0 PE00 PIE0 PUF0 ⎯⎯
Reserved
⎯
X
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
⎯
1
15 14 13 12 11 10 9 8
⎯
R/W
0
PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
76543210
PCS1
R/W
0
PCS2 PCS0 PCM2 PCM1 PCM0 ReservedReserved
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
76543210
D06
R/W
X
D07 D05 D04 D03 D02 D01 D00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15 14 13 12 11 10 9 8
D14
R/W
X
D15 D13 D12 D11 D10 D09 D08
MB90480/485 Series
44
(2) Block Diagram
• 8-bit PPG ch.0/2/4 block Diagram
S
RQ
PRLBHPRLL
PRLL
PPG0/2/4
PEN0
IRQ
PIE0
PUF0
Peripheral clock × 16
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock
Count clock
select
Timebase counter
output main clock
× 512
PCNT
(down counter)
“L”/“H” selector
PPG0/2/4
output enable
A/D converter
PPG0/2/4
output latch
ch.1/3/5 borrow
“L” data bus
“H” data bus
PPGC0 (operation mode control)
“L”/“H” select
MB90480/485 Series
45
• 8-bit PPG ch.1/3/5 Block Diagram
S
RQ
PRLBHPRLL
PRLL
PPG1/3/5
UART0
PEN1
IRQ
PIE1
PUF1
Peripheral clock × 16
Peripheral clock × 8
Peripheral clock × 4
Peripheral clock × 2
Peripheral clock
Count clock
select
Timebase counter
output main clock × 512
PCNT
(down counter)
“L”/“H” selector
PPG1/3/5 output
enable
PPG1/3/5
output latch
“L” data bus
“H” data bus
PPGC1 (operation mode control)
“L”/“H” select
MB90480/485 Series
46
6. 8/16-bit up/down Counter/Timer
8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two
8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits.
(1) Principal Functions
• 8-bit count register enables counting in the range 0 to 256.
(In 16-bit × 1 mode, counting is enabled in the range 0 to 65535)
• Count clock selection provides four count modes.
• In timer mode, there is a choice of two internal count clock signals.
• In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins.
• In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and
Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc.
• The ZIN pin provides a selection of two functions.
• A compare function and reload function are provided, each for use separately or in combination. Both functions
can be activated together for up/down counting in any desired bandwidth.
• Individual control over interrupts at compare, reload (underflow) and overflow events.
• Count direction flag enables identification of the last previous count direction.
• Interrupt generated when count direction changes.
Count modes Timer mode
Up/down count mode
Phase differential down count mode ( × 2)
Phase differential down count mode ( × 8)
Count clock 125 ns (8 MHz : × 2)
(at 16 MHz operation) 0.5 µs (2 MHz : × 8)
Edge detection Falling edge detection
Rising edge detection
Both rising/falling edge detection
Edge detection disabled
ZIN pin Counter clear function
Gate functions
Compare/reload function Compare function (output interrupt at compare events)
Compare function (output interrupt and clear counter at compare
events)
Reload function (output interrupt and reload at underflow events)
Compare/reload function
(output interrupt and clear counter at compare events, output interrupt
and reload at underflow events)
Compare/reload disabled
MB90480/485 Series
47
(2) Register List
CCRH0 (Counter Control Register High ch.0)
CCRH1 (Counter Control Register High ch.1)
CCRL0/1 (Counter Control Register Low ch.0/ch.1)
CSR0/1 (Counter Status Register ch.0/ch.1)
UDCR0/1 (Up Down Count Register ch.0/ch.1)
RCR0/1 (Reload/Compare Register ch.0/ch.1)
Initial value
Address : 00006DH00000000B
Initial value
Address : 000071H-0000000B
Address
Address
: 00006CH
: 000070H
Initial value
0X00X000B
Address
Address
: 000072H
: 000074H
Initial value
00000000B
Initial value
Address : 000069H00000000B
Initial value
Address : 000068H00000000B
Initial value
Address : 00006BH00000000B
Initial value
Address : 00006AH00000000B
RCR0
UDCR0UDCR1
RCR1
15 0
CCRL0
CSR0
CCRH0
CCRL1
CSR1
CCRH1
87
8-bit
8-bit
Reserved area
Reserved area
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
CDCFM16E CFIE CLKS CMS1 CMS0 CES1 CES0
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W
CDCF⎯CFIE CLKS CMS1 CMS0 CES1 CES0
76543210
R/W W R/W R/W W R/W R/W R/W
CTUTUDMS UCRE RLDE UDCC CGSC CGE1 CGE0
76543210
R/W R/W R/W R/W R/W R/W R R
CITECSTR UDIE CMPF OVFF UDFF UDF1 UDF0
15 14 13 12 11 10 9 8
RRRRRRRR
D16D17 D15 D14 D13 D12 D11 D10
76543210
RRRRRRRR
D06D07 D05 D04 D03 D02 D01 D00
15 14 13 12 11 10 9 8
WWWWWWWW
D16D17 D15 D14 D13 D12 D11 D10
76543210
WWWWWWWW
D06D07 D05 D04 D03 D02 D01 D00
MB90480/485 Series
48
(3) Block Diagram
CGE1 CGE0 CGSC
Carry
CMS1CMS0
UDMS
CES1CES0
CITE UDIE
UDF1 UDF0 CDCF CFIE
CTUT
UCRE RLDE
UDCC
CMPF
UDFF OVFF
CLKS
CSTR
8-bit
8-bit
AIN0
BIN0
ZIN0
UDCR0 (Up/down count register 0)
Edge/level detection Reload control
RCR0 (Reload/ compare register 0)
Up/down
count
clock selection
Prescaler
Data bus
Counter clear
Count
clock
Interrupt
output
MB90480/485 Series
49
7. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16LX CPU to activate the extended intelligent µDMAC or interrupt processing.
(1) Detailed Register Descriptions
(2) Block Diagram
Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register)
Interrupt/DTP Source Register (EIRR : External Interrupt Request Register)
Interrupt Level Setting Register (ELVR : External Level Register)
ENIR Initial value
Address : 00000CH00000000B
EIRR Initial value
Address : 00000DHXXXXXXXXB
Initial value
Address : 00000EH00000000B
Initial value
Address : 00000FH00000000B
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4
4
4
4
8
4
F2MC-16 bus
Interrupt/DTP enable register
Gate Source F/F Edge detection
circuit Request input
Interrupt/DTP source register
Interrupt level setting register
MB90480/485 Series
50
8. 16-bit Input/Output Timer
The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input
capture modules. These functions can be used to output six independent waveforms based on the 16-bit free
run timer, enabling input pulse width measurement and external clock frequency measurement.
• Register List
• 16-bit free run timer
• 16-bit output compare
• 16-bit input capture
CPCLR
15 0
000066/67H
000062/63H
000064/65H
TCDT
TCCS
Compare-clear register
Timer counter data register
Control status register
OCCP0 to OCCP5
15 0
OCS0/2/4OCS1/3/5
00004A, 4C, 4E, 50, 52, 54H
00004B, 4D, 4F, 51, 53, 55H
000056, 58, 5AH
000057, 59, 5BH
Output compare register
Output compare
control registers
IPCP0, IPCP1
15 0
ICS01
00005C, 5EH
00005D, 5FH
000060H
Input capture data register
Input capture control
status register
MB90480/485 Series
51
•Block Diagram
TQ
TQ
TQ
TQ
OUT0
OUT1
OUT2
OUT3
TQ
TQ
OUT4
OUT5
IN0
IN1
Bus
16-bit free run timer
Output
compare 0
Output
compare 1
Output
compare 2
Output
compare 3
Control logic
Interrupt
16-bit timer
Compare register 0
Clear
Compare register 1
Compare register 2
Compare register 3
Capture data register 0
Capture data register 1
To
each
block
Edge
selection
Edge
selection
Input
capture 0
Input
capture 1
Output
compare 5
Output
compare 4
Compare register 5
Compare register 4
MB90480/485 Series
52
(1) 16-bit Free Run Timer
The 16-bit free run timer is composed of a 16-bit up-down counter and control status register.
The counter value of this timer is used as the base timer for the input capture and output compare.
• The counter operation provides a choice of eight clock types.
• A counter overflow interrupt can be produced.
• A mode setting is available to initialize the counter value whenever the output compare value matches the
value in the compare clear register.
• Register List
Compare clear register (CPCLR)
Timer counter data register (TCDT)
Timer control status register (TCCS)
Initial value
000067HXXXXXXXXB
Initial value
000066HXXXXXXXXB
Initial value
000063H00000000B
Initial value
000062H00000000B
Initial value
000065H0--00000B
Initial value
000064H00000000B
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
CL14CL15 CL13 CL12 CL11 CL10 CL09 CL08
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
CL06CL07 CL05 CL04 CL03 CL02 CL01 CL00
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
T14T15 T13 T12 T11 T10 T09 T08
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
T06T07 T05 T04 T03 T02 T01 T00
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
⎯ECKE ⎯MSI2 MSI1 MSI0 ICLR ICRE
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
IVFEIVF STOP MODE SCLR CLK2 CLK1 CLK0
MB90480/485 Series
53
•Block Diagram
IVF IVFE STOP MODE SCLR CLK1 CLK0
ICLR
MSI2 to MSI0 ICRE
CLK2
φ
Compare circuit
Prescaler
Bus
Interrupt
request
A/D activation
16-bit free run timer
Count value output T15 to T00
Clock
Interrupt request
16-bit compare clear register
MB90480/485 Series
54
(2) Output Compare
The output compare module is composed of a 16-bit compare register, compare output pin unit, and control
register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output
levels can be inverted and an interrupt generated.
• There are six compare registers in all, each operating independently. A setting is available to allow two compare
registers to be used to control output.
• Interrupts can be set in terms of compare match events.
• Register List
Output compare registers (OCCP0 to OCCP5)
Output control registers (OCS1/OCS3/OCS5)
Output control registers (OCS0/OCS2/OCS4)
Initial value
00004BH
00004DH
00004FH
000051H
000053H
000055H
00000000B
Initial value
00004AH
00004CH
00004EH
000050H
000052H
000054H
00000000B
Initial value
000057H
000059H
00005BH
---00000B
Initial values
000056H
000058H
00005AH
0000--00B
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
C14C15 C13 C12 C11 C10 C09 C08
7654321
R/W R/W R/W R/W R/W R/W R/W R/W
C06C07 C05 C04 C03 C02 C01 C00
0
15 14 13 12 11 10 9 8
⎯⎯⎯R/W R/W R/W R/W R/W
⎯⎯⎯CMOD OTE1 OTE0 OTD1 OTD0
76543210
R/W R/W R/W R/W ⎯⎯R/W R/W
ICP0ICPIC ICE1 ICE0 ⎯⎯CST1 CST0
MB90480/485 Series
55
•Block Diagram
ICP1 ICP0 ICE0 ICE0
TQ
TQ
CMOD
OTE1
OTE0 OUT0 (2) (4)
OUT1 (3) (5)
Bus
16-bit timer counter value (T15 to T00)
Compare control
Compare register 0 (2, 4)
16-bit timer counter value (T15 to T00)
Compare control
Compare register 1 (3, 5)
Control unit
Individual
control blocks
Compare 1 (3) (5) interrupt
Compare 0 (2) (4) interrupt
MB90480/485 Series
56
(3) Input Capture
The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of
signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An
interrupt can also be generated at the instant of edge detection.
The input capture module consists of input capture registers and a control register. Each input capture module
has its own external input pin.
• Selection of three types of valid edge for external input signals.
Rising edge, falling edge, both edges.
• An interrupt can be generated when a valid edge is detected in the external input signal.
• Register List
•Block Diagram
Input capture data register (IPCP0, IPCP1)
Input capture control status register (ICS01)
Initial value
00005DH
00005FH
XXXXXXXXB
Initial value
00005CH
00005EH
XXXXXXXXB
Initial value
000060H00000000B
15 14 13 12 11 10 9 8
RRRRRRRR
CP14CP15 CP13 CP12 CP11 CP10 CP09 CP08
76543210
RRRRRRRR
CP06CP07 CP05 CP04 CP03 CP02 CP01 CP00
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
ICP0ICP1 ICE1 ICE0 EG11 EG10 EG01 EG00
IN0
EG11 EG10 EG01 EG00
ICP1 ICP0 ICE1 ICE0
IN1
Bus
Capture data register 0
16-bit timer counter value (T15 to T00)
Capture data register 1
Edge detection
Edge detection
Interrupt
Interrupt
MB90480/485 Series
57
9. I2C Interface (MB90485 series only)
The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus.
The I2C interface has the following functions.
• Master/slave transmit/receive
• Arbitration function
• Clock synchronization
• Slave address/general call address detection function
• Forwarding direction detection function
• Start condition repeated generation and detection
• Bus error detection function
(1) Register List
Bus Status Register (IBSR)
Bus control register (IBCR)
Clock control register (ICCR)
Address register (IADR)
Data register (IDAR)
Initial value
000088H00000000B
Initial value
000089H00000000B
Initial value
00008AH--0XXXXXB
Initial value
00008BH-XXXXXXXB
Initial value
00008CHXXXXXXXXB
765 43210
BB RSC AL LRB TRX AAS GCA FBT
RRR RRRRR
15 14 13 12 11 10 9 8
BER BEIE SCC MSS ACK GCAA INTE INT
R/W R/W R/W R/W R/W R/W R/W R/W
765 43210
EN CS4 CS3 CS2 CS1 CS0
R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W
765 43210
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
MB90480/485 Series
58
(2) Block Diagram
ICCR
CS4
CS3
CS2
CS1
CS0
IBSR
ICCR
EN
BB
RSC
LRB
TRX
FBT
AL
Last Bit
56 78
24816 3264128256 Sync
First Byte
SCL
SDA
IRQ
IBCR
IBCR
SCC
MSS
ACK
GCAA
IBSR
AAS
GCA
BER
BEIE
INTE
INT
IDAR
IADR
I
2
C enable
Peripheral clock
Clock selection 1
Clock dividing 1
Clock dividing 2
Clock selection 2
Shift clock generation
Change timing
of shift clock edge
Start/stop condition detection
Bus busy
Repeat start
Transmission/
Reception
Error
Arbitration lost detection
Interrupt request
End
Start
Master
ACK enable
GC-ACK enable
Start/stop condition
detection
Slave
Global call
Slave address
comparison
F
2
MC-16LX Bus
MB90480/485 Series
59
10. 16-bit Reload Timer
The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in
synchronization with three types of internal clock, as well as an event count mode that counts down at specified
edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in
count value from 0000H to FFFFH. Thus an underflow will occur when counting from the value “reload register
setting value + 1”. The choice of counting operations includes reload mode, in which the count setting values is
reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event
causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible.
(1) Register List
• TMCSR (Timer control status register)
Timer control status register (high) (TMCSR)
Timer control status register (low) (TMCSR)
• 16-bit timer register/16-bit reload register
TMR/TMRLR (high)
TMR/TMRLR (low)
0000CBH
Read/Write
Initial value
0000CAH
Read/Write
Initial value
0000CDH
Read/Write
Initial value
0000CCH
Read/Write
Initial value
⎯
⎯⎯
⎯⎯
⎯R/W
0
R/W
0
R/W
0
R/W
0
15 14 13 12 11 10 9 8
⎯
⎯
⎯
⎯⎯⎯CSL1 CSL0 MOD2 MOD1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
76543210
OUTE
R/W
0
MOD0 OUTL RELD INTE UF CNTE TRG
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15 14 13 12 11 10 9 8
D14
R/W
X
D15 D13 D12 D11 D10 D09 D08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
76543210
D06
R/W
X
D07 D05 D04 D03 D02 D01 D00
MB90480/485 Series
60
(2) Block Diagram
TMRLR
TMR
EN
OUTE
RELDOUTL
CLK
CLK
UF
3
3
2
16-bit reload register
16-bit timer register
(down counter)
Reload
control
circuit
Clock
selector
Timer control status register (TMCSR)
Operation
control circuit
Internal data bus
Count clock generator circuit
Machine
clock φPrescaler Valid clock
detection circuit
Gate
input
Clear
Pin
(TIN0)
Input control
circuit
External clock
Function
selection
Select signal
Reload signal
Wait signal
Output signal
generation circuit
Output signal
generation circuit
Pin
(TOT0)
To A/D
converter
Inverted
MB90480/485 Series
61
11. µPG Timer (MB90485 series only)
The µPG timer performs pulse output in response to the external input.
(1) Register List
(2) Block Diagram
µPG control status register (PGCSR)
Initial value
00008EH00000---B
76543210
PEN0 PE1 PE0 PMT1 PMT0
R/W R/W R/W R/W R/W
MT00
MT01
EXTC
MT00
Output latch
MT01
Output latch
Control circuit
Output enable
MB90480/485 Series
62
12. PWC Timer (MB90485 series only)
The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal.
A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide
ratio control register, a measurement input pin, and a 16-bit control register. These components provide the
following functions.
Timer function : • Capable of generating an interrupt request at fixed intervals specified.
• The internal clock used as the reference clock can be selected from
among three types.
Pulse width measurement function : •Measures the time between arbitrary events based on external pulse
inputs.
•The internal clock used as the reference clock can be selected from
among three types.
•Measurement modes
- “H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓)
- Rising cycle (↑ to ↑) /Falling cycle (↓ to ↓)
- Measurement between edges (↑ or ↓ to ↓ or ↑)
•The 8-bit input divider can be used for division measurement by dividing
the input pulse by 22 × n (n = 1, 2, 3, 4) .
•An interrupt can be generated upon completion of measurement.
•One-time measurement or fast measurement can be selected.
MB90480/485 Series
63
(1) Register list
PWC control/status register (PWCSR0 to PWCSR2)
PWC control/status register (PWCSR0 to PWCSR2)
PWC data buffer register (PWCR0 to PWCR2)
PWC data buffer register (PWCR0 to PWCR2)
Dividing ratio control register (DIVR0 to DIVR2)
000077H
00007BH
00007FH
Initial value
0000000XB
000076H
00007AH
00007EH
Initial value
00000000B
000079H
00007DH
000081H
Initial value
00000000B
000078H
00007CH
000080H
Initial value
00000000B
000082H
000084H
000086H
Initial value
------00B
15 14 13 12 11 10 9 8
STRT STOP EDIR EDIE OVIR OVIE ERR
R/W R/W R R/W R/W R/W R
Reserved
76543210
CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0
R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
DIV1 DIV0
R/WR/W
MB90480/485 Series
64
(2) Block Diagram
2
2
2
3
ERR
PWCR
16
2
CKS1/CKS0
16
PIS0/PIS1
ERR
CKS0/
CKS1
PWCSR
DIVR
15
PWC0
PWC1
Error detection
PWCR read
Internal clock (machine clock/4)
Reload
Data transfer
Overflow 16-bit up count timer
Clock
Timer clear
Count enable
Input
waveform
comparator
Dividing ratio selection
Overflow interrupt request
Dividing ON/OFF
Completion of
measurement interrupt request
Control bit output
Flag set etc.
Start of
measurement
edge
Start edge selection
Completion edge selection
Completion of
measurement edge
Control circuit
F
2
MC-16 Bus
Clock divider
8-bit divider
Edge detection
Divider clear
MB90480/485 Series
65
13. Watch Timer
The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined
intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer.
(1) Register List
(2) Block Diagram
Watch timer control register (WTC)
0000AAH
Read/write
Initial value
R
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
76543210
SCE
R/W
1
WDCS WTIE WTOF WTR WTC2 WTC1 WTC0
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
28
29
210
211
212
213
214
210 213 214 215
Sub clock
Watch counter Interval
selector
Interrupt
generator
circuit
Watch timer
interrupt
To watchdog timer
Watch timer control register (WTC)
Clear
MB90480/485 Series
66
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as a count
clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.
(1) Register List
(2) Block Diagram
Watchdog timer control register (WDTC)
0000A8H
Read/write
Initial value
⎯
X
R
X
R
X
R
X
W
1
W
1
W
1
76543210
R
X
PONR WRST ERST SRST WTE WT1 WT0
Reserved
PONR WRST ERST SRST WTE WT1 WT0
× 21× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
× 21
SCLK
CLR
CLR
× 22× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
2
4
4
Watchdog timer control register (WDTC)
Watchdog timer
Watch mode start
Timebase timer
mode start
Sleep mode start
Hold status start Counter
clear
control
circuit
Count
clock
selector
2-bit
counter
Watchdog
reset
generator
circuit
Clear
Internal
reset
generator
circuit
CLR and
start
Time-base counter
HCLK × 2
HCLK : Oscillator clock
SCLK : Sub clock
Watch timer control
register (WTO)
WDCS bit
Clock select register
(CKSCR)
SCM bit
Stop mode
start
Re-
served
MB90480/485 Series
67
15. Timebase Timer
The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the
internal count clock signal (base oscillator × 2) , and functions as an interval timer with a choice of four types of
time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait
period, and operating clock signal feed for other timer circuits such as the watchdog timer.
(1) Register List
(2) Block Diagram
Timebase timer control register (TBTC)
0000A9H
Read/write
Initial value
⎯
X
⎯
X
R/W
0
R/W
0
W
1
R/W
0
R/W
0
15 14 13 12 11 10 9 8
⎯
R/W
1
RESV ⎯TBIE TBOF TBR TBC1 TBC0
OF OF OF OF
× 21× 22× 28× 29× 210 × 211 × 212 × 213× 214 × 215 × 216 × 217 × 218
⎯⎯
RESV TBIE TBOF TBR TBC1 TBC0
Interval timer
selector
To PPG timer
Timebase
timer counter
HCLK × 2
To watchdog
timer
Power-on reset
Counter
clear
control
circuit
TBOF clear
Timebase timer control register (TBTC)
Timebase timer interrupt signal
To clock control
module oscillator
stabilization wait
time selector
TBOF
set
OF : Overflow
HCLK : Oscillator clock
*1 : Switch machine clock from main clock or sub clock to PLL clock.
*2 : Switch machine clock from sub clock to main clock.
Stop mode start
Hold status start
CKSCR : MCS = 1→0*1
CKSCR : SCS = 0→1*2
MB90480/485 Series
68
16. Clock
The clock generator module controls the operation of the internal clock circuits that serve as the operating clock
for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle is referred
to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from
the PLL oscillator are called the PLL clock.
(1) Register List
Clock select register (CKSCR)
PLL output select register (PLLOS)
0000A1H
Read/write
Initial value
0000CFH
Read/write
Initial value
R
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
15 14 13 12 11 10 9 8
MCM
R
1
SCM WS1 WS0 SCS MCS CS1 CS0
⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯W
X
W
0
15 14 13 12 11 10 9 8
⎯
⎯
⎯
⎯⎯⎯⎯ ⎯⎯PLL2
MB90480/485 Series
69
(2) Block Diagram
SCM
HCLK
SCLK
MCM WS1WS0SCSMCSCS1CS0
STP SLP SPL RST TMD CG1 CG0
Re-
served
2
2
X0A
X1A
RST
X0
X1
MCLK
⎯⎯⎯⎯⎯⎯⎯PLL2
× 4
× 2 ×
1024 × 2 × 4 × 4 × 4 × 2
PLL multiplier
circuit
Low-power consumption mode control register (LPMCR)
Interrupt release
CPU intermittent
operation selector
Pin high-impedance
control circuit
Clock
selector
Sub clock
generator
circuit
pin
Oscillator
stabilization
wait period
selector
Clock select register (CKSCR)
Timebase
timer
pin
Peripheral
clock control
circuit
Internal reset
generator circuit
Standby control circuit
pin
pin
To watchdog timer
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
Standby control
circuit
CPU clock
control circuit
pin
System
clock
generator
circuit
Clock generator module
Machine clock
Oscillator stabilization wait release
Pin
high-impedance
control
CPU clock
Internal reset
Stop, sleep signals
Stop signal
Peripheral
clock
Intermittent cycle selection
PLL output select register (PLLOS)
MB90480/485 Series
70
(3) Clock Feed Map
4
4
3
X0A
X1A
X0
HCLK MCLK
UART0
CPU, µDMAC
SCLK PCLK
X1
φ
1234
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
TIN0
TOT0
SCK0, SIN0
SOT0
SCK1, SCK2
SOT1, SOT2
OUT0, OUT1, OUT2,
IN0, IN1
AN0 to AN7, ADTG
CS0, CS1,
FRCK
IRQ0 to IRQ7
SIN1, SIN2
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
CS2, CS3
OUT3, OUT4, OUT5
Watchdog timer
Oscillator
stabilization
wait control
pin
pin
pin
pin
pins
× 4
× 2 Clock
selector
PLL multiplier
circuit
Watch timer
Timebase
timer
Sub clock
generator
circuit
System clock
generator
circuit
8/16-bit PPG
timer 0
8/16-bit PPG
timer 1
8/16-bit PPG
timer 2
16-bit reload
timer 0
Chip select
16-bit output
compare
16-bit free run
timer
16-bit input
capture
10-bit A/D
converter
pins
pins
pin
pin
pins
pin
pins
pins
pins
pins
pins
pin
pins
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
PCLK : PLL clock
φ : Machine clock
Peripheral functions
Clock generator module
pins
pin
Extended I/O
serial interface,
2 channels
8/16-bit
up/down counter
External interrupt
MB90480/485 Series
71
17. Low-power Consumption Mode
The MB90480/485 series uses operating clock selection and clock operation controls to provide the following
CPU operating modes :
• Clock modes
(PLL clock mode, main clock mode, sub clock mode)
• CPU intermittent operating modes
(PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode)
• Standby modes
(Sleep mode, timebase timer mode, stop mode, watch mode)
(1) Register List
Low-power consumption mode control register (LPMCR)
0000A0H
Read/write
Initial value
W
0
R/W
0
W
1
R/W
1
R/W
0
R/W
0
R/W
0
76543210
SLP
W
0
STP SPL RST TMD CG1 CG0 Reserved
MB90480/485 Series
72
(2) Block Diagram
SCM
HCLK
SCLK
MCM WS1WS0SCSMCSCS1CS0
STP SLP SPL RST TMD CG1 CG0 Re-
served
2
2
X0A
X1A
RST
X0
X1
MCLK
⎯⎯⎯⎯⎯⎯⎯PLL2
× 4
× 2 ×
1024 × 2 × 4 × 4 × 4 × 2
Low-power consumption mode control register (LPMCR)
Interrupt release
CPU intermittent
operating selector
Pin
high-impedance
control circuit
Clock
selector
Sub clock
generator
circuit
pin
Oscillator
stabiliza-
tion
wait period
selector
Clock select register (CKSCR)
Timebase
timer
pin
Peripheral
clock control
circuit
Internal reset
generator circuit
Standby control circuit
PLL multiplier
circuit
pin
pin
To watchdog timer
HCLK : Oscillator clock
MCLK : Main clock
SCLK : Sub clock
Standby control
circuit
CPU clock
control circuit
pin
System
clock
generator
circuit
Clock generator module
Machine clock
Oscillator stabilization wait release
Pin
high-impedance
control
CPU clock
Internal reset
Stop, sleep signals
Stop signal
Peripheral clock
Intermittent cycle selection
PLL output select register (PLLOS)
MB90480/485 Series
73
(3) Status Transition Chart
STP = 1 STP = 1 STP = 1
TMD = 0 TMD = 0 TMD = 0
SLP = 1 SLP = 1 SLP = 1
MCS = 0
MCS = 1
SCS = 0
SCS = 0
SCS = 1
SCS = 1
Power-on reset
Power-on
Main clock
mode
Main sleep
mode
Main timebase
timer mode
Main stop
mode
Main clock oscillator
stabilization wait
PLL clock
mode
PLL sleep
mode
PLL timebase
timer mode
PLL stop
mode
Main clock oscillator
stabilization wait
Sub clock
mode
Sub sleep
mode
Watch mode
Sub stop
mode
Sub clock oscillator
stabilization wait
Interrupt Interrupt Interrupt
Interrupt Interrupt Interrupt
Oscillator
stabilization
wait ends
Reset
External reset, watchdog timer reset, software reset
Interrupt Interrupt Interrupt
Oscillator
stabilization
wait ends
Oscillator
stabilization
wait ends
Oscillator
stabilization
wait ends
MB90480/485 Series
74
18. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus
connections to external circuits.
(1) Register List
(2) Block Diagram
• Auto ready function select register (ARSR)
• External address output control register (HACR)
• Bus control signal select register (EPCR)
Initial value
Address : 0000A5H0011--00B
Initial value
Address : 0000A6H********B
Initial value
Address : 0000A7H1000*10-B
W
−
*
: Write only
: Not used
: May be either “1” or “0”
WWW⎯⎯WW
15 14 13 12 11 10 9 8
IOR0
W
IOR1 HMR1 HMR0 ⎯⎯LMR1 LMR0
WW W W WWW
76543210
E22
W
E23 E21 E20 E19 E18 E17 E16
WWWW WW⎯
15 14 13 12 11 10 9 8
RYE
W
CKE HDE IOBS HMBS WRE LMBS ⎯
P3
P2
P1
P0
P0
P5
RB
P4
P5
Access control Access control
Address control
Data control
P0 direction
P0 data
MB90480/485 Series
75
19. Chip Select Function Description
The chip select module generates a chip select signals, which are used to facilitate connections to external
memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area
register setting that specifies the corresponding hardware area and select signal that is output when access to
the corresponding external address is detected.
• Chip select function features
The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to
detect memory areas in 64 Kbytes units by specifying the upper 8-bit of the address for match detection. The
other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match
detection.
Note that during external bus holds, the CS output is set to high impedance.
(1) Register List
Chip select area mask register (CMRx)
Chip select area register (CARx)
Chip select control register (CSCR)
Chip select active level register (CALR)
0000C0H
0000C2H
0000C4H
0000C6H
Read/write
Initial value
0000C1H
0000C3H
0000C5H
0000C7H
Read/write
Initial value
0000C8H
Read/write
Initial value
0000C9H
Read/write
Initial value
CMR1
CMR0CAR0
R/W
R/W
CAR1
15 0
CMR3
CMR2CAR2
R/W
R/W
CAR3
CSCR R/WCALR
87
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
76543210
M6
R/W
0
M7 M5 M4 M3 M2 M1 M0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15 14 13 12 11 10 9 8
A6
R/W
1
A7 A5 A4 A3 A2 A1 A0
⎯
⎯⎯
⎯⎯
⎯R/W
0
R/W
0
R/W
0
R/W
*
76543210
⎯
⎯
⎯
⎯⎯⎯OPL3 OPL2 OPL1 OPL0
⎯
⎯⎯
⎯⎯
⎯R/W
0
R/W
0
R/W
0
R/W
0
15 14 13 12 11 10 9 8
⎯
⎯
⎯
⎯⎯⎯ACTL3 ACTL2 ACTL1 ACTL0
* : The initial value of this bit is “1” or “0”.
The value depends on the mode pin (MD2, MD1 and MD0) .
MB90480/485 Series
76
(2) Block Diagram
A23 to A16
CMRx
CARx
F2MC-16LX Bus
Chip select output pins
MB90480/485 Series
77
20. ROM Mirror Function Select Module
The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read
by access to 00 bank.
(1) Register List
(2) Block Diagram
Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000H to
00FFFFH (008000H to 00FFFFH) .
• ROM mirror function select register (ROMM)
- : Not used
Initial value
Address : 00006FH------+1B
( + ) : MB90F489B : Read only, fixed at “1”
Other : Selectable, Initial value 0
R/W R/W
15 14 13 12 11 10 9 8
⎯⎯⎯⎯⎯⎯MS MI
(+)
ROM
Address area
FF bank 00 bank
ROM mirror function select
F2MC-16LX bus
MB90480/485 Series
78
21. Interrupt Controller
The interrupt control register is built in interrupt controller, and is supported for all I/O of interrupt function.
This register sets corresponding peripheral interrupt level.
(1) Register List
Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be
avoided.
Interrupt control registers
Address : ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
0000B1H
0000B3H
0000B5H
0000B7H
0000B9H
0000BBH
0000BDH
0000BFH
ICR01,
03, 05,
07, 09,
11, 13, 15
Read/write→
Initial value→
Interrupt control registers
Address : ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
ICR00,
02, 04,
06, 08,
10, 12, 14
Read/write→
Initial value→
15 14 13 12 11 10 9 8
W
X
W
X
W
X
R/W
0
R/W
1
R/W
1
R/W
1
⎯
W
X
⎯⎯⎯
Reserved IL2 IL1 IL0
76543210
W
X
W
X
W
X
R/W
0
R/W
1
R/W
1
R/W
1
⎯
W
X
⎯⎯⎯
Reserved IL2 IL1 IL0
MB90480/485 Series
79
(2) Block Diagram
IL2 IL1 IL0 3233
3
F2MC-16LX Bus
Interrupt priority setting
Interrupt requests
(Peripheral resources)
(CPU)
Interrupt level
MB90480/485 Series
80
22. µDMAC
The µDMAC is a simplified DMA module with functions equivalent to EI2OS. The µDMAC has 16 DMA data
transfer channels, and provides the following functions.
• Automatic data transfer between peripheral resources (I/O) and memory.
• CPU program execution stops during DMA operation.
• Incremental addressing for transfer source and destination can be turned on/off.
• DMA transfer control from the µDMAC enable register, µDMAC stop status register, µDMAC status register,
and descriptor.
• Stop requests from resources can stop DMA transfer.
• When DMA transfer is completed, the µDMAC status register sets a flag in the bit for the corresponding channel
on which transfer was completed, and outputs a completion interrupt to the interrupt controller.
(1) Register List
µDMAC enable register
Initial value
DERH : 0000ADH00000000B
µDMAC enable register
Initial value
DERL : 0000ACH00000000B
µDMAC stop status register
Initial value
DSSR : 0000A4H00000000B
µDMAC status register
Initial value
DSRH : 00009DH00000000B
µDMAC status register
Initial value
DSRL : 00009CH00000000B
R/W R/W
15 14 13 12 11 10 9 8
EN14EN15 EN13 EN12 EN11 EN10 EN9 EN8
R/W R/W R/W R/WR/W R/W
R/W R/W
76543210
EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0
R/W R/W R/W R/WR/W R/W
R/W R/W
76543210
STP6STP7 STP5 STP4 STP3 STP2 STP1 STP0
R/W R/W R/W R/WR/W R/W
R/W R/W
15 14 13 12 11 10 9 8
DE14DE15 DE13 DE12 DE11 DE10 DE9 DE8
R/W R/W R/W R/WR/W R/W
R/W R/W
76543210
DE6DE7 DE5 DE4 DE3 DE2 DE1 DE0
R/W R/W R/W R/WR/W R/W
MB90480/485 Series
81
(2) Block Diagram
CPU
DCT
BAP
IOA
F2MC-16LX Bus
Memory space
I/O register
µDMAC
descriptor
BufferTransfer
I/O register Peripheral function
(I/O)
DMA transfer request
If transfer not ended
Read by DER µDMA controller
If transfer is
ended
Interrupt
controller
IOA : I/O address pointer
BAP : Buffer address pointer
DER : µDMAC enable register (ENx selection)
DCT : Data counter
MB90480/485 Series
82
23. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction,
the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function
to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register List
• Program address detection register 0 (PADR0)
76543210 Initial value
XXXXXXXX B
R/W : Readable and writable
X : Undefined
RESV : Reserved bit
Address
PADR0 (Low order address) : 001FF0H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
XXXXXXXX B
Address
PADR0 (Middle order address) : 001FF1H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
XXXXXXXX B
Address
PADR0 (High order address) : 001FF2H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
XXXXXXXX B
Address
PADR1 (Low order address) : 001FF3H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
XXXXXXXX B
Address
PADR1 (Middle order address) : 001FF4H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
XXXXXXXX B
Address
PADR1 (High order address) : 001FF5H
R/W R/W R/W R/W R/W R/W R/W R/W
76543210 Initial value
00000000B
Address
00009EH
R/W R/W R/W R/W R/W R/W R/W R/W
• Program address detection register 1 (PADR1)
• Program address detection control status register (PACSR)
RESV RESV RESV RESV AD1E RESV AD0E RESV
MB90480/485 Series
83
(2) Block Diagram
Internal data bus
Compare
Address latch
Enable bit
F2MC-16LX
CPU core
Address detection
register INT9
instruction
MB90480/485 Series
84
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
*1 : This parameter is based on VSS = AVSS = 0.0 V.
*2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC.
*3 : VI and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*4 : Maximum output current is defined as the peak value for one of the corresponding pins.
*5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding
pins.
*6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins.
*7 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA3
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC3VSS − 0.3 VSS + 4.0 V
VCC5VSS − 0.3 VSS + 7.0 V
AVCC VSS − 0.3 VSS + 4.0 V *2
AVRH VSS − 0.3 VSS + 4.0 V *2
Input voltage*1VI
VSS − 0.3 VSS + 4.0 V *3
VSS − 0.3 VSS + 7.0 V *3, *8, *9
Output voltage*1VO
VSS − 0.3 VSS + 4.0 V *3
VSS − 0.3 VSS + 7.0 V *3, *8, *9
Maximum clamp current ICLAMP −2.0 +2.0 mA *7
Total maximum clamp current Σ⏐ICLAMP⏐⎯ 20 mA *7
“L” level maximum output current IOL ⎯10 mA *4
“L” level average output current IOLAV ⎯3mA*5
“L” level maximum total output current ΣIOL ⎯60 mA
“L” level total average output current ΣIOLAV ⎯30 mA *6
“H” level maximum output current IOH ⎯−10 mA *4
“H” level average output current IOHAV ⎯−3mA*5
“H” level maximum total output current ΣIOH ⎯−60 mA
“H” level total average output current ΣIOHAV ⎯−30 mA *6
Power consumption PD⎯320 mW
Operating temperature TA−40 +85 °C
Storage temperature Tstg −55 +150 °C
MB90480/485 Series
85
(Continued)
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
*8 : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin.
P76 and P77 is N-ch open drain pin.
*9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
Protective diode
Limiting
resistance
+B input (0 V to 16 V)
• Input/Output Equivalent circuits
MB90480/485 Series
86
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
* : MB90485 series only
P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage
VCC32.7 3.6 V During normal operation
1.8 3.6 V To maintain RAM state in stop mode
VCC52.7 5.5 V During normal operation*
1.8 5.5 V To maintain RAM state in stop mode*
“H” level input voltage
VIH 0.7 VCC VCC + 0.3 V All pins other than VIH2, VIHS, VIHM and
VIHX
VIH2 0.7 VCC VSS + 5.8 V MB90485 series only
P76, P77 pins (N-ch open drain pins)
VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins
VIHM VCC − 0.3 VCC + 0.3 V MD pin input
VIHX 0.8 VCC VCC + 0.3 V X0A pin, X1A pin
“L” level input voltage
VIL VSS − 0.3 0.3 VCC V All pins other than VILS, VILM and VILX
VILS VSS − 0.3 0.2 VCC V Hysteresis input pins
VILM VSS − 0.3 VSS + 0.3 V MD pin input
VILX VSS − 0.3 0.1 V X0A pin, X1A pin
Operating temperature TA−40 +85 °C
MB90480/485 Series
87
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Notes :•MB90485 series only
• P40 to P47 and P70 to P77 are N-ch open drain pins with control, which are usually used as CMOS.
• P76 and P77 are open drain pins without P-ch.
• For use as a single 3 V power supply products, set VCC = VCC3 = VCC5.
• When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and
P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
output voltage VOH All output
pins
VCC = 2.7 V,
IOH = −1.6 mA VCC3 − 0.3 ⎯⎯V
VCC = 4.5 V,
IOH = −4.0 mA VCC5 − 0.5 ⎯⎯VAt using 5 V
power supply
“L” level
output voltage VOL All output
pins
VCC = 2.7 V,
IOL = 2.0 mA ⎯⎯0.4 V
VCC = 4.5 V,
IOH = 4.0 mA ⎯⎯0.4 V At using 5 V
power supply
Input leakage
current IIL All input
pins
VCC = 3.3 V,
VSS < VI < VCC −10 ⎯+10 µA
Pull-up
resistance RPULL ⎯VCC = 3.0 V,
at TA = +25 °C20 53 200 kΩ
Open drain
output current Ileak P40 to P47,
P70 to P77 ⎯⎯0.1 10 µA
Power supply
current
ICC ⎯
At VCC = 3.3 V,
internal 25 MHz operation,
normal operation
⎯45 60 mA
At VCC = 3.3 V,
internal 25 MHz operation,
Flash programming
⎯55 70 mA
ICCS ⎯At VCC = 3.3 V,
internal 25 MHz operation,
sleep mode
⎯17 35 mA
ICCL ⎯
At VCC = 3.3 V,
external 32 kHz,
internal 8 kHz operation,
sub clock operation
(TA = +25 °C)
⎯15 140 µA
ICCT ⎯
At VCC = 3.3 V,
external 32 kHz,
internal 8 kHz operation,
watch mode (TA = +25 °C)
⎯1.8 40 µA
ICCH ⎯TA = +25 °C, stop mode,
At VCC = 3.3 V ⎯0.8 40 µA
Input
capacitance CIN
Other than
AVCC, AVSS,
VCC, VSS
⎯⎯515pF
MB90480/485 Series
88
4. AC Characteristics
(1) Clock Timing
(VSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : Be careful of the operating voltage.
*2 : Duty ratio should be 50 % ± 3 %.
Parameter Sym-
bol Pin name Condi-
tion
Value Unit Remarks
Min Typ Max
Clock frequency FCH X0, X1
⎯3⎯25
MHz
External crystal
oscillator
⎯3⎯50 External clock input
⎯4⎯25 1 multiplied PLL
⎯3⎯12.5 2 multiplied PLL
⎯3⎯6.66 3 multiplied PLL
⎯3⎯6.25 4 multiplied PLL
⎯3⎯4.16 6 multiplied PLL
⎯3⎯3.12 8 multiplied PLL
FCL X0A, X1A ⎯⎯32.768 ⎯kHz
Clock cycle time tCX0, X1 ⎯20 ⎯333 ns *1
tCL X0A, X1A ⎯⎯30.5 ⎯µs
Input clock pulse width
PWH
PWL X0 ⎯5⎯⎯ns
PWLH
PWLL X0A ⎯⎯15.2 ⎯µs*2
Input clock rise, fall time tcr
tcf X0 ⎯⎯⎯5 ns With external clock
Internal operating clock
frequency
fCP ⎯⎯1.5 ⎯25 MHz *1
fCPL ⎯⎯⎯8.192 ⎯kHz
Internal operating clock
cycle time
tCP ⎯⎯40.0 ⎯666 ns *1
tCPL ⎯⎯⎯122.1 ⎯µs
MB90480/485 Series
89
• X0, X1 clock timing
X0
t
C
t
cf
t
cr
0.8 V
CC
0.2 V
CC
P
WH
P
WL
• X0A, X1A clock timing
X0A
tCL
tcf tcr
0.8 VCC
0.2 VCC
PWLH PWLL
MB90480/485 Series
90
3.6
2.7
3.0
41.5 16
25
16
12
25
8
4
34 8 12.5 16 2520 32 50
20
6
1.5
9
18
24
5 6 10 40
Range of warranted PLL operation
Normal operating range
Power supply voltage
VCC (V)
Internal clock fCP (MHz)
Internal operating clock frequency vs. Power supply voltage
Base oscillator frequency vs. Internal operating clock frequency
Base oscillator clock FCH (MHz)
Internal clock fCP (MHz)
• Range of warranted PLL operation
Notes: • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”
• Only at 1 multiplied PLL, use with more than fCP = 4 MHz.
No multiplied
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, set
the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”.
[Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
[Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, the following
setting is also enabled.
2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PLLOS register : PLL2 bit = “1”
4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PLLOS register : PLL2 bit = “1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”.
[Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : PLL2 bit = “1”
[Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : PLL2 bit = “1”
1 × *1
2 × *1,*2
3 × *1
4 ×
*1,*2
6 × *3
8 × *3
MB90480/485 Series
91
AC standards are set at the following measurement voltage values.
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.7 VCC
0.3 VCC
• Input signal waveform
Hysteresis input pins
• Output signal waveform
Output pins
• Pins other than hysteresis input/MD input
MB90480/485 Series
92
(2) Clock Output Timing
(VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
Cycle time tCYC CLK ⎯tCP*⎯ns
CLK↑→CLK↓tCHCL CLK
VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15 ns at fCP = 25 MHz
VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20 ns at fCP = 16 MHz
VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64 ns at fCP = 5 MHz
CLK
t
CYC
2.4 V 2.4 V
0.8 V
t
CHCL
MB90480/485 Series
93
(3) Reset Input Standards
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
*2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several
milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to
several milliseconds. For an external clock signal the value is 0 ms.
Parameter Symbol Pin
name
Condi-
tions
Value Unit Remarks
Min Max
Reset input time tRSTL RST ⎯
16 tCP*1⎯ns Normal operation
Oscillator oscillation time*2
+ 4 tCP*1⎯ms Stop mode
RST
X0
4 t
CP
t
RSTL
0.2 Vcc 0.2 Vcc
• In stop mode
Internal
operating
clock
Internal reset
Oscillator
oscillation time
Oscillator stabilization wait time
Instruction execution
90 % of
amplitude
CL
• Condition for measurement of AC standards
Pin
CL : Load capacitance applied to pins during testing
CLK, ALE : CL = 30 pF
AD15 to AD00 (address data bus) , RD, WR,
A23 to A00/D15 to D00 : CL = 30 pF
MB90480/485 Series
94
(4) Power-on Reset Standards
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : Power rise time requires VCC < 0.2 V.
Notes: •The above standards are for the application of a power-on reset.
•Within the device, the power-on reset should be applied by switching the power supply off and on again.
Note : Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below,
when changing supply voltage during operation, it is recommended that voltage changes be suppressed
and a smooth restart be applied.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
Power rise time tRVCC ⎯0.05 30 ms *
Power down time tOFF VCC 1⎯ms In repeated operation
V
CC
t
R
t
OFF
2.7 V
0.2 V 0.2 V0.2 V
V
CC
V
SS
The slope of voltage increase
should be kept within 50 mV/ms.
RAM data maintenance
Main power supply voltage
Sub power supply voltage
MB90480/485 Series
95
(5) Bus Read Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
ALE pulse width tLHLL ALE ⎯
tCP* / 2 − 15 ⎯ns 16 MHz < fCP ≤
25 MHz
tCP* / 2 − 20 ⎯ns 8 MHz < fCP ≤
16 MHz
tCP* / 2 − 35 ⎯ns fCP ≤ 8 MHz
Valid address→
ALE↓time tAVLL Address,
ALE ⎯tCP* / 2 − 17 ⎯ns
tCP* / 2 − 40 ⎯ns fCP ≤ 8 MHz
ALE↓→
address valid time tLLAX ALE,
Address ⎯tCP* / 2 − 15 ⎯ns
Valid address→
RD↓time tAVRL RD,
address ⎯tCP* − 25 ⎯ns
Valid address→
valid data input tAVDV Address,
Data ⎯⎯5 tCP* / 2 − 55 ns
⎯5 tCP* / 2 − 80 ns fCP ≤ 8 MHz
RD pulse width tRLRH RD ⎯
3 tCP* / 2 − 25 ⎯ns 16 MHz < fCP ≤
25 MHz
3 tCP* / 2 − 20 ⎯ns 8 MHz < fCP ≤
16 MHz
RD↓→
valid data input tRLDV RD,
Data ⎯⎯3 tCP* / 2 − 55 ns
⎯3 tCP* / 2 − 80 ns fCP ≤ 8 MHz
RD↑→data hold time tRHDX RD,
Data ⎯0⎯ns
RD↑→ALE↑time tRHLH RD, ALE ⎯tCP* / 2 − 15 ⎯ns
RD↑→
address valid time tRHAX Address,
RD ⎯tCP* / 2 − 10 ⎯ns
Valid address→
CLK↑time tAVCH Address,
CLK ⎯tCP* / 2 − 17 ⎯ns
RD↓→CLK↑time tRLCH RD, CLK ⎯tCP* / 2 − 17 ⎯ns
ALE↓→RD↓time tLLRL RD, ALE ⎯tCP* / 2 − 15 ⎯ns
MB90480/485 Series
96
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.3 VCC
0.7 VCC
0.3 VCC
0.7 VCC
CLK
ALE
RD
A23 to A16
AD15 to AD00
2.4 V
tAVCH
tLHLL
tRHLH
tAVLL
tAVRL tRLDV
tRLRH
tRHAX
tRHDX
tLLAX
tLLRL
tRLCH
tAVDV
0.8 V
2.4 V
0.8 V
2.4 V
0.3 VCC
0.7 VCC
0.3 VCC
0.7 VCC
A23 to A00
D15 to D00
tRLDV
tRHAX
tRHDX
tAVDV
0.8 V
2.4 V
Address Read data
Read data
In multiplexed mode
In non-multiplexed mode
MB90480/485 Series
97
(6) Bus Write Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Parameter Sym-
bol Pin name Condi-
tion
Value Unit Remarks
Min Max
Valid address→WR↓time tAVWL Address, WR ⎯tCP* − 15 ⎯ns
WR pulse width tWLWH WRL, WRH
⎯3 tCP* / 2 − 25 ⎯ns 16 MHz < fCP ≤
25 MHz
⎯3 tCP* / 2 − 20 ⎯ns 8 MHz < fCP ≤
16 MHz
Valid data output →WR↑time tDVWH Data, WR ⎯3 tCP* / 2 − 15 ⎯ns
WR↑→data hold time tWHDX WR,
Data
⎯10 ⎯ns 16 MHz < fCP ≤
25 MHz
⎯20 ⎯ns 8 MHz < fCP ≤
16 MHz
⎯30 ⎯ns fCP ≤ 8 MHz
WR↑→address valid time tWHAX WR, Address ⎯tCP* / 2 − 10 ⎯ns
WR↑→ALE↑time tWHLH WR, ALE ⎯tCP* / 2 − 15 ⎯ns
WR↓→CLK↑time tWLCH WR, CLK ⎯tCP* / 2 − 17 ⎯ns
MB90480/485 Series
98
WR
(WRL, WRH) 0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
CLK
ALE
A23 to A16
AD15 to AD00
tWHLH
tAVWL
tDVWH
tDVWH
tWLWH
tWHAX
tWHDX
tWLCH
0.8 V
2.4 V
0.8 V
2.4 V
A23 to A00
D15 to D00
tWHAX
tWHDX
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
Address Write data
Write data
In multiplexed mode
In non-multiplexed mode
MB90480/485 Series
99
(7) Ready Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
RDY setup time tRYHS RDY
⎯35 ⎯ns
⎯70 ⎯ns at fCP = 8 MHz
RDY hold time tRYHH ⎯0⎯ns
tRYHH
2.4 V 2.4 V
0.2 VCC0.2 VCC
0.8 VCC 0.8 VCC
CLK
ALE
RD/WR
tRYHS
tRYHS
RDY wait
inserted
(1 cycle)
RDY wait not
inserted
MB90480/485 Series
100
(8) Hold Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
(9) UART Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : The above rating is in CLK synchronous mode.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
Pin floating→HAK↓time tXHAL HAK ⎯30 tCP*ns
HAK↓→pin valid time tHAHV HAK tCP*2 tCP*ns
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Max
Serial clock cycle time tSCYC ⎯
Internal shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
8 tCP*2⎯ns
SCK↓→SOT delay time tSLOV ⎯−80 +80 ns
−120 +120 ns fCP = 8 MHz
Valid SIN→SCK↑tIVSH ⎯100 ⎯ns
200 ⎯ns fCP = 8 MHz
SCK↑→valid SIN hold time tSHIX ⎯tCP*2⎯ns
Serial clock “H” pulse width tSHSL ⎯
External shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
4 tCP*2⎯ns
Serial clock “L” pulse width tSLSH ⎯4 tCP*2⎯ns
SCK↓→SOT delay time tSLOV ⎯⎯150 ns
⎯200 ns fCP = 8 MHz
Valid SIN→SCK↑tIVSH ⎯60 ⎯ns
120 ⎯ns fCP = 8 MHz
SCK↑→valid SIN hold time tSHIX ⎯60 ⎯ns
120 ⎯ns fCP = 8 MHz
HAK
tXHAL tHAHV
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
0.8 V
Pins High-Z
MB90480/485 Series
101
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN
t
SLSH
t
SHSL
t
SLOV
t
IVSH
t
SHIX
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
MB90480/485 Series
102
(10) Extended I/O Serial Interface Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Notes : • The above rating is in CLK synchronous mode.
• Values on this table are target values.
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Max
Serial clock cycle time tSCYC ⎯
Internal shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
8 tCP*2⎯ns
SCK↓→SOT delay time tSLOV ⎯−80 + 80 ns
−120 + 120 ns fCP = 8 MHz
Valid SIN→SCK↑tIVSH ⎯100 ⎯ns
200 ⎯ns fCP = 8 MHz
SCK↑→valid SIN hold time tSHIX ⎯tCP*2⎯ns
Serial clock “H” pulse width tSHSL ⎯
External shift clock
mode output pins :
CL*1 = 80 pF + 1 TTL
4 tCP*2⎯ns
Serial clock “L” pulse width tSLSH ⎯4 tCP*2⎯ns
SCK↓→SOT delay time tSLOV ⎯⎯150 ns
⎯200 ns fCP = 8 MHz
Valid SIN→SCK↑tIVSH ⎯60 ⎯ns
120 ⎯ns fCP = 8 MHz
SCK↑→valid SIN hold time tSHIX ⎯60 ⎯ns
120 ⎯ns fCP = 8 MHz
MB90480/485 Series
103
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN
t
SLSH
t
SHSL
t
SLOV
t
IVSH
t
SHIX
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
MB90480/485 Series
104
(11) Timer Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
(12) Timer Output Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
Input pulse width tTIWH
tTIWL
TIN0,
IN0, IN1,
PWC0 to PWC2
⎯4 tCP*⎯ns
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Max
CLK↑→Change time
PPG0 to PPG5 change time
OUT0 to OUT5 change time
tTO
TOT0,
PPG0 to PPG5,
OUT0 to OUT5
Load
conditions
80 pF
30 ⎯ns
0.8 VCC
TIN0
IN0, IN1
PWC0 to PWC2
0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
0.7 V
CC
CLK
TOT0
0.3 V
CC
0.7 V
CC
t
TO
PPG0 to PPG5
OUT0 to OUT5
MB90480/485 Series
105
(13) I2C Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock Timing”.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA and SCL set-up time”.
Note : VCC = VCC3 = VCC5
Parameter Symbol Condition Standard-mode Unit
Min Max
SCL clock frequency fSCL
When power supply voltage of
external pull-up resistance is 5.5 V
R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R = 1.6 kΩ, C = 50 pF*2
0 100 kHz
Hold time (repeated) START condition
SDA↓→SCL↓tHDSTA 4.0 ⎯µs
“L” width of the SCL clock tLOW 4.7 ⎯µs
“H” width of the SCL clock tHIGH 4.0 ⎯µs
Set-up time (repeated) START
condition SCL↑→SDA↓tSUSTA 4.7 ⎯µs
Data hold time
SCL↓→SDA↓↑ tHDDAT 0 3.45*3µs
Data set-up time
SDA↓↑→SCL↑tSUDAT
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1 ≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
fCP*1 ≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2
250*4⎯ns
When power supply voltage of
external pull-up resistance is 5.5 V
fCP*1 > 20 MHz, R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
fCP*1 > 20 MHz, R = 1.6 kΩ, C = 50 pF*2
200*4⎯ns
Set-up time for STOP condition
SCL↑→SDA↑tSUSTO When power supply voltage of
external pull-up resistance is 5.5 V
R = 1.3 kΩ, C = 50 pF*2
When power supply voltage of
external pull-up resistance is 3.6 V
R = 1.6 kΩ, C = 50 pF*2
4.0 ⎯µs
Bus free time between a STOP and
START condition tBUS 4.7 ⎯µs
MB90480/485 Series
106
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
SDA
SCL
6 tcp
• Note of SDA and SCL set-up time
Input data set-up time
SDA
SCL
tBUS
tLOW
fSCL
tHDDAT tHIGH
tSUDAT
tHDSTA tSUSTA
tHDSTA
tSUSTO
• Timing definition
MB90480/485 Series
107
(14) Trigger Input Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
(15) Up-down Counter Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Parameter Symbol Pin name Condi-
tions
Value Unit Remarks
Min Max
Input pulse width tTRGH
tTRGL
ADTG,
IRQ0 to IRQ7 ⎯5 tCP*⎯ns Normal operation
1⎯µs Stop mode
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
AIN input “H” pulse width tAHL
AIN0, AIN1,
BIN0, BIN1 Load
conditions
80 pF
8 tCP*⎯ns
AIN input “L” pulse width tALL 8 tCP*⎯ns
BIN input “H” pulse width tBHL 8 tCP*⎯ns
BIN input “L” pulse width tBLL 8 tCP*⎯ns
AIN↑→BIN↑ time tAUBU 4 tCP*⎯ns
BIN↑→AIN↓ time tBUAD 4 tCP*⎯ns
AIN↓→BIN↑ time tADBD 4 tCP*⎯ns
BIN↓→AIN↑ time tBDAU 4 tCP*⎯ns
BIN↑→AIN↑ time tBUAU 4 tCP*⎯ns
AIN↑→BIN↓ time tAUBD 4 tCP*⎯ns
BIN↓→AIN↑ time tBDAD 4 tCP*⎯ns
AIN↓→BIN↑ time tADBU 4 tCP*⎯ns
ZIN input “H” pulse width tZHL ZIN0, ZIN1 4 tCP*⎯ns
ZIN input “L” pulse width tZLL 4 tCP*⎯ns
0.8 V
CC
IRQ0 to IRQ7
ADTG
0.8 V
CC
0.2 V
CC
0.2 V
CC
t
TRGH
t
TRGL
MB90480/485 Series
108
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
0.8 V
CC
0.8 V
CC
0.2 V
CC
t
ALL
t
BLL
t
BHL
t
AHL
t
AUBU
t
BUAD
t
ADBD
t
BDAU
AIN
BIN
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
0.8 V
CC
0.2 V
CC
t
BUAU
t
AUBD
t
ZHL
t
ZLL
t
BDAD
t
ADBU
BIN
AIN
ZIN
MB90480/485 Series
109
(16) Chip Select Output Timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : Due to the configuration of the internal bus, the chip select output signals are changed simultaneously and
therefore may cause the bus conflict conditions. AC cannot be warranted between the ALE output signal
and the chip select output signal.
Parameter Sym-
bol Pin name Condi-
tions
Value Unit Remarks
Min Max
Chip select output valid time
→RD↓tSVRL CS0 to CS3,
RD ⎯tCP* / 2 − 7 ⎯ns
Chip select output valid
time→WR↓tSVWL CS0 to CS3,
WRH, WRL ⎯tCP* / 2 − 7 ⎯ns
RD↑→chip select output valid
time tRHSV RD,
CS0 to CS3 ⎯tCP* / 2 − 17 ⎯ns
WR↑→chip select output
valid time tWHSV WRH, WRL,
CS0 to CS3 ⎯tCP* / 2 − 17 ⎯ns
t
SVRL
t
SVWL
t
WHSV
t
RHSV
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
0.8 V
RD
A23 to A16
CS0 to CS3
D15 to D00
WRH, WRL
D15 to D00
Read data
Write data
Unde-
fined
MB90480/485 Series
110
5. A/D Converter Electrical Characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C)
*1 : At machine clock frequency of 25 MHz.
*2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) .
Parameter Sym-
bol Pin name Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯ ⎯ 10 bit
Total error ⎯⎯ ⎯ ⎯ ±3.0 LSB
Linear error ⎯⎯ ⎯ ⎯ ±2.5 LSB
Differential linearity
error ⎯⎯ ⎯ ⎯ ±1.9 LSB
Zero transition voltage VOT AN0 to
AN7 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV
Full scale transition
voltage VFST AN0 to
AN7 AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB mV
Conversion time ⎯⎯ 3.68 *1⎯⎯µs
Analog port input
current IAIN AN0 to
AN7 ⎯0.1 10 µA
Analog input voltage VAIN AN0 to
AN7 AVSS ⎯AVRH V
Reference voltage ⎯AVRH AVSS + 2.2 ⎯AVCC V
Power supply current IAAVCC ⎯1.4 3.5 mA
IAH AVCC ⎯⎯5 *2µA
Reference voltage
supply current
IRAVRH ⎯94 150 µA
IRH AVRH ⎯⎯5 *2µA
Offset between
channels ⎯AN0 to
AN7 ⎯⎯ 4LSB
MB90480/485 Series
111
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the register value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
Note : Concerning sampling time, and compare time when 3.6 V ≥ AVCC ≥ 2.7 V, then
Sampling time : 1.92 µs, compare time : 1.1 µs
Settings should ensure that actual values do not go below these values due to operating frequency changes.
R
C
During sampling : ON
Analog input Comparator
Note: The values are reference values.
• Analog input equivalent circuit
RC
MB90487B 2.5 kΩ (Max) 31.0 pF (Max)
MB90F481/F482 1.9 kΩ (Max) 25.0 pF (Max)
MB90F488B/F489B 1.9 kΩ (Max) 25.0 pF (Max)
MB90F481/F482
MB90F488B/F489B MB90487B
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 30 35
MB90F481/F482
MB90F488B/F489B MB90487B
20
18
16
14
12
10
8
6
4
2
0
0123456 8
7
(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)
Minimum sampling time [µs] Minimum sampling time [µs]
External impedance [kΩ]
External impedance [kΩ]
• The relationship between external impedance and minimum sampling time
MB90480/485 Series
112
•Flash Memory Program/Erase Characteristics
* : The value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
• Use of the X0/X1, X0A/X1A pins
• Sample use with external clock input
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase time
TA = + 25 °C,
VCC = 3.0 V
⎯115s
Excludes 00H programming
prior erasure
Chip erase time ⎯7⎯sExcludes 00H programming
prior erasure
Word (16-bit)
programming time ⎯16 3600 µs Excludes system-level overhead
Program/Erase cycle ⎯10000 ⎯⎯cycle
Flash Memory Data
hold time
Average
TA = + 85 °C10 ⎯⎯year *
X1
C3 C4
C2 C1
X0 X0A X1A
When used with a crystal oscillator
Pull-up
resistance 1
Damping
resistance 1 Damping
resistance 2
Internal
damping
resistance 0
In normal use :
Internal damping resistance 0 : Typ 600 Ω
Consult with the oscillator manufacturer.
Pull-up resistance 1,
Damping resistance 1, 2,
C1 to C4
X0
X1OPEN
MB90480/485 series
MB90480/485 Series
113
■EXAMPLE CHARACTERISTICS
• MB90F482
(Continued)
VOH − IOH
TA = + 25 °C
VOL − IOL
TA = + 25 °C
CMOS input characteristics
TA = + 25 °C
Hysteresis input characteristics
TA = + 25 °C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−1−2−3−4−5
VOH (V)
IOH (mA)
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
VCC = 3.9 V
1800
1600
1400
1200
1000
600
400
200
0
12345
800
VOL (mV)
IOL (mA)
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
VCC = 3.9 V
2.4
2.0
1.8
1.6
1.4
1.2
1.0
0.6
0.4
2.4 2.7 3.0 3.3 3.6
0.8
2.2
VCC (V)
VIH
VIL
CMOS input (V)
2.4
2.0
1.8
1.6
1.4
1.2
1.0
0.6
0.4
2.4 2.7 3.0 3.3 3.6
0.8
2.2
VCC (V)
VIHS
VILS
Hysteresis input (V)
MB90480/485 Series
114
(Continued)
40
30
20
10
0
50
60
2.4 2.7 3.0 3.3 3.6 3.9
f = 1 MHz
f = 2 MHz
f = 4 MHz
f = 10 MHz
f = 16 MHz
f = 20 MHz
f = 25 MHz
V
CC
(V)
I
CC
− V
CC
I
CC
(mA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.4 2.7 3.0 3.3 3.6 3.9
VCC (V)
ICCH (µA)
ICCH − VCC
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.4 2.7 3.0 3.3 3.6 3.9
VCC (V)
ICCT (µA)
ICCT − VCC
MB90480/485 Series
115
(Continued)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.4 2.7 3.0 3.3 3.6 3.9
V
CC
(V)
I
A
(mA)
I
A
− V
CC
1000
100
10
2.4 2.7 3.0 3.3 3.6 3.9
V
CC
(V)
R (kΩ)
R − V
CC
MB90480/485 Series
116
(Continued)
20
18
16
14
12
10
8
6
4
2
0
2.4 2.7 3.0 3.3 3.6 3.9
f = 1 MHz
f = 2 MHz
f = 4 MHz
f = 10 MHz
f = 16 MHz
f = 20 MHz
f = 25 MHz
V
CC
(V)
I
CCS
− V
CC
I
CCS
(mA)
20
18
16
14
12
10
8
6
4
2
02.4 2.7 3.0 3.3 3.6 3.9
VCC (V)
ICCL (µA)
ICCL − VCC
250
200
150
100
50
0
2.4 2.7 3.0 3.3 3.6 3.9
V
CC
(V)
I
R
(µA)
I
R
− V
CC
MB90480/485 Series
117
■ORDERING INFORMATION
Part number Package Remarks
MB90F481PF
MB90F482PF
MB90487BPF
MB90488BPF
MB90F488BPF
MB90483CPF
MB90F489BPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F481PFV
MB90F482PFV
MB90487BPFV
MB90488BPFV
MB90F488BPFV
MB90483CPFV
MB90F489BPFV
100-pin plastic LQFP
(FPT-100P-M05)
MB90480/485 Series
118
■PACKAGE DIMENSIONS
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.65g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M05)
(FPT-100P-M05)
C
2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX .059
–.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0˚~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB90480/485 Series
119
(Continued)
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(
FPT-100P-M06
)
C
2002 FUJITSU LIMITED F100008S-c-5-5
130
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00
+0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8
˚
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90480/485 Series
F0611
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
The company names and brand names herein are the trademarks or
registered trademarks of their respective owners.
Edited Business Promotion Dept.
