FAN4800IN_G - Fairchild Semiconductor

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

November 2010

FA N48 00 R ev. 1.0.6

FAN4800

Low Startup Current PFC/PWM Controller Combinations

Features

Low Startup Current (100µA Typical)

Low Operating Current (2.5mA Typical)

Low Total Harmonic Distortion, High Power Factor

Pin-Compatible Upgrade for the ML4800

Avera ge Curre nt, Co ntinuo us or Disc ontinu ous Boos t,

Leading-Edge PFC

Slew Rate Enhanced Transconductance Error

Amplifier for Ultra-Fast PFC Response

Internally Sync hron iz ed Lea din g-Ed ge PFC and

Trailing-Edge PWM

Reducti on of Ripple Current in the Storage Capacitor

between the PFC and PWM Sections

PWM Configurable for Current Mode or Voltage Mode

Additiona l Folde d-Back Curren t Limit for PWM Sectio n

20V BiCMOS Process

VIN OK Guaranteed Turn-on PWM at 2.25V

VCC OVP Comparator, Low-Power Detect Comparator

Current-Fed Gain Modulator for Improved Noise

Immunity

Brownout Control, Over-Voltage Protection, UVLO,

Soft-Start, and Reference OK

Avai lable in16-DIP Pack ag e

Applications

Desktop PC Power Supply

Internet Server Power Supply

Uninterruptible Power Supply (UPS)

Battery Charger

DC Motor Power Supply

Monitor Power Supply

Telecom System Power Supply

Distributed Power

Description

The FAN4800 is a controller for power-factor-corrected,

switched-mode power supplies. Power Factor Correction

(PF C) allow s the us e of sm aller, lower-c ost bul k capaci-

tors, reduces power line loading and stress on the

switching FETs, and results in a power supply that fully

compli es with I EC-100 0-3- 2 spec ificat ions. I ntende d as a

BiCMOS version of the industry-standard ML4800, the

FAN4800 includes circuits for the implementation of

leading-edge, average-current, boost-type power factor

correction and a trailing-edge Pulse Width Modulator

(PWM). A gate driver with 1A capabilities minimizes the

need for external driver circuits. Low-power require-

ments improve efficiency and reduce component costs.

An over-voltage comparator shuts down the PFC section

in the event of a sudden decrease in load. The PFC sec-

tion also includes peak current limiting and input voltage

brownout protection. The PWM section can be operated

in current or voltage mode, at up to 250kHz, and

includes an accurate 50% duty cycle limit to prevent

transformer saturation.

The FAN4800 includes a folded-back current limit for the

PWM section to provide short-circuit protection.

Ordering Information

16-PDIP

Part Number Operating

Temperature Range Package Packing

Method Marking

Code

FAN4800IN -40°C to +125°C 16-PDIP Rail FAN4800

FAN4800IN_G -40°C to +125°C 16-PDIP Rail FAN4800

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 2

Block Diagram

Figure 1. Internal Block Diagram

RAMP2

VFB

VREF

RAMP1

20μA

OSCILLATOR

2.25V

DUTY CYCLE

LIMIT

POWER FACTOR CORRECTO R

GAIN

MODULATOR

VFB

7.5V

REFERENCE

IEAO

VEAO

PFC OUT

UVLO

DC ILIMIT

PWM OUT

VCC

PULSE WIDTH MO DUL AT O R

VCC

0.9V

2.78V

-1V

GND

910

0.3V Low Power

Detector

VCC

TRI-FAULT

VCC OVP

350

PWM CMP

SS CMP

PFC OVP

PFC CMP

PWM DUTY

350

CLK

PFC

OUT

PWM

OUT

13116

3.5k

2.5V

IAC

ISENSE

VRMS

VDC

0.5V

17.9V

VIN OK

1.0V

DC ILIMIT

PFC ILIMIT

VCC VREF

FAN4800 Rev.02

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 3

Pin Configuration

Figure 2. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 IEAO PFC transconductance cu rrent erro r amplifier out put

2 IAC PFC gain control reference input

3 ISENSE Current sense input to the PFC current limit comparator

4 VRMS Input for PFC RMS line voltage compensation

5 SS Connection point for the PWM soft-start capacitor

6 VDC PWM voltage feedback input

7 RAMP1 (RtCt) Oscillator timing node; timing set by RT, CT

8 RAMP2 (PWM RAMP) In current mo de, this pin functio ns as the current -sense inp ut. In voltage mode,

it is the PWM input from the PFC output (feed forward ramp).

9 DC ILIMIT PWM current-limit co mparator input

10 GND Ground

11 PWM OUT PWM driver output

12 PFC OUT PFC driver output

13 VCC Positive supply

14 VREF Buffered output for the internal 7.5V reference

15 VFB PFC transconductance voltage error amplifier input

16 VEAO PFC transconductance voltage error amplifier output

ISENSE

VRMS

IEAO VEAO

VCC

GND

IAC 15

10RAMP1

98 RAMP2 DC ILIMIT

PWM OUT

PFC OUT

VREF

VFB

FAN4800 Rev.03

VDC

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble abov e the rec om me nd ed op erati ng cond iti ons and stres si ng the p arts to these levels is no t reco mm en ded. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Positive Supply Voltag e 20 V

IEAO PFC Transconductance Current Error Amplifier Output 0 5.5 V

VISENSE ISENSE Voltage -3.0 0.7 V

Voltage on Any Other Pin GND-0.3 VCC+0.3 V

IREF IREF Current 10 mA

IAC IAC Input Current 1 mA

IPFC_OUT Peak PFC OUT Current, Source or Sink 1 A

IPWM_OUT Peak PWM OUT Current, Source or Sink 1 A

PFC OUT, PWM OUT Energy per Cycle 1.5 µJ

TJJunction Temperature +150 °C

TSTG Storage Temperatur e Ran ge -65 +150 °C

TAOperating Temperature Range -40 +125 °C

TLLead Temperature (Soldering,10 Seconds) +260 °C

θJA Thermal Resistance 80 °C/W

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 5

Electric al Characteristics

Unles s othe rwis e st at ed, thes e spe ci fic ati ons appl y: VCC = 15V, RT = 52.3KΩ, CT = 470pF, and TA = -40°C to 125°C.

Symbol Parameter Condition Min. Typ. Max. Unit

VOLTAGE ERROR AMPLIFIER

VFB Input Voltage Range(1) 0 6 V

gm1 Transconductance 50 70 90 µmho

Vref(PFC) Feedback Reference Voltage TA = 25°C 2.45 2.50 2.55 V

Ib(VEAO) Input Bias Current(2) -1.00 -0.05 mA

VEAO(H) Output High-Voltage 5.8 6.0 V

VEAO(L) Output Low-Voltage 0.1 0.4 V

Isink(V) Sink Current TA = 25°C, VFB = 3V,

VEAO = 6.0V -35 -20 µA

Isource(V) Source Current TA = 25°C, VFB = 1.5V

VEAO = 1.5V 30 40 µA

GV Open-Loop Gain(1)(3) 50 60 dB

PSRR1 Power Supply Rejection Ratio(1) 11V < VCC < 16.5V 50 60 dB

CURRENT ERROR AMPLIFIER

VIEAO Input Voltage Range(1) -1.5 0.7 V

gm2 Transconductance 50 85 100 µmho

Voffset Input Offset Voltage TA = 25°C 25 mV

Ibeao Input Bias Current(1) -1 µA

IEAO(H) Output High-Voltage 4.00 4.25 V

IEAO(L) Output Low-Voltage 1.0 1.2 V

Isink(I) Sink Current ISENSE = +0.5, IEAO = 4.0V -65 -35 µA

Isource(I) Source Current ISENSE = -0.5, IEAO = 1.5V 35 75 µA

Gi Open-Loop Gain(1) 60 70 dB

PSRR2 Power Supply Rejection Ratio(1) 11V < VCC < 16.5V 60 75 dB

PFC OVP COMPARATOR

Vovp Threshold Voltage TA = 25°C 2.70 2.78 2.90 V

HY(ovp) Hysteresis TA = 25°C 230 350 mV

LOW-POWER DETECT COMPARATOR

Vth(lp) Threshold Voltage TA = 25°C 0.15 0.30 0.40 V

VCC OVP COMPARATOR

VCC_OVP Threshold Voltage TA = 25°C 17.5 17.9 18.5 V

HY(VCC_OVP) Hysteresis TA = 25°C 1.40 1.50 1.65 V

TRI-FAULT DETECT

td(F) Time to Fault Detect HIGH(1) VFB = VFault Detect LOW to

VFB = Open. 470pF from VFB

to GND 2 4 ms

F(L) Fault Detect LOW 0.4 0.5 0.6 V

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 6

Electric al Characteristics (Continued)

Unles s othe rwis e st at ed, thes e spe ci fic ati ons appl y: VCC = 15V, RT = 52.3kΩ, CT = 470pF, and TA = -40°C to 125°C.

Symbol Paramete r Condition Min. Typ. Max. Unit

PFC ILIMIT COMPARATOR

Vth(cs) Threshold Voltage -1.10 -1.00 -0.90 V

Vth(cs)-Vgm (PFC ILIMIT VTH – Gain Modulator

Output) 5 100 mV

td(pfc_off) Delay to Output(1) 250 ns

DC I LIMIT COMPARATOR

Vth(DC) Threshold Voltage 0.95 1.00 1.05 V

td(pwm_off) Delay to Output(1) 250 ns

VIN OK COMPARATOR

Vth(OK) Threshold Voltage 2.10 2.45 V

HY(OK) Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain(3)

IAC = 100μA, VRMS = 0,

VFB = 1V, TA = 25°C 0.70 0.84 0.95

Gain(3)

G2 IAC = 100μA, VRMS = 1.1V,

VFB = 1V, TA = 25°C 1.80 2.00 2.20

G3 IAC = 150μA, VRMS = 1.8V,

VFB = 1V, TA = 25°C 0.90 1.00 1.10

G4 IAC = 300μA, VRMS = 3.3V,

VFB = 1V, TA = 25°C 0.25 0.32 0.40

BW Band Width(1) I

AC = 100μA10 MHz

Vo(gm) Output Voltage

= 3.5kΩ x (ISENSE – IOFFSET) IAC = 250μA, VRMS = 1.1V,

VFB = 2V, TA = 25°C 0.80 1.00 1.20 V

OSCILLATOR

fosc1 Initial Accuracy TA = 25°C 68 81 kHz

Δfosc1 Voltage Stability 11V < VCC < 16.5V 1 %

Δfosc2 Temperature Stability 2 %

fosc2 Total Variation Line, Temp 66 84 kHz

Vramp Ramp Valley to Peak Voltage(1) 2.75 V

tdead PFC Dead Time 685 ns

Idis CT Discharge Current VRAMP2 = 0V, VRAMP1 = 2.5V 6.5 15.0 mA

REFERENCE

Vref1 Output Voltage TA = 25°C, I(VREF) = 1mA 7.4 7.5 7.6 V

ΔVref1 Line Regulation 11V < VCC < 16.5V 10 25 mV

ΔVref2 Load Regulation 0mA < I(VREF) < 7mA 10 20 mV

ΔVref4 Temperature Stability 0.4 %

Vref2 Total Variation(1) Line, Load, Temperature 7.35 7.65 V

ΔVref5 Long Term Stability(1) T

J = 125°C, 1000 hours 5 25 mV

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 7

Electric al Characteristics (Continued)

Unles s othe rwis e st at ed, thes e spe ci fic ati ons appl y: VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = -40°C to 125°C.

Notes:

1. This parameter, although guaranteed by design, is not 100% production tested.

2. Includes all bias currents to other circuits connected to the VFB pin.

3. Gain = K × 5.375V; K = (ISENSE – IOFFSET) × [IAC × (VEAO – 0.625)] -1; VEAO (MAX.) = 6V.

Symbol Parameter Condition Min. Typ. Max. Unit

PFC

Dmin. Minimum Duty Cycle VIEAO > 4.0V 0 %

Dmax. Maximum Duty Cycle VIEAO < 1.2V 92 95 %

RON(low)1 Output Low Rdson IOUT = -20mA at TA = 25°C 15 Ω

RON(low)2 IOUT = -100mA at TA = 25°C 15 Ω

Vol1 Output Low Voltage(1) IOUT = -10mA, VCC = 9V,

TA = 25°C 0.4 0.8 V

RON(high)1 Output High Rdson IOUT = 20mA at TA = 25°C 15 20 Ω

RON(high)2 IOUT = 100mA at TA = 25°C 15 20 Ω

tr(pfc) Rise/Fall Time(1) C

L = 1000pF 50 ns

PWM

D Duty Cycle Range 0-42 0-47 0-49 %

RON(low)3 Output Low Rdson IOUT = -20mA at TA = 25°C 15 Ω

RON(low)4 IOUT = -100mA at TA = 25°C 15 Ω

Vol2 Output Low Voltage IOUT = -10mA, VCC = 9V,

TA = 25°C 0.4 0.8 V

RON(high)3 Output High Rdson IOUT = 20mA at TA = 25°C 15 20 Ω

RON(high)4 IOUT = 100mA at TA = 25°C 15 20 Ω

tr(pwm) Rise/Fall Time CL = 1000pF(1) 50 ns

PWM(ls) PWM Comparator Level Shift 0.6 0.9 1.2 V

SUPPLY

Ist Startup Current VCC = 12V , CL = 0pF 100 200 µA

Iop Operating Current 14V, CL = 0pF 2.5 7.0 mA

Vth(start) Under-Voltage Lockout Threshold 12.74 13.00 13.26 V

Vth(hys) Under-Voltage Lockout Hysteresis 2.80 3.00 3.20 V

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN4800 Rev. 1.0.6 8

Typical Performanc e Character istics

Figure 3. Voltage Error Amplifier (gmv)

Transconductance Figure 4. Current Error Amplifier (gmi)

Transconductance

Figure 5. Gain Modulator Transfer Characteristic (K) Figure 6. Gain vs. VRMS

126

119

112

105

2.0 2.1 2.2 2.3 2.4 2.5

VFB (V)

Transconductance ( mho)

2.6 2.7 2.8 2.9 3.0

100

-10 0.0 0.2 0.4 0.6 0.8-0.2-0.4-0.6-0.8 ISENSE (V)

Transconductance ( mho)

0.35

0.40

0.30

0.25

0.20

0.15

0.10

0.05

0.00

0.0 0.5 1.0 1.5 2.0 2.5

VRMS (V)

Variable Gain Block Constant (K)

3.0 3.5 4.0 4.5 5.0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.01.51.00.50.0 VRMS (V)

Gain

GAINMOD OFFSET

KmV

(6 0.625) −

−

=×− (1) (2)

SENSE OFFSET

Gain I

−

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN4800 Rev. 1.0.6 9

Functional Description

The FAN4800 consists of an average-current controlled,

continuous boost Power Factor Correction (PFC) front-

end and a synchronized Pulse Width Modulator (PWM)

back-end. The PWM can be used in either current or

voltage mode. In voltage mode, feed forward from the

PFC output bus can be used to improve the PWM’s line

regulation. In either mode, the PWM stage uses conven-

tional trailing-edge, duty-cycle modulation. This propri-

etary leading/trailing edge modulation results in a higher

usable PFC error amplifier bandwidth and can signifi-

cantly reduce the size of the PFC DC bus capacitor.

The synchronization of the PWM with the PFC simplifies

the PWM compensation due to the controlled ripple on

the PFC output capacitor (the PWM input capacitor). The

PWM section of the FAN4800 runs at the same fre-

quency as the PFC.

In addition to power factor correction, a number of pro-

tection features are built into the FAN4800. These

include soft-sta rt, PFC over-voltage protection, peak cur-

rent lim iti ng, bro w nou t pro tec tio n, duty -c yc le lim it ing , an d

under-vo lt a ge loc ko ut (UVLO ).

Power Factor Correction

Power Factor Correction treats a nonlinear load like a

resistive load to the AC line. For a resistor, the current

drawn from the line is in phase with and proportional to

the line voltage, so the power factor is unity (one). A

common class of nonlinear load is the input of most

powe r suppli es, whic h use a bridge r ectifie r and capaci-

tive input filter fed from the line.

The peak charging effect, which occurs on the input filter

capacitor in these supplies, causes brief high-amplitude

pulses of current to flow from the power line, rather than

a sinusoidal current in phase with the line voltage. Such

supplies present a power factor to the line of less than

one (i.e., they cause significant current harmonics of the

power line frequency to appear at the input). If the input

current drawn by such a supply (or any nonlinear load)

can be made to follow the input voltage in instantaneous

ampl itude, it appears resistive to the supply.

To hold the input current draw of a device drawing power

from the AC line in phase with and proportional to the

input voltage, that device must be prevented from load-

ing the line except in proportion to the instantaneous line

voltage. To accomplish this, the PFC section of the

FAN4800 uses a boost mode DC-DC converter. The

input to the converter is the full-wave, rectified, AC line

voltage. No bulk filtering is applied following the bridge

rectifier, so the input voltage to the boost converter

ranges (at twice line the frequency) from zero volts to a

peak value of the AC input and back to zero. By forcing

the boos t conv erter to meet two sim ult aneous cond itions,

it is possible to ensure that the current drawn from the

power line is propor tional to the input line voltage.

One of these conditions is that the output voltage of the

boost converter must be set higher than the peak value

of the lin e v oltage. A commonly us ed va lue is 385VDC, to

allow for a hig h line of 270 VAC rms . The s econd condi tion

is that the current drawn from the line at any given

instant must be proportional to the line voltage. Estab-

lishing a suitable voltage control loop for the converter,

whic h in turn drives a cur rent err or amplif ier an d switch-

ing output driv er, satisfies the first of the se require me nt s .

The second requirement is met by using the rectified AC

line voltage to modulate the output of the voltage control

loop. Such modulation causes the current error amplifier

to command a power stage current that varies directly

with the inp ut v oltage. To prevent ripple, which ne ces s ar-

ily appears at the output of boost circuit (typically about

10VAC on a 385VDC level), from introducing distortion

back thro ugh the v olt age error a mplif ier, the ba ndwid th of

the voltage loop is deliberately kept low. A final refine-

ment is to adj ust the overal l g ain of the PFC se ction to b e

proportional to 1/VIN2, which linearizes the transfer func-

tion of the system as the AC input voltage.

Since th e b oo st co nverter in the FAN4800 PFC is current

averagi ng, no slope comp ens ati on is require d.

1. PFC Section

1.1 Gain Modulator

Figure 1 shows a block diagram of the PFC section of

the FAN4800. The gain modulator is the heart of the

PFC, as the circuit block controls the response of the

current loop to line voltage waveform and frequency,

RMS line voltage, and PFC output voltages. There are

three inputs to the gain modulator:

1. A current representing the inst a nt aneous i npu t vol t ag e

(amplitude and wave shape) to the PFC. The rectified

AC input sine wave is converted to a proportional cur-

rent via a res is tor and is then fed into th e gai n modula-

tor at IAC. Sampling current in this way minimizes

ground nois e, re qui red in hig h-power, switc hin g-po wer

conversion environments. The gain modulator

responds linearly to this current.

2. A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after

scaling and filtering. This signal is presented to the

gain modulator at VRMS. The output of the gain modu-

lator is inversely proportional to VRMS2 (except at

unusuall y low valu es of VRMS, where specia l gain co n-

touring takes over to limit power dissipation of the cir-

cuit components under heavy brownout conditions).

The relationship between VRMS and gain is called K

and is illustrated in Figure 5.

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN480 0 Rev. 1.0.6 10

3. The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variation in VEAO.

The output of the gain modulator is a current signal, in

the form of a full wave rectified sinusoid at twice the line

frequency. This current is applied to the virtual ground

(negative) input of the current error amplifier. In this way,

the gain modulator forms the reference for the current

error loop and ultimately controls the instantaneous cur-

rent draw of the PFC from the power line. The general

form of the output of the gain modulator is:

More precisely, the output current of the gain modulator

is gi ven by:

where K is in units of V-1.

The output current of the gain modulator is limited

aroun d 228.5 7µA a nd the m aximum outpu t vo lta ge of th e

gain modulator is limited to 228.57µA x 3.5K = 0.8V.

This 0.8V also determines the maximum input power.

However, IGAINMOD cannot be measured directly from

ISENSE. ISENSE = IGAINMOD – IOFFSET and IOFFSET can

only be measured when VEAO is less than 0.5V and

IGAINMOD is 0A. Typical IOFFSET is around 60µA.

1.2 Selecting RAC for IAC pin

IAC pin is the input of the gain modulator. IAC is also a

current mirror input and requires current input. Selecting

a proper resistor RAC provides a good sine wave current

derived from the line voltage and helps program the

maximum input power and minimum input line voltage.

RAC = VIN peak x 7.9K. For example, if the minimum line

voltage is 80VAC, the RAC = 80 x 1.414 x 7.9K = 894kΩ.

1.3 Current Error Amplifier, IEAO

The curre nt error ampli fier’s outp ut controls the PF C dut y

cycle to keep the average current through the boost

inducto r a line ar function of the lin e volt age. At the invert-

ing input to the current error amplifier, the output current

of the gain modulator is summed with a current, which

results from a negative voltage being impressed upon

the ISENSE pin.

The negative voltage on ISENSE repr ese nts the sum o f al l

current s flow ing in the PFC ci rcuit an d is typi call y derive d

from a current sense resistor in series with the negative

terminal of the input bridge rectifier.

The inverting input of the current error amplifier is a vir-

tual ground. Given this fact, and the arrangement of the

duty cycle modulator polarities internal to the PFC, an

increase in positive current from the gain modulator

causes the output stage to increase its duty cycle until

the voltage on ISENSE is adequately negative to cancel

this increased current. Similarly, if the gain modulator’s

output decreases, the output duty cycle decreases to

achieve a less negative voltage on the ISENSE pin.

1.4 Cycle-By-Cycle Current Limiter and Selecting RS

As well as being a part of the current feedback loop, the

ISENSE pin is a direct input to the cycle-by-cycle current

limiter for the PFC section. If the input voltage at this pin

is ever less than -1V, the output of the PFC is disabled

until the protection flip-flop is reset by the clock pulse at

the start of the next PFC power cycle.

RS is the sensing resistor of the PFC boost converter.

During the steady state, line input current x RS equals

IGAINMOD x 3.5K.

Since the maximum output voltage of the gain modulator

is IGAINMOD maximum x 3.5k = 0.8V during the steady

state, RS x line input current is limited to below 0.8V as

well. Therefore, to choose R

, use the following equation:

For exampl e, i f the m inimu m input voltag e is 80VAC and

the maximum input RMS power is 200Watt,

RS = (0.8V x 80V x 1.414) / (2 x 200) = 0.226Ω.

1.5 PFC OVP

In the F AN4800, the PFC OVP comparator serves to pro-

tect the power circuit from being subjected to excessive

voltages if the load changes suddenly. A resistor divider

from the high -volt age DC output of th e PFC is fed to VFB.

When the vo lt age on VFB exceeds 2.78V, the P FC o utp ut

drive r is sh ut dow n . The PWM se ction continues to oper-

ate. The OVP comparator has 280mV of hysteresis and

the PFC does not restart until the voltage at VFB drops

below 2.50V. VCC OVP can also serve as a redundant

PFC OVP protection. VCC OVP threshold is 17.9V with

1.5V hysteresis.

AC EAO

GAINMOD

RMS

=× (3)

( 0.625)GAINMOD EAO AC

IKV I=× − × (4)

(5)

0.8

2INPEAK

RLineInput Power

=×

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN480 0 Rev. 1.0.6 11

Figure 7. PFC Section Block Diagram

1.6 Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a neg-

ative resistor because an increase in the input voltage to

the PWM causes a decrease in the input current. This

response dictates the proper compensation of the two

transconductan ce error am plifi ers.

Figure 8 shows the types of compensation networks

most commonly used for the voltage and current error

amplifiers, along with their respective return points. The

current-loop compensation is returned to VREF to pro-

duc e a soft-star t cha racter istic on the PF C: As th e refe r-

ence voltage increases from 0V, it creates a

differentiated voltage on IEAO, which prevents the PFC

from immediately demanding a full duty cycle on its

boost converter.

1.7 PFC Voltage Loop

There are two major concerns when compensating the

voltage loop error amplifier (VEAO); stability and transient

response. Optimizing interaction between transient

response and stability requires that the error amplifier’s

open-loop crossover frequency half that of the line fre-

quency, or 23Hz for a 47Hz line (lowest anticipated inter-

national power frequency). The gain vs. input voltage of

the FAN4800’s voltage error amplifier (VEAO) has a spe-

cially shaped non-linearity, so that under steady-state

operating conditions, the transconductance of the error

amplifi er is at a local mini mu m. Rap id pe rturb atio n in lin e

or load conditions causes the input to the voltage error

amplifi er (VFB) to deviate from its 2.5V (nominal) value. If

this happens, the transconductance of the voltage error

amplifier increases significantly, as shown in the Figure

4. This raises the gain-bandwidth product of the voltage

loop, resulting in a much more rapid voltage loop

response to such perturbations than would occur with

conventional linear gain characteristics.

The voltage loop gain(s) is given by:

where:

ZC: Compensation network for the voltage loop.

GMV: Transconductance of VEAO.

PIN: Average PFC input power.

V2OUTDC: PFC boost output voltage (typical designed

value is 380V).

CDC: PFC boost output capacitor.

1.8 PFC Current Loop

The compensation of the current amplifier (IEAO) is simi-

lar to that of the voltage error amplifier (VEAO) with the

exception of the choice of crossover frequency. The

crossover frequency of the current amplifier should be at

least ten times that of the voltage amplifier to prevent

interaction with the voltage loop. It should also be limited

to less than one sixth of the switching frequency, e.g.,

16.7kHz for a 100kHz switching frequency.

The current loop gain(s) is given by:

RAMP1 OSCILLATOR

POWER FACTOR CORRECTOR

GAIN

MODULATOR

VFB

7.5V

REFERENCE

IEAO

VEAO

PFC OUT

2.78V

-1V

0.3V Low Power

Detector

VCC

TRI-FAULT

VCC OVP PFC OVP

PFC CMP

CLK

13116

3.5k

2.5V

IAC

ISENSE

VRMS

0.5V

17.9V

PFC ILIMIT

VCC VREF

FAN4800 Rev.02

(6)

OUT EAO

EAO OUT FB

OUTDC EAO DC

VVV

VV V

PV GM Z

VVSC

22.5

ΔΔΔ

=××

ΔΔ Δ

≈××

×Δ × ×

(7)

ISENSE OFF EAO

OFF EAO ISENSE

OUTDC S

ICI

VDI

DIV

GM Z

SL V2.5

ΔΔ

=××

ΔΔΔ

≈××

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN480 0 Rev. 1.0.6 12

where:

ZCI: Compensation network for the current loop.

GMI: Transconductance of IEAO.

VOUTDC: PFC boost output voltage (typical designed

value is 380V). The equation uses the worst-

case condi tion to calculate the ZCI.

RS: Sensing resistor of the boost converter.

2.5V: Amplitude of the PFC leading modulation

ramp.

L: Boost inductor.

A modest degree of gain contouring is applied to the

transfer characteristic of the current error amplifier to

increase its response speed to current-loop perturba-

tions. However, the boost inductor is usually the domi-

nant factor in overall current loop response. Therefore,

this contouring is significantly less marked than that of

the voltage error amplifier. This is illustrated in Figure 8.

Figure 8. Compens ation Netw ork Connectio n for the

Voltage and Current Error Amplifiers

There is an RC filter between RS and ISENSE pin .

There are two reasons to add a filter at the ISENSE pin:

1) Protection: During startup or in-rush current condi-

tions, there is a large voltage across RS, which is the

sensing resistor of the PFC boost converter. It

requires the ISENSE filter to attenua te the ene rgy.

2) To reduce L, th e boost inductor: T he I SENSE filter also

can reduce the boost inductor value since the ISENSE

filter behaves like an i nte grato r b efor e th e ISENSE pin,

which is the input of the current error amplifier, IEAO.

The ISENSE filte r is an R C f ilt er. Th e res ist or value of the

ISENSE filter is between 100Ω and 50Ω because IOFFSET

x RS can generate an offset voltage of IEAO.

Selectin g an R FILTER equal to 5 0Ω kee ps the o f fset of the

IEAO less than 5mV. Design the pole of ISENSE filter at

fpfc/6, one sixth of the PFC switching frequency, so the

boost inductor can be reduced six times without disturb-

ing the stability. The capacitor of the ISENSE filter, CFIL-

TER, is approximately 283nF.

Figure 9. Exte rnal Component Connection to VCC

1.9 Oscillator (RAMP1)

The oscillator frequency is determined by the values of

RT and CT, which determine the ramp and off-time of the

oscillator output clock:

The dead time of the oscillator is derived from the follow-

ing equation:

at VREF = 7.5V and tRAMP = CT x RT x 0.55 .

The dea d time of th e o sc il lato r m ay be d eterm in ed using:

The dead time is so small (tRAMP>>tDEAD) that the oper-

ating frequency can typically be approximated by:

VRMS

2Gain

Modulator

VFB

ISENSE

IAC

IEAO

VEAO

3.5k

2.5V

PFC CMP

PFC

Output

Vref

FAN4800 Rev.02

FAN4800

VCC

GND

VBIAS

RBIAS

0.22μF

Ceramic 15V

Zener

FAN4 800 Rev.03

(8)

OSC

RAMP DEAD

ftt

(9)

REF

RAMP T T

REF

V -1.00

tCRln

V-3.75

⎛⎞

=××

⎜⎟

⎝⎠

(10)

2.75

DEAD T T

tC227C

12.11mA

=×=×

(11)

OSC

RAMP

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN480 0 Rev. 1.0.6 13

1.10 Example

For the application circuit shown in Figures 12 and 13,

with the oscill ator runn ing at :

solving for CT x RT yields 1.96 x 10-4. CT is 390pF and

RT is 51.1kΩ, selecting standard components values.

The dead time of the oscillator adds to the maximum

PWM duty cycle (it is an input to the duty cycle limiter).

With zero oscillator dead time, the maximum PWM duty

cycle is typically 47%. Take care not to make CT too

large, which could extend the maximum duty cycle

beyond 50%. This can be accomplished by using no

greater than a 390pF capacitor for CT.

2. PWM Section

2.1 Pulse Width Modulator (PWM)

The operation of the PWM section of the FAN4800 is

straightforward, but there are several points that should

be noted. Foremost among these is the inherent syn-

chronization of PWM with the PFC section of the device,

from which it also derives its basic timing. The PWM is

capable of current-mode or voltage-mode operation. In

current-mode applications, the PWM ramp (RAMP2) is

usually derived directly from a current sensing resistor or

current transformer in the primary of the output stage. it

is thereby representative of the current flowing in the

convert er’s output st age . DC ILIMIT, which prov ides cycl e-

by-cycle current limiting, is typically connected to

RAMP2 in such applications. For voltage-mode opera-

tion and certain specialized applications, RAMP2 can be

connected to a separate RC timing network to generate

a voltage ramp against which VDC is compared. Under

these conditions, the use of voltage feed-forward from

the PFC bus can assist in line regulation accuracy and

response. As in current-mode operation, the DC ILIMIT

input is used for output stage over-current protection.

No voltage error amplifier is included in the PWM stage

of the FAN4800, as this function is generally performed

on the output side of the PWM’s isolation boundary. To

facilitate the desi gn of op to-c oup ler feedback circui try, an

offset has been built into the PWM’s RAMP2 input that

allows VDC to command a 0% duty cycle for input volt-

ages below typical 0.9V.

2.2 PWM Curren t Limit

The DC ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output flip-flop is

reset by the clock pulse at the start of the next PWM

power cycle. When the DC ILIMIT triggers the cycle-by-

cycle current, it also softly discharges the voltage of the

soft-start capacitor. It limits the PWM duty cycle mode

and the power dissipation is reduced during the dead-

short condition.

2.3 VIN OK Comparator

The VIN OK comparator monitors the DC output of the

PFC and inhibits the PWM if the voltage on VFB is less

than its nominal 2.25V. Once the voltage reaches 2.25V,

which corresponds to the PFC output capacitor being

charged to its rated boost voltage, the soft-start begins.

2.4 PWM Control (RAMP2)

When t he PW M s ect ion is use d in current mode, RAMP2

is generally used as the sampling point for a voltage,

represen tin g th e c urre nt i n th e p rim ary of the PWM ’ s ou t-

put transform er. The voltage is derived either from a cur-

rent sensing resistor or a current transformer. In voltage

mode, RAMP2 is the input for a ramp voltage generated

by a sec ond se t of tim ing com pone nts (RRAMP2, CRAMP2)

that have a minimum value of 0V and a peak value of

approximately 5V. In voltage mode, feed forward from

the PFC output bus is an excellent way to derive the tim-

ing ramp for the PWM stage.

2.5 Soft-Start (SS)

PWM startup is controlled by selection of the external

capacitor at soft-start. A current source of 20mA supplies

the charging current for the capacitor and startup of the

PWM begins at 0.9V. Startup delay can be programmed

by the following equation:

where CSS is the required soft-start capacitance and the

tDELAY is the desire d st art up del ay.

It is important that the time constant of the PWM soft-

start allows the PFC time to generate sufficient output

power for the PWM section. The PWM startup delay

should be at leas t 5ms.

Solving for the minimum value of CSS:

Use caution when using this minimum soft-start capaci-

tance value because it can cause premature charging of

the SS capacitor and activation of the PWM section if

VFB is in the hysteresis band of the VIN OK comparator

at startup. The magnitude of VFB at startup is related

both to line voltage and nominal PFC output voltage.

Typically, a 1.0µF soft-start capacitor allows time for VFB

and PFCOUT to reach their nominal values prior to acti-

vation of the PWM section at line voltages between

90Vrms and 265Vrms.

(12)

OSC

RAMP

f100kHz

(13)

SS DELAY

20μ

Ct 0.9V

=×

(14)

20μA

C 5ms 111nF

0.9V

=× =

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FAN480 0 Rev. 1.0.6 14

2.6 Generating V CC

After turning on the FAN4800 at 13V, the operating volt-

age can v ary from 10V to 17 .9V. The threshold vol tag e of

the VCC OVP comparator is 17.9V and its hysteresis is

1.5V. When VCC reaches 17.9V, PFC OUT is LOW, and

the PWM section is not disturbed. There are two ways to

generate VCC: use auxiliary power supply around 15V or

use bootstrap winding to self-bias the FAN4800 system.

The bootstrap winding can be either taped from the PFC

boost choke or from the transformer of the DC-to-DC

stage.

The ratio of the bootstrap’s winding transformer should

be set between 18V and 15V. A filter network is recom-

mended between VCC (pin 13) and bootstrap winding.

The resistor of the filter can be set as:

If VCC goes beyond 17.9V, the PFC gate (pin 12) drive

goes LOW and the PWM gate drive (pin 11) remains

working. The resistor’s value must be chosen to meet

the operating current requirement of the FAN4800 itself

(5mA, maximum) in addition to the current required by

the two gate driver ou tputs.

2.7 Example

To obtain a desired VBIAS voltage of 18V, a VCC of 15V,

and the FAN4800 driving a total gate charge of 90nC at

100kHz (e.g. one IRF840 MOSFET and two IRF820

MOSFET), the gate driver current required is:

Bypa ss the FAN4800 l ocall y wit h a 1.0μF ceramic capac-

itor. In most applications, an electrolytic capacitor of

between 47μF and 220μF is also required across the

part both for filtering and as a part of the startup boot-

strap circuitry.

2.8 Leading/Trailing Modulation

Conventional PWM techniques employ trailing-edge

modulation, in which the switch turns on right after the

trailing edge of the system clock. The error amplifier out-

put is then compared with the modulating ramp up. The

effective duty cycle of the trailing edge modulation is

determined during the on-time of the switch. Figure 10

shows a typic al trail ing-edge control scheme .

In the case of leading-edge modulation, the switch is

turned off exactly at the leading edge of the system

clock. When the modulating ramp reaches the level of

the error amplif ier out put volta ge, the sw i tch is tu rned on.

The effective duty-cycle of the leading-edge modulation

is determined during off-time of the switch. Figure 11

shows a leading-edge control scheme.

One of t he adva ntages of this co ntrol t echni que is t hat it

requires only one system clock. Switch 1 (SW1) turns off

and Switch 2 (SW2) turns on at the same instant to mini-

mize the momentary no-load period, thus lowering ripple

voltage generated by the switching action. With such

synchronized switching, the ripple voltage of the first

stag e is re duced . Calcu lation and ev aluati on hav e sho wn

that the 120Hz component of the PFC’s output ripple

voltage can be reduced by as much as 30% using the

leading-edge modulation method.

(15)

()

FILTER VCC

VCC OP PFCFET PWMFET SW OP

RI2V

II+Q +Q fI

2.5A (typ.)

,×≈

=×

GATEDRIVE

I 100kHz 90nC 9mA=×= (16)

(17)

BIAS CC

BIAS

CC G

RII

18V 15V

5mA 9mA

−

BIAS

Choose R 214Ω=(18)

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 15

Figure 10. Typical Trailing-Edge Control Scheme

Figure 11. Typical Leading-Edge Control Scheme

EA CMP

REF VEAO

VIN

SW1

CLK

DFF

OSC

RAMP

CLK

SW2 I2 I3

RAMP

TIME

VEAO

FAN4 800 Re v.02

EA CMP

REF

VEAO

VIN

SW1

CLK

DFF

OSC

RAMP

CLK

SW2 I2 I3

RAMP

TIME

VEAO

FAN4 800 Re v.02

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 16

Ty pical Application Circuit

Figure 12. Current-Mode Applicati on

IEAO

RAMP2

RAMP1

RMS

SENSE

VEAO

DC I

LIMIT

GND

PWM OUT

PFC OUT

REF

FAN4800

3.15A

0.68uF

BR1

4A, 600V

KBL06 R1A

500k

R1B

500k

R2A

453k

R2B

453k

110k

15.4k

R5A

1.2

R5B

1.2

R5C

1.2

R5D

1.2

0.47uF

0.1uF

41.7k

R7A

178k

R7B

178k

2.37k

1.1k

R10

6.2k

R11

845k

R12

71.5k

R13

10k

R14

R15

R17

R16

10k

R18

220

R19

220

R20A

2.2 R20B

2.2

R21

R23

1.5k

R24

1.2k

R26

10k

TL431A

MOC8112

R22

8.66k

R25

2.26k

R27

75k

R28

240

R30

4.7k

R31

100

10nF

100uF

450V

1.5nF

NOT USED

68nF

10nF

C10

15uF

C11

10nF

C12

10uF

35V

C13

0.1uF

C14

1uF

C15

10nF

C16

1uF

C17

220pF

C18

470pF

C19

1uF

C20

1uF

C21

2200uF

25V

C22

4.7uF

C23

100nF

C24

1uF

C25

0.1uF

C26

100nF

C30

330uF

25V

C31

1nF

ISL9R460P2

1N5406 D3

RGF1J

MMBZ5245B

RGF1J

MMBZ5245B

MBRS

140 D10

MBRS

140

MBRS

140

D11A

MBR2545CT

D11B

MBR2545CT

D12

1N5401

D13

1N5401

REF

RAMP1

SENSE

Q1G Q2G

Q3G

RAMP2 / DC I

LIMIT

PRI GND

12V RET

12V

RETURN

12V

12V,

100W

T1A

T1B

VDC / +380V

FQPF9N50 Q2

FQPF

6N50

FQPF6N50

NOTE : L1; PREMIER MAGNETICS TDS-1047

L2; PREMIER MAGNETICS VTP-05007

T1; PREMIER MAGNETICS PMGO-03

T2; PREMIER MAGNETICS TSO-735

AC INPUT

85 TO 265Vac

MMBT3904

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 17

Ty pical Application Circuit (Continued)

Figure 13. Voltage-Mode Application

IEAO

RAMP2

RAMP1

VDC

VRMS

ISENSE

IAC

VEAO

DC ILIMIT

GND

PWM OUT

PFC OUT

VCC

VREF

VFB

FAN4800

3.15A

0.68uF

BR1

4A, 600V

KBL06 R1A

500k

R1B

500k

R2A

453k

R2B

453k

110k

15.4k

R5A

1.2

R5B

1.2

R5C

1.2

R5D

1.2

0.47uF

0.1uF

41.7k

R7A

178k

R7B

178k

2.37k

1.1k

R10

6.2k

R11

845k

R12

71.5k

R13

10k

R14

R15

R17

R16

10k

R18

220

R19

220

R20A

2.2 R20B

2.2

R21

R23

1.5k

R24

1.2k

R26

10k

TL431A

MOC8112

R22

8.66k

R25

2.26k

R27

75k

R28

240

R30

4.7k

R31

100

10nF

100uF

450V

1.5nF

NOT USED

68nF

10nF

C10

15uF

C11

10nF

C12

10uF

35V

C13

0.1uF

C14

1uF

C15

10nF

C16

1uF

C17

220pF

C18

470pF

C19

1uF

C20

1uF

C21

2200uF

25V

C22

4.7uF

C23

100nF

C24

1uF

C25

0.1uF

C26

100nF

C30

330uF

25V

C31

1nF

ISL9R460P2

1N5406 D3

RGF1J

MMBZ5245B

RGF1J

MMBZ5245B

MBRS

140 D10

MBRS

140

MBRS

140

D11A

MBR2545CT

D11B

MBR2545CT

D12

1N5401

D13

1N5401

VFB

VCC

VREF

RAMP1

ISENSE

Q1G Q2G

Q3G

RAMP2 / DC ILIMIT

PRI GND

VDC

12V RET

12V

RETURN

12V

12V,

100W

T1A

T1B

VDC / +380V

FQPF9N50 Q2

FQPF

6N50

FQPF6N50

NOTE : L1; PREMIER MAGNETICS TDS-1047

L2; PREMIER MAGNETICS VTP-05007

T1; PREMIER MAGNETICS PMGO-03

T2; PREMIER MAGNETICS TSO-735

R29

61.9k

C27

470pF

AC INPUT

85 TO 265Vac

MMBT3904

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 18

Physical Dimensions

Figure 14. 16 -Lea d Plastic Dual In-Line Package (D IP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-

ically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

16 9

NOTES: UNLESS OTHERWISE SPECIFIED

A THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BB

B) ALL DIMENSIONS ARE IN MILLIMETERS.

D) CONFOR MS TO ASM E Y14.5M-1994

E) DRAWI NG F ILE NAM E: N16EREV 1

19.68

18.66

6.60

6.09

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR PROTRUSI ONS

3.42

3.17

3.81

2.92

(0.40)

2.54

17.78

0.58

0.35

1.78

1.14

5.33 MAX

0.3 8 M IN 8.13

7.62

0.35

0.20

8.69

TOP VIEW

SIDE VIEW

FAN4800 — Low Startup Current PFC/PWM Controller Combinations

FA N48 00 R ev. 1.0.6 19