NCP12510BSN65T1G - ON SEMICONDUCTOR

November, 2017 − Rev. 3 1Publication Order Number:

NCP12510/D

NCP12510

Current-Mode PWM

Controller for Off-line

Power Supplies

The NCP12510 is a highly integrated PWM controller capable of

delivering a rugged and high performance offline power supply in a

tiny TSOP−6 package. With a voltage supply range up to 35 V, the

controller hosts a jittered 65−kHz or 100−kHz switching circuitry

operated in peak current mode control. When the power on the

secondary side starts decreasing, the controller automatically folds

back its switching frequency down to a minimum level of 26 kHz. As

the power further goes down, the part enters skip cycle while limiting

the peak current.

Over Power Protection (OPP) is a difficult exercise especially when

no−load standby requirements drive the converter specifications. The

ON Semiconductor proprietary integrated OPP allows harness the

maximum delivered power without af fecting the standby performance

simply via two external resistors. An Over Voltage Protection (OVP)

input is also combined on the same pin and protects the whole circuitry

in case of optocoupler destruction or adverse open loop operation.

Finally, a timer−based short−circuit protection offers the best

protection scheme, allowing precisely select the protection trip point

without caring of a loose coupling between the auxiliary and the power

windings.

NCP12510 is improved and pin compatible controller based on very

popular flyback controller NCP1250.

Features

•Fixed−Frequency 65 kHz or 100 kHz Current−Mode Control

Operation

•Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load

Conditions

•Frequency Jittering in Normal and Frequency Foldback Modes

•Internal and Adjustable Over Power Protection (OPP) Circuit

•Auto−Recovery Over Voltage Protection (OVP) on the VCC Pin

•Internal and Adjustable Slope Compensation

•Internal Fixed 4 ms Soft−Start

•Auto−Recovery or Latched Short−Circuit Protection

•Pre−Short Ready for Latched OCP Version

•OVP/OTP Latch Input for Improved Robustness

•+300 mA/ −500 mA Source/Sink Drive Capability

•Improved Consumption

•Improved Reset Time in Latch State

•High Robustness and High ESD Capabilities

•EPS 2.0 Compliant

•This is a Pb−Free Device

Typical Applications

•Ac−dc Converters for TVs, Set−top Boxes and DVD

Players

•Offline Adapters for Notebooks and Netbooks

PIN CONNECTIONS

3CS

GND

OPP/Latch 4

DRV

(Top View)

5VCC

TSOP−6

(SOT23−6)

SN SUFFIX

CASE 318G

STYLE 13

MARKING

DIAGRAM

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(Note: Microdot may be in either location)

5DxAYWG

5Dx = Specific Device Code

x = A, 2, C, J, or K

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

See detailed ordering, marking and shipping information on

page 2 of this data sheet.

ORDERING INFORMATION

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Figure 1. Typical Application Example

Table 1. PIN DESCRIPTION

Pin No Pin Name Function Pin Description

1 GND − The controller ground.

2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.

3 OPP/Latch Adjust the Over Power

Protection Latches off the part A resistive divider from the auxiliary winding to this pin sets the OPP

compensation level during the on−time. When the voltage exceeds a certain

level at turn off, the part is fully latched off.

4 CS Current sense + slope

compensation This pin monitors the primary peak current but also offers a means to

introduce slope compensation.

5 VCC Supplies the controller −

protects the IC This pin is connected to an external auxiliary voltage. When the VCC exceeds a

certain level, the part enters an auto−recovery hiccup.

6 DRV Driver output The driver output to an external MOSFET gate.

Table 2. DEVICE OPTIONS AND ORDERING INFORMATION

Controller (Note 1) Package

Marking OCP Protection OVP/OTP

Protection Switching

Frequency Package Shipping†

NCP12510ASN65T1G 5DA Latched Latched 65 kHz

TSOP−6

(Pb−Free) 3000 /

Tape & Reel

NCP12510BSN65T1G 5D2 Auto−recovery Latched 65 kHz

NCP12510CSN65T1G 5DC Auto−recovery Auto−recovery 65 kHz

NCP12510ASN100T1G 5DJ Latched Latched 100 kHz

NCP12510BSN100T1G 5DK Auto−recovery Latched 100 kHz

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

1. Other options available upon customer request.

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Figure 2. Internal Circuit Architecture

65 / 100 kHz

Oscillator

Clamp

DRV

VCC and logic

management

VCC

VOVP

GND

OPP/

Latch

Vlatch

Up Counter

to 4

VFB(open)

Req Kratio

Frequency

foldback

Rramp

peak current

freeze

Soft-start

+Vlimit +V

OPP

VOPP

Up counter

to 8

Jittering

RST

tlatch(del)

tlatch(blank)

tOVP(del)

Vskip

Dmax

LEB

Vlimit

Fault timer

OCP

Fault

RST

DRV

pulse

VOPP

DRV pulse

Error

flag

DRV pulse

Latch / Auto-revery

management

Note: depend on IC

option

OVP/OTP

Latch

VCC(OVP)

IC stop

DRV stop

VCC(OVP)

VCC(min)

IC start

IC stop

IC reset

OCP Fault

OVP/OTP

Latch

Pre-short

Latch / Auto-

recovery mode

DRV stop

Latch / Auto-

recovery mode

Internal

supply

IC in regulation

Pre-short

1st DRV pulse

during IC start

VCC(min)

Armed flag

IC in regulation

FB@gnd

VCC(on)

Pre-short logic – available only for latched OCP version

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Table 3. MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VCC Power Supply voltage, VCC pin, continuous voltage −0.3 to 35 V

VDRV(tran) Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1) −0.3 to VCC + 0.3 V

VCS, VFB, VOPP Maximum voltage on low power pins CS, FB and OPP (Note 2) −0.3 to 5.5 V

VOPP(tran) Maximum negative transient voltage on OPP pin (Note 2) −1 V

Isource,max Maximum sourced current, pulsed width < 800 ns 0.6 A

Isink,max Maximum sinked current, pulse width < 800 ns 1.0 A

IOPP Maximum injected negative current into the OPP pin (pin 3) −2 mA

RθJ−A Thermal Resistance Junction−to−Air 360 °C/W

TJ,max Maximum Junction Temperature 150 °C

Storage Temperature Range −60 to +150 °C

HBM Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins) 4 kV

CDM Charged−Device Model ESD Capability per JEDEC JESD22−C101E 750 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.

2. See the Figure 3 for detailed specification of transient voltage.

3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

Figure 3. Negative Pulse for OPP Pin during On−time and Positive Pulse for All Low Power Pins

500 ns

-1 V

VOPP, max

VOPP

VOPP,max = -0.75 V, Tj=-25°C

VOPP,max = -0.65 V, Tj=25°C

VOPP,max =-0.3V,T

j=125°C – Worst case

VOPP must stay between 0V and –0.3 V for

a linear OPP operation

VOPP (t)

on-time 500 ns

7.5 V –

5.5 V –

VCS

VFB

VOPP

SOA

Max DC

voltage

Max transient

voltage

cycle-by-cycle

Max current during

overshoot can 't

exceed 3 mA

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Table 4. ELECTRICAL CHARACTERISTICS

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION

VCC(on) VCC increasing level at which driving pulses are authorized 5 16 18 20 V

VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.3 8.9 9.5 V

VCC(hyst) Hysteresis VCC(on) – VCC(min) 5 7.7 − − V

VCC(reset) Latched state reset voltage 5 − 8.6 − V

VCC(reset_

hyst) Defined hysteresis between minimum and reset voltage VCC(min) –

VCC(reset) 5 0.15 0.30 0.45 V

VCC(latch_hyst) Defined hysteresis for hiccupping between two voltage levels in latch mode 5 − 0.55 − V

ICC1 Start−up current (VCC(on) – 100 mV) 5 − 6 10 mA

ICC2 Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and CL = 0 nF

Internal IC consumption with VFB = 3.2 V, fSW = 100 kHz and CL = 0 nF 5 − 1.0

1.1 1.4

1.5 mA

ICC3 Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and CL = 1 nF

Internal IC consumption with VFB = 3.2 V, fSW = 100 kHz and CL = 1 nF 5 − 1.7

2.3 2.7

3.0 mA

ICC(no−load) Internal consumption in skip mode – non switching, VFB = 0 V 5 − 300 − mA

ICC(fault) Internal consumption in fault mode – during going−down VCC cycle,

VFB = 4 V 5 − 370 − mA

ICC(standby) Internal IC consumption in skip mode for 65 kHz version (VCC = 14 V,

driving a typical 7−A/600−V MOSFET, includes opto current) – (Note 4) 5 − 420 − mA

DRIVE OUTPUT

trOutput voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 − 40 − ns

tfOutput voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 − 30 − ns

ROH Source resistance, VCC = 12 V, IDRV = 100 mA 6 − 28 − W

ROL Sink resistance, VCC = 12 V, IDRV = 100 mA 6 − 7 − W

Isource Peak source current, VGS = 0 V 6 − 300 − mA

Isink Peak sink current, VGS = 12 V 6 − 500 − mA

VDRV(low) DR V pin level at V CC = VCC(min) + 100 mV with a 33 kW resistor to GND 6 8 − − V

VDRV(high) DRV pin level at VCC = VOVP – 100 mV (DRV unloaded) 6 10 12 14 V

CURRENT COMPARATOR

Vlimit Maximum internal current set point – TJ = 25°C – pin 3 grounded

Maximum internal current set point – TJ = −40°C to 125°C – pin 3 grounded 4 0.744

0.720 0.8

0.8 0.856

0.880 V

VCS(fold) Internal voltage setpoint for frequency foldback trip point – 59% of Vlimit 4 − 475 − mV

VCS(freeze) Internal peak current setpoint freeze (≈31% of Vlimit) 4 − 250 − mV

tDEL Propagation delay from CS pin to DRV output 4 − 50 80 ns

tLEB Leading Edge Blanking Duration 4 − 300 − ns

tSS Internal soft−start duration activated upon startup or auto−recovery 4 − 4 − ms

IOPPs Set point decrease for pin 3 grounded 3 − 0 − %

IOPPo Set point decrease for pin 3 biased to −250 mV 3 − 31.3 − %

IOOPv Voltage set point for pin 3 biased to −250 mV, TJ = 25°C

Voltage set point for pin 3 biased to −250 mV, TJ = −40° to 125°C3 0.51

0.50 0.55

0.55 0.60

0.62 V

INTERNAL OSCILLATOR

fOSC(nom) Oscillation frequency (65 kHz version)

Oscillation frequency (100 kHz version) − 61

92 65

100 71

108 kHz

Dmax Maximum duty−ratio − 76 80 84 %

fjitter Frequency jittering in percentage of fOSC – jitter is kept even in foldback

mode − − ±5 − %

4. Application parameter for information only.

5. 1−MW resistor is connected from pin 4 to the ground for the measurement.

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Table 4. ELECTRICAL CHARACTERISTICS

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

INTERNAL OSCILLATOR

fswing Swing frequency − − 240 − Hz

FEEDBACK SECTION

Req Internal equivalent feedback resistance 2 − 29 − kW

Kratio FB pin to current set point division ratio − − 4 − −

VFB(freeze) Feedback voltage below which the peak current is frozen 2 − 1.2 − V

VFB(limit) Feedback voltage corresponding with maximum internal current set point 2 − 3.2 − V

VFB(open) Internal pull−up voltage on FB pin 2 − 4 − V

FREQUENCY FOLDBACK

Vfold(start) Frequency foldback level on the FB pin – ≈59% of maximum peak current − − 1.9 − V

ftrans Minimum operating frequency − 22 26 30 kHz

Vfold(end) End of frequency foldback feedback level, fsw = ftrans − − 1.5 − V

Vskip Skip−cycle level voltage on the feedback pin − − 0.8 − V

Vskip(hyst) Hysteresis on the skip comparator − − 50 − mV

INTERNAL SLOPE COMPENSATION

Vramp Internal ramp level @ 25°C (Note 5) 4 − 2.5 − V

Rramp Internal ramp resistance to CS pin 4 − 20 − kW

PROTECTIONS

Vlatch Latching level input on OPP/Latch pin 3 2.85 3.0 3.15 V

tlatch(blank) Blanking time after Drive output turn off 3 − 1 − ms

tlatch(count) Number of clock cycles before latch is confirmed 3 − 4 −

tlatch(del) OVP/OTP delay time constant before latch is confirmed 3 − 600 − ns

VOVP Over voltage protection on the VCC pin 5 24.0 25.5 27.0 V

tOVP(del) Delay time constant before OVP on VCC is confirmed 5 − 20 − ms

tfault Internal fault timer duration − 100 115 130 ms

4. Application parameter for information only.

5. 1−MW resistor is connected from pin 4 to the ground for the measurement.

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TYPICAL CHARACTERISTICS

Figure 4. Figure 5.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

16.0

16.5

17.0

17.5

18.0

19.0

19.5

20.0

1251007550250−25−50

8.0

8.1

8.3

8.4

8.5

8.7

8.8

9.0

Figure 6. Figure 7.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

8.4

8.5

8.7

8.8

8.9

9.1

9.2

9.4

1251007550250−25−50

100

150

200

250

300

400

450

500

Figure 8. Figure 9.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

8.8

8.9

9.0

9.1

9.2

9.4

9.5

9.6

1251007550250−25−50

200

300

400

500

600

700

800

900

VCC(on) (V)

VCC(reset) (V)

VCC(min) (V)

VCC(reset_hyst) (mV)

VCC(hyst) (V)

VCC(latch_hyst) (V)

18.5

8.2

8.6

8.9

8.6

9.0

9.3

350

9.3

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TYPICAL CHARACTERISTICS

Figure 10. Figure 11.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

100

200

250

300

400

500

Figure 12. Figure 13.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

0.6

0.7

0.9

1.0

1.1

1.3

1.4

1.6

1251007550250−25−50

100

150

200

250

300

400

450

500

Figure 14. Figure 15.

TEMPERATURE (°C) ADAPTER OUTPUT CURRENT (A)

1251007550250−25−50

1.4

1.5

1.7

1.8

1.9

2.2

2.3

2.4

3.02.52.01.5 3.51.00.50

0.5

1.0

1.5

2.0

3.0

3.5

4.0

ICC1 (mA)

ICC(no−load) (mA)

ICC2 (mA)

ICC(fault) (mA)

ICC3 (mA)

ICC (mA)

150

350

450

0.8

1.2

1.5

350

2.0

1.6

2.1 2.5

65 kHz

VIN = 120 Vac

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TYPICAL CHARACTERISTICS

Figure 16. Figure 17.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

Figure 18. Figure 19.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

Figure 20. Figure 21.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

tr (ns)

ROH (W)

tf (ns)

VDRV(low) (V)

ROL (W)

VDRV(high) (V)

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TYPICAL CHARACTERISTICS

Figure 22. Figure 23.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

0.65

0.70

0.75

0.80

0.85

0.95

1.00

1251007550250−25−50

Figure 24. Figure 25.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

300

400

450

550

650

1251007550250−25−50

180

200

220

240

260

300

320

Figure 26. Figure 27.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

150

175

200

225

250

300

325

350

1251007550250−25−50

2.0

2.5

3.0

3.5

4.0

5.0

5.5

6.0

Vlimit (V)

tDEL (ns)

VCS(fold) (mV)

tLEB (ns)

VCS(freeze) (mV)

tSS (ms)

0.90

350

500

600

280

275 4.5

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TYPICAL CHARACTERISTICS

Figure 28. Figure 29.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

0.1

0.2

0.3

0.5

0.6

0.9

1.0

1251007550250−25−50

100

110

115

125

Figure 30. Figure 31.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

Figure 32. Figure 33.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

225

235

245

255

265

275

285

295

IOPPv (V)

fOSC(nom) (kHz)

IOPPo (%)

Dmax (%)

fOSC(nom) (kHz)

fswing (Hz)

0.7

105

120

0.4

0.8

85 65 kHz

100 kHz

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TYPICAL CHARACTERISTICS

Figure 34. Figure 35.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

1.2

1.6

1.8

2.0

2.4

2.8

Figure 36. Figure 37.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

1.5

3.5

4.5

5.5

6.5

7.5

1251007550250−25−50

0.8

1.0

1.2

1.4

1.6

2.0

2.2

2.4

Figure 38. Figure 39.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

0.2

0.4

0.6

0.8

1.0

1.6

1.8

2.0

1251007550250−25−50

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Req (kW)

Vfold(start) (V)

Kratio (−)

Vfold(end) (V)

VFB(freeze) (V)

Vskip (V)

1.4

2.2

2.6

2.5

1.8

1.4

1.2

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TYPICAL CHARACTERISTICS

Figure 40. Figure 41.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

24.5

25.5

26.0

26.5

27.0

27.5

Figure 42. Figure 43.

TEMPERATURE (°C) TEMPERATURE (°C)

1251007550250−25−50

100

105

110

115

120

125

130

Figure 44.

TEMPERATURE (°C)

1251007550250−25−50

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Vskip(hyst) (mV)

VOVP (V)

ftrans (kHz)

tfault (ms)

Vlatch (V)

25.0

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APPLICATION INFORMATION

Introduction

NCP12510 implements a standard current mode

architecture where the switch−off event is dictated by the

peak current set point. This component represents the ideal

candidate where low part−count and cost effectiveness are

the key parameters, particularly in low−cost ac−dc adapters,

open−frame power supplies etc. Updated controller, the

NCP12510 packs all the necessary components normally

needed in today modern power supply designs, bringing

several enhancements such as a non−dissipative OPP,

OVP/OTP implementation, short−circuit protection with

pre−short ready for latched version and improved

consumption, robustness and ESD capabilities.

•Current−mode operation with internal slope

compensation: implementing peak current mode

control at a 65 or 100 kHz switching frequency, the

NCP12510 offers an internal slope compensation signal

that can easily by summed up to the sensed current. Sub

harmonic oscillations can thus be fought via the

inclusion of a simple resistor in series with the

current−sense information.

•Internal OPP: by routing a portion of the negative

voltage present during the on−time on the auxiliary

winding to the dedicated OPP pin (pin 3), the user has a

simple and non−dissipative means to alter the

maximum peak current set point as the bulk voltage

increases. If the pin is grounded, no OPP compensation

occurs. If the pin receives a negative voltage, then a

peak current is reduced down.

•Low startup and standby current: reaching a low

no−load standby power always represents a difficult

exercise when the controller draws a significant amount

of current during startup. The NCP12510 brings

improved consumption to easing the design of low

standby power adapters.

•EMI jittering: an internal low−frequency modulation

signal varies the pace at which the oscillator frequency

is modulated. This helps spreading out energy in

conducted noise analysis. To improve the EMI

signature at low power levels, the jittering is kept in

frequency foldback mode (light load conditions).

•Frequency foldback capability: a continuous flow of

pulses is not compatible with no−load/light−load

standby power requirements. To excel in this domain,

the controller observes the feedback pin and when it

reaches a level of Vfold(start), it starts reduce switching

frequency. When the feedback level reaches Vfold(end),

the frequency hits its lower stop at ftrans. When the

feedback pin goes further down and reaches VFB(freeze),

the peak current setpoint is internally frozen. Below this

point, if power continues to drop, the controller enters

classical skip−cycle mode, as both frequency and peak

current are frozen.

•Internal soft−start: a soft−start precludes the main

power switch from being stressed upon start−up. The

soft−start duration is internally fixed for time tSS and it

is activated during new startup sequence or during

recovering after auto−recovery double hiccup.

•Latch input: the controller includes a latch input (pin

3) that can be used to sense an over voltage or an over

temperature event on the adapter. If this pin is brought

higher than the internal reference voltage Vlatch for four

consecutive cycles, then the circuit is latched off – VCC

hiccups from VCC(min) voltage level with hysteresis

VCC(latch_hyst) = 550 mV typically, until a reset occurs.

The latch reset occurs when the user disconnects the

adapter from the mains and lets the VCC falls below the

VCC(reset) level. For the C version, despite an OVP/OTP

detection, the circuit autorecovers and never latches.

•Auto−recovery OVP on VCC: an OVP protects the

circuit against VCC runaways. If the fault is present at

least for time tOVP(del) then the OVP is validated and

the controller enters double hiccup mode. When the

VCC returns to a nominal level, the controller resumes

operation.

•Short−circuit protection: short−circuit and especially

overload protections are difficult to implement when a

strong leakage inductance between auxiliary and power

windings affects the transformer (the aux winding level

does not properly collapse in presence of an output

short). In this controller, every time the internal

maximum peak current limit Vlimit is activated (or less

when OPP is used), an error flag is asserted and a time

period starts thanks to an internal timer. When the timer

has elapsed while a fault is still present, the controller is

latched or enters an auto−recovery mode, depending on

the selected OCP option.

Please note that with active Pre−short option (could be

active only for latched OCP version), the part becomes

sensitive to the first UVLO event during the start−up

sequence. Any other UVLO events are ignored

afterwards – auto−recovery operation. With the first

drive pulse is generated armed flag. Armed flag is reset

after the first successful start−up sequence (the

controller gets into regulation). This is to pass the

pre−short test at power up:).

1. if the internal armed flag is active and an UVLO

event is sensed, the part is immediately latched.

2. if an UVLO signal is detected but the armed flag is

not asserted, double−hiccup auto−recovery occurs.

3. if the controller gets into regulation, the armed flag

is reset. Then UVLO event is sensed, the part is in

auto−recovery operation.

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Start−up Sequence

The NCP12510 start−up voltage is made purposely high

to permit large energy storage in a small VCC capacitor

value. This helps operate with a small start−up current

which, together with a small VCC capacitor, will not hamper

the start−up time. To further reduce the standby power, the

start−up current of the controller is extremely low, below

10 mA. The start−up resistor can therefore be connected to

the bulk capacitor or directly to the mains input voltage to

further reduce the power dissipation.

Rstart-up

aux.

winding

Cbulk

CVCC

VCC

Input

mains

Figure 45. The startup resistor can be connected to the input mains for further power dissipation reduction.

The first step starts with the calculation of the needed

VCC capacitor which will supply the controller which it

operates until the auxiliary winding takes it over. Experience

shows that this time t1 can be between 5 and 20 ms. If we

consider we need at least an energy reservoir for a t1 time of

10 ms, the VCC capacitor must be larger than:

CVCC wICC @t1

VCC(on) *VCC(min) w1.7 m @10 m

18 *8.9 w1.9 mF

(eq. 1)

Let us select a 2.2 mF capacitor at first and experiments in

the laboratory will let us know if we were too optimistic for

the time t1. The VCC capacitor being known, we can now

evaluate the charging current we need to bring the VCC

voltage from 0 V to the VCC(on) of the IC. This current has

to be selected to ensure a start−up at the lowest mains

(85 Vrms) to be less than 3 s (2.5 s for design margin):

Icharge wVCC(on) @CVCC

tstart*up w18 @2.2 m

2.5 w16 mA(eq. 2)

If we account for the 10 mA (maximum) that will flow to

the controller, then the total charging current delivered by

the start−up resistor must be 26 mA. If we connect the

start−up network to the mains (half−wave connection then),

we know that the average current flowing into this start−up

resistor will be the smallest when VCC reaches the VCC(on)

of the controller:

ICVCC,min +

Vac,rms 2

p*VCC(on)

Rstart*up (eq. 3)

To make sure this current is always greater than 26 mA,

then, the minimum value for Rstart−up can be extracted:

start*up v

Vac,rms 2

p*VCC(on)

ICVCC(min) v

85 2

p*18

26 mv779 kW

(eq. 4

)

This calculation is purely theoretical, considering a

constant char ging current. In reality, the take over time can

be shorter (or longer!) and it can lead to a reduction of the

VCC capacitor. Thus, a decrease in charging current and an

increase of the start−up resistor can be experimentally

tested, for the benefit of standby power. Laboratory

experiments o n the prototype are thus mandatory to fine tune

the converter. If we chose the 750 kW resistor as suggested

by Equation 4, the dissipated power at high line amounts to:

PRstart*up,max [Vac,peak2

4@Rstart*up [ǒ230 @2

ǸǓ2

4@750 k [35 mW

(eq. 5)

Now that the first VCC capacitor has been selected, we

must ensure that the self−supply does not disappear when in

no−load conditions. In this mode, the skip−cycle can be so

deep that refreshing pulses are likely to be widely spaced,

inducing a large ripple on the VCC capacitor. If this ripple

is too large, chances exist to touch the VCC(min) and reset the

controller into a new start−up sequence. A solution is to

grow th i s c a p a c i t o r b u t i t w i l l o b v i o u s l y b e d e trimental to the

start−up time. The option offered in Figure 45 elegantly

solves this potential issue by adding an extra capacitor on the

auxiliary winding. However, this component is separated

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from the VCC pin via a simple diode. You therefore have the

ability to grow this capacitor as you need to ensure the

self−supply of the controller without affecting the start−up

time and standby power.

Internal Over Power Protection

There are several known ways to implement Over Power

Protection (OPP), all suffering from particular problems.

These problems range from the added consumption burden

on the converter or the skip−cycle disturbance brought by

the current−sense offset. A way to reduce the power

capability a t high line is to capitalize on the negative voltage

swing present on the auxiliary diode anode. During the

turn−on time, this point dips to –N2Vbulk, where N2 being the

turns ratio between the primary winding and the auxiliary

winding. The negative plateau observed on Figure 46 will

have amplitude depending on the input voltage. The idea

implemented in this chip is to sum a portion of this negative

swing with the internal voltage reference Vlimit = 0.8 V. For

instance, if t h e voltage swings down to −150 mV during the

on−time, then the internal peak current set point will be fixed

to the value 0.8 V – 0.150 V = 650 mV. The adopted principle

appears in Figure 47 and shows how the final peak current

set point is constructed.

Let’s assume we need to reduce the peak current from

2.5 A at low line, to 2 A at high line. This corresponds to a

20% reduction or a set point voltage of 640 mV. To reach this

level, then the negative voltage developed on the OPP pin

must reach:

VOPP +0.8 @Vlimit *Vlimit +0.64 *0.8 +−160 mV

(eq. 6)

1v(24)

464u 472u 480u 488u 496u

time in seconds

−40.0

−20.0

20.0

40.0

v(24) in volts

Plot1

−N2Vbulk

N1(Vout+Vf)

on−time

off−time

1v(24)

464u 472u 480u 488u 496u

time in seconds

−40.0

−20.0

20.0

40.0

v(24) in volts

Plot1

−N2Vbulk

N1(Vout+Vf)

on−time

off−time

Figure 46. The signal obtained on the auxiliary winding swings negative during the on−time.

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OPP

ROPPL

VCC

ROPPU

aux.

winding

IOPP

ref = 0.8V + VOPP

Vlimit =0.8V ±7%

driver reset

CS Rsense

SUM

ref

(VOPP is negative)

This point will be

adjusted to reduce

the „ref“ at hi line to

the desired level

swings to:

N1Vout during toff

-N2Vin during ton

Figure 47. The OPP circuitry affects the maximum peak current set point by summing a negative voltage to the

internal voltage reference.

Let us assume that we have the following converter

characteristics:

Vout = 19 V

Vin = 85 to 265 Vrms

N1 = Np:Ns = 1:0.25

N2 = Np:Naux = 1:0.18

Given the turns ratio between the primary and the auxiliary

windings, the on−time voltage at high line (265 Vrms) on the

auxiliary winding swings down to:

Vaux +−N2@Vin,max +−0.18 @375 +−67.5 V (eq. 7)

To obtain a level as imposed by Equation 7, we need to

install a divider featuring the following ratio:

Div +VOPP

Vaux +−0.16

−67.5 [2.4 m (eq. 8)

If we arbitrarily fix the pull−down resistor ROPPL to 1 kW,

then the upper resistor can be obtained by:

OPPU +

aux *

OPP

VOPP

OPPL

+−67.5 )0.16

−0.16

[422 kW(eq. 9

)

If we now plot the peak current set point obtained by

implementing the recommended resistor values, we obtain

the following curve, as shown in Figure 48.

Vbulk

Peak current

setpoint

100%

80%

375 V

Figure 48. The peak current regularly reduces down to 80% at 375 Vdc.

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The OPP pin is surrounded by Zener diodes stacked to

protect the pin against ESD pulses. These diodes accept

some peak current in the avalanche mode and are designed

to sustain a certain amount of energy. On the other side,

negative injection into these diodes (or forward bias) can

cause substrate injection which can lead to an erratic circuit

behavior. To avoid this problem, the pin is internal clamped

slightly below –300 mV which means that if more current i s

injected before reaching the ESD forward drop, then the

maximum peak reduction is kept to 40%. If the voltage

finally forward biases the internal zener diode, then care

must be taken to avoid injecting a current beyond –2 mA.

Given the value of ROPPU, there is no risk in the present

example.

Finally, please note that another comparator internally

fixes the maximum peak current set point to value Vlimit even

if the OPP pin is adversely biased above 0 V.

Frequency Foldback

The reduction of no−load standby power associated with

the need for improving the efficiency, requires a change in

the traditional fixed−frequency type of operation. This

controller implements a switching frequency foldback when

the feedback voltage passes below a certain level, Vfold(start).

At this point, the oscillator turns into a Voltage−Controlled

Oscillator (VCO) and reduces switching frequency down to

ftrans value, till to feedback voltage reaches the level

Vfold(end). Below this level Vfold(end), the frequency is fixed

and cannot go further down. The peak current setpoint is

following the feedback pin until its level reaches VFB(freeze).

Below this value, the peak current setpoint is frozen to

VCS(freeze) value or ≈31% of the maximum Vlimit setpoint.

The only way to further reduce the transmitted power is to

enter skip cycle, which is set when the feedback voltage

reaches the level Vskip. Skip cycle offers the best noise−free

performance in no−load conditions. Figure 49 and depicts

the adopted scheme for the part.

Frequency Peak current setpoint

VFB

fSW

VFB

VCS

fOSC(nom)

ftrans

Vskip Vfold(end) Vfold(start) VFB(open)

Vlimit

VCS(fold)

VCS(freeze)

Vskip VFB(freeze) Vfold(start)

min

max

VFB(limit)

Figure 49. By observing the voltage on the feedback pin, the controller reduces its switching frequency for an

improved performance at light load.

VFB [V]

Open loop

Skip mode

Ipeak, max

Ipeak, min

Peak current

is frozen

Peak current

is clamped

Peak current

is changing

fOSC(nom)

ftrans

fSW is fixed

to fOSC(nom)

fSW is changing

Vskip

Vfold(end)

Vfold(start)

VFB(open )

VFB(freeze )

VFB(limit )

Figure 50. Another look at the relationship between feedback and current setpoint while in frequency reduction

mode.

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Auto−Recovery Short−Circuit Protection

In case of output short−circuit or if the power supply

experiences a severe overloading situation, an internal error

flag is raised and the fault timer starts countdown. If the

UVLO has come (see Figure 51 – Short−circuit case I.) or the

error flag is asserted throughout the tfault time (see Figure 51

– Short−circuit case II.) – i.e. the fault timer has elapsed, the

driving pulses are stopped and the VCC falls down as the

auxiliary voltage are missing. When the supply voltage VCC

touches the VCC(min) level, the controller consumption is

down t o a few mA and the VCC slowly builds up again thanks

to the resistive startup network. When VCC reaches VCC(on),

the controller purposely ignores the re−start and waits for

another VCC cycle: this is the so−called double hiccup

auto−recovery mode. Illustration of such principle appears

in Figure 51. Please note that soft−start is activated upon

every re−start attempt.

Figure 51. An auto−recovery double hiccup mode is entered in case a faulty event longer than programmable

fault timer value is acknowledged by the controller.

VCC (t)

VDRV (t)

VCC(on)

VCC(min)

Error flag

VCS (t)

Vlimit

Short-circuit case II . -> Error flag raised ->

Fault timer elapsed -> auto-recovery

Fault timer has

elapsed

Short-circuit case I. -> Error flag

raised -> UVLO -> auto-recovery

Fault timer has

elapsed

Latched Short−Circuit Protection with Pre−Short

In some applications, the controller must be fully latched

in case of an output short circuit presence. In that case, you

would select a controller with an OCP latched option in the

Options table. When the error flag is asserted, meaning the

controller is asked to deliver its full peak current, the

controller latches off after the elapse of fault timer – i.e. the

pulses are immediately stopped and VCC hiccups between

two voltage levels, given by a VCC(min) level and added

hysteresis VCC(latch_hyst), until a reset occurs (VCC falls

down below VCC(reset)). However, in presence of damaged

or old VCC capacitor, it can very well be the case where the

stored energy does not give enough time to let the timer

elapse before VCC touches the UVLO level. When this

happens, the latch is not acknowledged since the timer

countdown has been prematurely aborted. To avoid this

situation, the NCP12510 is equipped with Pre−short logic

for OCP latched option, i.e. the Pre−short cannot be used for

auto−recovery OCP option. The Pre−short logic combines

the armed flag assertion together with the UVLO event to

confirm a pre−short situation: upon start−up with first drive

pulse, the armed flag is raised until regulation is met. If

during the time the flag is raised an UVLO event is detected,

the part latches off immediately. When IC is latched, VCC

enters hiccup mode. In normal operation, if an UVLO event

is detected for any reason, the controller will naturally

resume operations. Details of this behavior are given in

Figure 52.

Pre−short logic is active during the start−up sequence, i.e.

the first startup of power supply or after recovering from

double hiccup mode. The armed flag is asserted with the first

drive pulse. If an UVLO event occurs when the armed flag

is asserted, the part immediately latches off. If no UVLO

occurs, once the output voltage has reached regulation in 8

consecutive cycles, the internal armed flag is reset

(pre−short logic is no active anymore until new startup of

power supply) and any new UVLO events will

auto−recovery. Pre−short logic is available only on customer

request. It is not active in standard devices.

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VCC (t)

VDRV (t)

VCC(on)

VCC(min)

VCC(reset)

flag

VCS (t)

Vlimit

UVLO@start-up

AND

armed flag

latched new sequence

glitch

resumed

8 cycles

resumed

armed flag

UVLO@recovering

AND

armed flag

latched

UVLO after regulation

8 cycles

VCC(latch_hyst)

Figure 52. Full latc h occurs in case the UVLO@start−up or @recovering is detected while the armed flag is asserted

Armed

VCC (t)

VDRV (t)

VCC(on)

Error flag

VCS (t)

Vlimit

8 cycles

Fault timer has

elapsed

flag

latched

When the IC is latched, the user

have to unplugged and plugged

the adapter to the outlet

restart

UVLO@start-up

AND

armed flag

Armed flag

Error flag

VCC(min)

VCC(reset)

VCC(latch_hyst)

The VCC hysteresis in latch mode

significantly improves the reset time .

Figure 53. Full latch occurs in case the fault timer has elapsed or UVLO@start−up is detected with asserted

armed flag.

Armed

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Operation with Grounded Feedback Pin

The NCP12510 offers the operation mode when the

NCP12510 could be controlled by Master system via

Feedback pin (pin 2). When FB pin is grounded, the

controller driver pulses are stopped. This is the same

situation, when the controller is in skip mode, but with the

difference that FB pin could be forced to ground by Master

system anytime during operation, even at start−up sequence.

When the VCC touches VCC(on) level, the controller

internal logic starts and thus, first DRV pulse is authorized

after the safety period of 200 ms passes. But the last DRV

pulse can comes just before VCC(min) level. Therefore, there

are extended rules to generation and cancellation the armed

flag to avoid the false pre−short condition if the controller

can’t start properly because of the grounded FB pin.

VCC (t)

VDRV (t)

VCC(on)

VCC(reset)

Armed flag

VCS (t)

Vlimit

UVLO@start-up

AND

armed flag

latched new sequence

VFB (t)

UVLO@start-up

AND

armed flag

Grounded FB@VCC(on)

→ No Armed flag

latched new sequence

FB@

gnd

latched

FB@gnd

UVLO

AND

Armed

flag

Grounded FB@first going-

down VCC cycle → Double

hiccup → switching

allowed every odd V CC(on)

VCC(min)

VCC(latch_hyst)

Figure 54. The controller start−up sequence with grounded FB pin and Pre−short condition.

VCC (t)

VDRV (t)

VCC(on)

VCC(min)

VCC(reset)

Armed flag

VCS (t)

Vlimit

VFB (t)

UVLO and

NO armed flag

auto-recovery

8 cycles

new sequence

UVLO and

NO armed flag

auto-recovery

8 cycles

FB@

gnd

FB@

gnd

FB@

gnd

FB@

gnd

auto-recovery

UVLO

Figure 55. The controller behaviour during start−up sequence interupted by grounded FB pin.

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The armed flag is generated with first DRV pulse, but only

if the first DRV pulse is synchronized with VCC(on) event. If

the FB pin is forced to ground during the VCC(on) event and

it is released afterwards, the armed flag is not generated. The

Figure 54 shows the cases of grounded FB pin at the

beginning of start−up sequence.

If the armed flag isn’t active and UVLO comes, the

controller newly starts after double−hiccup auto−recovery

sequence. Then, if UVLO comes again, the controller is

latched o f f . DRV pulses are authorized during the whole first

VCC going−down cycle. If any DRV pulse doesn’t come

during this time, the double−hiccup auto−recovery sequence

is coming.

The armed flag could be canceled by two conditions.

When the controller gets into regulation after start−up

sequence, i.e. during the eight consecutive switching cycles

is current setpoint voltage under Vlimit, the armed flag is

called o ff – this is the first armed flag cancelation condition.

When the start−up sequence isn’t complete and is

interrupted by grounded FB pin, the armed flag is called of f

– this is the second armed flag cancelation condition. The

Figure 55 shows the cases of interrupted start−up sequence

by grounded FB pin.

If the start−up sequence is interrupted by grounded FB

pin, the armed flag is canceled. Then, if UVLO comes, the

controller newly starts after double−hiccup auto−recovery

sequence. Then, if UVLO comes again, the controller is

latched off.

The Figure 56 shows the case of operation, when the

controller can operate under some master system with

superordinate function. Then, the FB pin is used for

authorization or denial DRV pulses. If the normal operation

state is interrupted for a long time and afterwards the

soft−start is demanded for proper start−up of power supply,

the VCC have to be pulled−down below VCC(reset) level.

Then, if the FB isn’t grounded, the new start−up sequence

are initialized when VCC touches VCC(on) level + 200 ms

safety period. During this new start−up sequence is

generated the armed flag.

VCC (t)

VDRV (t)

VCC(on)

VCC(min)

VCC(reset)

flag

VCS (t)

Vlimit

VFB (t)

8 cycles

new sequence

FB@

gnd

8 cycles

FB@

gnd

Stop DRV pulses by

Master Sytem

Supply voltage VCC is

controlled by Master System

FB@

gnd

The IC must be reset to

ensure the soft-start

after release the FB

8 cycles

Grounded FB@VCC(on)

→ No Armed flag

Figure 56. The Master system driving the controller by forcing the FB pin to ground.

Armed

Slope Compensation

The NCP12510 includes an internal slope compensation

signal. This is the buffered oscillator clock delivered during

the on−time only. Its amplitude is around 2.5 V at the

maximum duty ratio. Slope compensation is a known means

used to cure sub harmonic oscillations in CCM−operated

current−mode converters. These oscillations take place at

half the switching frequency and occur only during

Continuous Conduction Mode (CCM) with a duty ratio

greater than 50%. To lower the current loop gain, one usually

injects between 50 and 100% of the primary inductance

downslope. Figure 57 depicts how the ramp is generated

internally. Please note that the ramp signal will be

disconnected from the CS pin during the off−time.

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2.5 V

tLEB

_CS Rcomp

Rsense

20 kΩ

ON time

From FB

Driver

reset

TSW

Dmax

Rramp

Figure 57. Inserting a resistor in series with the current sense information brings slope compensation and

stabilizes the converter in CCM operation.

In the NCP12510 controller, the oscillator ramp features

a 2.5 V swing. If the clock operates at a 65 kHz frequency,

then the available oscillator slope corresponds to:

ramp +

ramp,peak

max

+2.5

0.8 @15 m+208 mVńms(eq. 10

)

In our flyback design, let’s assume that our primary

inductance Lp is 770 mH, and the SMPS delivers 19 V with

a Np:Ns ratio of 1:0.25. The off−time primary current slope

Sp is thus given by:

Sp+

ǒVout )VfǓ@Ns

Lp+(19 )0.7)@4

770 m+102 mAńms

(eq. 11)

Given a sense resistor of 330 mW, the above current ramp

turns into a voltage ramp of the following amplitude:

Ssense +Sp@Rsense +102 m @0.33 +34 mVńms

(eq. 12)

If we select 50% of the downslope as the required amount

of slope compensation, then we shall inject a ramp whose

slope is 17 mV/ms. Our internal compensation being of

208 mV/ms, the divider ratio (divratio) between Rcomp and

the internal Rramp = 20 kW resistor is:

divratio +0.5 @Ssense

Sramp +0.082 (eq. 13)

The series compensation resistor value is thus:

Rcomp +Rramp @divratio +20 k @0.082 +1.64 kW

(eq. 14)

A resistor of the calculated value will then be inserted

from the sense resistor to the current sense pin. We

recommend adding a small capacitor of 100 pF, from the

current sense pin to the controller ground for an improved

immunity to the noise. Please make sure both components

are located very close to the controller.

Latching Off the Controller

The OPP pin not only allows a reduction of the peak

current set point in relationship to the line voltage, it also

offers a means to permanently latch−off the part. When the

part is latched−off, all pulses are immediately stopped and

VCC hiccups from VCC(min) voltage level with hysteresis

VCC(latch_hyst) until a reset occurs (VCC falls down below

level VCCreset), e.g. by un−plugging the converter from the

mains outlet. The VCC latch hysteresis helps significantly

reduce the reset time, because when the user unplugged the

adapter from the outlet in the less favorable time (VCC is in

its maximum), the VCC has to fall down from voltage level

given by 550 mV + 300 mV typically to reset level.

The latch detection is made by observing the OPP pin by

a comparator featuring a Vlatch reference voltage. However,

for noise reasons and in particular to avoid the leakage

inductance contribution at turn off, a blanking delay

tlatch−blank is introduced before the output of the OVP

comparator is checked. Then, the OVP comparator output is

validated only if its high−state duration lasts for a minimum

time tlatch−del. Below this value, the event is ignored. Then,

a counter ensures that only 4 successive OVP events have

occurred before actually latching the part. There are several

possible implementations, depending on the needed

precision and the parameters you want to control.

The first and easiest solution is the additional resistive

divider on top of the OPP one. This solution is simple and

inexpensive but requires the insertion of a diode to prevent

disturbing the OPP divider during the on−time.

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Vlatch

VCC (t)

VDRV (t)

VCC(on)

VCC(min)

VCC(reset)

Vlatch (t) The IC is latched after the fault is confirmed for 4

consecutive DRV cycles

The user unplugged and plugged

the adapter to the outlet

VCC(latch_hyst)

The time needs for IC reset is

significantly shorter due to the

VCC hysteresis used in latch mode .

Figure 58. Latching off the controller and resuming operation.

OPP/

Latch +

Vlatch

ROPPL

100p

VCC

ROPPU

ROVP

OVP OPP

aux.

winding

Figure 59. A simple resistive divider brings the OPP pin above 3 V in case of a VCC voltage runaway above 18 V.

First, calculate the OPP network with the above equations.

Then, suppose we want to latch off our controller when Vout

exceeds 25 V. On the auxiliary winding, the plateau reflects

the output voltage by the turns ratio between the power and

the auxiliary winding. In case of voltage runaway for our

19 V adapter, the plateau will go up to:

Vaux,OVP +Vout @Ns

Naux +25 @0.18

0.25 +18 V (eq. 15)

Since our OVP comparator trips at level Vlatch = 3 V,

across the 1 kW selected OPP pull−down resistor, it implies

a 3 mA current. From 3 V to go up to 18 V, we need an

additional 1 5 V. Under 3 mA and neglecting the series diode

forward drop, it requires a series resistor of:

ROVP +Vout @Vaux,OVP *Vlatch

VOVP

ROPPL

+18 *3

+5kW

(eq. 16)

In nominal conditions, the plateau establishes to around

14 V. Given the divide by 6 ratio, the OPP pin will swing to

14/6 = 2.3 V during normal conditions, leaving 700 mV for

the noise immunity. A 100 pF capacitor can be added to

improve it and avoid erratic trips in presence of external

surges. D o n ot i ncrease t his c apacitor t oo much o therwise t he

OPP signal will be affected by the integrating time constant.

A second solution for the OVP detection alone is to use a

Zener diode wired as recommended by Figure 60.

OPP /

Latch +Vlatch

ROPPL

22p

VCC

ROPPU

OVP OPP

aux.

winding

15 V D1

Figure 60. A Zener diode in series with a diode helps to improve the noise immunity of the system.

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In this case, to still trip at 18 V level, we have selected a

15 V Zener diode. In nominal conditions, the voltage on the

OPP pin is almost 0 V during the off−time as the Zener is

fully blocked. This technique clearly improves the noise

immunity of the system compared to that obtained from a

resistive string as in Figure 59. Please note the reduction of

the capacitor on the OPP pin to 10−22 pF. This is because of

the potential spike going through the Zener parasitic

capacitor and the possible auxiliary level shortly exceeding

its breakdown voltage during the leakage inductance reset

period (hence the internal blanking delay tlatch−blank at turn

off). This spike despite its very short time is energetic

enough to charge the added capacitor C1 and given the time

constant, could make it discharge slower, potentially

disturbing the blanking circuit. When implementing the

Zener option, it is important to carefully observe the OPP pin

voltage (short probe connections!) and check that enough

margin exists to that respect.

Over Temperature Protection

In a lot of designs, the adapter must be protected against

thermal runaways, e.g. when the temperature inside the

adapter box increases a certain value. Figure 61 shows how

to implement a simple OTP using an external NTC and a

series diode. The principle remains the same: make sure the

OPP network is not bothered by the additional NTC hence

the presence of this diode.

OPP/

Latch +

Vlatch

ROPPL

VCC

ROPPU

OVP OPP

aux.

winding

NTC D1

Figure 61. The internal circuitry hooked to OPP/Latch pin can be used to implement over temperature protection

(OTP).

When the NTC resistor will diminish as the temperature

increases, the voltage on the OPP pin during the off−time

will slowly increase and, once it passes Vlatch level for 4

consecutive clock cycles, the controller will permanently

latch off.

Back to our 19 V adapter, we have found that the plateau

voltage on the auxiliary diode was 14 V in nominal

conditions. We have selected an NTC which offers a 470 kW

resistance at 25°C and drops to 8.8 kW at 110°C. If our

auxiliary winding plateau is 14 V and we consider a 0.7 V

forward drop for the diode, then the voltage across the NTC

in fault mode must be:

NTC +Vaux *Vlatch *VF+14 *3*0.7 +10.3 V

(eq. 17

)

Based on the 8.8 kW NTC resistor at 110°C, the current

inside the device must be:

INTC +VNTC

RNTC(110) +10.3

8.8 k +1.2 mA (eq. 18)

As such, the bottom resistor ROPPL, can easily be calculated:

ROPPL +Vlatch

INTC +2.5 kW(eq. 19)

Now the pull down OPP resistor is known, we can

calculate the upper resistor value ROPPU to adjust the power

limit at the chosen output power level. Suppose we need a

200 mV decrease from the Vlimit setpoint and the on−time

swing o n t h e auxiliary anode is −67.5 V, then we need to drop

over ROPPU a voltage of:

OPPU

aux *

OPP +

−67.5

)

0.2

−67.3 V

(eq. 20

)

The current circulating the pull down resistor ROPPL in this

condition will be:

IROPPL +VOPP

ROPPL +−0.2

2.5 k +−80 mA(eq. 21)

The ROPPU value is therefore easily derived:

ROPPU +VROPPU

IROPPU

+−67.3

−80 m[841 kW(eq. 22)

Combining OVP and OTP

The OTP and Zener−based OVP can be combined

together as illustrated by Figure 62. In nominal V CC/output

conditions, when the Zener is not activated, the NTC can

drive the OPP pin and trigger the adapter in case of a fault.

On the contrary, in nominal temperature conditions, if the

loop is broken, the voltage runaway will be detected and

acknowledged by the controller.

In case the OPP pin is not used for either OPP or OVP, it

can simply be grounded.

NCP12510

www.onsemi.com

OPP /

Latch +

Vlatch

ROPPL

VCC

ROPPU

OVP OPP

aux.

winding

NTC

15 V D1

Figure 62. With the NTC back in place, the circuit nicely combines OVP, OTP and OPP on the same pin.

Filtering the Spikes

The auxiliary winding is the seat of spikes that can couple

to the OPP pin via the parasitic capacitances exhibited by the

Zener diode and the series diode. To prevent an adverse

triggering of the Over Voltage Protection circuitry, we

recommend the installation of a small RC filter before the

detection network as illustrated by Figure 63. The values of

resistance and capacitance must be selected to provide the

adequate filtering function without degrading the stand−by

power by an excessive current circulation.

OPP/

Latch +

Vlatch

ROPPL

VCC

ROPPU

OVP OPP

aux.

winding

NTC

15 V D1

Additional filter

Figure 63. A small RC filter prevents the fast rising spikes from reaching the protection pin OPP/latch in presence

of energetic perturbations superimposed on the input line.

NCP12510

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PACKAGE DIMENSIONS

ÉÉ

TSOP−6

CASE 318G−02

ISSUE V

456

0.05

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

AMIN NOM MAX

MILLIMETERS

0.90 1.00 1.10

A1 0.01 0.06 0.10

b0.25 0.38 0.50

c0.10 0.18 0.26

D2.90 3.00 3.10

E2.50 2.75 3.00

e0.85 0.95 1.05

L0.20 0.40 0.60

0.25 BSC

L2 −

0°10°

1.30 1.50 1.70

RECOMMENDED

NOTE 5

SEATING

PLANE

GAUGE

PLANE

DETAIL Z

0.60

3.20 0.95

0.95

PITCH

DIMENSIONS: MILLIMETERS

STYLE 13:

PIN 1. GATE 1

2. SOURCE 2

3. GATE 2

4. DRAIN 2

5. SOURCE 1

6. DRAIN 1

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