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SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

Product specification

Supersedes data of 2000 Apr 03 2000 Sep 22

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2

2000 Sep 22 853-2219 24638

DESCRIPTION

The SC28L91 is a new member of the IMPACT family of Serial

Communications Controllers. It is a single channel UART operating

at 3.3 and 5.0 volts Vcc, 8 or 16 byte FIFOs and is quite compatible

with software of the SC28L92 and previous UARTs offered by

Philips. It is a new part that is similar to our previous one channel

part but is vastly improved. The improvements being: 16 character

receiver, 16 character transmit FIFOs, watch dog timer for the

receiver, mode register 0 is added, extended baud rate, over all

faster bus and data speeds, programmable receiver and transmitter

interrupts and versatile I/O structure. (The previous one channel

part, SCC2691, is NOT being discontinued.)

Pin programming will allow the device to operate with either the

Motorola or Intel bus interface. Bit 3 of the MR0 register allows the

device to operate in an 8-byte FIFO mode if strict compliance with

an 8-byte FIFO structure is required.

The Philips Semiconductors SC28L91 Universal Asynchronous

Receiver/Transmitter (UART) is a single-chip CMOS-LSI

communications device that provides a full-duplex asynchronous

receiver/transmitter channel in a single package. It interfaces

directly with microprocessors and may be used in a polled or

interrupt driven system with modem and DMA interface.

The operating mode and data format of the channel can be

programmed independently. Additionally, the receiver and

transmitter can select its operating speed as one of 28 fixed baud

rates; a 16X clock derived from a programmable counter/timer, or an

external 1X or 16X clock. The baud rate generator and counter/timer

can operate directly from a crystal or from external clock inputs. The

ability to independently program the operating speed of the receiver

and transmitter make the UART particularly attractive for dual-speed

channel applications such as clustered terminal systems.

The receiver and transmitter is buffered by 8 or 16 character FIFOs

to minimize the potential of receiver overrun, transmitter underrun

and to reduce interrupt overhead in interrupt driven systems. In

addition, a flow control capability is provided via RTS/CTS signaling

to disable a remote transmitter when the receiver buffer is full.

DMA interface is and other general purpose signals are provided on

the SC28L91 via a multipurpose 7-bit input port and a multipurpose

8-bit output port. These can be used as general-purpose ports or

can be assigned specific functions (such as clock inputs or

status/interrupt outputs, FIFO conditions) under program control.

The SC28L91 is available in two package versions: a 44-pin PLCC

and 44-pin plastic quad flat pack (PQFP).

FEATURES

•Member of IMPACT family: 3.3 to 5.0 volt , –40°C to +85°C and

68K for 80xxx bus interface for all devices.

•A full-duplex independent asynchronous receiver/transmitter

•16 character FIFOs for each receiver and transmitter

•Pin programming selects 68K or 80xxx-bus interface

•Programmable data format

–5 to 8 data bits plus parity

–Odd, even, no parity or force parity

–– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•16-bit programmable Counter/T imer

•Programmable baud rate for each receiver and transmitter

selectable from:

–28 fixed rates: 50 to 230.4 k baud

–Other baud rates to 1 MHz at 16X

–Programmable user-defined rates derived from a programmable

counter/timer

–External 1X or 16X clock

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

–Normal (full-duplex)

–Automatic echo

–Local loop back

–Remote loop back

–Multi-drop mode (also called ‘wake-up’ or ‘9-bit’)

•Multi-function 7-bit input port (includes IACKN)

–Can serve as clock or control inputs

–Change of state detection on four inputs

–Inputs have typically >100k pull-up resistors

–Change of state detectors for modem control

•Multi-function 8-bit output port

–Individual bit set/reset capability

–Outputs can be programmed to be status/interrupt signals

–FIFO status for DMA interface

•Versatile interrupt system

–Single interrupt output with eight maskable interrupting

conditions

–Output port can be configured to provide a total of up to six

separate interrupt outputs that may be wire ORed.

–Each FIFO can be programmed for four different interrupt levels

–W atch dog timer for the receiver

•Maximum data transfer rates:

1X – 1Mb/sec, 16X – 1Mb/sec

•Automatic wake-up mode for multi-drop applications

•Start-end break interrupt/status with mid-character break detect.

•On-chip crystal oscillator

•Power down mode

•Receiver time-out mode

•Single +3.3V or +5V power supply

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 3

ORDERING INORMATION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Industrial

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

VCC = +3.3 ±10%, +5V ±10%

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁÁÁÁÁÁÁ

Tamb = –40 to +85°C

ÁÁÁÁÁÁÁÁÁÁÁ

Drawing Number

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

44-Pin Plastic Leaded Chip Carrier (PLCC)

ÁÁÁÁÁÁÁÁÁÁÁ

SC28L91A1A

ÁÁÁÁÁÁÁÁÁÁÁ

SOT187-2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

44-Pin Plastic Quad Flat Pack (PQFP)

ÁÁÁÁÁÁÁÁÁÁÁ

SC28L91A1B

ÁÁÁÁÁÁÁÁÁÁÁ

SOT307-2

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 4

PIN CONFIGURATION DIAGRAM

80XXX PIN CONFIGURATION

Pin Function

1A3

2 IP0

3 WRN

4 RDN

5V

CC

6 No Connection

7 OP1

8 OP3

9 OP5

10 OP7

11 I/M

12 D1

13 D3

14 D5

15 D7

Pin Function

16 GND

17 GND

18 INTRN

19 D6

20 D4

21 D2

22 D0

23 NC

24 OP6

25 OP4

26 OP2

27 OP0

28 TxDA

29 RxDA

30 x1/clk

Pin Function

31 x2

32 RESET

33 CEN

34 IP2

35 IP6

36 IP5

37 IP4

38 VCC

39 VCC

40 A0

41 IP3

42 A1

43 IP1

44 A2

PQFP

44 34

1

11

33

23

12 22

SD00698

1

39

17

28

40

29

18

7

PLCC

6

SD00699

Pin Function

1NC

2A0

3 IP3

4A1

5 IP1

6A2

7A3

8 IP0

9 WRN

10 RDN

11 VCC

12 I/M

13 No Connection

14 OP1

15 OP3

Pin Function

16 OP5

17 OP7

18 D1

19 D3

20 D5

21 D7

22 VSS

23 NC

24 INTRN

25 D6

26 D4

27 D2

28 D0

29 OP6

30 OP4

Pin Function

31 OP2

32 OP0

33 TxDA

34 NC

35 RxDA

36 X1/CLK

37 X2

38 RESET

39 CEN

40 IP2

41 IP6

42 IP5

43 IP4

44 VCC

Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 5

PIN CONFIGURATION DIAGRAM

68XXX PIN CONFIGURATION

Pin Function

1A3

2 IP0

3 R/WN

4 DACKN

5V

CC

6 No Connection

7 OP1

8 OP3

9 OP5

10 OP7

11 I/M

12 D1

13 D3

14 D5

15 D7

Pin Function

16 GND

17 GND

18 INTRN

19 D6

20 D4

21 D2

22 D0

23 NC

24 OP6

25 OP4

26 OP2

27 OP0

28 TxDA

29 RxDA

30 x1/clk

Pin Function

31 x2

32 RESETN

33 CEN

34 IP2

35 IACKN

36 IP5

37 IP4

38 VCC

39 VCC

40 A0

41 IP3

42 A1

43 IP1

44 A2

PQFP

44 34

1

11

33

23

12 22

SD00700

1

39

17

28

40

29

18

7

PLCC

6

SD00701

Pin Function

1NC

2A0

3 IP3

4A1

5 IP1

6A2

7A3

8 IP0

9 R/WN

10 DACKN

11 VCC

12 I/M

13 No Connection

14 OP1

15 OP3

Pin Function

16 OP5

17 OP7

18 D1

19 D3

20 D5

21 D7

22 VSS

23 NC

24 INTRN

25 D6

26 D4

27 D2

28 D0

29 OP6

30 OP4

Pin Function

31 OP2

32 OP0

33 TxDA

34 NC

35 RxDA

36 X1/CLK

37 X2

38 RESETN

39 CEN

40 IP2

41 IACKN

42 IP5

43 IP4

44 VCC

Note: Pins marked “No Connection” must NOT be connected.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 6

8

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

X1/CLK

X2

4

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR

ACR

CTL

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

MRA0, 1, 2

CRA

SRA

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

TxDA

RxDA

IP0-IP6

OP0-OP7

VCC

VSS

CONTROL

TIMING

INTERNAL DATABUS

IPCR

ACR

OPR

CTU

8

7

WATCH DOG TIMER

RECEIVE SHIFT

REGISTER

SD00702

GP

Figure 1. Block Diagram (80XXX mode)

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 7

8

D0–D7

R/WN

CEN

A0–A3

RESETN

INTRN

X1/CLK

X2

4

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSR

ACR

CTL

DATA CHANNEL

16 BYTE TRANSMIT

FIFO

TRANSMIT

SHIFT REGISTER

16 BYTE RECEIVE

FIFO

MRA0, 1, 2

CRA

SRA

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

TxDA

RxDA

IP0-IP5

OP0-OP7

VCC

VSS

CONTROL

TIMING

INTERNAL DATABUS

IPCR

ACR

OPR

CTU

8

6

WATCH DOG TIMER

RECEIVE SHIFT

REGISTER

SD00703

IVR

DACKN

IACKN

Figure 2. Block Diagram (68XXX mode)

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 8

PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL)

Symbol Pin

type Name and function

I/M IBus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.

D0–D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit.

CEN IChip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condi-

tion.

WRN IWrite Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The

transfer occurs on the rising edge of the signal.

RDN IRead Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the

data bus. The read cycle begins on the falling edge of RDN.

A0–A3 IAddress Inputs: Select the UART internal registers and ports for read/write operations.

RESET IReset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the

counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR point-

er to MR1. See Figure 4

INTRN OInterrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-

terrupting conditions are true. This pin requires a pull-up device.

X1/CLK ICrystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a

crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

X2 OCrystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin

to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

RxD IReceiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.

TxD OTransmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition

when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.

OP0 OOutput 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-

ceive or transmit.

OP1 OOutput 1: General-purpose output.

OP2 OOutput 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output.

OP3 OOutput 3: General-purpose output.

OP4 OOutput 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control

OP5 OOutput 5: General-purpose output

OP6 OOutput 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control

OP7 OOutput 7: General-purpose output.

IP0 IInput 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector.

IP1 IInput 1: General-purpose input. Has Change of State Dector.

IP2 I Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

IP3 IInput 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

IP4 IInput 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

IP5 IInput 5: General-purpose input

IP6 IInput 6: General-purpose input

VCC Pwr Power Supply: +3.3 or +5V supply input ±10%

GND Pwr Ground

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 9

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Symbol

ÁÁÁ

Á

ÁÁÁ

type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Name and function

ÁÁÁÁ

I/M

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ÁÁÁÁ

D0–D7

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the

CPU. D0 is the least significant bit.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

CEN

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on

D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ÁÁÁÁ

R/WN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.

ÁÁÁÁ

IACKN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in

response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

DACKN

ÁÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to

indicate proper transfer of data between the CPU and the UART.

ÁÁÁÁ

A0–A3

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Inputs: Select the UART internal registers and ports for read/write operations.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RESETN

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,

stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets

MR pointer to MR1. See Figure 4

ÁÁÁÁ

INTRN

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable

interrupting conditions are true. This pin requires a pullup.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

X1/CLK

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When

a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

ÁÁÁÁ

X2

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this

pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

ÁÁÁÁ

RxD

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

TxD

ÁÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition

when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

ÁÁÁÁ

OP0

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on

receive or transmit.

ÁÁÁÁ

OP1

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 1: General-purpose output.

ÁÁÁÁ

OP2

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.

ÁÁÁÁ

OP3

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 3: General purpose output.

ÁÁÁÁ

OP4

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control

ÁÁÁÁ

OP5

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 5: General-purpose output.

ÁÁÁÁ

OP6

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control

ÁÁÁÁ

OP7

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 7: General-purpose output.

ÁÁÁÁ

IP0

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.

ÁÁÁÁ

IP1

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 1: General purpose input. Has Change of State Dector.

ÁÁÁÁ

IP2

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

ÁÁÁÁ

IP3

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IP4

ÁÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

ÁÁÁÁ

IP5

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 5: General purpose input.

ÁÁÁÁ

VCC

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply: +3.3 or +5V supply input ±10%

ÁÁÁÁ

GND

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 10

ABSOLUTE MAXIMUM RATINGS1

Symbol Parameter Rating Unit

Tamb Operating ambient temperature range2Note 4 °C

Tstg Storage temperature range –65 to +150 °C

VCC Voltage from VCC to GND3–0.5 to +7.0 V

VSVoltage from any pin to GND3–0.5 to VCC +0.5 V

PDPackage power dissipation (PLCC44) 2.4 W

PDPackage power dissipation (PQFP44) 1.78 W

Derating factor above 25°C (PLCC44) 19 mW/°C

Derating factor above 25°C (PQFP44) 14 mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not

implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature and voltage range.

DC ELECTRICAL CHARACTERISTICS1, 2, 3

VCC = 5V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low voltage 0.8 V

VIH Input high voltage (except X1/CLK) 2.4 1.5 V

VIH Input high voltage (X1/CLK) 0.8*VCC 2.4 V

VOL Output low voltage IOL = 2.4mA 0.2 0.4 V

VOH Output high voltage (except OD outputs)4IOH = -400µAVCC -0.5 V

IIX1PD X1/CLK input current - power down VIN = 0 to VCC 0.5 0.05 0.5 µA

IILX1 X1/CLK input low current - operating VIN = 0 –130 0µA

IIHX1 X1/CLK input high current - operating VIN = VCC 0 130 µA

Input leakage current:

IIAll except input port pins VIN = 0 to VCC –0.5 0.05 +0.5 µA

Input port pins5VIN = 0 to VCC –8 0.05 +0.5 µA

IOZH Output off current high, 3-State data bus VIN = VCC 0.5 µA

IOZL Output off current low, 3-State data bus VIN = 0V –0.5 µA

IODL Open-drain output low current in off-state VIN = 0 –0.5 µA

IODH Open-drain output high current in off-state VIN = VCC 0.5 µA

Power supply current6

ICC Operating mode CMOS input levels 7 25 mA

Power down mode CMOS input levels ≤1 5 mA

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8V and

2.0V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS.

Input port pins at VCC source 0.0 µA.

6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2 V and VSS + 0.2 V.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 11

DC ELECTRICAL CHARACTERISTICS1, 2, 3

VCC = 3.3V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low voltage 0.65 0.2*VCC V

VIH Input high voltage 0.8*VCC 1.7 V

VOL Output low voltage IOL = 2.4mA 0.2 0.4 V

VOH Output high voltage (except OD outputs)4IOH = –400µAVCC–0.5 VCC–0.2 V

IIX1PD X1/CLK input current - power down VIN = 0 to VCC –0.5 0.05 +0.5 µA

IILX1 X1/CLK input low current - operating VIN = 0 –80 0µA

IIHX1 X1/CLK input high current - operating VIN = VCC 0 80 µA

Input leakage current:

IIAll except input port pins VIN = 0 to VCC –0.5 0.05 +0.5 µA

Input port pins5VIN = 0 to VCC –8 0.5 +0.5 µA

IOZH Output off current high, 3-State data bus VIN = VCC 0.5 µA

IOZL Output off current low, 3-State data bus VIN = 0V –0.5 µA

IODL Open-drain output low current in off-state VIN = 0 –0.5 µA

IODH Open-drain output high current in off-state VIN = VCC 0.5 µA

Power supply current6

ICC Operating mode CMOS input levels 5 mA

Power down mode CMOS input levels ≤1 5.0 mA

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

5. Input port pins have active pull-up transistors that will source a typical 2 µA from VCC when the input pins are at VSS.

Input port pins at VCC source 0.0 µA.

6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC –0.2 V and VSS+0.2 V.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 12

AC CHARACTERISTICS (5 VOLT) 1, 2, 3, 4

VCC = 5.0V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁ

Min

ÁÁÁ

Typ

ÁÁÁÁ

Max

ÁÁÁÁ

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing (See Figure 4)

ÁÁÁÁ

tRES

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset pulse width

ÁÁÁ

100

ÁÁÁ

18

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing5 (See Figure 5)

ÁÁÁÁ

t*AS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 setup time to RDN, WRN Low

ÁÁÁ

10

ÁÁÁ

6

ÁÁÁÁ

ns

ÁÁÁÁ

t*AH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 hold time from RDN, WRN low

ÁÁÁ

20

ÁÁÁ

12

ÁÁÁÁ

ns

ÁÁÁÁ

t*CS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time to RDN, WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*CH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN Hold time from RDN. WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*RW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRN, RDN pulse width (Low time)

ÁÁÁ

15

ÁÁÁ

8

ÁÁÁÁ

ns

ÁÁÁÁ

t*DD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)

ÁÁÁ

40

ÁÁÁÁ

55

ÁÁÁÁ

ns

ÁÁÁÁ

t*DA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN low to data bus active6

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus floating after RDN or CEN high

ÁÁÁ

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

t*DI

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN or CEN high to data bus invalid7

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus setup time before WRN or CEN high (write cycle)

ÁÁÁ

25

ÁÁÁ

17

ÁÁÁÁ

ns

ÁÁÁÁ

t*DH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data hold time after WRN high

ÁÁÁ

0

ÁÁÁ

–12

ÁÁÁÁ

ns

ÁÁÁÁ

t*RWD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between read and/or write cycles5, 7

ÁÁÁ

15

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port Timing5 (See Figure 9)

ÁÁÁÁ

t*PS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in setup time before RDN low (Read IP ports cycle)

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in hold time after RDN high

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OP port valid after WRN or CEN high (OPR write cycle)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing (See Figure 10)

ÁÁÁÁ

t*IR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

INTRN (or OP3–OP7 when used as interrupts) negated from:

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read RxFIFO (RxRDY/FFULL interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write TxFIFO (TxRDY interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Command (delta break change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stop C/T command (Counter/timer interrupt

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read IPCR (delta input port change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write IMR (Clear of change interrupt mask bit(s))

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock Timing (See Figure 11)

ÁÁÁÁ

t*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK high or low time

ÁÁÁ

30

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

f*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK frequency8 (for higher speeds contact factory)

ÁÁÁ

0.1

ÁÁÁ

3.686

ÁÁÁÁ

8.0

ÁÁÁÁ

MHz

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) high or low time (C/T external clock input)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) frequency8 (for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

8.0

ÁÁÁÁ

MHz

ÁÁÁÁ

t*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (16X)(for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (1x)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁ

t*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC High or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16X) (for higher speeds contact factory)

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (1X)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing, external clock (See Figure 12)

ÁÁÁÁ

t*TXD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low (TxC input pin)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

t*TCS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output delay from TxC output pin low to TxD data output

ÁÁÁ

6

ÁÁÁÁ

30

ÁÁÁÁ

ns

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 13

ÁÁÁÁ

Unit

ÁÁÁÁ

Max

ÁÁÁ

Typ

ÁÁÁ

Min

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing, external clock (See Figure 13)

ÁÁÁÁ

t*RXS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high

ÁÁÁ

50

ÁÁÁ

40

ÁÁÁÁ

ns

ÁÁÁÁ

t*RXH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high

ÁÁÁ

50

ÁÁÁ

40

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

68000 or Motorola bus timing (See Figures 6, 7, 8)10

ÁÁÁÁ

tDCR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (read cycle) from X1 High10

ÁÁÁ

15

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

tDCW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (write cycle) from X1 High

ÁÁÁ

15

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

tDAT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN High impedance from CEN or IACKN High

ÁÁÁ

8

ÁÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

tCSC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN or IACKN setup time to X1 High for minimum DACKN cycle

ÁÁÁ

10

ÁÁÁ

8

ÁÁÁÁ

ns

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

4. Typical values are the average values at +25°C and 5 V.

5. T iming is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for tRWD to guarantee that any status register changes are valid.

8. Minimum frequencies are not tested but are guaranteed by design.

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

10.Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the

bus cycle. DACKN low or CEN high completes the write cycle.

0 20 40 60 80 100 120 140 160 180 200 220 240

60

55

50

45

40

35

30

25

20

15

10

5

0

VCC = 3.3V @ +25°C

5.0V @ +25°C

pF

Tdd

(ns)

125 pF30 pF 230 pF

SD00684

12 pF 100 pF

NOTES:

Bus cycle times:

(80XXX mode): tDD + tRWD = 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals

(68XXX mode) = tCSC + tDAT + 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals

Figure 3. Port Timing vs. Capacitive Loading at typical conditions

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 14

AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3, 4

VCC = 3.3V ± 10%, Tamb = –40°C to +85°C, unless otherwise specified.

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁ

Min

ÁÁÁ

Typ

ÁÁÁÁ

Max

ÁÁÁÁ

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing (See Figure 4)

ÁÁÁÁ

tRES

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset pulse width

ÁÁÁ

100

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing5 (See Figure 5)

ÁÁÁÁ

t*AS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 setup time to RDN, WRN Low

ÁÁÁ

10

ÁÁÁ

6

ÁÁÁÁ

ns

ÁÁÁÁ

t*AH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A3 hold time from RDN, WRN low

ÁÁÁ

25

ÁÁÁ

16

ÁÁÁÁ

ns

ÁÁÁÁ

t*CS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time to RDN, WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*CH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN Hold time from RDN. WRN low

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*RW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRN, RDN pulse width (Low time)

ÁÁÁ

20

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

t*DD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)

ÁÁÁ

46

ÁÁÁÁ

75

ÁÁÁÁ

ns

ÁÁÁÁ

t*DA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN low to data bus active6

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DF

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus floating after RDN or CEN high

ÁÁÁ

15

ÁÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

t*DI

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RDN or CEN high to data bus invalid7

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t*DS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data bus setup time before WRN or CEN high (write cycle)

ÁÁÁ

25

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

t*DH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data hold time after WRN high

ÁÁÁ

0

ÁÁÁ

–15

ÁÁÁÁ

ns

ÁÁÁÁ

t*RWD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between read and/or write cycles5, 7

ÁÁÁ

20

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port Timing5 (See Figure 9)

ÁÁÁÁ

t*PS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in setup time before RDN low (Read IP ports cycle)

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port in hold time after RDN high

ÁÁÁ

0

ÁÁÁ

–20

ÁÁÁÁ

ns

ÁÁÁÁ

t*PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

OP port valid after WRN or CEN high (OPR write cycle)

ÁÁÁ

50

ÁÁÁÁ

70

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing (See Figure 10)

ÁÁÁÁ

t*IR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

INTRN (or OP3–OP7 when used as interrupts) negated from:

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read RxFIFO (RxRDY/FFULL interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write TxFIFO (TxRDY interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Command (delta break change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Stop C/T command (Counter/timer interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read IPCR (delta input port change interrupt)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write IMR (Clear of change interrupt mask bit(s))

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock Timing (See Figure 11)

ÁÁÁÁ

t*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK high or low time

ÁÁÁ

30

ÁÁÁ

25

ÁÁÁÁ

ns

ÁÁÁÁ

f*CLK

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK frequency8 (for higher speeds contact factory)

ÁÁÁ

0.1

ÁÁÁ

3.686

ÁÁÁÁ

8

ÁÁÁÁ

MHz

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) high or low time (C/T external clock input)

ÁÁÁ

30

ÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

f*CTC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T Clk (IP2) frequency8 (for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

8

ÁÁÁÁ

MHz

ÁÁÁÁ

t*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time (16X)

ÁÁÁ

30

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

f*RX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (16X) (for higher speeds contact factory)

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC Frequency (1x)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁ

t*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC High or low time (16X)

ÁÁÁ

30

ÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

f*TX

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16X) (for higher speeds contact factory)

ÁÁÁ

ÁÁÁÁ

16

ÁÁÁÁ

MHz

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (1X)8, 9

ÁÁÁ

0

ÁÁÁ

ÁÁÁÁ

1

ÁÁÁÁ

MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing, external clock (See Figure 12)

ÁÁÁÁ

t*TXD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low (TxC input pin)

ÁÁÁ

40

ÁÁÁÁ

60

ÁÁÁÁ

ns

ÁÁÁÁ

t*TCS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output delay from TxC output pin low to TxD data output

ÁÁÁ

8

ÁÁÁÁ

30

ÁÁÁÁ

ns

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 15

ÁÁÁÁ

Unit

ÁÁÁÁ

Max

ÁÁÁ

Typ

ÁÁÁ

Min

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Parameter

ÁÁÁÁ

Symbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing, external clock (See Figure 13)

ÁÁÁÁ

t*RXS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high

ÁÁÁ

50

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁ

t*RXH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high

ÁÁÁ

50

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

68000 or Motorola bus timing (See Figures 6, 7, 8)10

ÁÁÁÁ

tDCR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (read cycle) from X1 High10

ÁÁÁ

18

ÁÁÁÁ

25

ÁÁÁÁ

ns

ÁÁÁÁ

tDCW

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Low (write cycle) from X1 High

ÁÁÁ

18

ÁÁÁÁ

25

ÁÁÁÁ

ns

ÁÁÁÁ

tDAT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN High impedance from CEN or IACKN High

ÁÁÁ

10

ÁÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁ

tCSC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN or IACKN setup time to X1 High for minimum DACKN cycle

ÁÁÁ

15

ÁÁÁ

10

ÁÁÁÁ

ns

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*VCC. All time measurements are referenced at input voltages of 0.8 V and

2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.

3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

4. Typical values are the average values at +25°C and 3.3 V.

5. T iming is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. Guaranteed by characterization of sample units.

7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for tRWD to guarantee that any status register changes are valid.

8. Minimum frequencies are not tested but are guaranteed by design.

9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.

10.Minimum DACKN time is tDCR = tDSC + tDCR + two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used

while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be

written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the

bus cycle. DACKN low or CEN high completes the write cycle.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 16

Block Diagram

The SC28L91 UART consists of the following seven major sections:

data bus buffer, operation control, interrupt control, timing, Rx and

Tx FIFO Buffers, input port and output port control. Refer to the

Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the UART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all currently

active interrupting conditions. Outputs OP3–OP7 can be

programmed to provide discrete interrupt outputs for the transmitter,

receiver, and counter/timer. Programming the OP3 to OP7 pins as

interrupts causes their output buffers to change to an open drain

active low configuration. The OP pins may be used for DMA and

modem control as well. (See output port notes).

FIFO Configuration

Each receiver and transmitter has a 16 byte FIFO. These FIFOs

may be configured to operate at a fill capacity of either 8 or 16 bytes.

This feature may be used if it is desired to operate the 28L91 in

close compliance to 26C92 software. The 8-byte/16-byte mode is

controlled by the MR0[3] bit. A 0 value for this bit sets the 8-bit mode

( the default); a 1 sets the 16-byte mode.

The FIFO fill interrupt level automatically follow the programming of

the MR0[3] bit. See Tables 3 and 4.

68XXX mode

When the I/M pin is connected to VSS (ground), the operation of the

SC28L91 switches to the bus interface compatible with the Motorola

bus interfaces. Several of the pins change their function as follows:

•IP6 becomes IACKN input

•RDN becomes DACKN

•WRN becomes R/WN

The interrupt vector is enabled and the interrupt vector will be placed

on the data bus when IACKN is asserted low. The interrupt vector

register is located at address 0xC. The contents of this register are

set to 0x0F on the application of RESETN.

The generation of DACKN uses two positive edges of the X1 clock

as the DACKN delay from the falling edge of CEN. If the CEN is

withdrawn before two edges of the X1 clock occur, the

generation of DACKN is terminated. Systems not strictly requiring

DACKN may use the 68XXX mode with the bus timing of the 80XXX

mode greatly decreasing the bus cycle time.

TIMING CIRCUITS

Crystal Clock

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer , and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the Baud

Rate Generator (BRG), the counter/timer, and other internal circuits.

A clock signal within the limits specified in the specifications section

of this data sheet must always be supplied to the UART. If an

external clock is used instead of a crystal, X1 should be driven using

a configuration similar to the one in Figure 11. X2 should be open or

driving a nominal gate load. Nominal crystal rate is 3.6864 MHz.

Rates up to 8 MHz may be used.

BRG

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 28 commonly used data

communications baud rates ranging from 50 to 38.4 K baud.

Programming bit 0 of MR0 to a “1” gives additional baud rates of

57.6 kB, 115.2 kB and 230.4 kB (500 kHz with X1 at 8.0 MHz).

These will be in the 16X mode. A 3.6864 MHz crystal or external

clock must be used to get the standard baud rates. The clock

outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

the receiver and transmitter, of any of these baud rates or external

timing signal.

Counter/Timer

The counter timer is a 16-bit programmable divider that operates in

one of three modes: counter, timer, and time out. In the timer mode it

generates a square wave. In the counter mode it generates a time

delay. In the time out mode it monitors the time between received

characters. The C/T uses the numbers loaded into the

Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper

Register (CTUR) as its divisor.

The counter/timer clock source and mode of operation (counter or

timer) is selected by the Auxiliary Control Register bits 6 to 4

(ACR[6:4]). The output of the counter/timer may be used for a baud

rate and/or may be output to the OP pins for some external function

that may be totally unrelated to data transmission. The counter/timer

also sets the counter/timer ready bit in the Interrupt Status Register

(ISR) when its output transitions from 1 to 0. A register read address

(see Table 1) is reserved to issue a start counter/timer command

and a second register read address is reserved to issue a stop

command. The value of D[7:0] is ignored. The START command

always loads the contents of CTUR, CTLR to the counting registers.

The STOP command always resets the ISR[3] bit in the interrupt

status register.

Timer Mode

In the timer mode a symmetrical square wave is generated whose

half period is equal in time to division of the selected counter/timer

clock frequency by the 16-bit number loaded in the CTLR CTUR.

Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the

CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be

set each time the counter/timer transitions from 1 to 0. (High to low)

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 17

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command.

NOTE: Reading of the CTU and CTL registers in the timer mode is

not meaningful. When the C/T is used to generate a baud rate and

the C/T is selected through the CSR then the receiver and/or

transmitter will be operating in the 16x mode. Calculation for the

number ‘n’ to program the counter timer upper and lower registers is

shown below.

N+cńtclockrate

2 * 16 * Baud rate

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect. Reading the

C/T in the counter mode outputs the present state of the C/T. If the

C/T is not stopped, a read of the C/T may result in changing data on

the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The processor

would be interrupted any time the data stream had stopped for more

than one character time. NOTE: This is very similar to the watch dog

timer of MR0. The difference is in the programmability of the delay

timer and that this indicates that the data stream has stopped. The

watchdog timer is more of an indicator that data is in the FIFO is not

enough to cause an interrupt. The watchdog is restarted by either a

receiver load to the RxFIFO or a system read from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘0xAn’ to CR will invoke the timeout

mode for that channel. Writing a ‘Cx’ to CR will disable the timeout

mode. The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

Bit, ISR[3], will be set. If IMR [3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR [3], and the interrupt. Invoking the ‘Set T imeout Mode On’

command, CRx = 0xAn, will also clear the counter ready bit and stop

the counter until the next character is received. The counter timer is

controlled with six commands: Start/Stop C/T, Read/Write

Counter/Timer lower register and Read/Write Counter/Timer upper

register. These commands have slight differences depending on the

mode of operation. Please see the detail of the commands under the

CTLR CTUR Register descriptions.

Time Out Mode Caution

When operating in the special time out mode it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Communications

The communications channel of the SC28L91 comprises a

full-duplex asynchronous receiver/transmitter (UART). The operating

frequency for the receiver and transmitter can be selected

independently from the baud rate generator, the counter/timer, or

from an external input. The transmitter accepts parallel data from the

CPU, converts it to a serial bit stream, inserts the appropriate start,

stop, and optional parity bits and outputs a composite serial stream

of data on the TxD output pin. The receiver accepts serial data on

the RxD pin, converts this serial input to parallel format, checks for

start bit, stop bit, parity bit (if any), or break condition and sends an

assembled character to the CPU via the receive FIFO. Three status

bits (Break Received, Framing and Parity Errors) are also FIFOed

with the data character.

Input Port

The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be

read by the CPU by performing a read operation at address 0xD. A

High input results in a logic 1 while a Low input results in a logic 0.

D7 will always read as a logic 1. The pins of this port can also serve

as auxiliary inputs to certain portions of the UART logic, modem and

DMA.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs, lasting longer than 25–50 ∝s, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

The input port change of state detection circuitry uses a 38.4 kHz

sampling clock derived from one of the baud rate generator taps.

This results in a sampling period of slightly more than 25 ∝s (this

assumes that the clock input is 3.6864 MHz). The detection circuitry,

in order to guarantee that a true change in level has occurred,

requires two successive samples at the new logic level be observed.

As a consequence, the minimum duration of the signal change is

25 ∝s if the transition occurs “coincident with the first sample pulse”.

The 50 ∝s time refers to the situation in which the change-of-state is

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 18

“just missed” and the first change-of-state is not detected until 25 ∝s

later.

Output Port

The output ports are controlled from six places: the OPCR, OPR,

MR, Command, SOPR and ROPR registers. The OPCR register

controls the source of the data for the output ports OP2 through

OP7. The data source for output ports OP0 and OP1 is controlled by

the MR and CR registers. When the OPR is the source of the data

for the output ports, the data at the ports is inverted from that in the

OPR register. The content of the OPR register is controlled by the

“Set Output Port Bits Command” and the “Reset Output Bits

Command”. These commands are at E and F, respectively. When

these commands are used, action takes place only at the bit

locations where ones exist. For example, a one in bit location 5 of

the data word used with the “Set Output Port bits” command will

result in OPR[5] being set to one. The OP5 would then be set to

zero (VSS). Similarly, a one in bit position 5 of the data word

associated with the “Reset Output Ports Bits” command would set

OPR[5] to zero and, hence, the pin OP5 to a one (VDD).

These pins along with the IP pins and their change of state detectors

are often used for modem and DMA control.

OPERATION

Transmitter

The SC28L91 is conditioned to transmit data when the transmitter is

enabled through the command register. The SC28L91 indicates to

the CPU that it is ready to accept a character by setting the TxRDY

bit in the status register. This condition can be programmed to

generate an interrupt request at OP6 or OP7 and INTRN. When the

transmitter is initially enabled the TxRDY and TxEMPT bits will be

set in the status register. When a character is loaded to the transmit

FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)

the transmit FIFO is empty and the transmit shift register has

finished transmitting the stop bit of the last character written to the

transmit FIFO, or 2) the transmitter is disabled and then re-enabled.

The TxRDY bit is set whenever the transmitter is enabled and the

TxFIFO is not full. Data is transferred from the holding register to

transmit shift register when it is idle or has completed transmission

of the previous character. Characters cannot be loaded into the

TxFIFO while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial

bit stream on the TxD output pin. It automatically sends a start bit

followed by the programmed number of data bits, an optional parity

bit, and the programmed number of stop bits. The least significant

bit is sent first. Following the transmission of the stop bits, if a new

character is not available in the TxFIFO, the TxD output remains

High and the TxEMT bit in the Status Register (SR) will be set to 1.

T ransmission resumes and the TxEMT bit is cleared when the CPU

loads a new character into the TxFIFO.

If the transmitter is disabled it continues operating until the character

currently being transmitted and any characters in the TxFIFO,

including parity and stop bits, have been transmitted. New data

cannot be loaded to the TxFIFO when the transmitter is disabled.

When the transmitter is reset it stops sending data immediately.

The transmitter can be forced to send a break (a continuous low

condition) by issuing a START BREAK command via the CR

register. The break is terminated by a STOP BREAK command or a

transmitter reset.

If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1

must be Low in order for the character to be transmitted. The

transmitter will check the state of the CTS input at the beginning of

the character transmitted. If it is found to be High, the transmitter will

delay the transmission of any following characters until the CTS has

returned to the low state. CTS going high during the serialization of

a character will not affect that character.

The transmitter can also control the RTSN outputs, OP0 or OP1 via

MR2[5]. When this mode of operation is set, the meaning of the OP0

or OP1 signals will usually be ‘end of message’. See description of

the MR2[5] bit for more detail. This feature may be used to

automatically “turn around” a transceiver in simplex systems.

Receiver

The SC28L91 is conditioned to receive data when enabled through

the command register. The receiver looks for a High-to-Low

(mark-to-space) transition of the start bit on the RxD input pin. If a

transition is detected, the state of the RxD pin is sampled the 16X

clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of

the bit time clock (1X clock mode). If RxD is sampled high, the start

bit is invalid and the search for a valid start bit begins again. If RxD

is still Low, a valid start bit is assumed and the receiver continues to

sample the input at one-bit time intervals at the theoretical center of

the bit. When the proper number of data bits and parity bit (if any)

have been assembled, and one/half stop bit has been detected the

byte is loaded to the RxFIFO. The least significant bit is received

first. The data is then transferred to the Receive FIFO and the

RxRDY bit in the SR is set to a 1. This condition can be

programmed to generate an interrupt at OP4 or OP5 and INTRN. If

the character length is less than 8 bits, the most significant unused

bits in the RxFIFO are set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However if a framing error occurs (a non-zero

character was received without a stop bit) and then RxD remains

low one/half bit time the receiver operates as if a new start bit was

detected. It then continues to assemble the next character.

The parity error, framing error, and overrun error (if any) are strobed

into the SR from the next byte to be read from the Rx FIFO.

If a break condition is detected (RxD is Low for the entire character

including the stop bit), a character consisting of all zeros will be

loaded into the RxFIFO and the received break bit in the SR is set to

1. The RxD input must return to high for two (2) clock edges of the

X1 crystal clock for the receiver to recognize the end of the break

condition and begin the search for a start bit.

This will usually require a high time of one X1 clock period or 3 X1

edges since the clock of the controller is not synchronous to the X1

clock.

Transmitter Reset and Disable

Note the difference between transmitter disable and reset. A

transmitter reset stops transmitter action immediately, clears the

transmitter FIFO and returns the idle state. A transmitter disable

withdraws the transmitter interrupts but allows the transmitter to

continue operation until all bytes in its FIFO and shift register have

been transmitted including the final stop bits. It then returns to its

idle state.

Receiver FIFO

The RxFIFO consists of a First-In-First-Out (FIFO) stack with a

capacity of 8 or 16 characters. Data is loaded from the receive shift

register into the topmost empty position of the FIFO. The RxRDY bit

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 19

in the status register is set whenever one or more characters are

available to be read, and a FFULL status bit is set if all 8 or 16 stack

positions are filled with data. Either of these bits can be selected to

cause an interrupt. A read of the RxFIFO outputs the data at the top

of the FIFO. After the read cycle, the data FIFO and its associated

status bits (see below) are ‘popped’ thus emptying a FIFO position

for new data.

A disabled receiver with data in its FIFO may generate an interrupt

(see “Receiver Status Bits”, below). Its status bits remain active and

its watchdog, if enabled, will continue to operate.

Receiver Status Bits

In addition to the data word, three status bits (parity error, framing

error, and received break) are also appended to the data character

in the FIFO. The overrun error, MR1[5], and the change of break

(ISR[2]) are not FIFOed.

The status of the Rx FIFO may be provided in two ways, as

programmed by the error mode control bit in the mode register

(MR1[5]). In the ‘character’ mode, status is provided on a

character-by-character basis; the status applies only to the

character at the top of the FIFO. In the ‘block’ mode, the status

provided in the SR for these three bits is the logical-OR of the status

for all characters coming to the top of the FIFO since the last ‘reset

error’ from the command register was issued. In either mode

reading the SR does not affect the FIFO. The FIFO is ‘popped’ only

when the RxFIFO is read. Therefore the status register should be

read prior to reading the FIFO.

If the FIFO is full when a new character is received, that character is

held in the receive shift register until a FIFO position is available. If

an additional character is received while this state exits, the

contents of the FIFO are not affected; the character previously in the

shift register is lost and the overrun error status bit (SR[4]) will be

set-upon receipt of the start bit of the new (overrunning) character.

The receiver can control the deactivation of RTS. If programmed to

operate in this mode, the RTSN output will be negated when a valid

start bit was received and the FIFO is full. When a FIFO position

becomes available, the RTSN output will be re-asserted (set low)

automatically. This feature can be used to prevent an overrun, in the

receiver, by connecting the RTSN output to the CTSN input of the

transmitting device.

If the receiver is disabled, the FIFO characters can be read.

However, no additional characters can be received until the receiver

is enabled again. If the receiver is reset, the FIFO and all of the

receiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Reset and Disable

Receiver disable stops the receiver immediately—data being

assembled in the receiver shift register is lost. Data and status in the

FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected.

A receiver reset will discard the present shift register date, reset the

receiver ready bit (RxRDY), clear the status of the byte at the top of

the FIFO and re-align the FIFO read/write pointers.

Watchdog

A ‘watchdog timer’ is associated with the receiver . Its interrupt is

enabled by MR0[7]. The purpose of this timer is to alert the control

processor that characters are in the RxFIFO which have not been

read. This situation may occur at the end of a transmission when the

last few characters received are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the receiver shift register to the

RxFIFO or a read of the RxFIFO is executed.

Receiver Time-out Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its 16-bit

programmability allows much greater precision of time out intervals.

The time-out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

register to the RxFIFO, the counter is restarted. If a new character is

not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new data

during the programmed time interval, the counter ready bit will get

set, and an interrupt can be generated.

The time-out mode is enabled by writing the appropriate command

to the command register. Writing an 0xAn to CR will invoke the

time-out mode for that channel. Writing a ‘Cx’ to CR will disable the

time-out mode. The time-out mode should only be used by one

channel at once, since it uses the C/T. CTU and CTL must be

loaded with a value greater than the normal receive character

period. The time-out mode disables the regular START/STOP

Counter commands and puts the C/T into counter mode under the

control of the received data stream. Each time a received character

is transferred from the shift register to the RxFIFO, the C/T is

stopped after 1 C/T clock, reloaded with the value in CTU and CTL

and then restarted on the next C/T clock. If the C/T is allowed to end

the count before a new character has been received, the counter

ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an

interrupt. Receiving a character after the C/T has timed out will clear

the counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set

T ime-out Mode On’ command, CRx = ‘Ax’, will also clear the counter

ready bit and stop the counter until the next character is received.

Watchdog and Time Out Mode Differences

The watchdog timer is restarted each time a character is read from

or written to the Rx FIFO. It is an indicator that data is in the FIFO

that has not been read. If the Rx FIFO is empty no action occurs. In

the time out mode the C/T is stopped and restarted each time a

character is written to the Rx FIFO. From this point of view the time

out of the C/T is an indication that the data stream has stopped.

After the time out mode is invoked the timer will not start until the

first character is written to the Rx FIFO.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 20

latency is longer than the pause in the data stream.) In this case,

when a new character has been received, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

Multi-drop Mode (9-bit or Wake-Up)

The UART is equipped with a wake up mode for multi-drop

applications. This mode is selected by programming bits MR1[4:3]or

to ‘11’. In this mode of operation, a ‘master’ station transmits an

address character followed by data characters for the addressed

‘slave’ station. The slave station(s) whose receiver(s) that are

normally disabled, examine the received data stream and ‘wakeup’

the CPU (by setting RxRDY) only upon receipt of an address

character. The CPU compares the received address to its station

address and enables the receiver if it wishes to receive the

subsequent data characters. Upon receipt of another address

character, the CPU may disable the receiver to initiate the process

again.

A transmitted character consists of a start bit, the programmed

number of data bits, and Address/Data (A/D) bit, and the

programmed number of stop bits. The polarity of the transmitted A/D

bit is selected by the CPU by programming bit MR1[2]. MR1[2]= 0

transmits a zero in the A/D bit position, which identifies the

corresponding data bits as data. MR1[2] = 1 transmits a one in the

A/D bit position, which identifies the corresponding data bits as an

address. The CPU should program the mode register prior to

loading the corresponding data bits into the TxFIFO.

MR1[2] = 1 transmits a one in the A/D bit position, which identifies

the corresponding data bits as an address. The CPU should

program the mode register prior to loading the corresponding data

bits into the TxFIFO.

In this mode, the receiver continuously looks at the received data

stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one (address tag), but discards the received

character if the received A/D bit is a zero (data tag). If enabled, all

received characters are transferred to the CPU via the RxFIFO. In

either case, the data bits are loaded into the data FIFO while the

A/D bit is loaded into the status FIFO position normally used for

parity error (SR[5] ). Framing error, overrun error, and break detect

operate normally whether or not the receiver is enabled.

PROGRAMMING

The operation of the UART is programmed by writing control words

into the appropriate registers. Operational feedback is provided via

status registers which can be read by the CPU. The addressing of

the registers is described in Table 1.

The contents of certain control registers are initialized to zero on

RESET. Care should be exercised if the contents of a register are

changed during operation, since certain changes may cause

operational problems.

For example, changing the number of bits per character while the

transmitter is active may cause the transmission of an incorrect

character. In general, the contents of the MR, the CSR, and the

OPCR should only be changed while the receiver(s) and

transmitter(s) are not enabled, and certain changes to the ACR

should only be made while the C/T is stopped.

The channel has 3 mode registers (MR0, 1, 2) which control the

basic configuration of the channel. Access to these registers is

controlled by independent MR address pointers. These pointers are

set to 0 or 1 by MR control commands in the command register

“Miscellaneous Commands”. Each time the MR registers are

accessed the MR pointer increments, stopping at MR2. It remains

pointing to MR2 until set to 0 or 1 via the miscellaneous commands

of the command register. The pointer is set to 1 on reset for

compatibility with previous Philips Semiconductors UART software.

Refer to Table 2 for register bit descriptions. The reserved registers

at addresses 0x02 and 0x0A should never be read during normal

operation since they are reserved for internal diagnostics.

Table 1. SC28L91 register addressing

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Address Bits

A[3:0]

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

READ (RDN = 0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

WRITE (WRN = 0)

0000Mode Register(MR0, MR1, MR2) Mode Register(MR0, MR1, MR2)

0001Status Register(SR) Clock Select Register(CSR)

0 0 1 0 Reserved Command Register(CR)

0011Rx Holding Register(RxFIFO) Tx Holding Register(RxFIFO)

0100Input Port Change Register (IPCR) Aux. Control Register (ACR)

0101Interrupt Status Register (ISR) Interrupt Mask Register (IMR)

0110Counter/Timer Upper (CTU) C/T Upper Preset Register (CTPU)

0111Counter/Timer Lower (CTL) C/T Lower Preset Register (CTPL)

1100Interrupt vector (68K mode), Misc. register in Intel mode Interrupt vector (68K mode), Misc. register in Intel mode

1100IVR Motorola mode, Misc. register (Intel mode) IVR Motorola mode, Misc. register (Intel mode)

1101Input Port (IPR) Output Port Configuration Register (OPCR)

1110Start Counter Command Set Output Port Bits Command (SOPR)

1111Stop Counter Command Reset output Port Bits Command (ROPR)

NOTE:

1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 21

Register Acronyms and Read / Write Capability

(R/W = Read/Write, R = Read only, W = Write only)

Mode Register MRn R/W

Status Register SR R

Clock Select CSR W

Command Register CR W

Receiver FIFO RxFIFO R

T ransmitter FIFO RxFIFO W

Input Port Change Register IPCR R

Auxiliary Control Register ACR W

Interrupt Status Register ISR R

Interrupt Mask Register IMR W

Counter T imer Upper Value CTU R

Counter T imer Lower Value CTL R

Counter T imer Preset Upper CTPU W

Counter T imer Preset Lower CTPL W

Input Port Register IPR R

Output Configuration Register OPCR W

Set Output Port Bits W

Reset Output Port Bits W

Interrupt vector or GP register IVR/GP R/W

Table 2. Condensed Register bit formats

Name Adr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MR0 0WATCH

DOG RxINT BIT 2 TxINT [1:0] FIFO SIZE BAUD RATE

EXTENDED

II

TEST 2 BAUD RATE

EXTENDED 1

MR1 0RxRTS

Control RxINT BIT 1 Error Mode Parity Mode Parity Type Bits per Character

MR2 0Channel Mode TxRTS Con-

trol CTSN Enable

Tx Stop Bit Length

CSR 1Receiver Clock, Select Code T ransmitter Clock select code,

SR 1Received

Break Framing Er-

ror Parity Error Overrun Error TxEMT TxRDY RxFULL RxRDY

CR 2Channel Command codes Disable Tx Enable Tx Disable Rx Enable Rx

RxFIFO 3Read 8 bits from Rx FIFO

TxFIFO 3Write 8 bits to Tx FIFO

IPCR 4Delta IP3 Delta IP2 Delta IP1 Delta IP0 State of IP3 State of IP2 State of IP1 State of IP0

ACR 4Baud Group Counter Timer mode and clock select Enable IP3 Enable IP2 Enable IP1 Enable IP0

ISR 5Change In-

put Port Ignore in ISR Reads Counter

Ready Change

Break RxRDY TxRDY

IMR 5Change In-

put Port Set to 0 Set to 0 Set to 0 Counter

Ready Change

Break RxRDY TxRDY

CTU 6Read 8 MSb of the BRG T imer divisor.

CTPU 6Write 8 MSb of the BRG Timer divisor.

CTL 7Read 8 LSb of the BRG T imer divisor.

CTPL 7Write 8 LSb of the BRG Timer divisor.

IPR DState of IP State of IP 6 State of IP 5 State of IP 4 State of IP 3 State of IP 2 State of IP1 State of IP 0

OPCR DConfigure

OP7 Configure

OP6 Configure

OP5 Configure

OP4 Configure OP3 Configure OP2

Strt C/T ERead Address E to start Counter T imer

SOPR ESet OP 7 Set OP 6 Set OP 5 Set OP 4 Set OP 3 Set OP 2 Set OP 1 Set OP 0

Stp C/T FRead Address F to stop counter T imer

ROPR FReset OP 7 Reset OP 6 Reset OP 5 Reset OP 4 Reset OP 3 Reset OP 2 Reset OP 1 Reset OP 0

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 22

REGISTER DESCRIPTIONS MODE REGISTERS

MR0 – Mode Register 0

Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.

ÁÁÁÁÁ

Addr

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁ

BIT 6

ÁÁÁÁÁ

BITS 5:4

ÁÁÁÁÁÁ

BIT 3

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁÁÁ

BIT 0

ÁÁÁÁÁ

MR0

ÁÁÁÁÁ

Rx

WATCHDOG

ÁÁÁÁÁ

RxINT BIT 2

ÁÁÁÁÁ

TxINT (1:0)

ÁÁÁÁÁÁ

FIFO SIZE

ÁÁÁÁÁ

BAUD RATE

EXTENDED II

ÁÁÁÁ

TEST 2

ÁÁÁÁÁÁ

BAUD RATE

EXTENDED 1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0x00

0x08

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = Disable

1 = Enable

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

See Tables in

MR0 descrip-

tion

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

See Table 4

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 = 8 byte FIFO

1 = 16 byte FIFO

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = Normal

1 = Extend II

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Set to 0

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 = Normal

1 = Extend

MR0[7]—W atchdog Control

This bit controls the receiver watchdog timer. 0 = disable,

1 = enable. When enabled, the watch dog timer will generate a

receiver interrupt if the receiver FIFO has not been accessed within

64 bit times of the receiver 1X clock. This is used to alert the control

processor that data is in the RxFIFO that has not been read. This

situation may occur when the byte count of the last part of a

message is not large enough to generate an interrupt.

MR0[6]—Rx Interrupt bit 2

Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1

sets the fill level of the FIFO that generates the receiver interrupt.

MR0[6], MR1[6] Rx Interrupt bits

Note that this control is split between MR0 and MR1. This is for

backward compatibility to legacy software of the SC2692 and

SCN2681 dual UART devices.

Table 3. Receiver FIFO

Interrupt fill level (MR0(3) = 0 (8 bytes)

ÁÁÁÁÁÁÁ

MR0[6] MR1[6]

ÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Condition

ÁÁÁÁÁÁÁ

00

ÁÁÁÁÁÁÁÁÁÁÁ

1 or more bytes in FIFO (Rx RDY)

ÁÁÁÁÁÁÁ

01

ÁÁÁÁÁÁÁÁÁÁÁ

6 or more bytes in FIFO

ÁÁÁÁÁÁÁ

10

ÁÁÁÁÁÁÁÁÁÁÁ

4 or more bytes in FIFO

ÁÁÁÁÁÁÁ

11

ÁÁÁÁÁÁÁÁÁÁÁ

8 bytes in FIFO (Rx FULL)

Table 3a. Receiver FIFO

Interrupt fill level(MR0(3)=1 (16 bytes)

ÁÁÁÁÁÁÁ

MR0[6] MR1[6]

ÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Condition

ÁÁÁÁÁÁÁ

00

ÁÁÁÁÁÁÁÁÁÁÁ

1 or more bytes in FIFO (Rx RDY)

ÁÁÁÁÁÁÁ

01

ÁÁÁÁÁÁÁÁÁÁÁ

8 or more bytes in FIFO

ÁÁÁÁÁÁÁ

10

ÁÁÁÁÁÁÁÁÁÁÁ

12 or more bytes in FIFO

ÁÁÁÁÁÁÁ

11

ÁÁÁÁÁÁÁÁÁÁÁ

16 bytes in FIFO (Rx FULL)

For the receiver these bits control the number of FIFO positions

filled when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

MR0[5:4]—Tx interrupt fill level.

Table 4. Transmitter FIFO

Interrupt fill level MR0(3) = 0 (8 bytes)

ÁÁÁÁÁ

MR0[5:4]

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Condition

ÁÁÁÁÁ

00

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 bytes empty (Tx EMPTY)

ÁÁÁÁÁ

01

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

4 or more bytes empty

ÁÁÁÁÁ

10

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

6 or more bytes empty

ÁÁÁÁÁ

11

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

1 or more bytes empty (Tx RDY)

Table 4a. Transmitter FIFO

Interrupt fill level MR0(3) = 1 (16 bytes)

ÁÁÁÁÁ

MR0[5:4]

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Condition

ÁÁÁÁÁ

00

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

16 bytes empty (Tx EMPTY)

ÁÁÁÁÁ

01

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 or more bytes empty

ÁÁÁÁÁ

10

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

12 or more bytes empty

ÁÁÁÁÁ

11

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

1 or more bytes empty (Tx RDY)

For the transmitter these bits control the number of FIFO positions

empty when the transmitter will attempt to interrupt. After the reset

the transmit FIFO has 8 bytes empty. It will then attempt to interrupt

as soon as the transmitter is enabled. The default setting of the MR0

bits [5:4] condition the transmitter to attempt to interrupt only when it

is completely empty. As soon as one–byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

MR0[3]—FIFO size

Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4

MR0[2:0]—Baud Rate Group Selection

These bits are used to select one of the six–baud rate groups.

See Table 5 for the group organization.

•000 Normal mode

•001 Extended mode I

•100 Extended mode II

Other combinations of MR2[2:0] should not be used.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 23

MR1 – Mode Register 1

ÁÁÁÁ

Addr

ÁÁÁÁÁ

BIT 7

ÁÁÁÁÁÁ

BIT 6

ÁÁÁÁÁ

BIT 5

ÁÁÁÁ

BIT 4

ÁÁÁÁÁ

BIT 3

ÁÁÁÁÁ

BIT 2

ÁÁÁÁ

BIT 1

ÁÁÁÁ

BIT 0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

MR1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Rx CONTROLS

RTS

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

RxINT

BIT 1

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ERROR

MODE

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

PARITY MODE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

PARITY TYPE

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

BITS PER

CHARACTER

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0x00

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = No

1 = Yes

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 = RxRDY

1 = FFULL

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = Char

1 = Block

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

00 = With Parity

01 = Force Parity

10 = No Parity

11 = Multi-drop Mode

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = Even

1 = Odd

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

00 = 5

01 = 6

10 = 7

11 = 8

NOTE:

In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.

MR1 is accessed when the MR pointer points to MR1. The pointer is

set to MR1 by RESET or by a ‘set pointer’ command applied via CR

command 0x10. After reading or writing MR1, the pointer will point to

MR2 and will not move from MR2 on subsequent MR reads or

writes.

MR1[7]— Receiver Request–to–Send Control (Flow Control)

This bit controls the deactivation of the RTSN output (OP0) by the

receiver. This output is normally asserted by setting OPR[0] and

negated by resetting OPR[0]. Proper automatic operation of flow

control requires OPR[0] to be set to logical 1.

MR1[7] = 1 causes RTSN to be negated (OP0 is driven to a ‘1’

[VCC]) upon receipt of a valid start bit if the FIFO is full. This is the

beginning of the reception of the ninth byte. If the FIFO is not read

before the start of the tenth or 17th byte, an overrun condition will

occur and the tenth or 17th or 17th byte will be lost. However, the bit

in OPR[0] is not reset and RTSN will be asserted again when an

empty FIFO position is available. This feature can be used for flow

control to prevent overrun in the receiver by using the RTSN output

signal to control the CTSN input of the transmitting device.

MR1[6]—Rx Interrupt Bit 1

Bit 1 of the receiver interrupt control. See description under MR0[6].

MR1[5]— Error Mode Select

This bit selects the operating mode of the three FIFOed status bits

(FE, PE, and received break) for. In the ‘character’ mode, status is

provided on a character-by-character basis; the status applies only

to the character at the top of the FIFO. In the ‘block’ mode, the

status provided in the SR for these bits is the accumulation

(logical-OR) of the status for all characters coming to the top of the

FIFO since the last ‘reset error’ command was issued.

MR1[4:3|— Parity Mode Select

If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data MR1[4:3] = 11 selects operation in the special

multi–drop mode described in the Operation section.

MR1[2]— Parity Type Select

This bit selects the parity type (odd or even) if the ‘with parity’ mode

is programmed by MR1[4:3], and the polarity of the forced parity bit

if the ‘force parity’ mode is programmed. It has no effect if the ‘no

parity’ mode is programmed. In the special multi-drop mode it

selects the polarity of the A/D bit.

MR1[1:0]— Bits Per Character Select

This field selects the number of data bits per character to be

transmitted and received. The character length does not include the

start, parity, and stop bits.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 24

MR2 – Mode Register 2

MR2 is accessed when the MR pointer points to MR2, which occurs after any access to MR1. Accesses to MR2 do not change the pointer.

ÁÁÁÁ

ADDR

ÁÁÁÁ

BIT 7

ÁÁÁÁ

BIT 6

ÁÁÁÁÁÁ

BIT 5

ÁÁÁÁÁ

BIT 4

ÁÁÁÁ

BIT 3

ÁÁÁÁÁ

BIT 2

ÁÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

MR

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

CHANNEL MODE

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Tx CONTROLS

RTS

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

CTS

ENABLE Tx

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

STOP BIT LENGTH

NOTE: Add 0.5 to binary codes 0–7 for 5 bit character lengths.

ÁÁÁÁ

0x00

ÁÁÁÁÁÁÁ

00 = Normal

ÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

0 = 0.563

ÁÁÁÁÁ

4 = 0.813

ÁÁÁÁÁ

8 = 1.563

ÁÁÁÁÁ

C = 1.813

ÁÁÁÁ

ÁÁÁÁÁÁÁ

01 = Auto-Echo

ÁÁÁÁÁÁ

0 = No

ÁÁÁÁÁ

0 = No

ÁÁÁÁ

1 = 0.625

ÁÁÁÁÁ

5 = 0.875

ÁÁÁÁÁ

9 = 1.625

ÁÁÁÁÁ

D = 1.875

ÁÁÁÁ

ÁÁÁÁÁÁÁ

10 = Local loop

ÁÁÁÁÁÁ

1 = Yes

ÁÁÁÁÁ

1 = Yes

ÁÁÁÁ

2 = 0.688

ÁÁÁÁÁ

6 = 0.938

ÁÁÁÁÁ

A = 1.688

ÁÁÁÁÁ

E = 1.938

ÁÁÁÁ

ÁÁÁÁÁÁÁ

11 = Remote loop

ÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

3 = 0.750

ÁÁÁÁÁ

7 = 1.000

ÁÁÁÁÁ

B = 1.750

ÁÁÁÁÁ

F = 2.000

NOTE:

Add 0.5 to values shown for 0–7 if channel is programmed for 5 bits/char.

MR2[7:6]— Mode Select

The channel of the UART can operate in one of four modes.

MR2[7:6] = 00 is the normal mode, with the transmitter and receiver

operating independently .

MR2[7:6] = 01 places the channel in the automatic echo mode,

which automatically retransmits the received data. The following

conditions are true while in automatic echo mode:

1. Received data is reclocked and retransmitted on the TxD output.

2. The receive clock is used for the transmitter.

3. The receiver must be enabled, but the transmitter needs not be

enabled.

4. The TxRDY and TxEMT status bits are inactive.

5. The received parity is checked, but is not regenerated for

transmission, i.e. transmitted parity bit is as received.

6. Character framing is checked, but the stop bits are retransmitted

as received.

7. A received break is echoed as received until the next valid start

bit is detected.

8. CPU to receiver communication continues normally, but the CPU

to transmitter link is disabled.

MR2[7:6] = 10 selects local loop back diagnostic mode. In this

mode:

1. The transmitter output is internally connected to the receiver

input.

2. The transmit clock is used for the receiver.

3. The TxD output is held High.

4. The RxD input is ignored.

5. The transmitter must be enabled, but the receiver need not be

enabled.

6. CPU to transmitter and receiver communications continue

normally.

MR2[7:6] = 11 selects remote loop back diagnostic mode. In this

mode:

1. Received data is reclocked and retransmitted on the TxD

out–put.

2. The receive clock is used for the transmitter.

3. Received data is not sent to the local CPU, and the error status

conditions are inactive.

4. The received parity is not checked and is not regenerated for

transmission, i.e., transmitted parity is as received.

5. The receiver must be enabled.

6. Character framing is not checked, and the stop bits are

retransmitted as received.

7. A received break is echoed as received until the next valid start

bit is detected.

The user must exercise care when switching into and out of the

various modes. The selected mode will be activated immediately

upon mode selection, even if this occurs in the middle of a received

or transmitted character. Likewise, if a mode is deselected the

device will switch out of the mode immediately.

An exception to this occurs when switching out of auto echo or

remote loop back modes. If the de-selection occurs just after the

receiver has sampled the stop bit (indicated in auto echo by

assertion of RxRDY) and the transmitter is enabled, then the

transmitter will remain in auto echo mode until the stop bit(s) have

been re-transmitted.

In most situations the above is rendered transparent by other

system considerations. However recall that the stop bit sequence

may be very long compared to bus cycles. If rapid reconfiguration of

the transmitter is desired in the above conditions the controlling

system should wait for the TxEMT bit to set or issue a Tx software

reset before reconfiguration begins.

MR2[5]— T ransmitter Request–to–Send Control

This bit controls the deactivation of the RTSN output (OP0) by the

transmitter. This output is normally asserted by setting OPR[0] and

negated by resetting OPR[0]. MR2[5] = 1 caused OPR[0] to be

reset automatically one bit time after the characters in the transmit

shift register and in the TxFIFO, if any, are completely transmitted

including the programmed number of stop bits, if the transmitter is

not enabled.

This feature can be used to automatically terminate the transmission

of a message as follows (“line turnaround”):

1. Program auto–reset mode: MR2[5] = 1.

2. Enable transmitter .

3. Asset RTSN: OPR[0] = 1.

4. Send message.

5. Disable transmitter after the last character is loaded into the

TxFIFO.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 25

6. The last character will be transmitted and OPR[0] will be reset

one bit time after the last stop bit, causing RTSN to be negated.

MR2[4]— Clear-to-Send Control

If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1,

the transmitter checks the state of CTSN (IP0) the time it is ready to

send a character. If IP0 is asserted (Low), the character is

transmitted. If it is negated (High), the TxD output remains in the

marking state and the transmission is delayed until CTSN goes low.

Changes in CTSN while a character is being transmitted do not

affect the transmission of that character..

MR2[3:0]— Stop Bit Length Select

This field programs the length of the stop bit appended to the

transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2

bits, in increments of 1/16 bit, can be programmed for character

lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16

to 2 stop bits can be programmed in increments of 1/16 bit. In all

cases, the receiver only checks for a ‘mark’ condition at the center

of the stop bit position (one half-bit time after the last data bit, or

after the parity bit if enabled is sampled).

If an external 1X clock is used for the transmitter, then MR2[3] = 0

selects one stop bit and MR2[3] = 1 selects two stop bits to be

transmitted.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 26

CSR CLOCK SELECT REGISTER

ÁÁÁÁ

Addr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CSR (7:4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CSR (3:0)

ÁÁÁÁ

CSR

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RECEIVER CLOCK SELECT

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TRANSMITTER CLOCK SELECT

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0x01

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See Text and table 5

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See Text and table 5

Table 5. Baud rate (base on a 3.6864MHz crystal clock)

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MR0[0] = 0 (Normal Mode)

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MR0[0] = 1 (Extended Mode I)

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MR0[2] = 1 (Extended Mode II)

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CSRA[7:4]

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ACR[7] = 0

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ACR[7] = 1

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ACR[7] = 0

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ACR[7] = 1

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ACR[7] = 0

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ACR[7] = 1

0000 50 75 300 450 4,800 7,200

0001 110 110 110 110 880 880

0010 134.5 134.5 134.5 134.5 1,076 1,076

0011 200 150 1200 900 19.2K 14.4K

0100 300 300 1800 1800 28.8K 28.8K

0101 600 600 3600 3600 57.6K 57.6K

0110 1,200 1,200 7200 7,200 115.2K 115.2K

0111 1,050 2,000 1,050 2,000 1,050 2,000

1000 2,400 2,400 14.4K 14.4K 57.6K 57.6K

1001 4,800 4,800 28.8K 28.8K 4,800 4,800

1010 7,200 1,800 7,200 1,800 57.6K 14.4K

1011 9,600 9,600 57.6K 57.6K 9,600 9,600

1100 38.4K 19.2K 230.4K 115.2K 38.4K 19.2K

1101 Timer Timer Timer Timer Timer Timer

1110 IP4–16X IP4–16X IP4–16X IP4–16X IP4–16X IP4–16X

1111 IP4–1X IP4–1X IP4–1X IP4–1X IP4–1X IP4–1X

NOTE:

1. The receiver clock is always a 16X clock except for CSR[7:4] = 1111. CSR[3:0]— Transmitter Clock Select. This field selects the baud rate

clock for the transmitter.

The field definition is as shown in Table 5, except as follows:

CSR[3:0]

1110 IP3 –16X

1111 IP3 –1X

The transmitter clock is always a 16X clock except for CSR[3:0] = 1111.

Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz

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NORMAL RATE (BAUD)

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ACTUAL 16X CLOCK (KHz)

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ERROR (%)

50 0.8 0

75 1.2 0

110 1.759 –0.069

134.5 2.153 0.059

150 2.4 0

200 3.2 0

300 4.8 0

600 9.6 0

1050 16.756 –0.260

1200 19.2 0

1800 28.8 0

2000 32.056 0.175

2400 38.4 0

4800 76.8 0

7200 115.2 0

9600 153.6 0

19.2K 307.2 0

38.4K 614.4 0

NOTE:

Duty cycle of 16X clock is 50% 1%

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 27

CR—Command Register

CR is a register used to supply commands to the UART. Multiple

commands can be specified in a single write to CR as long as the

commands are non–conflicting, e.g., the ‘enable transmitter’ and

‘reset transmitter’ commands cannot be specified in a single

command word.

CR COMMAND REGISTER

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Addr

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Bit 7

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BIT 6

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BIT 5

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BIT 4

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BIT 3

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BIT 2

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BIT 1

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BIT 0

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CR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

MISCELLANEOUS COMMANDS

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Disable Tx

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Enable Tx

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Disable Rx

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Enable Rx

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0x02

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

See Text of Channel Command Register

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1 = Yes

0 = No

ÁÁÁÁ

1 = Yes

0 = No

ÁÁÁÁÁ

1 = Yes

0 = No

ÁÁÁÁÁ

1 = Yes

0 = No

NOTES:

Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.

CR[7:4]—Miscellaneous Commands

Execution of the commands in the upper four bits of this register

must be separated by 3 X1 clock edges. Other reads or writes

(including writes to the lower four bits) may be inserted to achieve

this separation.

CR[7:4]—Commands

0000 No command.

0001 Reset MR pointer. Causes the MR pointer to point to

MR1.

0010 Reset receiver. Resets the receiver as if a hardware

reset had been applied. The receiver is disabled and

the FIFO is flushed.

0011 Reset transmitter. Resets the transmitter as if a hard-

ware reset had been applied.

0100 Reset error status. Clears the Received Break, Parity

Error, and Overrun Error bits in the status register

(SR[7:4]). Used in character mode to clear OE status

(although Received Break, PE and FE bits will also be

cleared) and in block mode to clear all error status after

a block of data has been received.

0101 Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be

cleared to zero

0110 Start break. Forces the TxD output Low (spacing). If the

transmitter is empty the start of the break condition will

be delayed up to two bit times. If the transmitter is ac-

tive the break begins when transmission of the charac-

ter is completed. If a character is in the TxFIFO, the

start of the break will be delayed until that character, or

any other loaded subsequently are transmitted. The

transmitter must be enabled for this command to be

accepted.

0111 Stop break. The TxD line will go High (marking) within

two bit times. TxD will remain High for one bit time be-

fore the next character, if any, is transmitted.

1000 Assert RTSN. Causes the RTSN output to be asserted

(Low).

1001 Negate RTSN. Causes the RTSN output to be negated

(High)

1010 Set Timeout Mode On. The receiver in this channel will

restart the C/T as the receive character is transferred

from the shift register to the RxFIFO. The C/T is placed

in the counter mode, the START/STOP counter com-

mands are disabled, the counter is stopped, and the

Counter Ready Bit, ISR[3], is reset. (See also W atch-

dog timer description in the receiver section.)

1011 Set MR pointer to ‘0’

1100 Disable T imeout Mode. This command returns control

of the C/T to the regular START/STOP counter com-

mands. It does not stop the counter, or clear any pend-

ing interrupts. After disabling the timeout mode, a ‘Stop

Counter’ command should be issued to force a reset of

the ISR[3] bit

1101 Not used.

1110 Power Down Mode On. In this mode, the UART oscilla-

tor is stopped and all functions requiring this clock are

suspended. The execution of commands other than

disable power down mode (1111) requires a X1/CLK.

While in the power down mode, do not issue any com-

mands to the CR except the disable power down mode

command. The contents of all registers will be saved

while in this mode. It is recommended that the transmit-

ter and receiver be disabled prior to placing the UART

into power down mode.

1111 Disable Power Down Mode. This command restarts the

oscillator. After invoking this command, wait for the os-

cillator to start up before writing further commands to

the CR.

CR[3]—Disable Transmitter

This command terminates transmitter operation and reset the

TxRDY and TxEMT status bits. However, if a character is being

transmitted or if a character is in the TxFIFO when the transmitter is

disabled, the transmission of the character(s) is completed before

assuming the inactive state.

CR[2]—Enable Transmitter

Enables operation of the transmitter. The TxRDY and TxEMT status

bits will be asserted if the transmitter is idle.

CR[1]—Disable Receiver

This command terminates operation of the receiver immediately—a

character being received will be lost. The command has no effect on

the receiver status bits or any other control registers. If the special

multi-drop mode is programmed, the receiver operates even if it is

disabled. See Operation section.

CR[0]—Enable Receiver

Enables operation of the receiver. If not in the special wakeup mode,

this also forces the receiver into the search for start–bit state.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 28

SR Status Register

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SR RECEIVED

BREAK1FRAMING

ERROR1PARITY

ERROR1OVERRUN

ERROR TxEMT TxRDY FFULL RxRDY

0x01 0 = No

1 = Yes 0 = No

1 = Yes

1. These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from

the top of the FIFO together with bits [4:0]. These bits are cleared by a “reset error status” command. In character mode they are discarded

when the corresponding data character is read from the FIFO. In block error mode, the error–reset command (command 4x or receiver

reset) must used to clear block error conditions.

SR[7]— Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received: further entries to the

FIFO are inhibited until the RxD line returns to the marking state for

at least one-half a bit time two successive edges of the internal or

external 1X clock. This will usually require a high time of one X1

clock period or 3 X1 edges since the clock of the controller is

not synchronous to the X1 clock.

When this bit is set, the ‘change in break’ bit in the ISR (ISR[2]) is

set. ISR[2] is also set when the end of the break condition, as

defined above, is detected.

The break detect circuitry can detect breaks that originate in the

middle of a received character. However, if a break begins in the

middle of a character, it must persist until at least the end of the next

character time in order for it to be detected.

This bit is reset by command 4 (0100) written to the command

register or by receiver reset.

SR[6]— Framing Error

This bit, when set, indicates that a stop bit was not detected (not a

logical 1) when the corresponding data character in the FIFO was

received. The stop bit check is made in the middle of the first stop bit

position.

SR[5]— Parity Error

This bit is set when the ‘with parity’ or ‘force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity.

In the special multi-drop mode the parity error bit stores the receive

A/D (Address/Data) bit.

SR[4]— Overrun Error

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the FIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost.

This bit is cleared by a ‘reset error status’ command.

SR[3]— T ransmitter Empty (TxEMT)

This bit will be set when the transmitter under runs, i.e., both the

TxEMT and TxRDY bits are set. This bit and TxRDY are set when

the transmitter is first enabled and at any time it is re-enabled after

either (a) reset, or (b) the transmitter has assumed the disabled

state. It is always set after transmission of the last stop bit of a

character if no character is in the THR awaiting transmission.

It is reset when the THR is loaded by the CPU, a pending

transmitter disable is executed, the transmitter is reset, or the

transmitter is disabled while in the under run condition.

SR[2]— Transmitter Ready (TxRDY)

This bit, when set, indicates that the transmit FIFO is not full and

ready to be loaded with another character. This bit is cleared when

the transmit FIFO is loaded by the CPU and there are (after this

load) no more empty locations in the FIFO. It is set when a

character is transferred to the transmit shift register. TxRDY is reset

when the transmitter is disabled and is set when the transmitter is

first enabled. Characters loaded to the TxFIFO while this bit is 0 will

be lost. This bit has different meaning from ISR[0].

SR[1]— FIFO Full (FFULL)

This bit is set when a character is transferred from the receive shift

register to the receive FIFO and the transfer causes the FIFO to

become full, i.e., all eight (or 16) FIFO positions are occupied. It is

reset when the CPU reads the receive FIFO. If a character is waiting

in the receive shift register because the FIFO is full, FFULL will not

be reset when the CPU reads the receive FIFO. This bit has

different meaning from IRS when MR1 6 is programmed to a ‘1’.

SR[0]— Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the FIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the FIFO and reset

when the CPU reads the receive FIFO, only if (after this read) there

are no more characters in the FIFO – the Rx FIFO becomes empty.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 29

OPCR Output Port Configuration Register

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OPCR OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

0x0D 0 = OPR[7] 0 = OPR[6] 0 = OPR[5] 0 = OPR[4] 00 = OPR[3] 00 = OPR[2]

1 = Reserved 1 = TxRDY 1 = Reserved 1 = RxRDY/FFULL 01 = C/T OUTPUT 01 = TxC(16X)

10 = Reserved 10 = TxC(1X)

11 = Reserved 11 = RxC(1X)

OPCR[7]—OP7 Output Select

This bit programs the OP7 output to provide one of the following:

0 The complement of OPR[7].

1 reserved

OPCR[6]—OP6 Output Select

This bit programs the OP6 output to provide one of the following:

0 The complement of OPR[6].

1 The transmitter interrupt output which is the complement of

ISR[0]. When in this mode OP6 acts as an open-drain out-

put. Note that this output is not masked by the contents of

the IMR.

OPCR[5]—OP5 Output Select

This bit programs the OP5 output to provide one of the following:

0 The complement of OPR[5].

1 Reserved

OPCR[4]—OP4 Output Select

This field programs the OP4 output to provide one of the following:

0 The complement of OPR[4].

1 The receiver interrupt output which is the complement of

ISR[1]. When in this mode OP4 acts as an open-drain out-

put. Note that this output is not masked by the contents of

the IMR.

OPCR[3:2]—OP3 Output Select

This bit programs the OP3 output to provide one of the following:

00 The complement of OPR[3].

01 The counter/timer output, in which case OP3 acts as an

open-drain output. In the timer mode, this output is a square

wave at the programmed frequency. In the counter mode,

the output remains High until terminal count is reached, at

which time it goes Low. The output returns to the High state

when the counter is stopped by a stop counter command.

Note that this output is not masked by the contents of the

IMR.

10 Reserved

11 Reserved

OPCR[1:0]—OP2 Output Select

This field programs the OP2 output to provide one of the following:

00 The complement of OPR[2].

01 The 16X clock for the transmitter . This is the clock selected

by CSR[3:0], and will be a 1X clock if CSR[3:0] = 1111.

10 The 1X clock for the transmitter, which is the clock that shifts

the transmitted data. If data is not being transmitted, a free

running 1X clock is output.

11 The 1X clock for the receiver, which is the clock that samples

the received data. If data is not being received, a free run-

ning 1X clock is output.

SOPR—Set the Output Port Bits (OPR)

SOPR[7:0]—Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This

allows software to set individual bits with our keeping a copy of the OPR bit configuration.

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SOPR OP 7 OP 6 OP 5 OP 4 OP 3 OP 2 OP 1 OP 0

0x0E 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit

0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change

ROPR—Reset Output Port Bits (OPR)

ROPR[7:0]—Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This

allows software to reset individual bits with our keeping a copy of the OPR bit configuration.

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ROPR OP 7 OP 6 OP 5 OP 4 OP 3 OP 2 OP 1 OP 0

0x0F 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit

0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 30

OPR Output Port Register

The output pins (OP pins) drive the compliment of the data in this register as controlled by SOPR and ROPR.

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

N/A OP 7 OP 6 OP 5 OP 4 OP 3 OP 2 OP 1 OP 0

N/A 0 = Pin High 0 = Pin High 0 = Pin High 0 = Pin High 0 = Pin High 0 = Pin High 0 = Pin High 0 = Pin High

1 = Pin Low 1 = Pin Low 1 = Pin Low 1 = Pin Low 1 = Pin Low 1 = Pin Low 1 = Pin Low 1 = Pin Low

ACR Auxiliary Control Register

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ACR BRG SET

Select Counter Timer Mode

Mode and clock sour select Delta IP3 int

enable Delta IP3 int

enable

0x04 0 = set 1 See table 7 0 = off 0 = off 0 = off 0 = off

1 = set 2 1 = enabled 1 = enabled 1 = enabled 1 = enabled

ACR—Auxiliary Control Register

ACR[7]—Baud Rate Generator Set Select

This bit selects one of two sets of baud rates to be generated by the

BRG (see Table 5).

The selected set of rates is available for use by the receiver and

transmitter as described in CSR. Baud rate generator characteristics

are given in Table 6.

ACR[6:4]—Counter/T imer Mode And Clock Source Select

This field selects the operating mode of the counter/timer and its

clock source as shown in Table 7

ACR [3:0]—IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable

This field selects which bits of the input port change register (IPCR)

cause the input change bit in the interrupt status register (ISR [7]) to

be set. If a bit is in the ‘on’ state the setting of the corresponding bit

in the IPCR will also result in the setting of ISR [7], which results in

the generation of an interrupt output if IMR [7] = 1. If a bit is in the

‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].

Table 7. ACR 6:4 field definition

ACR

6:4 MODE CLOCK SOURCE

000 Counter External (IP2)

001 Counter TxC – 1X clock of transmitter

010 reserved

011 Counter Crystal or X1/CLK clock divided by 16

100 Timer External (IP2)

101 Timer External (IP2) divided by 16

110 Timer Crystal or external clock (X1/CLK)

111 Timer Crystal or external clock (X1/CLK) divided

by 16

NOTE:

1. The timer mode generates a square wave

IPCR Input Port change Register

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IPCR Delta IP3 Delta IP3 Delta IP3 Delta IP3 IP 3 IP 2 IP 1 IP 0

0x04 0 = no change 0 = no change 0 = no change 0 = no change 0 = low 0 = low 0 = low 0 = low

1 = change 1 = change 1 = change 1 = change 1 = High 1 = High 1 = High 1 = High

IPCR [7:4]—IP3, IP2, IP1, IP0 Change-of-State

These bits are set when a change-of-state, as defined in the input

port section of this data sheet, occurs at the respective input pins.

They are cleared when the IPCR is read by the CPU. A read of the

IPCR also clears ISR [7], the input change bit in the interrupt status

register. The setting of these bits can be programmed to generate

an interrupt to the CPU.

IPCR [3:0]—IP3, IP2, IP1, IP0 Change-of-State

These bits provide the current state of the respective inputs. The

information is unlatched and reflects the state of the input pins at the

time the IPCR is read.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 31

ISR—Interrupt Status Register

This register provides the status of all potential interrupt sources.

The contents of this register are masked by the Interrupt Mask

Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in

the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the

corresponding bit in the IMR is a zero, the state of the bit in the ISR

has no effect on the INTRN output. Note that the IMR does not mask

the reading of the ISR – the true status will be provided regardless

of the contents of the IMR. The contents of this register are

initialized to 0x00’ when the UART is reset.

ISR Interrupt Status Register

Addr Bit 7 Bits[6:4] BIT 3 BIT 2 BIT 1 BIT 0

ISR INPUT

PORT

CHANGE

Ignore in ISR reads.

Reserved for future function Counter

Ready Delta

Break RxRDY/

FFULL TxRDY

0x05 0 = not active 0 = not active 0 = not active 0 = not active 0 = not active

1 = active 1 = active 1 = active 1 = active 1 = active

ISR[7]—Input Port Change Status

This bit is a ‘1’ when a change–of–state has occurred at the IP0,

IP1, IP2, or IP3 inputs and that event has been selected to cause an

interrupt by the programming of ACR[3:0]. The bit is cleared when

the CPU reads the IPCR.

ISR[6:4]—Not used, Ignore in ISR read.

ISR[3]—Counter Ready.

In the counter mode, this bit is set when the counter reaches

terminal count and is reset when the counter is stopped by a stop

counter command.

In the timer mode, this bit is set once the cycle of the generated

square wave (every other time that the counter/timer reaches zero

count). The bit is reset by a stop counter command. The command,

however, does not stop the counter/timer .

ISR[2]— Change in Break

This bit, when set, indicates that the receiver has detected the

beginning or the end of a received break. It is reset when the CPU

issues a ‘reset break change interrupt’ command.

ISR[1]—Rx Interrupt

This bit indicates that the receiver is interrupting according to the fill

level programmed by the MR0 and MR1 registers. This bit has a

different meaning than the receiver ready/full bit in the status

register.

ISR[0]—Tx Interrupt

This bit indicates that the transmitter is interrupting according to the

interrupt level programmed in the MR0[5:4] bits. This bit has a

different meaning than the TxRDY bit in the status register.

IMR—Interrupt Mask Register

The programming of this register selects which bits in the ISR

causes an interrupt output. If a bit in the ISR is a ‘1’ and the

corresponding bit in the IMR is also a ‘1’ the INTRN output will be

asserted. If the corresponding bit in the IMR is a zero, the state of

the bit in the ISR has no effect on the INTRN output. Note that the

IMR does not mask the programmable interrupt outputs OP3–OP7

or the reading of the ISR.

IMR Interrupt Mask Register

Addr Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IMR INPUT

PORT

CHANGE

Reserved Reserved Reserved Counter

Ready Delta

Break RxRDY/

FFULL TxRDY

0x05 0 = not en-

abled Set to 0 Set to 0 Set to 0 0 = not en-

abled 0 = not en-

abled

1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled

IVR/GP– Interrupt Vector Register (68k mode) or General–purpose register (80XXX mode)

IVR/GP Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0x0C Interrupt Vector Register (68XXX mode) or General–purpose register (80XXX mode)

This register stores the Interrupt Vector. It is initialized to 0x0F on

hardware reset and is usually changed from this value during

initialization of the SC28L91 for the 68K Mode. The contents of this

register will be placed on the data bus when IACKN is asserted low

or a read of address 0xC is performed.

When not operating in the 68XXX mode, this register may be used

as a general-purpose one-byte storage register. A convenient use

may the storing a “shadow” of the contents of another SC28L91

register (IMR, for example).

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 32

CTPU and CTPL – Counter/Timer Registers

CTPU Counter Timer Preset Upper

CTPU Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0x06 The lower eight (8) bits for the 16 bit counter timer preset register

CTPL Counter –Timer Preset Low

CTPL Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0x07 The Upper eight (8) bits for the 16 bit counter timer preset register

The CTPU and CTPL hold the eight MSbs and eight Labs,

respectively, of the value to be used by the counter/timer in either

the counter or timer modes of operation. The minimum value which

may be loaded into the CTPU/CTPL registers is H‘0002’. Note that

these registers are write-only and cannot be read by the CPU.

In the timer mode, the C/T generates a square wave whose period is

twice the value (in C/T clock periods) of the CTPU and CTPL. The

waveform so generated is often used for a data clock. The formula

for calculating the divisor n to load to the CTPU and CTPL for a

particular 1X data clock is shown below.

n = (C/T Clock Frequency) divided by (2 x 16 x Baud rate desired)

Often this division will result in a non-integer number; 26.3, for

example. One can only program integer numbers in a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability asynchronous mode

of operation.

The C/T will not be running until it receives an initial ‘Start Counter’

command (read at address A3–A0 = 1110). After this, while in timer

mode, the C/T will run continuously. Receipt of a start counter

command (read with A3–A0 = 1110) causes the counter to terminate

the current timing cycle and to begin a new cycle using the values in

CTPU and CTPL. If the value in CTPU and CTPL is changed, the

current half-period will not be affected, but subsequent half periods

will be affected.

The counter ready status bit (ISR[3]) is set once each cycle of the

square wave. The bit is reset by a stop counter command (read with

A3–A0 = 0xF). The command however, does not stop the C/T. The

generated square wave is output on OP3 if it is programmed to be

the C/T output. In the counter mode, the value C/T loaded into

CTPU and CTPL by the CPU is counted down to 0. Counting begins

upon receipt of a start counter command. Upon reaching terminal

count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The

counter continues counting past the terminal count until stopped by

the CPU. If OP3 is programmed to be the output of the C/T, the

output remains high until terminal count is reached, at which time it

goes low. The output returns to the High state and ISR[3] is cleared

when the counter is stopped by a stop counter command. The CPU

may change the values of CTPU and CTPL at any time, but the new

count becomes effective only on the next start counter commands. If

new values have not been loaded, the previous count values are

preserved and used for the next count cycle.

In the counter mode, the current value of the upper and lower 8 bits

of the counter (CTU, CTL) may be read by the CPU. It is

recommended that the counter be stopped when reading to prevent

potential problems which may occur if a carry from the lower 8 bits

to the upper 8 bits occurs between the times that both halves of the

counter are read. However, note that a subsequent start counter

command will cause the counter to begin a new count cycle using

the values in CTPU and CTPL.

When the C/T clock divided by 16 is selected, the maximum divisor

becomes 1,048,575.

Output Port Notes

The output ports are controlled from four places: the OPCR register,

the OPR register, the MR registers and the command register

(except the 2681 and 68681) The OPCR register controls the source

of the data for the output ports OP2 through OP7. The data source

for output ports OP0 and OP1 is controlled by the MR and CR

registers. When the OPR is the source of the data for the output

ports, the data at the ports is inverted from that in the OPR register.

The content of the OPR register is controlled by the “Set Output Port

Bits Command” and the “Reset Output Bits Command”. These

commands are at E and F, respectively. When these commands are

used, action takes place only at the bit locations where ones exist.

For example, a one in bit location 5 of the data word used with the

“Set Output Port Bits” command will result in OPR[5] being set to

one. The OP5 would then be set to zero (V SS ). Similarly, a one in

bit position 5 of the data word associated with the “Reset Output

Ports Bits” command would set OPR[5] to zero and, hence, the pin

OP5 to a one (VDD).

The CTS, RTS, CTS Enable Tx signals

CTS (Clear To Send) is usually meant to be a signal to the

transmitter meaning that it may transmit data to the receiver. The

CTS input is on pin IP0 for Tx. The CTS signal is active low; thus, it

is called CTSN for TxRTS is usually meant to be a signal from the

receiver indicating that the receiver is ready to receive data. It is

also active low and is, thus, called RTSN for Rx. RTSN is on pin

OP0. A receiver’s RTS output will usually be connected to the CTS

input of the associated transmitter. Therefore, one could say that

RTS and CTS are different ends of the same wire!

MR2[4] is the bit that allows the transmitter to be controlled by the

CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input

is driven high, the transmitter will stop sending data at the end of the

present character being serialized. It is usually the RTS output of the

receiver that will be connected to the transmitter’s CTS input. The

receiver will set RTS high when the receiver FIFO is full AND the

start bit of the ninth or 17th character is sensed. T ransmission then

stops with nine or 17 valid characters in the receiver. When MR2[4]

is set to one, CTSN must be at zero for the transmitter to operate. If

MR2[4] is set to zero, the IP pin will have no effect on the operation

of the transmitter. MR1[7] is the bit that allows the receiver to control

OP0. When OP0 (or OP1) is controlled by the receiver, the meaning

of that pin will be.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 33

RESETN

tRES

SD00696

RESETN

tRES

80XXX Mode 68XXX Mode

Figure 4. Reset Timing

A0–A3

CEN

tAS

tCS tCH

RDN

tRW tRWD

D0–D7

(READ)

tDD tDF

FLOAT FLOATVALID

NOT

VALID

WDN

tRWD

VALID

D0–D7

(WRITE)

tDS

tDH

tAH

SD00087

NOTE:

Bus action in the 80XXX mode terminates on the rise of CEN, WRN, or RDN which ever one occurs first.

Figure 5. Bus Timing (80XXX mode)

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 34

X1/CLK

A1–A4

RWN

CSN

D0–D7

DTACKN

tCSC

tAS

tCS

tDF

tDAT

tDAH

tCH

tRWD

tDD

tDCR

tAH

DATA VALID

NOT

VALID

tDA

NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.

SD00687

Figure 6. Bus Timing (Read Cycle) (68XXX mode)

X1/CLK

A1–A4

RWN

CSN

D0–D7

DTACKN

tCSC

tAS

tCS

tDH

tDAT

tDAH

tCH

tRWD

tDS

tDCW

tAH

NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.

SD00688

Figure 7. Bus Timing (Write Cycle) (68XXX mode)

NOTE:

For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and

registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 35

X1/CLK

INTRN

IACKN

D0–D7

DTACKN

tCSC

tDD tDF

tCSD

tDAL

tDCR tDAH

tDAT

NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.

SD00149

Figure 8. Interrupt Cycle Timing (68XXX mode)

(b) OUTPUT PINS

RDN

IP0–IP6

WRN

OP0–OP7

tPS tPH

tPD

OLD DATA NEW DATA

(a) INPUT PINS

SD00135

Figure 9. Port Timing

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 36

NOTES:

1. INTRN or OP3-OP7 when used as interrupt outputs.

2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching

signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and

test environment are pronounced and can greatly affect the resultant measurement.

VM

VOL +0.5V

VOL

WRN

INTERRUPT1

OUTPUT

tIR

VM

VOL +0.5V

VOL

RDN

INTERRUPT1

OUTPUT

tIR

SD00136

Figure 10. Interrupt Timing (80xxx mode)

C1 = C2 ∼ 24pF FOR CL = 20pF

tCLK

tCTC

tRx

tTx

X1/CLK

CTCLK

RxC

TxC

tCLK

tCTC

tRx

tTx

VCC

470Ω

X1

X2*

CLK

*NOTE: X2 MUST BE LEFT OPEN.

X2

3.6864MHz

X1

C1

C2

SC28L91

NOTE:

RESISTOR REQUIRED

FOR TTL INPUT.

TO UART

CIRCUIT

50kΩ

to

100kΩ

3pF

C1 and C2 should be chosen according to the crystal manufacturer’s specification.

C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.

Gain at 3.6864MHz: 9 to 13 dB

2pF

4pF

Package capacitance approximately 4pF.

SD00704

PARASITIC CAPACITANCE

Figure 11. Clock Timing

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 37

tTXD

tTCS

1 BIT TIME

(1 OR 16 CLOCKS)

TxD

TxC

(INPUT)

TxC

(1X OUTPUT)

SD00138

Figure 12. Transmitter External Clocks

tRXS tRXH

RxC

(1X INPUT)

RxD

SD00139

Figure 13. Receiver External Clock

TRANSMITTER

ENABLED

TxD D1 D2 D3 D4 D6BREAK

TxRDY

(SR2)

WRN

D1 D8 D9 D10 D12START

BREAK STOP

BREAK D11 WILL

NOT BE

WRITTEN TO

THE TxFIFO

CTSN1

(IP0)

RTSN2

(OP0)

OPR(0) = 1 OPR(0) = 1

NOTES:

1. Timing shown for MR2(4) = 1.

2. Timing shown for MR2(5) = 1.

SD00155

Figure 14. Transmitter Timing

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 38

D1 D2 D8 D9 D10 D11 D12 D13

RxD

D12, D13 WILL BE LOST

DUE TO RECEIVER DISABLE.

RECEIVER

ENABLED

RxRDY

(SR0)

FFULL

(SR1)

RxRDY/

FFULL

(OP5)2

RDN

STATUS DATA

D1

STATUS DATA

D2

STATUS DATA

D3

STATUS DATA

D10

D11 WILL BE LOST

DUE TO OVERRUN

OVERRUN

(SR4) RESET BY COMMAND

RTS1

(OP0)

OPR(0) = 1

NOTES:

1. Timing shown for MR1(7) = 1.

2. Shown for OPCR(4) = 1 and MR(6) = 0.

SD00156

Figure 15. Receiver Timing

TRANSMITTER

ENABLED

TxD ADD#1

TxRDY

(SR2)

WRN

MR1(4–3) = 11

MR1(2) = 1

1

BIT 9

D0 0

BIT 9

ADD#2 1

BIT 9

MASTER STATION

ADD#1MR1(2) = 0 D0 MR1(2) = 1 ADD#2

RxD ADD#1 1

BIT 9

D0 0

BIT 9

ADD#2 1

BIT 9

PERIPHERAL STATION

0

BIT 9

0

BIT 9

RECEIVER

ENABLED

RxRDY

(SR0)

RDN/WRN

MR1(4–3) = 11 ADD#1 STATUS DATA

D0

STATUS DATA

ADD#2

SD00096

Figure 16. Wake-Up Mode

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 39

INTRN

DACKN

D0–D7

TxDA/B

OP0–OP7

125pF

+5V

I = 2.4mA

125pF

I = 2.4mA VOL return to VCC for a 0 level

I = 400µA VOH return to VSS for a 1 level

SD00690

Figure 17. Test Conditions on Outputs

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 40

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 41

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22 42

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may af fect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 2000

Date of release: 09-00

Document order number: 9397 750 07549

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Data sheet

status

Objective

specification

Preliminary

specification

Product

specification

Product

status

Development

Qualification

Production

Definition [1]

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.