Eight Character 5.0 mm (0.2 inch) Hermetic Smart 5 X 7 Alphanumeric Displays For Military Applications Technical Data Features Wide Operating Tempera- ture Range -55C to +85C True Hermetic Package for Yellow, Orange and High Efficiency Red Displays!" * TXVB Version Conforms to MIL-D-87157 Quality Level A Test Tables Smart Alphanumeric Display On-Board CMOS IC Built-In RAM ASCH Decoder LED Drive Circuitry 128 ASCII Character Set 16 User Definable Charac- ters Programmable Features Individual Flashing Character Full Display Blinking Multi-Level Dimming and Blanking Self Test Clear Function e Read/Write Capability Fall TTL Compatibility HDSP-2131/-2133/-2179 Use- able in Night Vision Light- ing Applications Categorized for Luminous Intensity HDSP-2131/2133 Categor- ized for Color Excellent ESD Protection Wave Solderable X-Y Stackable Description The HDSP-2131 (yellow), HDSP-2179 (orange), HDSP-2132 (high efficiency red) and the HDSP-2133 (green) are eight-digit, 5 x 7 dot matrix, alphanumeric displays. The 5.0 mm {0.2 inch) high characters are packaged in a standard 7.64 mm (0.30 inch) 32 pin DIP. The on-board CMOS IC has the abil- ity to decode 128 ASCII char- acters, which are permanently stored in ROM. In addition, 16 programmable symbols may be HEWLETT PACKARD GD HDSP-2131/2131TXV/ 2131TXVB HDSP-2132/2132TXV/ 2132TXVB HDSP-2133/2133TXV/ 2133TXVB HDSP-2179/2179TXV/ 2179TXVB stored in an on-board RAM. Seven brightness levels provide versatility in adjusting the dis- play intensity and power con- sumption. The HDSP-213X is designed for standard micro- processor interface techniques. The display and special features are accessed through a bidirec- tional eight-bit data bus. These features make the HDSP-213X ideally suited for applications where an hermetic, low power alphanumeric display is required. Devices Yellow High Efficiency Red High Performance Green Orange HDSP-2131 HDSP-2132 HDSP-2133 HDSP-2179 HDSP-2131TXV HDSP-2132TXV HDSP-2133TXV HDSP-2179TXV | HDSP-2131TXVB HDSP-2132TXVB HDSP-2133TXVB HDSP-2179TXVB Note: 1. The HDSP-2133 high pefarmance green displays conform to MIL-D-87157 hermeticity requirements. 4-232Package Dimensions __ 42.72 (1.68) 267 TYP (0 105) _| 5.33 TYP (0.270) ee PIN 17 | | - 4.96 (0.142) PART NUMBER i DATE CODE PIN 1 IDENTIFIER Li 6.10 REF, (0.24) 0.38 TYP. (0.015) toh {0,300} | / LIGHT INTENSITY CATEGORY COLOR BIN (NOTE 3) of ny - ime i Pal) nose xxx xz f. * 6.35 MAX, YYWw (0.280) NON-ACCUM HOSP-213K/2179/TXV/TXVB PIN NO 1 2 3 4 5 SEATING PLANE fe 8 1 ( 9 2.29 TYP. --| 1270 | 0.51 TYP. 10 (0.090) * 3 60} _ 020) 11 12 254 TYP 4.27 TYP 10.100) (0.050) 13 14 15 16 4.B3 (0,190) PIN FUNCTION | NO. FUNCTION cLs 17 | GND (SUPPLY) CLK 18 | GND (LOGIC) 1.78 TYP. WR 19 | D4 (0.070) CE 20 | DS ey RST 21 | D gS RD 22 | D7 ra NO PIN 23 | NO PIN re NO PIN | 24 | NOPIN NO PIN | 25 | NOPIN NO PIN | 26 | NOPIN po 27 | FL D1 28 | AO D2 29 | At D3 30 | A2 NC 31 | A3 Voo 32 | Aa Note: 1. All dimensions are in mm (inches). 2. Unless otherwise specified tolerance is +0.30 mm (+0.015). 3. For green and yellow devices only. 4. Leads are copper alloy, solder dipped. Absolute Maximum Ratings Supply Voltage, V,, to Ground!) oo. -0.3 to 7.0V Operating Voltage, V,,, to Ground?) eects 5.5V Input Voltage, Any Pin to Ground................ .-0.3 to Vyp +0.3 V Free Air Operating Temperature Range, T, ............... -55C to +85C Storage Temperature, T, HDSP-213 1/-2132/-2179 ....ccccsccccccesesssessceescsteeneccseens -65C to +125C HDSP-2138 ......ccccsccsscsseeseesesctecseeceeseseeses .-55C to +100C CMOS IC Junction Temperature, T, (IC) 00.0... ees +150C Maximum Solder Temperature at Seating Plane, t < 5 SC ooo... eccecscsesseeesecenetscssesseeseneenenns 260C ESD Protection @ 1.5 kQ, 100 pF.... .V, =4kV (each pin) Notes: 1. Maximum Voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness. ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED WITH THE HDSP-2131, HDSP-2132, HDSP-2133, AND HDSP-2179. 4-233Character Set ov BS < TT os %, o4 103} 02)D1/Do Ly [tow 0000 a 0001 pmac on10 0011 9100 O10 omz--amo c H A rR A T R s 4-234Recommended Operating Conditions Parameter Symbol Minimum Nominal Maximum Units 4.5 5.0 5.5 Vv Supply Voltage Vv, DD Electrical Characteristics Over Operating Temperature Range 4.5 < V,, < 5.5 V (unless otherwise specified) 25C 25C Parameter Symbol | Min. | Typ." | Max." | Max. | Units | Test Conditions Input Leakage I, -10.0 +10.0 HA | Vi = 0to Vz, (Input without pullup) pins CLK, D,-D,, A,A, Input Current Ip -30.0 11 18 30 pA | V,,=O0toV,,, a (Input with pullup) pins RST, CLS, WR, us RD, CE, FL ge I,,, Blank Ty) (BLK) 0.5 15 20 | mA |V,=Vop lyp 8 digits lwn() 200 | 255 | 330 | mA |"V"oninall8 12 dots/character?! locations In) 8 digits I) 300 | 370 | 430 | mA | #"oninall8 20 dots/character"! locations Input Voltage High Vin 2.0 Vop V1 Vip = 5.5 V +0.3 Input Voltage Low Vi GND 0.8 Vv Vip = 4.5 V -0.3V Output Voltage High Vou 2.4 Vs Van = 4.5 V, 1, = -40 HA __| OH _ Output Voltage Low Vo. 0.4 Vv Vip = 4.5 V, D,-D, I,,, = 1.6 mA Output Voltage Low 0.4 Vv Vip = 4.5 V, CLK 1, = 40 HA Thermal Resistance RQ, un 11 C/W IC Junction-to-PIN Notes: 1. V,,, = 5.0 V. 2. Maximum I, occurs at -55C. 3. Average I, measured at full brightness. See Table 2 in Control Word Section for I,,, at lower brightness levels. Peak Ihp = 28/15 x Average Iyy {#). 4-235Optical Characteristics at 25C"! Vyp = 5.0 V at Full Brightness High Efficiency Red HDSP-2132 ' Description Symbol Minimum | Typical Units Luminous Intensity Character Average (#) ly 2.5 7.5 med Peak Wavelength ApEAK 635 nm Dominant Wavelength da 626 nm Orange HDSP-2179 Description Symbol Minimum | Typical Units Luminous Intensity Character Average (#) ly 2.5 7.5 med Peak Wavelength peAK 600 nm Dominant Wavelength : AG 602. nm Yellow HDSP-2131 Description Symbol Minimum | Typical Dnits Luminous Intensity Character Average (#) ly 2.5 7.5 med Peak Wavelength ApeaK 583 nm Dominant Wavelength AG 585 nm High Performance Green HDSP-2133 Description Symbol Minimum | Typical Units Luminous Intensity Character Average (#) ly 2.5 | 7.5 med Peak Wavelength ppaK 568 nm Dominant Wavelength 7 ra 574 nm Note: 4. Refers to the initial case temperature of the device immediately prior to the light measurement. 4-236AC Timing Characteristics Over Temperature Range Vip = 4.5 to 5.5 V unless otherwise specified. Reference Number Symbol Description Min.) Units 1 trace Display Access Time Write 210 Read 230 ns 2 trog Address Setup Time to Chip Enable 10 ns 3 toy Chip Enable Active Time? ) Write 140 Read 160 ns 4 teon Address Hold Time to Chip Enable 20 ns oe 5 tonp Chip Enable Recovery Time 60 ns 7 6 tog Chip Enable Active Prior to Rising Edge of!!! Write 140 Read 160 ns 7 torn Chip Enable Hold Time to Rising Edge of Read/Write Signal? *) 0 ns 8 ty Write Active Time!) 100 ns 9 twp Data Valid Prior to Rising Edge of Write Signal 50 ns 10 toy Data Write Hold Time 20 ns T 11 ty Chip Enable Active Prior to Valid Data 160 ns 12 ten Read Active Prior to Valid Data 75 ns 4 13 typ Read Data Float Delay 10 ns tre Reset Active Time"! 300 ns Notes: 1. Worst case values occur at an IC junction temperature of 150C. 2. For designers who do not need to read from the display, the Read line can be tied to V,, and the Write and Chip Enable 3. 4. lines can be tied together. _ Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. The display must not be accessed until after 3 clock pulses (110 us min. using the internal refresh clock) after the rising edge of the reset line. 4-237Symbol Description 25C Typical Minimum"! Units Pose Oscillator Frequency 57 28 kHz F, Display Refresh Rate 256 128 Hz FA" Character Flash Rate 2 1 Hz ten! Self Test Cycle Time 4.6 9.2 Sec Notes: 5. Fup = Fo gc/224 6. Py, = Fogc/28,672 7. ton = 262,144/F Kon Write Cycle Timing Diagram *" XXX XXX INPUT PULSE LEVELS D6EVTO24V 4-238Read Cycle Timing Diagram C @ eo O oo e \ / \ ) @ 1) = KRXXXKKKXXKKKKNY INPUT PULSE LEVELS: 06 VTO 24V OUTPUT REFERENCE LEVELS: 0.6 VTO22V OUTPUT LOADING = 1 TTL LOAD AND 100pF Character Font (Not to Scale) I a+ L 7 SEB REE 2.86 (0.112) ] cs @r Mr Gas es Bers Gh ac ae BEEBE EE &: 4.83 (0.190) TYP 0.65 (0.026) TYP Relative Luminous Intensity vs. Temperature 40 ] "| dobiciet = i Qs 1 g 34h HOSP -2132 {HER} -2179 (ORANGE) | zx i | Be HOSP2131 {YELLOW} 5% 25 + -+ + $5 NX HDSP2133 (GREEN) 25 20b- ~ =a 3N a a 15h 22 GREEN to 1.0---+- ae ae o5+ 4 ORANGE/HER | YELLOW 55-35 15 5 26 45 65 85 Ta AMBIENT TEMPERATURE "C 4-239 105 ar es Ei gu paisElectrical Description Pin Function RESET (RST, pin 5) FLASH (FT, pin 27) ADDRESS INPUTS (A,-A,, pins 28-32) CLOCK SELECT (CLS, pin 1) CLOCK INPUT/OUTPUT (CLK, pin 2) WRITE (WR, pin 3) CHIP ENABLE (CE, pin 4) READ (RD, pin 6) DATA Bus (D,-D,, pins 11-14, 19-22) GND GND Vv DD(POWER) isupriy (pin 17) (LOGIC) (pin 18) (pin 16) Reset initializes the display. FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A,-A,. Each location in memory has a distinct address. Address inputs (A,-A,) select a specific location in the Character RAM, the Flash RAM ora particular row in the UDC (User-Defined Character) RAM. A,-A, are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory FL A, A, Section of Memory A, A, A, 0 xX X Flash RAM Character Address 1 0 0 UDC Address Register Don't Care 1 0 1 | UDCRAM Row Address 1 1 0 Control Word Register Don't Care 1 1 1 Character RAM Character Address This input is used to select either an internal or external clock source. Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. Data is written into the display when the WR input is low and the CE input is low. This input must be at a logic low to read or write data to the display and must go high between each read and write cycle. Data is read from the display when the RD input is low and the CE input is low. The Data bus is used to read from or write to the display. This is the analog ground for the LED drivers. This is the digital ground for internal logic. This is the positive power supply input. 4-240RES riod) ele ToE La mBserq Yolg [eure] XE1Z-dSCH 1 andy 9079 101NO9 43934 13S MOU anv yee ONIWLL Hsv13 ALISN3LNI ONIWIL waav BYHS Oo 1sal 1 t1nsau 1S31 4138 43834 LuvLs wy agsal asa, 4138 wou ASaL TWNSIA o NI 41831 Asa a8) 435 ONIALL Na 434SI93y quom JOH 1NOD SuaAlIdG MOY 4ASaL 373s 13S MOH wiv Loa SNIWEL yadv HvHS *g-"q Lasad H sea suaaiua 4300930 Q fvefy xs e Loa wosy (NB a a-%q 4M %g-9q AVY du H3LIVHVHO 3 x Vivd 100 fa-%q Na 435 MO woav 9an 138 dud 479 tq-%q uM ay waist938 oN waav Jan $73 4-241Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP- 213X display. The CMOS IC consists of an 8 byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC chronize the decoding and driv- ing of eight 5 x 7 dot matrix characters. The major user Address Register, a Control Word Register, and the refresh circuitry necessary to syn- accessible portions of the dis- play are listed below: Character RAM Flash RAM User-Defined Character RAM (UDC RAM) User-defined Character Address Register (UDC Address Register) Control Word Register This RAM stores either ASCII character data or a UDC RAM address. This is a 1 x 8 RAM which stores Flash data. This RAM stres the dot pattern for custom characters. This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. This register allows the user to adjust the display brightness, flash individual characters, blink, self test or clear the display. Character Ram Figure 2 shows the logic levels needed to access the HDSP-213X Character RAM. During a normal access the CE = "0" and either RD = "0" or WR = "0". However, erroneous data may be written into the Charac- ter RAM if the Address lines are unstable when CE = "0" regard-, less of the logic levels of the RD or WR lines. Address lines A,-A, are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D, is used to differentiate between an ASCII character and a UDC RAM address. D, = 0 enables the ASCII decoder and D, = 1 enables the UDC RAM. D,-D, are used to input ASCII data and D,-D, are used to input a UDC address. cE AST UNDEFINED WRITE TO OISPL AY READ FROM DISPLAY UNOEFINED CONTROL SIGNALS Fi Ap Ay Ao T Ag AS ' ' CHARACTER . ADDRESS CHARACTER AAM ADDRESS O00 LEFT MOST 1t) AIGHT MOST Oq Dy; D2 Dy Do 0 126 ASCI| CODE 1 x x x CHARACTER RAM DATA FORMAT UDC COOE DIG, DIG, BIG, DIG, OIG, DIG, DIG, OIG, 000 001 010 on 100 | 101 Wa WwW SYMBOL (S ACCESSED IN LOCATION SPECIFIEQ BY THE CHARACTER ADORESS ABOVE DISPLAY Oe LOGIC 0: + =LOGIC 1. X = 00 NOT CARE Figure 2. Logic Levels to Access the Character RAM. 4-242UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D,-D,) are used to select one of the 16 UDC locations. The upper four bits (D,-D,) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character requires eight write cycles. One cycle is used to store the UDC RAM address in the UDC Address Register. Seven cycles are used to store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an F". A,-A, are used to select the row to be accessed and D,-D, are used to transmit the row dot data. The upper three bits (D,- D,) are ignored. D, (least signifi- cant bit) corresponds to the right most column of the 5x 7 matrix and D, (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM. Address lines A,-A, are ignored. Address lines A,-A, are used to select the location in the Flash RAM to store the attribute. D, is used to store or remove the flash attribute. D, "1" stores the attribute and D, "0" removes the attribute. UNDEFINED UNDEFINED CONTRO SIGNALS FL kay kg UOC ADDRESS REGISTER ADORESS D2 OF WRITE TO DISPLAY AEAD FROM DISPLAY Do upc CODE UNDEFINED UNDEFINEO CONTROL SIGNALS Ag oA To Ay Ay 1 Ag pepe} Row SELECT UOC ARAM ADORESS. 110 WRITE TO DISPLAY READ FROM DISPLAY | 4 z= Ww P-3 ed ve Tr Db ae bas oo ROW) ROW? Dr OK Ds De Da 02 Gy Dg | x x | DOT OATA | UOC FAM DATA FOAMAT =roo 0 LOGICG:1 LOGIC 1;x DO NOT CARE wron Figure 3. Logic Levels to Access a UDC Character. eccce oo0o00 kkk bee 12 3 4 5 voc Dy Dy 02 Dy Op CHARACTER 1 t 1 1 1 AoW! an 4 0 0 0 Oo ROW 2 100 0 0 ROW 3 111 4 0 ROW 4 1 obo oO 0 ROW 5 10000 ROW 6 1900 0 Row? IGNORED OSLOGIC 0. 1= LOGIC 1, * = ILLUMINATED LEO Figure 4. Data to Load '""F" into the UDC RAM. When the attribute is enabled through bit 3 of the Control Word and a1" is stored in the Flash RAM, the corresponding character will flash at approxi- mately 2 Hz. The actual rate is 4-243 dependent on the clock fre- quency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672.UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL a Ag yh) CHARACTER 000 LEFT MOST AODRESS 111 RIGHT MOST FLASH RAM ADDRESS GO; O Ds 04 03 Dy 01 Do Qo | * x x x x x = FLASH RAM DATA FORMAT 0 LOGIC O:1 LOGIC 1,% OO NOT CARE Control Word Register Figure 6 shows how to access the Control Word Register. This is an eight bit register which performs five functions. They are Brightness control, Flash RAM control, Blinking, Self Test and Clear. Each function is independent of the others. How- ever, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of I). I) can be caleu- lated at any brightness level by multiplying the percent bright- ness level by the value of I,,, at the 100% brightness level. These values of I, are shown in Table 2. bp Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a"1, the output of the Flash RAM is checked. If the content of a loca- tion in the Flash RAM isa"1, the associated digit will flash at Figure 5. Logic Levels to Access the Flash RAM. | CONTAOL SIGNALS FLO OAy og UNDEFINEQ WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED Az Ay CONTROL WORD ADDRESS O. 03; 07 Di Oe REMOVE FLASH AT SPECIFIED OIGIT LOCATION STORE FLASH aT SPECIFIED DIGIT LOCATION | | | | | 2 BRIGHTNESS ee CONTROL > LEVELS wes g000 asoe4~a80 O DISABLE FLASH | 1 ENABLE FLASH 0 DISABLE BLINKING 1 ENABLE BLINKING a X NORMAL OPERATION: X IS IGNORED 1 X START SELF TEST: RESULT GIVEN IN K x OFAHED xX 1 PASSED 0 NORMAL OPERATION 1 CLEAR FLASH AND CHARACTER RAMS CONTROL WORD DATA FORMAT 0 LOGIC 0:1 LOGIC 1:X DONOT CARE Figure 6. Logic Levels to Access the Control Word Register Table 2. Current Requirements at Different Brightness Levels % 25C Symbol | D, D, OD, | Brightness | Typical Ip) | 0 Oo 0 100 200 mA 0 0 1 80 160 mA 0 1 0 53 106 mA 0 1 1 40 80 mA 1 0 0 27 54 mA 1 0 1 20 40 mA 1 1 0 13 26 mA approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0", the content of the Flash RAM is ignored. To use this function with multiple dis- play systems see the Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of 4-244 all eight digits of the display. When this bit is a "1" all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see the Reset. section.Self Test Function (Bits 5, 6) Bit 6 of the Control Word Regis- ter is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test and bit 5 = "0" indicates a failed self test. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal rou- tines which exercises major por- tions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to "1". The second routine provides a visual test of the LEDs using the drive circuitry. This is accom- plished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds, During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test func- tion, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address Register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a "1" will start the clear func- tion. Three clock cycles (110 us min. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been com- pleted, bit 7 will be reset toa "0". The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "0's. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected. Display Reset Figure 7 shows the logic levels needed to Reset the display. The display should be Reset on Power-up. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 ps min. using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Charac- ter code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all "0"s. The UDC RAM and UDC Address RSt CE WA AD FL Ag-Ap O7-Do O=LOGIC 0: 1 = LOGIC 1. X = DO NOT CARE NOTE: 1 AS. TE AND WA ARE LOW, UNKNOWN DATA MAY BE WRITTEN INTO THE DISPLAY. Figure 7. Logic Levels to Reset the Display. 4-245 Register are unaffected. All displays which operate with the same clock source must be simultaneously reset to syn- chronize the Flashing and Blinking functions. Mechanical and Elec- trical Considerations The HDSP-213X is a 32 pin dual-in-line package with 24 external pins, which can be stacked horizontally and verti- cally to create arrays of any size. The HDSP-218X is de- signed to operate continuously from -55C to +85C with a maximum of 20 dots ON per character. Illuminating all thirty-five dots at full bright- ness is not recommended. [ORT el) ed 2a ae) eat The HDSP-213X is assembled by die attaching and wire bond- ing 280 LED chips and a CMOS IC to a ceramic substrate. A glass window is placed over the ceramic substrate creating an air gap over the LED wire bonds. A second glass window creates an air gap over the CMOS IC. This package con- struction makes the display highly tolerant to temperature cycling and allows wave solder- ing and visual inspection of the IC. a Fak ht) | ft phere aueeate 2 35 )(45 556578 BB HCHO Tra-"C Figure 8. Maximum Power Dissipa- tion vs. Ambient Temperature Derating Based on T,MAX = 125C.The inputs to the CMOS IC are protected against static dis- charge and input current latch- up. However, for best results standard CMOS handling pre- cautions should be used. Prior to use, the HDSP-213X should be stored in antistatic packages or conductive material, During assembly, a grounded conduc- tive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic ma- terial should be avoided since they are prone to static charge buildup. Input current latchup is caused when the CMOS in- puts are subjected to either a voltage below ground (V,, < ground) or to a voltage higher than V,,, (V,y > Vpp) and when a high current is forced into the input. To prevent input current latchup and ESD damage, un- used inputs should be connected either to ground or to V)). Volt- ages should not be applied to the inputs until V,,, has been applied to the display. Tran- sient input voltages should be eliminated. Thermal Considerations The HDSP-213X has been de- signed to provide a low thermal resistance path from the CMOS IC to the 24 package pins. This heat is then typically conducted through the traces of the user's printed circuit board to free air. For most applications no addi- tional heatsinking is required. The maximum operating IC junction temperature is 150C. The maximum IC junction tem- perature can be calculated using the following equation: TC) MAX = T, + (P,MAX) (RO,,,,, + RO J-PIN pina) Where P,,MAX = (V,,,,MAX) (1,,,MAX) Ip MAX = 370 mA with 20 dots ON in eight character locations at 25C ambient. This value is from the Electrical Characteris- tics table. P,MAX = (5.5 V)(0.370 A) = 2.04 W Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the ana- log ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnects between the dis- play and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be con- nected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the cur- rent introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with re- spect to the logic ground. Volt- age below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch. ESD Susceptibility These displays have ESD sus- ceptibility ratings of CLASS 3 per DOD-STD-1686 and CLASS B per MIL-STD-883C. 4-246 Soldering and Post Solder Cleaning Instructions for the HDSP-213X The HDSP-213X may be hand soldered or wave soldered with SN63 solder. When hand solder- ing it is recommended that an electronically temperature con- trolled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin- based RMA flux can be used. The solder wave temperature should be set at 245C + 5C (473F + 9F), and dwell in the wave should be set between 1-1/2 to 3 seconds for optimum soldering. The preheat tempera- ture should not exceed 105C (221F) as measured on the solder side of the PC board. Post solder cleaning may be performed using water or Freon/ alcohol mixtures formulated for vapor cleaning processing or Freon/alcohol mixtures formu- lated for room temperature cleaning. Freon/alcohol vapor cleaning processing for up to 2 minutes in vapors at boiling temperature is permissible. Suggested solvents include Freon TF, Freon TE, Genesolv DI-15, Genesolv DE-15, Genesolv DES, and water. An aqueous cleaning process may be used. A saponifier, such as Kester Bio-Kleen Formula 5799 or its equivalent, may be added to the wash cycle of an aqueous process to remove rosin flux residues. Organic acid flux residues must be thoroughly removed by an aqueous cleaning process to prevent corrosion of the leads and solder connections. The optimum water temper-ature is 60C (140F). The maximum cumulative exposure of the HDSP-213X to wash and rinse cycles should not exceed 15 minutes. For additional information on soldering and post solder cleaning, see Appli- cation Note 1027. High Reliability Testing Two standard high reliability testing programs are available. The TXVB program is in con- formance with MIL-D-87157 level A Test Tables. The TXVB product is tested to Tables I, II, Illa and IVa. The TXV program is an HP modification to the full conformance program and offers the 100% screening of Quality Level A, Table I, and Group A, Table II. Contrast Enhancement When used with the proper con- trast enhancement filters, the HCMS-213X series displays are readable daylight ambients. Refer to Application Note 1029 Luminous Contrast and Sun- light Readability of the HDSP- 238X Series Alphanumeric Displays for Military Applica- tions for information on contrast enhancement for daylight ambients. Refer to Application Note 1015 Contrast Enhance- ment Techniques for LED Displays for information on con- trast enhancement in moderate ambients. Night Vision Lighting When used with the proper NVG/DV filters, the HDSP-2131, HDSP-2179 and HDSP-2133 may be used in night vision lighting applica- tions. The HDSP-2131 (yellow), HDSP-2179 (orange) displays are used as master caution and warning indicators. The HDSP- 2133 (high performance green) displays are used for general instrumentation. For a list of NVG/DV filters and a discussion on night vision lighting technol- ogy, refer to Application Note 1030 LED Displays and Indica- tors and Night Vision Imaging System Lighting. An external dimming circuit must be used to dim these displays to night vision lighting levels to meet NVIS radiance requirements. Refer to AN 1039 Dimming HDSP-213X Displays to Meet Night Vision Lighting Levels. 100% Screening Table I. Quality Level A of MIL-D-87157 MIL-STD-750 Test Screen Method Conditions 1. Precap Visual 2072 Interpreted by HP Procedure 5956-75 12-52 2. High Temperature Storage 1032 T, = 125C"), Time = 24 hours 3. Temperature Cycling 1051 Condition B! , 10 cycles, 15 minute dwell 4. Constant Acceleration 2006 10,000 Gs at Y, & Y, orientation 5. Fine Leak 1071 Condition H 6. Gross Leak 1071 Condition C or K! 7. Interim Electrical/ _ Typ(BLRK), 1,,0V), Typ), Tape Lie Low Tos Ly Optical Tests! and Visual Function T, = 25C 8. Burn-In!! 1015 Condition B at V,,, = 5.5 V, cycle through character set 1 per second, T, = +85C, Time = 160 hours 9. Final Electrical Test! Same as step 7 10. Delta Determinations _ I, (V) & 1,,,(#) = 10%, I, = -20% 11. External Visual!" 2009 Notes: 1. MIL-STD-883 Test Method applies. 2. Limits and conditions are per the electrical/aptical characteristics. 3. T, = +100C for HDSP-2133. 4.T, = -55C Lo +100C for HDSP-2133. A 5. Fluid temperature = +100C for HDSP-2133. 4-247 on Tet Pe Za. irrets ; ira}Table II. Group A Electrica] Tests - MIL-D-87157 Subgroup Test Parameters LTPD Subgroup 1 DC Electrical Tests at 25C"! 1,,(BLK), 1,)(V), Top #), Tn Taps Tous Low Lys 5 and function test Subgroup 2 DC Electrical Tests at High Same as Subgroup 1 except delete I, and visual 7 Temperature"! function. T, = +85C Subgroup 3 ; DC Electrical Tests at Low Same as Subgroup 1 except delete I, and visual q Temperature"! function. T, = -55C Subgroup 4, 5, and 6 not applicable Subgroup 7 Optical and Functional Tests Satisfied by Subgroup 1 5 at 25C Subgroup 8 External Visual MIL-STD-883, Method 2009 7 Notes: 1. Limits and conditions are per the electricaVYoptical characteristics. 4-248Table IIIa. Group B Electrical Tests ~ MIL-D-87157 MIL-STD-750 Subgroup Test Method Conditions Sample Size Subgroup 1 | Resistance to Solvents 1022 4 Devices 0 Failures Interna] Visual and Design 207551 1 Device Verification" 0 Failures Subgroup 2'3) Solderability 2026 T, = 245C for 5 seconds LTPD = 15 Subgroup 3 Thermal Shock Temperature Cycle 1051 Condition B1, 15 minute dwell Moisture Resistance"! 1021 Ee id Fine Leak 1071 Condition H LTPD = 15 es ne Gross Leak 1071 Condition C or K! Electrical/Optical Endpoints _ 1,)(BLK), 1,,,(V), 1,50); tas tn, Ia Ty) 1, & function, 4 = 25C Subgroup 4 Operating Life Test 340 hrs 1027 T, = +85C @V,, =5.5V LTPD = 10 Electrical/Optical Endpoints"! Same as Subgroup 3 Subgroup 5 Non-Operating Storage Life 1032 T, = +125C) Test 340 hrs LTPD = 10 Electrical/Optical Endpoints | Same as Subgroup 3 Notes: M . Visual inspection is performed through the display window. 2. Whenever clectrical/optical tests are not required as endpoints, clectrical rejects may be used. The LTPD applies to the number of leads inspected except in no case shall less than 3 displays be used to provide the number of leads required. Initial conditioning is a 15 inward bend for one cycle. . Limits and conditions as per the electrical/optical characteristics. Equivalent to MIL-STD-883, Method 2014. The steam aging is not performed on gold plated leads. . Fluid temperature = +100C for HDSP-2133. . T, = +100C for HDSP-2133. te Sanaa 4-249Table IVa, Group C, Class A and B of MIL-D-87157 DD MIL-STD-750 Subgroup Test Method Conditions Sample Size Subgroup 1"! Physical Dimensions 2066 2 Devices 0 Failures Subgroup 2!) Lead Integrity'?! 2004 Condition B2 Fine Leak 1071 Condition H LTPD = 15 Gross Leak 1071 Condition C or K!!! Subgroup 3 Shock 2016 1500 G. Time = 0.5 ms, 5 blows in each orientation X,, Y,, Z, Vibration Variable Frequency 2056 Constant Acceleration 2006 10,000G at Y,, Y, orientation LTPD = 15 External Visual"! 1010 or 1011 Electrical/Optical Endpoints! 1, (BLK), 1,,,0V), 1,0), Lp we Top To, ty and Visual Function, T, = 25C Subgroup 4!!3) Salt Atmosphere 1041 LTPD = 15 External Visual"! 1010 or 1011 Subgroup 5 Bond Strength! 2037 Condition A LTPD = 20 C=0 Subgroup 6 Operating Life Test! 1026 T, = +85C at V,, =5.5 V d= 10 Electrical/Optical Endpoints ) Same as Subgroup 3 Notes: ran Ne of leads required. Pom ce Solderability samples shall not be used. Visual requirements shall be as specified in MIL-STD-883, Methods 1010 or 1011. Displays may be selected prior to seal. If a given inspection lot undergoing Group B inspection has been selected to satisfy Group C inspection requirements, the . Whenever electricaVoptical tests are not required as endpoints, electrical rejects may be used. . The LTPD applies to the number of leads inspected except in no case shall less than 3 displays be used to provide the number 340 hour life tests may be continucd on test to 1000 hours in order to satisfy the Group C life test requirements. In such cases cither the 340 hour endpoint measurements shall be made a basis for Group B lot acceptance or the 1000 hour endpoint measurement shall be used as the basis for both Group B and Group C acceptance. MIL-STD-883 test method applics. oon Limits and conditions are per the electricaloptical characteristics. Initial conditioning is a 15 inward bend for three cycles. Fluid temperature = +100C for HDSP-2133. 4-250