Supertex inc. HV9964
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9964
A100112
Features
► Switch-mode controller for single switch converters
● Boost
● SEPIC
► Current loop closed with sub-microsecond PWM
dimming pulses supports PWM dimming >20kHz
► High PWM dimming ratio (>10,000:1)
► Internal 40V linear regulator
► Internal ±2% voltage reference
► Programmable constant frequency operation
► Programmable slope compensation
► Programmable soft start
► 10V, +0.25A/-0.5A MOSFET gate drivers
► Hiccup mode protection for both short circuit and
open circuit conditions
► Latching protection from open loop
► Active-Low, open-drain output to indicate a fault
condition
Applications
► LED backlights for LCD Displays
General Description
The HV9964 is a current mode control LED driver IC designed to
control single switch PWM converters (boost or SEPIC) in a constant
frequency mode. The controller uses a peak current-mode control
scheme (with programmable slope compensation) and includes an
internal transconductance amplier to accurately control the output
current over all line and load conditions. The IC also provides a load
switch gate drive output, which can be used to disconnect the LEDs
in case of a fault condition using an external load switch. The 10V
external FET drivers allow the use of standard level FETs. The low
voltage 5V AVDD is used to power the internal logic and also acts
as a reference voltage to set the current level.
The HV9964 features Supertex’ proprietary PWM dimming control
algorithm achieving a dimming pulse of a few hundred nanoseconds
from a continuous conduction mode (CCM) or discontinuous-
conduction mode (DCM) boost converter, while maintaining the
instantaneous LED constant current determined by the reference
voltage input. This feature permits dimming frequency outside of
the audible range. The feature can also yield a wide dimming ratio
in excess of 10,000:1 at low dimming frequency.
The HV9964 provides a full protection feature set, including output-
short and open-circuit protection with auto-restart, and latching
open-loop protection with an open-drain ag output.
The HV9964 is powered by a built-in 40V linear regulator.
Typical Boost Application Circuit
CCM Boost LED Driver with Sub-Microsecond
PWM Dimming and Open Loop Protection
CIN
CPVDD
CO
CCCAVDD
CSS
CHCP
ROVP2
ROVP1
RCS
RSC
L1
Q1
D1
RR2
RR1
RT
RT
FLT
PWMD
OVP
DIS
FB
HCP SS COMP AVDD IREF
PVDD VIN GT CS GND
RS
Q2
HV9964
2
HV9964
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9964
A100112
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Parameter Value
VIN to GND -0.5V to +45V
PVDD to GND -0.3V to +12V
GT, DIS to GND -0.3V to (PVDD +0.3V)
AVDD to GND -0.3V to 6.0V
IREF to GND -0.3V to 3.0V
All other pins to GND -0.3V to (AVDD +0.3V)
Junction temperature +150°C
Storage ambient temperature range -65°C to +150°C
Continuous power dissipation (TA = +25°C) 1000mW
Sym Description Min Typ Max Unit Conditions
Input
VINDC Input DC supply voltage range -9.0 -40 V DC input voltage
IINSD Shut-down mode supply current - - - 1.5 mA PWMD = GND
Internal Regulator for Gate Drivers
PVDD Internally regulated voltage -9.5 10 10.5 V VIN = 12 - 40V, fS = 500kHz,
PWMD = VDD
UVLORISE VDD under voltage lockout threshold *6.65 -7.20 V PVDD rising
UVLOHYST VDD under voltage hysteresis - - 500 -mV PVDD falling
PVDD,MIN Minimum VDD voltage *8.0 - - VVIN = 9.0V, PWMD = VDD,
fS = 500kHz, CGT = 2.0nF
Part Number Package Options Packing
HV9964NG-G 16-Lead SOIC 45/Tube
HV9964NG-G M934 16-Lead SOIC 2500/Reel
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AVDD
VIN
DIS
PVDD
GT
GND
CS
RT
FLT
HCP
OVP
PWMD
FB
IREF
COMP
SS
Pin Description
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
T
op
M
ar
ki
ng
Bottom Marking
HV9964NG
YWW LLLLLLLL
CCCCCCCCC AAA
16-Lead SOIC (NG)
Electrical Characteristics
(The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications are
at TA = 25OC. VIN = 24V, CPVDD = 1.0μF, CAVDD = 1.0μF, CGT = 1.0nF, CRT = 1.0nF, CDIS = 330pF unless otherwise noted.)
Typical Thermal Resistance
Package θja
16-Lead SOIC 83OC/W
Ordering Information
16-Lead SOIC (NG)
Package may or may not include the following marks: Si or
3
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Sym Description Min Typ Max Unit Conditions
Internal Low Voltage Regulator
AVDD Internally regulated voltage *4.9 5.0 5.1 V VIN = 9 - 40V, PWMD = VDD
IAVDD_ext External current draw -0-500 μA ---
PWM Dimming
VPWMD(lo) PWMD input low voltage * - - 0.8 V ---
VPWMD(hi) PWMD input high voltage *2.0 - - V---
tdLatching delay time - - 100 -ns ---
RPWMD PWMD pull down resistor -50 100 150 kΩ VPWMD = 3.3V
GT Output
ISOURCE Short circuit current, sourcing -0.25 - - A VGT = 0V
ISINK Sinking current -0.50 - - A VGT = 10V
TRISE Output rise time - - 34 -ns PVDD = 10V
TFALL Output fall time - - 13 -ns PVDD = 10V
Over Voltage Protection
VOVP,rising Over voltage rising trip point *1.94 2.00 2.06 V OVP rising
VOVP,HYST Over voltage hysteresis - - 0.20 -V OVP falling
Hiccup Timer
KHCP+ Multiplier for charging current - - 0.50 - -
CHCP = 10nF – 100nF;
10μA current @ 100kHz
switching frequency
KHCP- Multiplier for discharging current - - 0.75 - -
CHCP = 10nF – 100nF;
15μA current @ 100kHz
switching frequency
VFC Voltage level to start gate driver - - 1.8 -V---
VDLY Voltage level for open loop detection - - 2.0 -V---
VRST Voltage level restart HCP timer - - 0.1 -V---
IDIS Discharging current (pull down FET) -10 - - mA VTMR = 5.0V
Soft Start
KSS+ Multiplier for charging current - - 0.5 - -
CSS = 1nF - 10nF; 10μA
current @ 100kHz switching
frequency
ISS- Discharging current -1.0 - - mA VSS = 5.0V
Electrical Characteristics (cont.)
(The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications are
at TA = 25OC. VIN = 24V, CPVDD = 1.0μF, CAVDD = 1.0μF, CGT = 1.0nF, CRT = 1.0nF, CDIS = 330pF unless otherwise noted.)
Note:
# Denotes specications guaranteed by design
4
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Sym Description Min Typ Max Unit Conditions
Slope Compensation
ISLOPE Peak current out of CS pin -150 180 216 μA ---
TSETTLING Settling time for current sourced - - - 800 ns ---
Current Sense
TBLANK Leading edge blanking *100 -250 ns ---
TDELAY1
Delay to output of output
comparator - - - 200 ns COMP = AVDD,
50mV overdrive at CS
Rdiv
Internal resistor divider ratio –
COMP to CS # - 1/12 - - ---
VOFFSET Comparator offset voltage --10 -+10 mV ---
Internal Transconductance Opamp
GB Gain-bandwidth product # - 1.0 -MHz 75pF capacitance at COMP pin
AVOpen loop DC gain -65 - - dB Output open
VCM Input common-mode range #-0.3 -3.0 V ---
VCOMP Output voltage range #0.7 -AVDD
-0.7 V AV > 50dB
GmTransconductance - - 1.5 -mA/V ---
VOFFSET Input offset voltage *-3.0 -3.0 mV ---
ICOMP+ COMP sink current # - 0.2 -mA VFB = AVDD, VIREF = 0,
VCOMP = 0
ICOMP- COMP source current # - 0.2 -mA VFB = 0V, VIREF = AVDD,
VCOMP = AVDD -0.7V
IBIAS Input bias current # - 0.5 1.0 nA ---
ICOMP,DIS Discharging current -10 - - mA VCOMP = 5.0V
Oscillator
fOSC1 Oscillator frequency * 88 100 112 kHz RT = 193kΩ
fOSC2 Oscillator frequency *440 500 560 kHz RT = 39kΩ
FOSC Output frequency range # 88 - 560 kHz ---
DMAX Maximum duty cycle * 87 - 93 % ---
Note:
# Denotes specications guaranteed by design
Electrical Characteristics (cont.)
((The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications
are at TA = 25OC. VIN = 24V, CPVDD = 1.0μF, CAVDD = 1.0μF, CGT = 1.0nF, CRT = 1.0nF, CDIS = 330pF unless otherwise noted.)
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HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Sym Description Min Typ Max Unit Conditions
Output Short Circuit
GSC Gain for short circuit comparator -1.8 2.0 2.2 - ---
VOMIN
Minimum output voltage of the
gain stage *0.14 0.20 0.26 V IREF = GND
TOFF
Propagation time for short circuit
detection - - - 250 ns
PWMD = VDD, IREF = 400mV;
FB step from 0 to 900mV;
FLT goes from high to low;
no capacitance at DIS pin
TRISE,DIS DIS output rise time - - - 100 ns 330pF capacitance at DIS pin
TFALL,DIS DIS output fall time - - - 100 ns 330pF capacitance at DIS pin
TBLANK,SC Blanking time *500 -700 ns ---
Fault Monitor
VFLT(LOW) FLT low voltage -0-0.3 V IFLT = 1.0mA
Open Loop Detection
VFB(TH) FB threshold voltage -85 -115 mV ---
VCOMP (TH) COMP threshold voltage -AVDD
-0.3 - - V---
Electrical Characteristics (cont.)
(The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications are
at TA = 25OC. VIN = 24V, CPVDD = 1.0μF, CAVDD = 1.0μF, CGT = 1.0nF, CRT = 1.0nF, CDIS = 330pF unless otherwise noted.)
6
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Functional Block Diagram
Linear
Regulator
DP
Block
min
PVDD DISGNDGT
PWMD
HCP
FLT
OVP
VIN
AVDD
RT
CS
COMP
SS
IREF FB
S
R
Q
Q
S
R
Q
Q
S
R
Q
Q
2
Dimming
LPF
Td
LPF
Linear
Regulator
LPF
Clock
TBLANK
S
R
Q
Q
S
R
Q
Q
TOFF_MIN
DIM
TOFF_MIN
POR
7.0V/6.5V
4.5V/4.0V
DIM_B
REF
TOFF_MIN
VCLK
IRT
K*VCLK
KSS*IRT
KHCP*IRT
KHCP*IRT
DIM
FC
FC
DIM
OL
FLT
RST
FC
DLY
0.1V
1.8V
2.0V
DIM_L
DIM_B
DLY
FLT
RST
POR
DIM
2.0V/1.8V
DIM
DIM
DIM
0.1V
OL
DLY
REF-0.3V
REF
FC
DIM
FC
11RR
DIM_L
+ -
+ -
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
7
HV9964
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9964
A100112
Power Topology
The HV9964 is a switch-mode LED driver designed to con-
trol a boost or SEPIC converter in a constant frequency
mode. The IC includes internal linear regulators, which en-
ables it to operate at input voltages from 9 to 40V. The IC
includes features typically required in LED drivers like open
LED protection, output short circuit protection, linear and
PWM dimming, and accurate control of the LED current. It
also includes logic to enable enhanced PWM dimming which
allows dimming ratios in excess of 10,000:1.
Power Supply to the IC (VIN, PVDD and AVDD)
The HV9964 can be powered directly from its VIN pin that
takes a voltage up to 40V. There are two linear regulators
within the HV9964 – a 10V linear regulator (PVDD), which
is used for the two FET drivers, and a 5.0V linear regulator
(AVDD) which supplies power to the rest of the control logic.
The IC also has a built in under-voltage lockout which shuts
off the IC if the voltage at either VDD pin falls below its UVLO
threshold. Both VDD pins must by bypassed by a low ESR
capacitor (≥0.1μF) for proper operation. The input current
drawn from the external power supply (or VIN pin) is a sum
of the 1.5mA (max) current drawn by the all the internal cir-
cuitry and the current drawn by the gate driver (which in turn
depends on the switching frequency and the gate charge of
the external FET).
IIN = 1.5mA + QG1 • fS + QG2 • fPWMD
In the above equation, fS is the switching frequency of the
converter, fPWMD is the frequency of the applied PWM dim-
ming signal, QG1 is the gate charge of the external boost FET
and QG2 is the gate charge of the load switch (both of which
can be obtained from the FET datasheets). The AVDD pin
can also be used as a reference voltage to set the LED cur-
rent using a resistor divider to the IREF pin.
Timing Resistor (RT)
The switching frequency of the converter is set by connect-
ing a resistor between RT and GND. The resistor value can
be determined as:
RT ≈ 1 + 880Ω
fS • 52pF
The oscillator is also timed to the PWM dimming signal to
improve the PWM dimming performance. The oscillator is
turned off when PWMD is low and is enabled when PWMD
goes high.
PWM Dimming
PWM dimming in the HV9964 can be accomplished using a
TTL compatible square wave source at the PWMD pin. The
HV9964 has an enhanced PWM dimming capability, which
allows PWM dimming to widths a few hundred nanoseconds
with no drop in the LED current. The enhanced PWM dim-
ming performance of the HV9964 can be best explained
by considering typical boost converter circuits without this
functionality. When the PWM dimming pulse becomes very
short, the boost converter is turned off before the input cur-
rent can reach its steady state value. This causes the input
power to drop, which is manifested in the output as a drop in
the LED current (Figure. 1b; for a CCM design).
Figure 1a: PWM dimming width much greater than
switching period TS
Figure 1b: Sub-TS PWM dimming width
In Figures 1a and 1b, IO(SS) and IL(SS) refer to the steady state
values (PWMD = 100%) for the output current and inductor
current respectively. As it can be seen, the inductor current
does not rise high enough to trip the CS comparator. This
causes the closed loop amplier to lose control over the LED
current, and the COMP output rails to VDD.
In the HV9964, however, this problem is overcome by keep-
ing the boost converter running even though the PWMD
pulse has ended. This is to ensure enough power delivered
to the output. Thus, the amplier still has control over the
LED current, and the LED current is in regulation as shown
in Figure 2.
PWMD
ILED
IINDUCTOR
IO(SS)
IL(SS)
TS
PWMD
I
LED
I
INDUCTOR
I
O(SS)
I
L(SS)
8
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Figure 2: Sub-TS PWM dimming width with the HV9964
Note that the GT output is not limited by its maximum duty
cycle DMAX past the PWMD signal trailing edge. The gate is
kept active until the corresponding CS reference is met by
IINDUCTOR. When the PWMD signal is high, the GT and DIS
pins are enabled, and the output of the transconductance
op-amp is connected to the external compensation net-
work. Thus, the internal amplier controls the output cur-
rent. When the PWMD signal goes low, the output of the
transconductance amplier is disconnected from the com-
pensation network. Thus, the integrating capacitor maintains
the voltage across itself. The DIS pin goes low, turning off
the disconnect switch. However, the GT output is kept ac-
tive.
Note that disconnecting the LED load during PWM dimming
causes the energy stored in the inductor to be dumped into
the output capacitor. The chosen lter capacitor should be
large enough so that it can absorb the inductor energy with-
out signicant change of the voltage across it. If the capacitor
voltage change is signicant, it would cause a turn-on spike
in the inductor current when PWMD becomes high again.
Figure 3: Deep PWM dimming performance: LED cur-
rent maintained in regulation
Current Sense (CS)
The current sense input is used to sense the source current
of the switching FET. The CS input of the HV9964 includes
a built in 100ns (minimum) blanking time to prevent spurious
turn off due to the initial current spike when the FET turns on.
The IC includes an internal resistor divider network, which
steps down the voltage at the COMP pins by a factor of 12
(11R:1R). This voltage is used as the reference for the cur-
rent sense comparators. Since the maximum voltage of the
COMP pin is AVDD - 0.7V, this voltage determines the maxi-
mum reference current for the current sense comparator
and thus the maximum inductor current. The current sense
resistor RCS should be chosen so that the input inductor cur-
rent is limited to below the saturation current level of the
input inductor. For discontinuous conduction mode of opera-
tion, no slope compensation is necessary. In this case, the
current sense resistor is chosen as:
RCS = AVDD - 0.7V
12 • ISAT
where ISAT is the maximum desired peak inductor current.
For continuous conduction mode converters operating in the
constant frequency mode, slope compensation becomes
necessary to ensure stability of the peak current mode con-
troller, if the operating duty cycle is greater than 0.5. This
factor must also be accounted for when determining RCS
(see Slope Compensation section).
Slope Compensation
Choosing a slope compensation that is one half of the down
slope of the inductor current ensures that the converter will
be stable for all duty cycles. The HV9964 slope compensa-
tion circuit uses an external resistor RSC at CS pin to program
the voltage slew rate. The current sourced out of the CS pin
is proportional to the internal oscillator ramp. This current
ramp has a peak value of 180µA. Therefore, the slope com-
pensation ramp is programmed as:
DS =
dVCS = RSC • 180µA • fS
dt
where fS is switching frequency.
Assuming a down slope of DS (A/μs) for the inductor current,
the current sense resistor can be computed as:
RCS = AVDD - 0.7V • 1
12 DS + ISAT
2fS
PWMD
ILED
IINDUCTOR
IO(SS)
IL(SS)
LED Current
PWMD Input
200ns/div
Pulse 1 Pulse 2
9
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
The slope compensation resistor is chosen to provide the
required amount of slope compensation required to maintain
stability.
RSC = DS
fS • 180µA
Soft Start
Soft start of the LED current can be achieved by connect-
ing a capacitor at the SS pin. The rate of voltage rise of
SS pin limits the LED current’s rate of rise. Upon start-up,
the capacitance at the COMP network is being charged by
the 200μA sourcing current of the transconductance ampli-
er. Without the soft-start function, this larger current would
cause the COMP voltage to increase faster than the boost
converter’s response time, causing overshoots in the LED
current during start-up. The SS pin is used to prevent these
LED current overshoots by limiting the COMP voltage slew
rate. A capacitor at the soft start pin programs this slew rate.
dVSS =
2V
dt CSS • RT
The HV9964 includes a latch which clamps the SS pin to
ground, but releases it upon the rst PWMD rising edge after
power-on. This ensures soft start for the LED current inde-
pendent of the power sequencing between VIN and PWMD.
DIS Output
The DIS pin is used to control a load switch when driving
boost and SEPIC converters. In the case of boost convert-
ers, when there is a short circuit fault at the output, there is a
direct path from the input source to ground which can cause
high currents to ow. The load switch is used to interrupt this
path and prevent damage to the converter. The load switch
also helps to disconnect the output lter capacitors for the
boost and SEPIC converters from the LED load during PWM
dimming and enables a fast dimming transitions.
Fault Conditions and Hiccup Timer
The HV9964 is a robust controller which can protect the
LEDs and the LED driver in case of fault conditions. The
HV9964 includes both open LED protection and output short
circuit protection. In both cases, the HV9964 shuts down
and attempts a restart. The hiccup time is programmed by
the capacitor at the HCP pin. When a fault condition is de-
tected, both GT and DIS outputs are disabled. The COMP,
SS and HCP pins are pulled to GND. Once the voltage at
the HCP pin falls below 0.1V, and the fault condition(s) have
disappeared, the capacitor at the HCP pin is released and
is charged slowly by a current source proportional to the RT
current. The HCP timing capacitor is programmed as:
CHCP ≈
tHICCUP
RT
Once the capacitor is charged to 1.8V, the COMP and SS
pins are released and GT and DIS pins are allowed to turn
on. The HV9964 resumes operation, beginning with the soft-
start mode ensuring smooth recovery of the LED current.
Short Circuit Protection
When a short circuit condition is detected (output current be-
comes higher than twice the steady state current), the gate
and DIS outputs are pulled low. As soon as the load switch
is turned off, the output current goes to zero and the short
circuit condition disappears. At this time, the hiccup timer is
started. Once the timing is complete, the converter attempts
to restart. If the fault condition still persists, the converter
shuts down and goes through the cycle again. If the fault
condition is cleared (due to a momentary output short) the
converter will start regulating the output current normally.
This behavior of the HV9964 allows the LED driver to re-
cover from accidental shorts without having to power the IC
down. Note that the power rating of the LED current sense
resistor has to be chosen adequately to be able to survive a
persistent fault condition.
The power rating of the resistor can be determined using:
PRS ≥
ISAT
2RS (TBLANK,CS + TOFF)
=
ISAT
2RS • 0.95µs
RT RT
where ISAT is the saturation current of the disconnect FET.
Open Loop Detection
The HV9964 includes protection circuitry disabling the boost
converter when there is a short circuit between the anode
and cathode of the LED string. However, if the string is short-
ed to ground, the sense resistor RS is bypassed, causing the
IC to lose the feedback signal. The voltage at FB becomes
0V, and COMP rails to the AVDD potential. Nevertheless, the
boost converter keeps on running, producing a potentially
damaging LED current.
To detect and to prevent this type of a fault, an open loop de-
tection circuit is added. If COMP > AVDD - 0.3V, and FB < 0.1V
simultaneously, then a discharge current of 15µA is activated at
10
HV9964
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Doc.# DSFP-HV9964
A100112
the HCP pin. With a 10µA sourcing current and a 15µA sink-
ing current, the total current discharging the HCP capacitor
is 5µA. This current will discharge the HCP capacitor from
AVDD to 2.0V. When the voltage at HCP drops below 2.0V,
the IC interprets it as an open loop condition, issues a logic
low state at the FLT output, and shuts GT and DIS down.
The discharge time provides a programmable delay to the
detection event. This delay time is needed because the open
loop condition may happen during startup when the SS ca-
pacitance is insufcient. To prevent misinterpretation of this
condition as the current loop open, the delay is introduced.
It is recommended, that the input supply voltage is shut off
by the host upon issuing FLT low, as shutting the HV9964 off
may not necessarily interrupt the current in the LED string in
the case of a partial short circuit to chassis.
Figure 8: Wiring short circuit to GND: detection and
shutdown.
FB Input
FLT Output
500μs/div
Short to GND
COMP Output
LED Current
11
HV9964
Supertex inc.
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Doc.# DSFP-HV9964
A100112
Pin Description (16-Lead SOIC)
Pin # Name Description
1 AVDD This is a power supply pin for all internal control circuits. This voltage is also used as the reference volt-
age both internally and externally. It must be bypassed with a low ESR capacitor to GND (at least 0.1μF).
2 VIN This pin is the input of a 40V high voltage regulator.
3DIS This pin is used to drive an external load switch which disconnects the load from the circuit during a
fault condition or during PWM dimming to achieve a very high dimming ratio.
4 PVDD This pin is a regulated 10V supply for the two gate drivers (DIS and GT). It must be bypassed with a low
ESR capacitor to GND (at least 1.0μF).
5 GT This is the gate driver output for the switching FET.
6 GND Ground return for all the low power analog internal circuitry as well as the gate drivers. This pin must be
connected to the return path from the input.
7 CS This pin is used to sense the source current of the external power FET. It includes a built-in 100ns (min)
blanking time.
8RT
This pin sets the frequency of the power circuit. A resistor between RT and GND will program the circuit
in constant frequency mode. The switching frequency is synchronized to the PWMD input and oscillator
will turn on once PWMD goes high. This pin must be bypassed to AVDD using a 1.0nF capacitor.
9SS This pin is used to provide soft start upon turn-on of the IC. A capacitor at this pin programs the soft start
time.
10 COMP Stable Closed loop control can be accomplished by connecting a compensation network between COMP
and GND.
11 IREF
The voltage at this pin sets the output current level. The current reference can be set using a resistor
divider from the AVDD pin. Connecting a voltage greater than 1.25V at this pin will disable the short
circuit comparator.
12 FB This pin provides output current feedback to the HV9964 by using a current sense resistor.
13 PWMD When this pin is pulled to GND (or left open), switching of the HV9964 is disabled. When an external TTL
high level is applied to it, switching will resume.
14 OVP
This pin provides the over voltage protection for the converter. When the voltage at this pin exceeds
1.25V, the gate output of the HV9964 is turned off and DIS goes low. The IC will turn on when the voltage
at the pin goes below 1.125V.
15 HCP This pin provides the hiccup timer in case of a fault. A capacitor at this pin programs the hiccup time.
16 FLT This open-drain, active-low output indicates the presence of a fault condition.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
12
HV9964
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9964
A100112
16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 9.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-16SONG, Version G041309.
Top View
Side View View A-A
View B
A
A
Seating
Plane
16
1
Seating
Plane
Gauge
Plane
L
L1
L2
θ1
θ
View B
h
h
b
AA2
A1
e
E
E1
D
Note 1
(Index Area
D/2 x E1/2)
Note:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be:
a molded mark/identier; an embedded metal marker; or a printed indicator.
