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V43658R04VATG-75 Rev. 1.3 September 2001
MO SEL VITELIC
V43658R04VATG-75
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD-Table for PC133 modules:
Byte Number Function Described SPD Entry Value
Hex Value
8Mx64
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x16 SDRAM) 9 09
5 Number of DIMM Banks 1 01
6 Module Data Width 64 40
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54
11 Dimm Config (Error Det/Corr.) none 00
12 Refresh Rate/Type Self-Refresh, 15.6µs80
13 SDRAM width, Primary x16 10
14 ErrorCheckingSDRAMDataWidth n/a/x8 00
15 Minimum Clock Delay from Back to Back Random
Column Address tccd =1CLK 01
16 Burst Length Supported 1, 2, 4, 8,full page 8F
17 Number of SDRAM Banks 4 04
18 Supported CAS Latencies CL = 3 04
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E
23 MinimumClockCycleTimeatCASLatency = 2 Not Supported 00
24 Maximum Data Access Time from Clock for CL = 2 Not Supported 00
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time 20 ns 14
28 Minimum Row Active to Row Active Delay tRRD 15 ns 0F
29 Minimum RAS to CAS Delay tRCD 20 ns 14
30 Minimum RAS Pulse Width tRAS 45 ns 2D