SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DImproved Stability Over Supply Voltage and
Temperature Ranges
DConstant-Current Outputs
DHigh Speed
DStandard Supply Voltages
DHigh Output Impedance
DHigh Common-Mode Output Voltage Range
. . . −3 V to 10 V
DTTL-Input Compatibility
DInhibitor Available for Driver Selection
DGlitch Free During Power Up/Power Down
DSN75112 and External Circuit Meets or
Exceeds the Requirements of CCITT
Recommendation V.35
description/ordering information
The SN55110A, SN75110A, and SN75112 dual
line drivers have improved output current
regulation with supply-voltage and temperature
variations. In addition, the higher current of the
SN75112 (27 mA) allows data to be transmitted
over longer lines. These drivers offer optimum
performance when used with the SN55107A,
SN75107A, and SN75108A line receivers.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (N)
Tube of 25
SN75110AN SN75110AN
PDIP (N) Tube of 25 SN75112N SN75112N
Tube of 50 SN75110AD
SN75110A
0°C to 70°C
SOIC (D)
Reel of 2500 SN75110ADR SN75110A
0C to 70 C
SOIC (D) Tube of 50 SN75112D
SN75112
Reel of 2500 SN75112DR SN75112
SOP (NS) Reel of 2000 SN75110ANSR SN75110A
CDIP (J)
Tube of 25
SN55110AJ SN55110AJ
−55°C to 125°C
CDIP (J) Tube of 25 SNJ55110AJ SNJ55110AJ
−55
°
C to 125
°
C
CFP (W) Tube of 150 SNJ55110AW SNJ55110AW
LCCC (FK) Tube of 55 SNJ55110AFK SNJ55110AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
! "#$ %!&
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1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1C
2C
2A
2B
GND
VCC+
1Y
1Z
VCC−
D
2Z
2Y
SN55110A ...J OR W PACKAGE
SN75110A . . . D, N, OR NS PACKAGE
SN75112 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1Z
NC
VCC−
NC
D
1C
NC
2C
NC
2A
SN55110A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
2Z 1Y
2B
GND
NC CC+
V
2Y
NC − No internal connection
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SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These drivers feature independent channels with common voltage supply and ground terminals. The significant
difference between the three drivers is in the output-current specification. The driver circuits feature a constant
output current that is switched to either of two output terminals by the appropriate logic levels at the input
terminals. The output current can be switched of f (inhibited) by low logic levels on the enable inputs. The output
current nominally is 12 mA for the ’110A devices and is 27 mA for the SN75112.
The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe
or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output
current in the inhibited mode, IO(off), is specified so that minimum line loading is induced when the driver is used
in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high.
The output impedance of a transistor is biased to cutoff.
The driver outputs have a common-mode voltage range of −3 V to 10 V, allowing common-mode voltage on the
line without affecting driver performance.
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at
2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure
400-mV noise margin when interfaced with TTL Series 54/74 devices.
The SN55110A is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN75110A and SN75112 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each driver)
LOGIC
INPUTS ENABLE
INPUTS OUTPUTS†
A B C D Y Z
X X L X Off Off
XXXLOffOff
LXHHOnOff
XLHHOnOff
H H H H Off On
H = high level, L = low level, X = irrelevant
†When using only one channel of the line drivers,
the other channel should be inhibited and/or have
its outputs grounded.
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each driver)
To Other Driver
Y
Z
GND
B
A
...V
CC+ Bus
...V
CC− Bus
To Other
Driver
C
D
2.2 kΩ
NOM
VCC−
Common to Both Drivers
2.2 kΩ
NOM
VCC+
Pin numbers shown are for the D, J, N, NS, and W packages.
+
−
14
3, 4
10
1, 5
2, 6
7
11
8, 13
9, 12
+
−
−
−
+
+
− −
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VCC+ (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC− (see Note 1) −7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −5 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJC (see Notes 4 and 5): FK package 13.42°C/W. . . . . . . . . . . . . . . . . . . . . . . .
J package 15.05°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
W package 14.65°C/W. . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package 300°C. . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) − TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
5. The package thermal impedance is calculated in accordance with MIL-STD-883.
recommended operating conditions (see Note 6)
SN55110A SN75110A
SN75112
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC+Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VCC− Supply voltage −4.5 −5 −5.5 −4.75 −5 −5.25 V
Positive common-mode output voltage 0 10 0 10 V
Negative common-mode output voltage 0 −3 0 −3 V
VIH High-level input voltage 2 2 V
VIL Low-level output voltage 0.8 0.8 V
TAOperating free-air temperature −55 125 0 70 °C
NOTE 6: When using only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
†SN55110A
SN75110A SN75112
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK Input clamp voltage VCC± = MIN, IL = −12 mA −0.9 −1.5 −0.9 −1.5 V
VCC± = MAX, VO = 10 V 12 15 27 40
IO(on)
On-state output current
VCC = MIN to MAX,
24
28
32
mA
IO(on) On-state output current
VCC = MIN to MAX,
VO = −1 V to 1 V, TA = 25°C24 28 32 mA
VCC± = MIN, VO = −3 V 6.5 12 15 27
IO(off) Off-state output current VCC± = MIN, VO = 10 V 100 100 µA
II
Input curren
t
at maximum
A, B, or C inputs
VCC = MAX,
VI = 5.5 V
1 1
mA
II
at maximum
input voltage D input VCC± = MAX, VI = 5.5 V 2 2 mA
IIH
High-level
A, B, or C inputs
VCC = MAX,
VI = 2.4 V
40 40
A
IIH
High-level
input curren
t
D input VCC± = MAX, VI = 2.4 V 80 80 µA
IIL
Low-level
A, B, or C inputs
VCC = MAX,
VI = 0.4 V
−3 −3
mA
IIL
Low-level
input curren
t
D input VCC± = MAX, VI = 0.4 V −6 −6 mA
ICC+(on) Supply current from VCC
with driver enabled
VCC± = MAX,
A and B inputs at 0.4 V,
C and D inputs at 2 V 23 35 25 40 mA
ICC−(on)
Supply current from VCC−
VCC± = MAX,
A and B inputs at 0.4 V,
−34
−50
−65
−100
mA
ICC−(on
)
Supply current from VCC−
with driver enabled
CC
A and B inputs at 0.4 V,
C and D inputs at 2 V −3
4
−5
0
−6
5
−10
0
mA
ICC+(off) Supply current from VCC−
with driver inhibited VCC± = MAX,
A, B, C, and D inputs at 0.4 V 21 30 mA
ICC−(off) Supply current from VCC±
with driver inhibited VCC± = MAX,
A, B, C, and D inputs at 0.4 V −17 −32 mA
†For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.
‡All typical values are at VCC+ = 5 V, VCC− = −5 V, TA = 25°C.
switching characteristics, VCC± = ±5 V, TA = 25°C (see Figure 1)
PARAMETER§FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH
A or B
Y or Z
CL = 40 pF,
RL = 50 Ω
9 15
ns
tPHL A or B Y or Z CL = 40 pF, RL = 50 Ω, 9 15 ns
tPLH
C or D
Y or Z
CL = 40 pF,
RL = 50 Ω
16 25
ns
tPHL
C or D
Y or Z
C
L
= 40 pF,
R
L
= 50
Ω, 13 25
ns
§tPLH = propagation delay time, low- to high-level output
tPHL = propagation delay time, high- to low-level output
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Input A or B
Pulse
Generator
(See Note B)
Pulse
Generator
(See Note B)
Input A or B
Enable C or D
3 V
0 V
3 V
0 V
TEST CIRCUIT
Off
On
tPLH tPHL tPHL
tPLH
tPHL
On
Off
Output Y
Output Z
VOLTAGE WAVEFORMS
890 ΩOutput Y
Output Z
RL = 50 Ω
890 Ω
VCC+ VCC−
To Other Driver
50 ΩSee Note C
RL = 50 Ω
50 Ω
Input C or D
CL = 40 pF
(see Note A)
CL = 40 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generators have the following characteristics: ZO = 50 Ω, tr = tf = 10 ± 5 ns, tw1 = 500 ns, PRR ≤ 1 MHz, tw2 = 1 µs,
PRR ≤ 500 kHz.
C. For simplicity, only one channel and the enable connections are shown.
tw1 tw2
tPLH
50% 50%
50% 50%
50% 50% 50% 50%
50% 50%
Figure 1. Test Circuit and Voltage Waveforms
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VCC− − Negative Supply Voltage − V
Figure 2
12
10
8
6
4
14
−3 −7−4 −5 −6
2
0
− On-State Output Current − mAIO(on)
SN55110A, SN75110A
ON-STATE OUTPUT CURRENT
vs
NEGATIVE SUPPLY VOLTAGE
VCC+ = 4.5 V
VO = −3 V
TA = 25°C
Figure 3
−3
35
−7
0−4 −5 −6
5
10
15
20
25
30
VCC− − Negative Supply Voltage − V
SN75112
ON-STATE OUTPUT CURRENT
vs
NEGATIVE SUPPLY VOLTAGE
VCC+ = 4.5 V
VO = −3 V
TA = 25°C
− On-State Output Current − mAIO(on)
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
special pulse-control circuit
Figure 4 shows a circuit that can be used as a pulse-generator output or in many other testing applications.
Input
2.5 V
To Other Logic and
Strobe Inputs
1/2 ’110A
or SN75112 VCC−
VCC+
Output
Output Pulse
Input Pulse
Switch
Position
0
V
0 V
INPUT
A
High
Low Off
On On
Off
123 456
A
B
C
D
Y
Z
GND
−5 V
5 V
2
1
345
6
2
1
34
5
6
1
2
3456
OUTPUTS
YZ
Figure 4. Pulse-Control Circuit
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
using the SN75112 as a CCITT-recommended V.35 line driver
The SN75112 dual line driver, the SN75107A dual line receiver, and some external resistors can be used to
implement the data-interchange circuit of CCITT recommendation V.35 (1976) modem specification. The circuit
of one channel is shown in Figure 5 and meets the requirement of the interface as specified by Appendix 11
of CCITT V.35 and is summarized in Table 1 (V.35 has been replaced by ITU V.11).
Table 1. CCITT V.35 Electrical Requirements
GENERATOR MIN MAX UNIT
Source impedance, Zsource 50 150 Ω
Resistance to ground, R 135 165 Ω
Differential output voltage, VOD 440 660 mV
10% to 90% rise time, tr40 ns
or 0.01 × ui†
Common-mode output voltage, VOC −0.6 0.6 V
LOAD (RECEIVER) MIN MAX UNIT
Input impedance, ZI90 110 Ω
Resistance to ground, R 135 165 Ω
†ui = unit interval or minimum signal-element pulse duration
Data Ou
t
1Y
Data In
1B
Enable
1C
1A
R3
390 Ω
R1
1.3 kΩ
R5
75 Ω
R4
390 Ω
R2
1.3 kΩ
R6
50 Ω
R7
50 Ω
R8
100 pF
All resistors are 5%, 1/4 W.
5 V 5 V 5 V
5 V
13
12
1/2 SN75112
1
2
10
3
100 pF
1Y
1Z
1
2
125 Ω
1A
1B
1/2 SN75107A
Enable
1G
4
5
6Strobe
Figure 5. CCITT-Recommended V.35 Interface Using the SN75112 and SN75107A
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-87547012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8754701CA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-8754701DA ACTIVE CFP W 14 1 TBD Call TI Call TI
SN55110AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SN75110AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110AJ OBSOLETE CDIP J 14 TBD Call TI Call TI
SN75110AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75110ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75110ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75110ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN75112DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75112N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75112NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ55110AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ55110AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ55110AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55110A, SN75110A :
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
•Catalog: SN75110A
•Military: SN55110A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75110ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75110ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75110ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN75112DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75110ADR SOIC D 14 2500 333.2 345.9 28.6
SN75110ADR SOIC D 14 2500 367.0 367.0 38.0
SN75110ANSR SO NS 14 2000 367.0 367.0 38.0
SN75112DR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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