1000
800
600
400
200
0
-200
400
600
800
1000
-
-
-
-
V (mV)
OS
-20 -15 -10 -5 0 5 10 15 20
V (V)
CM
V = -18.1 V
CM
10 Typical Units Shown
350
250
150
50
-50
150
250
350
-
-
-
V (mV)
OS
0 2 4 6 8 16 20
V (V)
SUPPLY
V = ±2.25 V to 18 V
10 Typical Units Shown
SUPPLY ±
18141210
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA171
,
OPA2171
,
OPA4171
SBOS516F –SEPTEMBER 2010–REVISED APRIL 2018
OPAx171 36-V, Single-Supply, SOT-553, General-Purpose Operational Amplifiers
1
1 Features
1• Supply Range: 2.7 to 36 V, ±1.35 V to ±18 V
• Low Noise: 14 nV/√Hz
• Low Offset Drift: ±0.3 µV/°C (Typical)
• RFI Filtered Inputs
• Input Range Includes The Negative Supply
• Input Range Operates To Positive Supply
• Rail-to-Rail Output
• Gain Bandwidth: 3 MHz
• Low Quiescent Current: 475 µA per Amplifier
• High Common-Mode Rejection: 120 dB (Typical)
• Low-Input Bias Current: 8 pA
• Industry-Standard Packages:
– 8-Pin SOIC
– 8-Pin MSOP
– 14-Pin TSSOP
•microPackages:
– Single in SOT-553
– Dual in VSSOP-8
2 Applications
• Tracking Amplifier in Power Modules
• Merchant Power Supplies
• Transducer Amplifiers
• Bridge Amplifiers
• Temperature Measurements
• Strain Gauge Amplifiers
• Precision Integrators
• Battery-Powered Instruments
• Test Equipment
SPACE
3 Description
The OPA171, OPA2171, and OPA4171 (OPAx171)
are a family of 36-V, single-supply, low-noise
operational amplifiers with the ability to operate on
supplies ranging from 2.7 V (±1.35 V) to 36 V (±18
V). These devices are available in micro-packages
and offer low offset, drift, and bandwidth with low
quiescent current. The single, dual, and quad
versions all have identical specifications for maximum
design flexibility.
Unlike most operational amplifiers, which are
specified at only one supply voltage, the OPAx171
family is specified from 2.7 to 36 V. Input signals
beyond the supply rails do not cause phase reversal.
The OPAx171 family is stable with capacitive loads
up to 300 pF. The input can operate 100 mV below
the negative rail and within 2 V of the top rail during
normal operation. These devices can operate with full
rail-to-rail input 100 mV beyond the top rail, but with
reduced performance within 2 V of the top rail.
The OPAx171 series of operational amplifiers are
specified from –40°C to +125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
OPA171 SOT-23 (5) 1.60 mm × 2.90 mm
OPA2171 SOIC (8) 3.90 mm × 4.90 mm
OPA4171 TSSOP (14) 4.40 mm × 5.00 mm
SOIC (14) 3.90 mm × 8.65 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Offset Voltage vs Common-Mode Voltage Offset Voltage vs Power Supply
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information: OPA171 .................................. 8
6.5 Thermal Information: OPA2171 ................................ 8
6.6 Thermal Information: OPA4171 ................................ 8
6.7 Electrical Characteristics........................................... 9
6.8 Typical Characteristics: Table of Graphs................ 11
6.9 Typical Characteristics ........................................... 12
7 Detailed Description............................................ 18
7.1 Overview................................................................. 18
7.2 Functional Block Diagram....................................... 18
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 20
8 Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................ 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support................. 28
11.1 Related Links ........................................................ 28
11.2 Community Resources.......................................... 28
11.3 Trademarks........................................................... 28
11.4 Electrostatic Discharge Caution............................ 28
11.5 Glossary................................................................ 28
12 Mechanical, Packaging, and Orderable
Information........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2015) to Revision F Page
• Changed minimum supply voltage value from ±20 V to 0 V in Absolute Maximum Ratings table ....................................... 7
• Added maximum supply voltage value of 40 V to Absolute Maximum Ratings table ........................................................... 7
• Rewrote Electrical Overstress subsection content in Application Information section ........................................................ 21
Changes from Revision D (September 2012) to Revision E Page
• Changed device title (removed "Value Line Series").............................................................................................................. 1
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision C (June 2011) to Revision D Page
• Added "Value Line Series" to title........................................................................................................................................... 1
Changes from Revision B (November 2010) to Revision C Page
• Added MSOP-8 package to device graphic ........................................................................................................................... 1
• Added MSOP-8 package to Features bullets......................................................................................................................... 1
• Added MSOP-8 package to Product Family table.................................................................................................................. 1
• Updated pinout configurations for OPA2171 and OPA4171.................................................................................................. 4
• Added MSOP-8 package to OPA2171 Thermal Information table......................................................................................... 8
• Added new row for Voltage Output Swing from Rail parameter to Output subsection of Electrical Characteristics............ 10
• Changed Voltage Output Swing from Rail parameter to over temperature in Output subsection of Electrical
Characteristics...................................................................................................................................................................... 10
• Changed Figure 9................................................................................................................................................................. 12
3
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,
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Changes from Revision A (November, 2010) to Revision B Page
• Changed input offset voltage specification............................................................................................................................. 9
• Changed input offset voltage, over temperature specification ............................................................................................... 9
• Changed quiescent current per amplifier, over temperature specification........................................................................... 10
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
1
2
3
5
4
V+
-IN
OUT
V-
+IN
1
2
3
5
4
V+
OUT
IN+
V-
IN-
4
OPA171
,
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,
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5 Pin Configuration and Functions
OPA171 DRL Package
5-Pin SOT-553
Top View
OPA171 DBV Package
5-Pin SOT-23
Top View
OPA171 D Package
8-Pin SOIC
Top View
(1) NC- no internal connection
Pin Functions: OPA171
PIN I/O DESCRIPTION
NAME DRL DBV D
+IN 1 3 3 I Noninverting input
–IN 3 4 2 I Inverting input
OUT 4 1 6 O Output
V+ 5 5 7 — Positive (highest) supply
V– 2 2 4 — Negative (lowest) supply
NC — — 1, 5, 8 — No internal connection (can be left floating)
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
5
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,
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OPA2171 D, DCU, and DCK Packages
8-Pin SO, VSSOP and MSOP
Top View
Pin Functions: OPA2171
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input
+IN B 5 I Noninverting input
–IN A 2 I Inverting input
–IN B 6 O Inverting input
OUT A 1 O Output
OUT B 7 — Output
V+ 8 — Positive (highest) supply
V– 4 — Negative (lowest) supply
1
2
3
4
14
13
12
11
OUTD
-IND
+IND
V-
OUTA
-INA
+INA
V+
5
6
7
10
9
8
+INC
-INC
OUTC
+INB
-INB
OUTB
6
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,
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,
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OPA4171 D and PW Packages
14-Pin SO and TSSOP
Top View
Pin Functions: OPA4171
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input
+IN B 5 I Noninverting input
+IN C 10 I Noninverting input
+IN D 12 I Noninverting input
–IN A 2 I Inverting input
–IN B 6 I Inverting input
–IN C 9 I Inverting input
–IN D 13 I Inverting input
OUT A 1 O Output
OUT B 7 O Output
OUT C 8 O Output
OUT D 14 O Output
V+ 4 — Positive (highest) supply
V– 11 — Negative (lowest) supply
7
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage 0 40 V
Signal input terminals Voltage (V–) – 0.5 (V+) + 0.5 V
Current –10 10 mA
Output short circuit(2) Continuous
Operating temperature –55 150 °C
Junction temperature 150 °C
Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) V
Specified temperature –40 125 °C
8
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,
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information: OPA171
THERMAL METRIC(1)
OPA171
UNITD (SO) DBV (SOT-23) DRL (SOT-553)
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 149.5 245.8 208.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 97.9 133.9 0.1 °C/W
RθJB Junction-to-board thermal resistance 87.7 83.6 42.4 °C/W
ψJT Junction-to-top characterization parameter 35.5 18.2 0.5 °C/W
ψJB Junction-to-board characterization parameter 89.5 83.1 42.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report .
6.5 Thermal Information: OPA2171
THERMAL METRIC(1)
OPA2171
UNITD (SO) DGK (MSOP) DCU (VSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 134.3 175.2 195.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 72.1 74.9 59.4 °C/W
RθJB Junction-to-board thermal resistance 60.6 22.2 115.1 °C/W
ψJT Junction-to-top characterization parameter 18.2 1.6 4.7 °C/W
ψJB Junction-to-board characterization parameter 53.8 22.8 114.4 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4171
THERMAL METRIC(1)
OPA4171
UNITD (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 51.8 24.4 °C/W
RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W
ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W
ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
9
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,
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(1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for
additional information.
6.7 Electrical Characteristics
at TA= 25°C, VS= 2.7 to 36 V, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.25 ±1.8 mV
Over temperature TA= –40°C to +125°C 0.3 ±2 mV
dVOS/dT Drift TA= –40°C to +125°C 0.3 ±2 µV/°C
vs power supply VS= 4 to 36 V
TA= –40°C to +125°C 1 ±3 µV/V
Channel separation, DC DC 5 µV/V
INPUT BIAS CURRENT
IBInput bias current ±8 ±15 pA
Over temperature TA= –40°C to +125°C ±3.5 nA
IOS Input offset current ±4 pA
Over temperature TA= –40°C to +125°C ±3.5 nA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 3 µVPP
enInput voltage noise density f = 100 Hz 25 nV/√Hz
f = 1 kHz 14 nV/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range(1) (V–) – 0.1
V(V+) – 2 V V
CMRR Common-mode rejection ratio
VS= ±2 V
(V–) – 0.1 V < VCM < (V+) – 2 V
TA= –40°C to +125°C 90 104 dB
VS= ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
TA= –40°C to +125°C 104 120 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ|| pF
Common-mode 6 || 3 1012Ω||
pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS= 4 V to 36 V
(V–) + 0.35 V < VO< (V+) – 0.35 V
TA= –40°C to +125°C 110 130 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product 3 MHz
SR Slew rate G = 1 1.5 V/µs
tSSettling time
To 0.1%
VS= ±18 V, G = 1
10-V step 6 µs
To 0.01% (12 bit)
VS= ±18 V, G = 1
10-V step 10 µs
Overload recovery time VIN × gain > VS2 µs
THD+N Total harmonic distortion + noise G = 1, f = 1 kHz
VO= 3 VRMS 0.0002%
OUTPUT
10
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Electrical Characteristics (continued)
at TA= 25°C, VS= 2.7 to 36 V, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO
Voltage output swing from rail VS= 5 V
RL= 10 kΩ30 mV
Over temperature RL= 10 kΩ
AOL ≥110 dB
TA= –40°C to +125°C (V–) +
0.35 (V+) –
0.35 V
ISC Short-circuit current +25/–35 mA
CLOAD Capacitive load drive See Typical Characteristics pF
ROOpen-loop output resistance f = 1 MHz
IO= 0 A 150 Ω
POWER SUPPLY
VSSpecified voltage range 2.7 36 V
IQ
Quiescent current per amplifier IO= 0 A 475 595 µA
Over temperature IO= 0 A
TA= –40°C to +125°C 650 µA
TEMPERATURE
Specified range –40 125 °C
Operating range –55 150 °C
11
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6.8 Typical Characteristics: Table of Graphs
Table 1. Characteristic Performance Measurements
DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5
Offset Voltage vs Power Supply Figure 6
IBand IOS vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Output Voltage Swing vs Output Current (Maximum Supply) Figure 9
CMRR and PSRR vs Frequency (Referred-to Input) Figure 10
CMRR vs Temperature Figure 11
PSRR vs Temperature Figure 12
0.1-Hz to 10-Hz Noise Figure 13
Input Voltage Noise Spectral Density vs Frequency Figure 14
THD+N Ratio vs Frequency Figure 15
THD+N vs Output Amplitude Figure 16
Quiescent Current vs Temperature Figure 17
Quiescent Current vs Supply Voltage Figure 18
Open-Loop Gain and Phase vs Frequency Figure 19
Closed-Loop Gain vs Frequency Figure 20
Open-Loop Gain vs Temperature Figure 21
Open-Loop Output Impedance vs Frequency Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23,Figure 24
No Phase Reversal Figure 25
Positive Overload Recovery Figure 26
Negative Overload Recovery Figure 27
Small-Signal Step Response (100 mV) Figure 28,Figure 29
Large-Signal Step Response Figure 30,Figure 31
Large-Signal Settling Time (10-V Positive Step) Figure 32
Large-Signal Settling Time (10-V Negative Step) Figure 33
Short-Circuit Current vs Temperature Figure 34
Maximum Output Voltage vs Frequency Figure 35
Channel Separation vs Frequency Figure 36
10000
8000
6000
4000
2000
0
-2000
4000
6000
8000
10000
-
-
-
-
V (mV)
OS
15.5 16 16.5 17 17.5 18 18.5
V (V)
CM
10 Typical Units Shown
Normal
Operation V = 18.1 V
CM
350
250
150
50
-50
150
250
350
-
-
-
V (mV)
OS
0 2 4 6 8 16 20
V (V)
SUPPLY
V = ±2.25 V to 18 V
10 Typical Units Shown
SUPPLY ±
18141210
600
400
200
0
200
400
600
800
-
-
-
-
OffsetVoltage( V)m
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
5TypicalUnitsShown
1000
800
600
400
200
0
-200
400
600
800
1000
-
-
-
-
V (mV)
OS
-20 -15 -10 -5 0 5 10 15 20
V (V)
CM
V = -18.1 V
CM
10 Typical Units Shown
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-100
0
100
200
300
400
500
600
700
800
900
1000
1200
OffsetVoltage( V)m
PercentageofAmplifiers(%)
16
14
12
10
8
6
4
2
0
-200
1100
DistributionTakenFrom3500Amplifiers
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.1
1.2
1.3
2
OffsetVoltageDrift( V/ C)m °
PercentageofAmplifiers(%)
25
20
15
10
5
0
1
DistributionTakenFrom110Amplifiers
1.5
1.7
1.9
1.8
1.6
1.4
12
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6.9 Typical Characteristics
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution
Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage
Figure 5. Offset Voltage vs Common-Mode Voltage (Upper
Stage) Figure 6. Offset Voltage vs Power Supply
30
20
10
0
10
20
30
-
-
-
Common-ModeRejectionRatio( V/V)m
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
V =2.7V
S
V =4V
S
V =36V
S
3
2
1
0
1
2
3
-
-
-
Power-SupplyRejectionRatio( V/V)m
-75 -50 -25 0 25 150
Temperature( C)°
50 12510075
V =2.7Vto36V
S
V =4Vto36V
S
18
OutputVoltage(V)
0 2 4 6 8 16
OutputCurrent(mA)
10 12 14
17
16
15
14.5
-14.5
-15
-16
-17
-18
- °40 C
+25 C°
+85 C°
+125 C°
140
120
100
80
60
40
20
0
Common-ModeRejectionRatio(dB),
Power-SupplyRejectionRatio(dB)
1 10 100 1k 10k 10M
Frequency(Hz)
100k 1M
+PSRR
-PSRR
CMRR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I andI (pA)
B OS
-20 -12 -6 0 6 20
V (V)
CM
12
-IB
+IB
-IOS
-18 18
V = 18.1V-
CM V =16V
CM
IB+
IB-
IOS
10000
1000
100
10
1
0
Input Bias Current (pA)
-40 -25 0 25
Temperature (°C)
50 12510075
IB
IOS
13
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Typical Characteristics (continued)
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 7. IBand IOS vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply) Figure 10. CMRR and PSRR vs Frequency (Referred-to
Input)
Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature
0.65
0.6
0.55
0.5
0.45
0.4
0.35
I (mA)
Q
-75 -50 -25 0 25 150
Temperature( C)°
1251007550
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
I (mA)
Q
0 4 8 12 16 36
Supply Voltage (V)
32282420
Specified Supply-Voltage Range
0.01
0.001
0.0001
0.00001
TotalHarmonicDistortion+Noise(%)
10 100 1k 10k 20k
Frequency(Hz)
TotalHarmonicDistortion+Noise(dB)
V =3V
BW=80kHz
OUT RMS
G=+1,R =10kW
L
G= 1,R =2k- W
L
-80
-100
-120
-140
0.1
0.01
0.001
0.0001
0.00001
TotalHarmonicDistortion+Noise(%)
0.01 0.1 1 10 20
OutputAmplitude(V )
RMS
-80
TotalHarmonicDistortion+Noise(dB)
BW=80kHz
G=+1,R =10kW
L
G= 1,R =2k- W
L
-100
-120
-140
1000
100
10
1
VoltageNoiseDensity(nV/ )ÖHz
1 10 100 1k 10k 1M
Frequency(Hz)
100k
1 V/divm
Time(1s/div)
14
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Typical Characteristics (continued)
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 13. 0.1-Hz to 10-Hz Noise Figure 14. Input Voltage Noise Spectral Density vs
Frequency
Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude
Figure 17. Quiescent Current vs Temperature Figure 18. Quiescent Current vs Supply Voltage
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
18 V
-18 V
ROUT
CL
TLV171-Q1
RL
G = 1
R = 0 Ω
OUT
R = 25
OUT Ω
R = 50
OUT Ω
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
TLV171-Q1
R =
I10 kW
ROUT
CL
RF= 10 kW
18 V
-18 V
G = -1
R = 0 W
OUT
R = 25 W
OUT
R = 50 W
OUT
1M
100k
10k
1k
100
10
1
1m
Z ( )W
O
1 10 100 1k 10k 10M
Frequency(Hz)
100k 1M
3
2.5
2
1.5
1
0.5
0
A (mV/V)
OL
Temperature (°C)
-25-40 0
5 Typical Units Shown
125100755025
V = 2.7 V
S
V = 4 V
S
V = 36 V
S
180
135
90
45
0
45-
Gain(dB)
1 10 100 1k 10k 10M
Frequency(Hz)
1M100k
Phase
Gain
Phase( )°
180
135
90
45
0
-45
25
20
15
10
5
0
5
10
15
20
-
-
-
-
Gain(dB)
10k 100M
Frequency(Hz)
1M100k 10M
G=10
G=1
G= 1-
15
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Typical Characteristics (continued)
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 19. Open-Loop Gain and Phase vs Frequency Figure 20. Closed-Loop Gain vs Frequency
Figure 21. Open-Loop Gain vs Temperature Figure 22. Open-Loop Output Impedance vs Frequency
Figure 23. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Time(20 s/div)m
20mV/div
+18V
-18V
R 2kW
F=
R 2kW
I=
CL
OPA171
G= 1-
C =100pF
L
2V/div
Time (5ms/div)
Time(5 s/div)m
5V/div
VIN
VOUT
2kW
20kW
VIN
VOUT
OPA171
G= 10-
+18V
-18V
20mV/div
Time(1 s/div)m
+18V
-18V CL
RL
OPA171
G=+1
R =10k
C =100pF
W
L
L
Time(5 s/div)m
5V/div
VIN
VOUT
2kW
20kW
VIN
VOUT
OPA171
G= 10-
+18V
-18V
Output
Output
Time (100ms/div)
5V/div
18 V
-18 V
37 VPP
Sine Wave
(±18.5 V)
TLV171-Q1
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Typical Characteristics (continued)
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery
Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV)
Figure 29. Small-Signal Step Response (100 mV) Figure 30. Large-Signal Step Response
-60
70
80
90
100
110
120
-
-
-
-
-
-
ChannelSeparation(dB)
10 100 1k 10k 100k
Frequency(Hz)
15
12.5
10
7.5
5
2.5
0
Output Voltage (V )
PP
10k 100k 10M
Frequency (Hz)
V = ±15 V
S
V = ±5 V
S
Maximum output voltage without
slew-rate induced distortion.
1M
10
8
6
4
2
0
-2
4
6
8
10
-
-
-
-
D From Final Value (mV)
0 36
Time (ms)
84 28 3224201612
12-Bit Settling
(±1/2LSB = 0.024%)±
50
45
40
35
30
25
20
15
10
5
0
I (mA)
SC
-40 -25 0 25
Temperature (°C)
50 125
I , Source
SC
10075
I , Sink
SC
10
8
6
4
2
0
-2
4
6
8
10
-
-
-
-
D From Final Value (mV)
0 36
Time (ms)
84 28 3224201612
12-Bit Settling
(±1/2LSB = 0.024%)±
Time (4ms/div)
2V/div
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Typical Characteristics (continued)
VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, (unless otherwise noted)
Figure 31. Large-Signal Step Response Figure 32. Large-Signal Settling Time (10-V Positive Step)
Figure 33. Large-Signal Settling Time (10-V Negative Step) Figure 34. Short-Circuit Current vs Temperature
Figure 35. Maximum Output Voltage vs Frequency Figure 36. Channel Separation vs Frequency
NCH
Input Stage
PCH
Input Stage 2nd Stage Output
Stage
+IN
-IN
Ca
Cb
PCH
FF Stage
OUT
OPA171
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7 Detailed Description
7.1 Overview
The OPAx171 operational amplifiers provide high overall performance, and are designed for many general-
purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire
temperature range. In addition, the series offers good overall performance with high CMRR, PSRR, and AOL. As
with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close
to the device pins. In most cases, 0.1-µF capacitors are adequate.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx171 family of amplifiers is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics .
7.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This family can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 2.
Output
Output
Time (100ms/div)
5V/div
18 V
-18 V
37 VPP
Sine Wave
(±18.5 V)
TLV171-Q1
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Feature Description (continued)
7.3.3 Phase-Reversal Protection
The OPAx171 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx171 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown
in Figure 37.
Figure 37. No Phase Reversal
Table 2. Typical Performance Range
PARAMETER MIN TYP MAX UNIT
Input common-mode voltage (V+) – 2 (V+) + 0.1 V
Offset voltage 7 mV
vs temperature 12 µV/°C
Common-mode rejection 65 dB
Open-loop gain 60 dB
GBW 0.7 MHz
Slew rate 0.7 V/µs
Noise at f = 1 kHz 30 nV/√Hz
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx171-Q1 family of devices have been optimized for commonly
encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases
the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive
loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for
example, ROUT equal to 50 Ω) in series with the output. Figure 38 and Figure 39 show small-signal overshoot
versus capacitive load for several values of ROUT. For details of analysis techniques and application circuits, see
Applications Bulletin AB-028, available for download from TI.com.
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
18 V
-18 V
ROUT
CL
TLV171-Q1
RL
G = 1
R = 0 Ω
OUT
R = 25
OUT Ω
R = 50
OUT Ω
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
TLV171-Q1
R =
I10 kW
ROUT
CL
RF= 10 kW
18 V
-18 V
G = -1
R = 0 W
OUT
R = 25 W
OUT
R = 50 W
OUT
20
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Figure 38. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) Figure 39. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171 family extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
These devices can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance
within 2 V of the top rail. The typical performance in this range is summarized in Table 2.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx171 operational amplifiers provide high overall performance, and are designed for many general-
purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire
temperature range. In addition, the series offers good overall performance with high CMRR, PSRR, and AOL. As
with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close
to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 40 shows the ESD circuits contained in the OPAx171 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
Power-Supply
ESD Cell
2.5 NŸ
2.5 NŸ
IN±
IN+
R1
RS
RF
TVS
RL
VIN
±VS
ID+
±
TVS
+VS
+
±
+
+
±
22
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Application Information (continued)
Figure 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device contains a trigger (or threshold voltage) that is above the normal operating voltage of the OPAx171 but
below the device breakdown level. When this threshold is exceeded, the absorption device quickly activates and
clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 40), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise when an applied voltage exceeds the operating voltage of a given pin. If this condition
occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such
current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 40 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper steering diodes conducts and directs current to V+. Excessively high current levels can
flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the
input current to 10 mA.
If the supply is not capable of sinking the current, VIN begins sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
LOAD ISO
o ISO LOAD
1 + C × R × s
T(s) = 1 + R + R × C × s
+
CLOAD
+
±
VIN
VOUT
+VS
RISO
VS
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Application Information (continued)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V, or at a
level below the input signal amplitude. If the supplies appear to be high-impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition. Most likely, the amplifier does not operate normally. If the supplies are low-impedance, then the
current through the steering diodes can be quite high. The current level depends on the ability of the input source
to deliver current and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 40. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe operating, supply-voltage level.
The OPAx171 input pins are protected from excessive differential voltage with back-to-back diodes; see
Figure 40. In most circuit applications, the input protection circuitry does not affect the application. However, in
low gain or G = 1 circuits, fast-ramping input signals can forward bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently
limited, an input series resistor can be used to limit the input signal current. This input series resistor degrades
the low noise performance of the OPAx171. Figure 40 shows an example configuration that implements a
current-limiting feedback resistor.
8.2 Typical Application
Figure 41. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 42 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 42. Not shown in Figure 42 is the open-loop output resistance of the operational amplifier, Ro.
(1)
The transfer function in Equation 1 contains a pole and a zero. The frequency of the pole (fp) is determined by
(Ro+ RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). Select RISO such
that the rate of closure (ROC) between the open-loop gain (AOL) and 1/βis 20 dB/decade to obtain a stable
system. Figure 42 shows the concept. The 1/βcurve for a unity-gain buffer is 0 dB.
Gain (dB)
0
AOL
1/
20
40
60
80
10 100 1k 10k 100k 1M
100
120
10M 100M
Frequency (Hz)
20 dB
ROC dec
40 dB
1 dec
zISO LOAD
1
f2 R CŒ
u u u
pISO o LOAD
1
f2 R R CŒ
u u u
24
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Typical Application (continued)
Figure 42. Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPAx171, see
Capacitive Load Drive Solution using an Isolation Resistor.
Table 3. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN OVERSHOOT AC GAIN PEAKING
45° 23.3% 2.35 dB
60° 8.8% 0.28 dB
8.2.2.1 Capacitive Load and Stability
The dynamic characteristics of the OPAx171 are optimized for commonly encountered operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. Figure 38 and Figure 39 illustrate graphs of small-signal overshoot versus capacitive load for
several values of ROUT. See Applications Bulletin AB-028, available for download from the TI website for details
of analysis techniques and application circuits.
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
18 V
-18 V
ROUT
CL
TLV171-Q1
RL
G = 1
R = 0 Ω
OUT
R = 25
OUT Ω
R = 50
OUT Ω
50
45
40
35
30
25
20
15
10
5
0
Overshoot (%)
0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
TLV171-Q1
R =
I10 kW
ROUT
CL
RF= 10 kW
18 V
-18 V
G = -1
R = 0 W
OUT
R = 25 W
OUT
R = 50 W
OUT
25
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Figure 43. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) Figure 44. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Capacitive Load (nF)
Isolation Resistor, RISO (:)
0.01 0.1 1 10 100 1000
1
10
100
1000
10000
D001
45q Phase Margin
60q Phase Margin
26
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8.2.3 Application Curve
The OPAx171 meets the supply voltage requirements of 30 V. The OPAx171 is tested for various capacitive
loads and RISO is adjusted to get an overshoot corresponding to Table 3. The results of the these tests are
summarized in Figure 45.
Figure 45. RISO vs CLOAD
NC
±IN
+IN
V±
V+
OUTPUT
NC
NC
VS+
VS±GND
Ground (GND) plane on another layer
VOUT
VIN
GND
Run the input traces
as far away from
the supply lines
as possible RF
RG
Place components close
to device and to each
other to reduce parasitic
errors
Use low-ESR,
ceramic bypass
capacitor
GND
Use a low-ESR,
ceramic bypass
capacitor
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9 Power Supply Recommendations
The OPAx171 family is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Specifications section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For detailed information on bypass capacitor placement, see the Layout Guidelines
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the devices, good printed circuit board (PCB) layout practices are
recommended. Low-loss, 0.1-µF bypass capacitors must be connected between each supply pin and ground,
placed as close to the devices as possible. A single bypass capacitor from V+ to ground is applicable to single-
supply applications.
10.2 Layout Example
Figure 46. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
OPA171 Click here Click here Click here Click here Click here
OPA2171 Click here Click here Click here Click here Click here
OPA4171 Click here Click here Click here Click here Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA171AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O171A
OPA171AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSUI
OPA171AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSUI
OPA171AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O171A
OPA171AIDRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAP
OPA171AIDRLT ACTIVE SOT-5X3 DRL 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAP
OPA2171AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2171A
OPA2171AIDCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPOC
OPA2171AIDCUT ACTIVE VSSOP DCU 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPOC
OPA2171AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPMI
OPA2171AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPMI
OPA2171AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2171A
OPA4171AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4171
OPA4171AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4171
OPA4171AIPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4171
OPA4171AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4171
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2017
Addendum-Page 2
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA171, OPA2171, OPA4171 :
•Automotive: OPA171-Q1, OPA2171-Q1, OPA4171-Q1
•Enhanced Product: OPA2171-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2017
Addendum-Page 3
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA171AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
OPA171AIDBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA171AIDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
OPA171AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA171AIDRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
OPA171AIDRLT SOT-5X3 DRL 5 250 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
OPA2171AIDCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
OPA2171AIDCUT VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
OPA2171AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2171AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4171AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4171AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA171AIDBVR SOT-23 DBV 5 3000 213.0 191.0 35.0
OPA171AIDBVT SOT-23 DBV 5 250 195.0 200.0 45.0
OPA171AIDBVT SOT-23 DBV 5 250 223.0 270.0 35.0
OPA171AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA171AIDRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
OPA171AIDRLT SOT-5X3 DRL 5 250 202.0 201.0 28.0
OPA2171AIDCUR VSSOP DCU 8 3000 202.0 201.0 28.0
OPA2171AIDCUT VSSOP DCU 8 250 202.0 201.0 28.0
OPA2171AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA2171AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA4171AIDR SOIC D 14 2500 367.0 367.0 38.0
OPA4171AIPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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