ADTR1107-EVAL User Guide UG-1684 One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106, U.S.A. * Tel: 781.329.4700 * Fax: 781.461.3113 * www.analog.com Evaluating the ADTR1107 with 6 GHz to 18 GHz, Front-End IC FEATURES ADTR1107-EVAL PHOTOGRAPHS 2-layer Rogers 4350 evaluation board with heat sink End launch 2.9 mm RF connectors Through calibration path (unpopulated) EVALUATION KIT CONTENTS 2-layer, Rogers 4350, ADTR1107-EVAL evaluation board with heat sink EQUIPMENT NEEDED 22147-001 RF signal generator RF spectrum analyzer RF network analyzer 5 V, 1 A power supply 3.3 V, 500 mA power supply 0 V to -2 V, 100 mA power supply Dual supply 3.3 V, 100 mA power supply Figure 1. ADTR1107-EVAL Top Side GENERAL DESCRIPTION The TX_IN, ANT, RX_OUT, and CPLR_OUT ports are populated by 2.9 mm, female coaxial connectors. The respective RF traces of the ports have a 50 characteristic impedance. The ADTR1107-EVAL is populated with components suitable for use over the -40C to +85C operating temperature range of the ADTR1107. To calibrate board trace losses, a through calibration path is provided. However, to use the through calibration path, users must install and populate the path with RF connectors. Access to drain, ground, and gate control voltages is through two, 24-pin headers. 22147-002 The ADTR1107-EVAL evaluation board consists of a two-layer printed circuit board (PCB) fabricated from a 10 mil thick, Rogers 4350B copper clad mounted to an aluminum heat sink. The heat sink assists in providing thermal relief to the device as well as mechanical support to the PCB. Mounting holes on the heat sink allow attachment to larger heat sinks for improved thermal management. Figure 2. ADTR1107-EVAL Bottom Side For more information about the ADTR1107, refer to the ADTR1107 data sheet. Consult the ADTR1107 data sheet in conjunction with this user guide when using the ADTR1107EVAL evaluation board. RF traces are 50 grounded, coplanar waveguide. Package ground leads and the exposed paddle connect directly to the ground plane. Multiple vias connect the top and bottom ground planes with particular focus on the area directly beneath the ground paddle to provide adequate electrical conduction and thermal conduction to the heat sink. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 6 UG-1684 ADTR1107-EVAL User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Bias Sequences ...................................................3 Evaluation Kit Contents ................................................................... 1 Through Path Insertion Loss .......................................................4 Equipment Needed ........................................................................... 1 Evaluation Board Schematic and Artwork.....................................5 General Description ......................................................................... 1 Ordering Information .......................................................................6 ADTR1107-EVAL Photographs ..................................................... 1 Bill of Materials ..............................................................................6 Revision History ............................................................................... 2 Operating the ADTR1107-EVAL ................................................... 3 REVISION HISTORY 1/2020--Revision 0: Initial Version Rev. 0 | Page 2 of 6 ADTR1107-EVAL User Guide UG-1684 OPERATING THE ADTR1107-EVAL A 5 V, 1 A power supply is required to provide the bias to the power amplifier in the transmit path. The 5 V power supply is connected through Pin 10 of the J6 header. Additionally, a 0 V to -2 V, 100 mA power supply is required to provide the required gate control voltage. The gate control voltage is supplied through Pin 6 of the J6 header. A 3.3 V, 100 mA power supply is required to provide the bias to the low noise amplifier (LNA) in the receive path. The 3.3 V supply is connected to the VGG_LNA pin through Pin 6 of the J5 header. The dual 3.3 V, 100 mA supply is required to provide the bias to the switch. The 3.3 V supply connects to the VDD_SW pin through Pin 22 of the J5 header. The -3.3 V supply connects to the VSS_SW pin through Pin 18 of the J5 header. Control the state of the switch by applying the proper logic level to Pin 20 of the J5 header, as defined in the Table 1. Use the biasing sequences described in the Transmit State Power-Up section, the Transmit State Power-Down section, the Receive State Power-Up section, and the Receive State PowerDown section when powering up and powering down. Refer to Table 2 for the ADTR1107 pin connections through the header connector. Table 1. Switch Logic Truth Table Control Input (VCTRL) State Low High Signal Path State TX_IN to ANT ANT to RX_OUT On Off Off On RECOMMENDED BIAS SEQUENCES Transmit State Power-Up The recommended bias sequence during the transmit state power-up is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Connect all GND pins to ground. Set the VDD_SW pin to 3.3 V. Set the VSS_SW pin to -3.3 V. Set the CTRL_SW pin to 0 V. Set the VGG_LNA pin to 0 V. Set the VDD_LNA pin to 0 V. Set the VGG_PA pin to -1.75 V. Set the VDD_PA pin to 5 V. Increase the VGG_PA pin voltage to achieve the desired quiescent current (IDQ_PA) of the power amplifier. 10. Apply the RF signal to the TX_IN pin. Transmit State Power-Down The recommended transmit state bias sequence during power-down is as follows: 1. 2. 3. 4. 5. Turn off the RF signal. Decrease the VGG_PA pin voltage to -1.75 V. Set the VDD_PA pin to 0 V. Set the VSS_SW to 0 V. Set the VDD_SW to 0 V. Receive State Power-Up The recommended bias sequence during the receive state power-up is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Connect all GND pins to ground. Set the VDD_SW pin to 3.3 V. Set the VSS_SW pin to -3.3 V. Set the CTRL_SW pin to 3.3 V. Set the VGG_PA pin to -1.75 V. Set the VDD_PA pin to 0 V. Set the VGG_LNA pin to 0 V. Set the VDD_LNA pin to 3.3 V. Apply the RF signal to the ANT pin. Receive State Power-Down The recommended receive state bias sequence during power-down is as follows: 1. 2. 3. 4. 5. 6. Turn off the RF signal. Set the VDD_PA pin to 0 V. Set the VGG_PA pin to 0 V. Set the CTRL_SW pin to 0 V. Set the VSS_SW pin to 0 V. Set the VDD_SW pin to 0 V. Table 2. J5 and J6 Header Connections to the ADTR1107 Connector J5 J6 Rev. 0 | Page 3 of 6 Header 1 to 5, 7 to 9, 11 to 17, 19, 21, 23, 24 6 10 18 20 22 1 to 5, 7 to 9, 11 to 24 6 10 ADTR1107 Pin GND VDD_LNA VGG_LNA VSS_SW CTRL_SW VDD_SW GND VGG_PA VDD_PA UG-1684 ADTR1107-EVAL User Guide Table 3. Insertion Loss and Input and Output Return Loss of the Through Calibration Path THROUGH PATH INSERTION LOSS Figure 3 shows the data plot in Table 3 of the through calibration path (J7 to J8). -5 INPUT RETURN LOSS INSERTION LOSS OUTPUT RETURN LOSS -10 -15 -20 -25 -30 -35 -40 6 8 10 12 14 FREQUENCY (GHz) 16 18 22147-005 INSERTION LOSS AND RETURN LOSS (dB) 0 Frequency (GHz) 6 6.5 8 8.5 10 10.5 12 12.5 14 14.5 16 16.5 18 Figure 3. Insertion Loss and Return Loss (Input and Output) of the Through Calibration Path Rev. 0 | Page 4 of 6 Insertion Loss (dB) -0.5 -0.5 -0.6 -0.7 -0.8 -0.8 -0.9 -0.9 -1.1 -1.1 -1.1 -1.2 -1.4 ADTR1107-EVAL User Guide UG-1684 EVALUATION BOARD SCHEMATIC AND ARTWORK J5 24 22 20 18 16 14 12 10 8 6 4 2 VGG_LNA VDD_LNA GND EPAD 24 23 22 21 20 19 GND VDD_SW CTRL_SW VSS_SW GND ANT GND GND GND GND ANT 18 17 16 15 14 13 CPLR_OUT 7 8 9 10 11 12 TX_IN GND RX_OUT GND GND ADTR1107 TX_IN GND VGG_PA VDD_PA NIC NIC GND CPLR_OUT 1 2 3 4 5 6 U1 EPAD VDD_LNA VGG_LNA GND VSS_SW CTRL_SW VDD_SW RX_OUT GND J6 24 22 20 18 16 14 12 10 8 6 4 2 R1 DNI R2 DNI VDD_PA VGG_PA J7 J8 GND DNI DNI Figure 4. ADTR1107-EVAL Evaluation Board Schematic GND GND GND GND NC GND CTRLSW GND NC GND VSSSW GND NC GND GND GND GND GND GND GND GND GND GND GND GND GND VGGLNA GND VDDPA GND GND GND GND GND VDDLNA GND VGGPA GND GND GND GND GND GND GND GND GND 22147-004 1 1 GND VDDSW Figure 5. ADTR1107-EVAL Assembly Drawing (J7, J8, R1, and R2 Not Installed) Rev. 0 | Page 5 of 6 23 21 19 17 15 13 11 9 7 5 3 1 GND 22147-003 23 21 19 17 15 13 11 9 7 5 3 1 UG-1684 ADTR1107-EVAL User Guide ORDERING INFORMATION BILL OF MATERIALS Table 4. Reference Designator TX_IN, RX_OUT, ANT, CLPR_OUT J7, J8 J5 and J6 R1 and R2 U1 Not Applicable Description Connectors, Type K, jack edge Connectors, Type K, jack edge, do not install (DNI) PCB connector headers, 24-position male headers, unshrouded double row, surface-mount (SMT), 2.54 mm pitch Thick film resistor chip. DNI IC, transmit/receive module 2.51 inch x 1.9 inch heat sink Manufacturer Winchester Connector Winchester Connector Samtec, Inc. Part Number 25-146-1000-92 25-146-1000-92 TSM-112-01-L-DV Not applicable Analog Devices, Inc. Not applicable Not applicable ADTR1107ACCZ Not applicable ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the "Evaluation Board"), you are agreeing to be bound by the terms and conditions set forth below ("Agreement") unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you ("Customer") and Analog Devices, Inc. ("ADI"), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. 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