DS1086LU-455+T - Maxim Integrated

DS1086L

3.3V Spread-Spectrum EconOscillator

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

General Description

The DS1086L EconOscillator™ is a 3.3V programmable

clock generator that produces a spread-spectrum

(dithered) square-wave output of frequencies from

130kHz to 66.6MHz. The selectable dithered output

reduces radiated-emission peaks by dithering the fre-

quency 0.5%,1%, 2%, 4%, or 8% below the pro-

grammed frequency. The DS1086L has a power-down

mode and an output-enable control for power-sensitive

applications. All the device settings are stored in non-

volatile (NV) EEPROM memory allowing it to operate in

stand-alone applications.

Applications

Printers

Copiers

PCs

Computer Peripherals

Cell Phones

Cable Modems

Features

♦User-Programmable Square-Wave Generator

♦Frequencies Programmable from 130kHz to

66.6MHz

♦0.5%, 1%, 2%, 4%, or 8% Selectable Dithered

Output

♦Adjustable Dither Rate

♦Glitchless Output-Enable Control

♦2-Wire Serial Interface

♦Nonvolatile Settings

♦2.7V to 3.6V Supply

♦No External Timing Components Required

♦Power-Down Mode

♦5kHz Master Frequency Step Size

♦EMI Reduction

♦Industrial Temperature Range: -40°C to +85°C

PDN

OEGND

SCL

SDASPRD

VCC

OUT

SOP

TOP VIEW

DS1086L

Pin Configuration

Ordering Information

XTL1/OSC1

μP

XTL2/OSC2

DITHERED 130kHz TO

66.6MHz OUTPUT

DECOUPLING CAPACITORS

(0.1μF and 0.01μF)

*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS

TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.

SPRD

OUT

VCC

GND

N.C.

SCL*

SDA*

PDN

DS1086L

Typical Operating Circuit

19-6226; Rev 2; 3/12

PART TEMP RANGE PIN-PACKAGE

DS1086LU -40°C to +85°C 8 μSOP (118 mils)

DS1086LU+ -40°C to +85°C 8 μSOP (118 mils)

EconOscillator is a trademark of Maxim Integrated Products, Inc.

Note: Contact the factory for custom settings.

Denotes a lead(Pb)-free/RoHS-compliant package.

3.3V Spread-Spectrum EconOscillator

2 Maxim Integrated

DS1086L

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC (Note 1) 2.7 3.3 3.6 V

High-Level Input Voltage

(SDA, SCL, SPRD, PDN, OE) VIH 0.7 x

VCC

VCC +

0.3 V

Low-Level Input Voltage

(SDA, SCL SPRD, PDN, OE) VIL -0.3 0.3 x

VCC V

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

High-Level Output Voltage (OUT) VOH IOH = -4mA, VCC = min 2.4 V

Low-Level Output Voltage (OUT) VOL IOL = 4mA 0 0.4 V

VOL1 3mA sink current 0 0.4

Low-Level Output Voltage (SDA) VOL2 6mA sink current 0 0.6 V

High-Level Input Current IIH VCC = 3.6V 1 μA

Low-Level Input Current IIL VIL = 0V -1 μA

Supply Current (Active) ICC CL = 15pF (output at default frequency) 10 mA

Standby Current (Power-Down) ICCQ Power-down mode 10 μA

Voltage Range on VCC Relative to Ground ..........-0.5V to +6.0V

Voltage Range on SPRD, PDN, OE, SDA, and SCL

Relative to Ground* ..................................-0.5 to (VCC + 0.5V)

Continuous Power Dissipation (TA= +70°C)

μSOP (derate 4.5mW/°C above +70°C)........................362mW

Operating Temperature Range ...........................-40°C to +85°C

Programming Temperature Range .........................0°C to +70°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-55°C to +150°C

Soldering Temperature (reflow)

Lead(Pb)-free................................................................+260°C

Containing lead(Pb) ......................................................+240°C

This voltage must not exceed 6.0V.

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 3

DS1086L

MASTER OSCILLATOR CHARACTERISTICS

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Master Oscillator Frequency fOSC (Note 2) 33.3 66.6 MHz

Default Master Oscillator Frequency f0Factory-programmed default 48.65 MHz

Default frequency (f0) -0.5 +0.5

Master Oscillator Frequency

Tolerance

Δ f 0

VCC = 3.3V,

TA = +25°C

(Notes 3,17) DAC step size -0.5 +0.5

Default frequency -0.75 +0.75

Voltage Frequency Variation Δ f V

Over voltage range,

TA = +25°C (Note 4) DAC step size -0.75 +0.75 %

Default frequency -2.0 +0.75

66.6MHz -2.0 +0.75Temperature Frequency Variation Δ f T

Over temperature

range, VCC = 3.3V

(Note 5) 33.3MHz -2.5 +0.75

Prescaler bits JS2, JS1, JS0 = 000 0.5

Prescaler bits JS2, JS1, JS0 = 001 1

Prescaler bits JS2, JS1, JS0 = 010 2

Prescaler bits JS2, JS1, JS0 = 100 4

Dither Frequency Range (Note 6) Δ f

Prescaler bits JS2, JS1, JS0 = 111 8

Integral Nonlinearity of Frequency INL Entire range (Note 7) -0.6 +0.3 %

DAC Step Size Δ between two consecutive DAC values

(Note 8) 5 kHz

DAC Span Frequency range for one offset setting

(Table 2) 5.12 MHz

DAC Default Factory default register setting 500 decimal

Offset Step Size Δ between two consecutive offset values

(Table 2) 2.56 MHz

Offset Default OS Factory default OFFSET register setting

(5 LSBs) (Table 2)

RANGE

(5 LSBs of

RANGE register)

hex

Prescaler bits JS4, JS3 = 00 f0/8192

Prescaler bits JS4, JS3 = 01 f0/4096Dither Rate

Prescaler bits JS4, JS3 = 10 f0/2048

3.3V Spread-Spectrum EconOscillator

4 Maxim Integrated

DS1086L

AC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Frequency Stable After Prescaler

Change 1 period

Frequency Stable After DAC or

Offset Change tDACstab (Note 9) 0.1 1 ms

Power-Up Time t

or + tstab (Note 10) 0.1 0.5 ms

Enable of OUT After Exiting

Power-Down Mode tstab (Note 18) 200 μs

OUT High-Z After Entering

Power-Down Mode tpdn 100 μs

Load Capacitance CL(Note 11) 15 50 pF

Output Duty Cycle (OUT) Default frequency 45 55 %

Rise and Fall Time (OE, PDN)1μs

AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Fast mode 400

SCL Clock Frequency fSCL Standard mode (Note 12) 100 kHz

Fast mode 1.3

Bus Free Time Between a STOP

and START Condition tBUF Standard mode (Note 12) 4.7 μs

Fast mode 0.6

Hold Time (Repeated) START

Condition tHD:STA Standard mode (Notes 12, 13) 4.0 μs

Fast mode 1.3

LOW Period of SCL tLOW Standard mode (Note 12) 4.7 μs

Fast mode 0.6

HIGH Period of SCL tHIGH Standard mode (Note 12) 4.0 μs

Fast mode 0.6

Setup Time for a Repeated

START tSU:STA Standard mode (Note 12) 4.7 μs

Fast mode

Data Hold Time tHD:DAT Standard mode (Notes 12, 14, 15) 0 0.9 μs

Fast mode 100

Data Setup Time tSU:DAT Standard mode (Note 12) 250 ns

Fast mode 20 + 0.1CB300

Rise Time of Both SDA and SCL

Signals tRStandard mode (Note 16) 20 + 0.1CB1000 ns

Fast mode 20 + 0.1CB300

Fall Time of Both SDA and SCL

Signals tFStandard mode (Note 16) 20 + 0.1CB1000 ns

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 5

DS1086L

AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued)

(VCC = 2.7V to 3.6V, TA= -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Fast mode 0.6

Setup Time for STOP tSU:STO Standard mode 4.0 μs

Capacitive Load for Each Bus

Line CB(Note 16) 400 pF

EEPROM Write Cycle Time tWR 10 ms

Input Capacitance CI5pF

NONVOLATILE MEMORY CHARACTERISTICS

(VCC = 2.7V to 3.6V)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EEPROM Writes +70°C 10,000

Note 1: All voltages are referenced to ground.

Note 2: DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.

Correct operation of the device is not guaranteed if these limits are exceeded.

Note 3: This is the absolute accuracy of the master oscillator frequency at the default settings.

Note 4: This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at

TA= +25°C.

Note 5: This is the percentage frequency change from the +25°C frequency due to temperature at VCC = 3.3V. The maximum temper-

ature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequen-

cy (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz).

Note 6: The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.

Note 7: The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end-

points (fosc(MIN) to fosc(MAX)) of the range. The error is in percentage of the span.

Note 8: This is true when the prescaler = 1.

Note 9: Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original

value to the new value.

Note 10: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally

introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore

depends on the programmed clock frequency.

Note 11: Output voltage swings can be impaired at high frequencies combined with high output loading.

Note 12: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met.

This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does

stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT =

1000ns + 250ns = 1250ns before the SCL line is released.

Note 13: After this period, the first clock pulse is generated.

Note 14: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

Note 15: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Note 16: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC.

Note 17: Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr

+125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr

max VCC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr

121°C/2 ATM Steam/Unbiased Autoclave.

Note 18: tstab is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of tDACstab

is required before the frequency will be within its specified tolerance.

3.3V Spread-Spectrum EconOscillator

6 Maxim Integrated

DS1086L

Typical Operating Characteristics

(VCC = 3.3V, TA= 25°C, unless otherwise noted.)

SUPPLY CURRENT vs.

MASTER OSCILLATOR FREQUENCY

DS1086L toc01

MASTER FREQUENCY (MHz)

SUPPLY CURRENT (mA)

636036 39 42 48 51 5445 57

33 66

15pF LOAD

4.7pF LOAD

PRESCALER = 1

SUPPLY CURRENT vs. TEMPERATURE

DS1086L toc02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

603510-15

-40 85

fO = 66MHz

fO = 50MHz

fO = 33.3MHz

PRESCALER = 1

15pF LOAD

SUPPLY CURRENT vs. PRESCALER

DS1086L toc03

PRESCALER

SUPPLY CURRENT (mA)

10010

1 1000

fO = 50MHz

15pF LOAD

MASTER OSCILLATOR FREQUENCY PERCENT

CHANGE vs. SUPPLY VOLTAGE

DS1086L toc04

SUPPLY VOLTAGE (V)

PERCENT CHANGET (%)

3.33.0

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5

2.7 3.6

fO = 66MHz

fO = 50MHz

fO = 33.3MHz

PRESCALER = 1

MASTER OSCILLATOR FREQUENCY PERCENT

CHANGE vs. TEMPERATURE

DS1086L toc05

TEMPERATURE (°C)

PERCENT CHANGE (%)

6035-15 10

-1.25

-1.00

-0.75

-0.50

-0.25

0.25

0.50

-1.50

-40 85

fO = 66MHz

fO = 50MHz

fO = 33.3MHz

PRESCALER = 1

15pF LOAD

DUTY CYCLE vs. TEMPERATURE

DS1086L toc06

TEMPERATURE (°C)

DUTY CYCLE (%)

603510-15

-40 85

fO = 66MHz

fO = 50MHz

fO = 33.3MHz

PRESCALER = 1

DUTY CYCLE vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

3.3

3.02.7 3.6

DS1086L toc07

DUTY CYCLE (%)

fO = 66MHz

fO = 50MHz

fO = 33.3MHz

PRESCALER = 1

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 7

DS1086L

POWER-DOWN CURRENT vs. TEMPERATURE

DS1086L toc09

TEMPERATURE (°C)

POWER-DOWN CURRENT (μA)

603510-15

1.46

1.48

1.50

1.52

1.54

1.56

1.58

1.60

1.62

1.64

1.44

-40 85

SUPPLY CURRENT WITH OUTPUT

DISABLED vs. SUPPLY VOLTAGE

DS1086L toc10

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.7 3.6

fO = 66MHz

SUPPLY CURRENT WITH OUTPUT

DISABLED vs. TEMPERATURE

DS1086L toc11

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

603510-15

2.3

2.4

2.5

2.6

2.7

2.2

-40 85

fO = 66MHz

Typical Operating Characteristics (continued)

(VCC = 3.3V, TA= 25°C, unless otherwise noted.)

POWER-DOWN CURRENT vs.

SUPPLY VOLTAGE

DS1086L toc08

SUPPLY VOLTAGE (V)

POWER-DOWN CURRENT (μA)

3.0 3.3

1.1

1.2

1.3

1.4

1.6

1.5

1.7

1.8

1.0

2.7 3.6

3.3V Spread-Spectrum EconOscillator

8 Maxim Integrated

DS1086L

Pin Description

PIN NAME FUNCTION

1 OUT Oscillator Output. The output frequency is determined by the OFFSET, DAC, and prescaler registers.

2 SPRD Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.

CC Power Supply

4 GND Ground

5OE

Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is

disabled but the master oscillator is still on.

6PDN Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master

oscillator is disabled (power-down mode).

7 SDA 2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and

can be wire-ORed with other open-drain or open-collector interfaces.

8 SCL 2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on

falling edges.

DITHERED 260kHz TO

133MHz OUTPUT

DECOUPLING CAPACITORS

(0.1μF and 0.01μF)

SPRD

OUT

VCC

4.7kΩ4.7kΩ

VCC

2-WIRE

INTERFACE

GND

SCL

SDA

PDN

DS1086L

Processor-Controlled Mode

XTL1/OSC1

μP

XTL2/OSC2

DITHERED 130kHz TO

66.6MHz OUTPUT

DECOUPLING CAPACITORS

(0.1μF and 0.01μF)

*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS

TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.

SPRD

OUT

VCC

GND

N.C.

SCL*

SDA*

PDN

DS1086L

Stand-Alone Mode

SPECTRUM COMPARISON

(12OkHz BW, SAMPLE DETECT)

DS1086L fig01

FREQUENCY (MHz)

POWER SPECTRUM (dBm)

51494745

-80

-70

-60

-50

-40

-30

-20

-10

-90

43 53

0.5% NO

SPREAD

fo = 50MHz

DITHER RATE = fo/4096

Figure 1. Clock Spectrum Dither Comparison

MAXIMUM THERMAL VARIATION vs.

MASTER OSCILLATOR FREQUENCY

DS1086L fig02

MASTER FREQUENCY (MHz)

SUPPLY CURRENT (mA)

636036 39 42 48 51 5445 57

-4%

-3%

-2%

-1%

-5%

33 66

Figure 2. Temperature Variation Over Frequency

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 9

DS1086L

Detailed Description

A block diagram of the DS1086L is shown in Figure 3.

The internal master oscillator generates a square wave

with a 33.3MHz to 66.6MHz frequency range. The fre-

quency of the master oscillator can be programmed

with the DAC register over a two-to-one range in 5kHz

steps. The master oscillator range is larger than the

range possible with the DAC step size, so the OFFSET

over which the DAC spans. The prescaler can then be

set to divide the master oscillator frequency by 2x

(where x equals 0 to 8) before routing the signal to the

output (OUT) pin.

A programmable triangle-wave generator injects an off-

set element into the master oscillator to dither its output

0.5%, 1%, 2%, 4%, or 8%. The dither magnitude is con-

trolled by the JS2, JS1, and JS0 bits in the PRESCALER

word and enabled with the SPRD pin. Futhermore, the

dither rate is controlled by the JS4 and JS3 bits in the

PRESCALER word and determines the frequency of the

dither. The maximum spectral attenuation occurs when

the prescaler is set to 1 and is reduced by 2.7dB for

every factor of 2 that is used in the prescaler. This

happens because the prescaler’s divider function tends

to average the dither in creating the lower frequency.

However, the most stringent spectral emission limits are

imposed on the higher frequencies where the prescaler

is set to a low divider ratio.

The external control input, OE, gates the clock output

buffer. The PDN pin disables the master oscillator and

turns off the clock output for power-sensitive applica-

tions*. On power-up, the clock output is disabled until

power is stable and the master oscillator has generated

512 clock cycles. Both controls feature a synchronous

enable that ensures there are no output glitches when

the output is enabled.

The control registers are programmed through a 2-wire

interface and are used to determine the output frequen-

cy and settings. Once programmed into EEPROM,

since the register settings are NV, the settings only

need to be reprogrammed if it is desired to reconfigure

the device.

SDA

VCC

SCL

2-WIRE

INTERFACE

VCC

DAC

OFFSET

EEPROM CONTROL

REGISTERS

PRESCALER

ADDR

RANGE

SPRD

PDN

OUT

DAC

TRIANGLE WAVE

GENERATOR

VOLTAGE-CONTROLLED

OSCILLATOR

PRESCALER

BY 1, 2, 4...256

GND

MASTER

OSCILLATOR

OUTPUT

DITHER SIGNAL

DITHER

CONTROL

FREQUENCY

CONTROL VOLTAGE

DS1086L

Figure 3. Block Diagram

The power-down command must persist for at least two out-

put frequency cycles plus 10μs for deglitching purposes.

3.3V Spread-Spectrum EconOscillator

10 Maxim Integrated

DS1086L

The output frequency is determined by the following

equation:

where:

min frequency of selected OFFSET range

is the

lowest frequency (shown in Table 2 for the correspond-

ing offset).

DAC value

is the value of the DAC register (0 to 1023).

Prescaler

is the value of 2xwhere x = 0 to 8.

See the

Example Frequency Calculations

section for a

more in-depth look at using the registers.

________________Register Definitions

The DS1086L registers are used to program the output

frequency, dither percent, dither rate, and 2-wire

address. Table 1 shows a summary of the registers and

detailed descriptions follow below.

PRESCALER (02h)

The PRESCALER word is a two-byte value containing

control bits for the prescaler (P3 to P0), output control

(Lo/HiZ), the jitter rate (JS4 to JS3), as well as control

bits for the jitter percentage (JS2 to JS0). The

PRESCALER word is read and written using two-byte

reads and writes beginning at address 02h.

JS4 to JS3: Jitter Rate. This is the frequency of the tri-

angle wave generator and the modulation frequency

that the output is dithered. It can be programmed to the

master oscillator frequency, fOSC, divided by either

8192, 4096, or 2048.

JS4 JS3 JITTER RATE

00 f

OSC/8192

01 f

OSC/4096 (default)

10 f

OSC/2048

OUTPUT

MINFREQUENCY OF SELECTED OFFSET(

)

()

RANGE

DAC VALUE kHz STEP SIZE

PRESC

+×5

AALER

OFFSET FREQUENCY RANGE (MHz)

OS - 6 30.74 to 35.86

OS - 5 33.30 to 38.42

OS - 4 35.86 to 40.98

OS - 3 38.42 to 43.54

OS - 2 40.98 to 46.10

OS - 1 43.54 to 48.66

OS* 46.10 to 51.22

OS + 1 48.66 to 53.78

OS + 2 51.22 to 56.34

OS + 3 53.78 to 58.90

OS + 4 56.34 to 61.46

OS + 5 58.90 to 64.02

OS + 6 61.46 to 66.58

Factory default setting. OS is the integer value of the five LSBs

of the RANGE register.

DEFAULT ACCESS

PRESCALER 02h JS4 JS3 JS2 JS1 JS0 LO/HiZ P3 P2 0 1 1 0 0 0 0 0 R/W

PRESCALER — P1 P0 XXXXXXXXXXXX0 0 X X X X X R/W

DAC (MSB) 08h b9 b8 b7 b6 b5 b4 b3 b2 01111101b R/W

DAC (LSB) — b1 b0 X0X0X0X0X0X000000000b R/W

OFFSET 0Eh X1X1X1b4 b3 b2 b1 b0 1 1 1 - - - - - b R/W

ADDR 0Dh X1X1X1X1WC A2 A1 A0 11110000b R/W

RANGE 37h XXXXXXb4 b3 b2 b1 b0 x x x - - - - - b R

WRITE EE 3Fh NO DATA ——

Table 1. Register Summary

X0= Don’t care, reads as zero.

X1= Don’t care, reads as one.

XX= Don’t care, reads indeterminate.

X = Don’t care.

Table 2. Offset Settings

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 11

DS1086L

JS2 to JS0: Jitter Percentage. These three bits select

the amount of jitter in percent. The SPRD pin must be a

logic high for the jitter to be enabled. Bit combinations

not shown are reserved.

Lo/HiZ: Output Low or High-Z. This bit determines the

state of the output pin when the device is in power-

down mode or when the output is disabled. If Lo/HiZ =

0, the output is HiZ when in power-down or disabled. If

Lo/HiZ = 1, the output is held low when in power-down

or disabled.

P3 to P0: Prescaler Divider. These bits divide the

master oscillator frequency by 2x, where x is P3 to P0

and can be from 0 to 8. Any prescaler value entered

greater than 8 decodes as 8.

DAC (08h)

B9 to B0: DAC Setting. The DAC word sets the master

oscillator frequency to a specific value within the cur-

rent offset range. Each step of the DAC changes the

master oscillator frequency by 5kHz. The DAC word is

read and written using two-byte reads and writes

beginning at address 08h.

OFFSET (0Eh)

B4 to B0: Offset. This value selects the master oscilla-

tor frequency range that can be generated by varying

the DAC word. Valid frequency ranges are shown in

Table 2. Correct operation of the device is not guaran-

teed for values of OFFSET not shown in the table.

The default offset value (OS) is factory trimmed and

can vary from device to device. Therefore, to change

frequency range, OS must be read so the new offset

value can be calculated relative to the default. For

example, to generate a master oscillator frequency

within the largest range (61.4MHz to 66.6MHz), Table 2

indicates that the OFFSET must be programmed to OS

+ 6. This is done by reading the RANGE register and

adding 6 to the value of bits B4 to B0. The result is then

written into bits B4 to B0 of the OFFSET register.

Additional examples are provided in the

Example

Frequency Calculations

section.

RANGE (37h)

B4 to B0: Range: This read-only, factory programmed

value is a copy of the factory default offset (OS). OS is

required to program new master oscillator frequencies

shown in Table 2. The read-only backup is important

because the offset register is EEPROM and is likely to

be overwritten.

ADDR (0Dh)

WC: EEPROM Write Control Bit. The WC bit

enables/disables the automatic writing of registers to

EEPROM. This prevents EEPROM wear out and elimi-

nates the EEPROM write cycle time. If WC = 0 (default),

WC = 1, register writes are stored in SRAM and only

written into EEPROM when the user sends a WRITE EE

command. If power is cycled to the device, then the

last value stored in EEPROM is recalled. WC = 1 is

ideal for applications that frequently modify the fre-

quency/registers.

Regardless of the value of the WC bit, the value of the

ADDR register is always written immediately to EEPROM.

A2 to A0: Device Address Bits. These bits determine

the 2-wire slave address of the device. They allow up to

eight devices to be attached to the same 2-wire bus

and to be addressed individually.

WRITE EE Command (3Fh)

This command can be used when WC = 1 (see the WC

bit in ADDR register) to transfer all registers from SRAM

into EEPROM. The time required to store the values is

one EEPROM write cycle time. This command is not

needed if WC = 0.

JS2 JS1 JS0 JITTER %

0000.5

001 1

010 2

100 4

111 8

3.3V Spread-Spectrum EconOscillator

12 Maxim Integrated

DS1086L

Example Frequency Calculations

Example #1:

Calculate the register values needed to

generate a desired output frequency of 11.0592MHz.

Since the desired frequency is not within the valid mas-

ter oscillator range of 33.3MHz to 66.6MHz, the

prescaler must be used. Valid prescaler values are 2x

where x equals 0 to 8 (and x is the value that is pro-

grammed into the P3 to P0 bits of the PRESCALER reg-

ister). Equation 1 shows the relationship between the

desired frequency, the master oscillator frequency, and

the prescaler.

By trial and error, x is incremented from 0 to 8 in

Equation 2, finding values of x that yield master oscillator

frequencies within the range of 33.3MHz to 66.6MHz.

Equation 2 shows that a prescaler of 4 (x = 2) and a

master oscillator frequency of 44.2368MHz generates

our desired frequency. Writing 0080h to the

PRESCALER register sets the PRESCALER to 4. Be

aware that other settings also reside in the PRESCALER

fMASTER OSCILLATOR = fDESIRED x prescaler = fDESIRED x 2X

fMASTER OSCILLATOR = 11.0592MHz x 22= 44.2368MHz

Once the target master oscillator frequency has been

calculated, the value of offset can be determined.

Using Table 2, 44.2368MHz falls within both OS - 1 and

OS - 2. However, choosing OS - 1 would be a poor

choice since 44.2368MHz is so close to OS - 1’s mini-

mum frequency. On the other hand, OS - 2 is ideal

since 44.2368MHz is close to the center of

OS - 2’s frequency span. Before the OFFSET register

can be programmed, the default value of offset (OS)

must be read from the RANGE register (last five bits). In

this example, 12h (18 decimal) was read from the

RANGE register. OS - 2 for this case is 10h (16 deci-

mal). This is the value that is written to the OFFSET reg-

ister.

Finally, the two-byte DAC value needs to be deter-

mined. Since OS - 2 only sets the range of frequencies,

the DAC selects one frequency within that range as

shown in Equation 3.

fMASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET

RANGE) + (DAC value x 5kHz)

Valid values of DAC are 0 to 1023 (decimal) and 5kHz

is the step size. Equation 4 is derived from rearranging

Equation 3 and solving for the DAC value.

Since the two-byte DAC register is left justified, 647 is

converted to hex (0287h) and bit-wise shifted left six

places. The value to be programmed into the DAC reg-

ister is A1C0h.

In summary, the DS1086L is programmed as follows:

PRESCALER = 0080h

OFFSET = OS - 2 or 10h (if range was read as 12h)

DAC = A1C0h

Notice that the DAC value was rounded. Unfortunately,

this means that some error is introduced. To calculate

how much error, a combination of Equation 1 and

Equation 3 is used to calculate the expected output fre-

quency. See Equation 5.

MIN FREQUENCY OF SELECTED OFFSET

OUTPUT

(

=)( )RANGE DAC VALUE x kHz STEP SIZE

pres

ccaler

fMHz x kHz

OUTPUT

(. )( )

=+41 0 647 5

4==

44 235

411 05875

MHz MHz

DAC VALUE

MIN FREQU

MASTER OSCILLATOR

(

−

EENCY OF SELECTED

OFFSET RANGE

kHz STEP SI

)

5ZZE

DAC VALUE MHz MHz

kHz S

(. . )

=−44 2368 41 0

5TTEP SIZE

decimal.()=≈647 36 647

prescaler

DESIRED MASTER OSCILLATOR

AASTER OSCILLATOR

(1)

(4)

(2)

(3)

(5)

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 13

DS1086L

The expected output frequency is not exactly equal to the

desired frequency of 11.0592MHz. The difference is

450Hz. In terms of percentage, Equation 6 shows that the

expected error is 0.004%. The expected error assumes

typical values and does not include deviations from the

typical as specified in the electrical tables.

Example #2:

Calculate the register values needed to

generate a desired output frequency of 50MHz.

Since the desired frequency is already within the valid

master oscillator frequency range, the prescaler is set

to divide by 1, and hence, PRESCALER = 0000h

(currently ignoring the other setting).

fMASTER OSCILLATOR = 50.0MHz x 20= 50.0MHz

Next, looking at Table 2, OS + 1 provides a range of

frequencies centered around the desired frequency. To

determine what value to write to the OFFSET register,

the RANGE register must first be read. Assuming 12h

was read in this example, 13h (OS + 1) is written to the

OFFSET register.

Finally, the DAC value is calculated as shown in

Equation 8.

The result is then converted to hex (0118h) and then

left-shifted, resulting in 4600h to be programmed into

the DAC register.

In summary, the DS1086L is programmed as follows:

PRESCALER = 0000h

OFFSET = OS + 1 or 13h (if RANGE was read as 12h)

DAC = 4600h

Since the expected output frequency is equal to the

desired frequency, the calculated error is 0%.

fMHz kHz

OUTPUT

(. )( )

=+× =

48 6 280 5

50 0

MMHz MHz

150 0.=

DAC VALUE MHz MHz

kHz STEP SI

(. . )

=−50 0 48 6

5ZZE decimal.( )=280 00

%ERROR ff

EXPECTED DESIRED EXPECTED

DESIR

=−

EED

EXPECTED

ERROR MHz

%..

=−

100

11 0592 11 055875

11 0592 100

450

11 0592

MHz

=×.%100 0 004=

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12 678 9 12 893–7

Figure 4. 2-Wire Data Transfer Protocol

(6)

(7)

(8)

(9)

3.3V Spread-Spectrum EconOscillator

14 Maxim Integrated

DS1086L

_______2-Wire Serial Port Operation

2-Wire Serial Data Bus

The DS1086L communicates through a 2-wire serial

interface. A device that sends data onto the bus is

defined as a transmitter, and a device receiving data

as a receiver. The device that controls the message is

called a “master.” The devices that are controlled by

the master are “slaves.” A master device that generates

the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions must con-

trol the bus. The DS1086L operates as a slave on the 2-

wire bus. Connections to the bus are made through the

open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (see

Figures 4 and 6):

• Data transfer can be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH are

interpreted as control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data

line, from HIGH to LOW, while the clock is HIGH,

defines a START condition.

Stop data transfer: A change in the state of the data

line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

Data valid: The state of the data line represents valid

data when, after a START condition, the data line is sta-

ble for the duration of the HIGH period of the clock sig-

nal. The data on the line must be changed during the

LOW period of the clock signal. There is one clock

pulse per bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

SDA

SCL

tHD:STA

tLOW

tHIGH

tRtF

tBUF

tHD:DAT

tSU:DAT REPEATED

START

tSU:STA

tHD:STA

tSU:STO

tSP

STOP START

Figure 6. 2-Wire AC Characteristics

MSB

DEVICE

IDENTIFIER

DEVICE

ADDRESS

READ/WRITE BIT

1 0 1 1 A2 A1 A0 R/W

LSB

Figure 5. Slave Address

3.3V Spread-Spectrum EconOscillator

Maxim Integrated 15

DS1086L

data bytes transferred between START and STOP con-

ditions is not limited, and is determined by the master

device. The information is transferred byte-wise and

each receiver acknowledges with a ninth bit.

Within the bus specifications a standard mode (100kHz

clock rate) and a fast mode (400kHz clock rate) are

defined. The DS1086L works in both modes.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowledge

after the byte has been received. The master device

must generate an extra clock pulse that is associated

with this acknowledge bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable LOW during the HIGH period

of the acknowledge-related clock pulse. Of course,

setup and hold times must be taken into account.

When the DS1086L EEPROM is being written to, it is

not able to perform additional responses. In this case,

the slave DS1086L sends a not acknowledge to any

data transfer request made by the master. It resumes

normal operation when the EEPROM operation is com-

plete.

A master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has

been clocked out of the slave. In this case, the slave

must leave the data line HIGH to enable the master to

generate the STOP condition.

Figures 4, 5, 6, and 7 detail how data transfer is

accomplished on the 2-wire bus. Depending upon the

state of the R/Wbit, two types of data transfer are pos-

sible:

1) Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master

is the slave address. Next follows a number of

data bytes. The slave returns an acknowledge bit

after each received byte.

2) Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is

transmitted by the master. The slave then returns

an acknowledge bit. Next follows a number of

data bytes transmitted by the slave to the master.

The master returns an acknowledge bit after all

received bytes other than the last byte. At the end

of the last received byte, a not acknowledge is

returned.

The master device generates all the serial clock pulses

and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START

condition. Since a repeated START condition is also the

beginning of the next serial transfer, the bus is not

released.

The DS1086L can operate in the following two modes:

Slave receiver mode: Serial data and clock are

received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START

and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is per-

formed by hardware after reception of the slave

address and direction bit.

Slave transmitter mode: The first byte is received and

handled as in the slave receiver mode. However, in this

mode, the direction bit indicates that the transfer direc-

tion is reversed. Serial data is transmitted on SDA by

the DS1086L while the serial clock is input on SCL.

START and STOP conditions are recognized as the

beginning and end of a serial transfer.

Slave Address

Figure 5 shows the first byte sent to the device. It

includes the device identifier, device address, and the

R/Wbit. The device address is determined by the

ADDR register.

Registers/Commands

See Table 1 for the complete list of registers/com-

mands and Figure 7 for an example of using them.

__________Applications Information

Power-Supply Decoupling

To achieve the best results when using the DS1086L,

decouple the power supply with 0.01μF and 0.1μF

high-quality, ceramic, surface-mount capacitors.

Surface-mount components minimize lead inductance,

which improves performance, and ceramic capacitors

tend to have adequate high-frequency response for

decoupling applications. These capacitors should be

placed as close to pins 3 and 4 as possible.

Stand-Alone Mode

SCL and SDA cannot be left unconnected when they

are not used. If the DS1086L never needs to be pro-

grammed in-circuit, including during production test-

ing, SDA and SCL can be tied high. The SPRD pin

must be tied either high or low.

3.3V Spread-Spectrum EconOscillator

16 Maxim Integrated

DS1086L

SLAVE

ACK

10 1

1R/WA0*A1* SLAVE

ACK

A2*

MSB LSB

DEVICE IDENTIFIER DEVICE

ADDRESS

READ/

WRITE

MSB LSB

COMMAND/REGISTER ADDRESS

SLAVE

ACK

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0 SLAVE

ACK STOP

*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST

MATCH THE ADDRESS SET IN THE ADDR REGISTER.

DATA

TYPICAL 2-WIRE WRITE TRANSACTION

EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)

A) SINGLE BYTE WRITE

-WRITE OFFSET REGISTER

B) SINGLE BYTE READ

-READ OFFSET REGISTER

C) TWO BYTE WRITE

-WRITE DAC REGISTER

D) TWO BYTE READ

-READ DAC REGISTER

START

B0h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

0Eh

08h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

DATA

SLAVE

ACK STOP

OFFSET10110000

10110000

10110000 10110001

REPEATED

START

SLAVE

ACK DAC MSB MASTER

ACK DAC LSB

DATA

MASTER

NACK STOP

DATA

B1h

b7 b6 b5 b4 b3 b2 b1 b0

00001110

00001000

REPEATED

START

DATA

OFFSET MASTER

NACK STOP

SLAVE

ACK

10110001

B1h

STOP

SLAVE

ACK

DAC LSB

DATA

SLAVE

ACK

DAC MSB

DATA

Figure 7. 2-Wire Transactions

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

SUBSTRATE CONNECTED TO GROUND

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

8 μSOP U8+1 21-0036 90-0092

3.3V Spread-Spectrum EconOscillator

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

DS1086L

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 11/03 Initial release 

1 9/07 Updated Table 2 10

2 3/12

Updated the Ordering Information,Absolute Maximum Ratings, and Package

Information 1, 2, 16

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Maxim Integrated:

DS1086LU+T DS1086LU-12F+ DS1086LU-12F+T DS1086LU-21D+ DS1086LU-21D+T DS1086LU-455+

DS1086LU-455+T DS1086LU-533+ DS1086LU-533+T DS1086LU-834+ DS1086LU-834+T&R DS1086LU-8CL+

DS1086LU-8CL+T DS1086LU-A12+ DS1086LU-A12+T DS1086LU-B66+ DS1086LU-B66+T DS1086LU-C01+

DS1086LU-C01+T DS1086LU-C02+ DS1086LU-C02+T DS1086LU+C66 DS1086LU-8CL DS1086LU-222+

DS1086LU-222+T DS1086LU+ DS1086LU-440/V+ DS1086LU-440/V+T DS1086LU-440+ DS1086LU-527+

DS1086LU-527+T DS1086LU-455/T+W