Application Note 350
2 of 6 102999
NEW PIN DEFINITIONS FOR DS2152/54 AND DS21352/354/552/554 SCTs
(DS2152/54 ONLY APPLY TO PINS 61 AND 83) Table 4
PIN PREVIOUS
SYMBOL NEW
SYMBOL TYPE DESCRIPTION
76 NC FMS I Framer Mode Select [FMS]. Selects the
DS2152/54 mode when HIGH or the DS21x52/x54
mode when LOW. If High, the JTRST is internally
pulled LOW. If LOW, JTRST has normal JTAG
functionality. This pin has a 10k pull up resistor.
5NC JTRSTIIEEE 1149.1 Test Reset [JTRST]. This signal is used
to asynchronously reset the test access port controller.
At power up, JTRST must be toggled from LOW to
HIGH. This action will set the device into the
DEVICE ID mode allowing normal device operation.
This pin has a 10k pull up resistor. When FMS=1, this
pin is tied LOW internally. Tie JTRST LOW if JTAG
is not used and the framer is in DS21x5y mode (FMS
LOW).
2NC JTMSIIEEE 1149.1 Test Mode Select [JTMS]. This pin is
sampled on the rising edge of JTCLK and is used to
place the test access port into the various defined IEEE
1149.1 states. This pin has a 10k pull up resistor.
4NC JTCLKIIEEE 1149.1 Test Clock Signal [JTCLK]. This
signal is used to shift data into JTDI on the rising edge
and out of JTDO on the falling edge.
7NC JTDIIIEEE 1149.1 [JTDO]. Test instructions and data are
clocked into this pin on the rising edge of JTCLK. This
pin has a 10k pull up resistor.
10 NC JTDO O IEEE 1149.1 [JTDO]. Test instructions and data are
clocked out of this pin on the falling edge of JTCLK.
If not used, this pin should be left unconnected.
36 NC CI I Carry In [CI]. Input. A rising edge on this pin causes
RSER and RSIG to come out of HIGH Z state and
TSER and TSIG to start sampling on the next rising
edge of RSYSCLK/TSYSCLK beginning an I/O
sequence of 8 or 256 bits of data.
54 NC CO O Carry Out [CO]. An output which is set HIGH when
the last bit of the 8 or 256 IBO output sequence has
occurred on RSER and RSIG.
INTERLEAVED PCM BUS OPERATION (IBO)
The new DS21352/354/552/554 SCTs have a feature which will allow multiple SCTs to share a PCM bus
for data or signaling. This is possible by internally gating the RSYSCLK and TSYSCLK inputs on the
SCTs. When this feature is enabled 2 or 4 SCTs can share a 4.096 MHz or 8.192 MHz bus respectively.
There are 4 register bits and two hardware pins which control the Interl eaved Bus Operation ( IBO). Usin g
the IBO, the user must first set the IBOEN bit to a logic 1. Then select the byte or frame interleave mode
via the INTSEL bit. MSEL1 and MSEL2 together determine both the slave or master mode for that
specific SCT and how many SCTs are being multiplexed together. Two devices will require a 4.096 MHz
clock to be applied to RSYSCLKs and TSYSCLKs while four devices will require an 8.192 MHz clock.