AD7190WBRUZ - ANALOG DEVICES - Datasheet.Directory

4.8 kHz Ultralow Noise 24-Bit

Sigma-Delta ADC with PGA

Data Sheet AD7190

Rev. C Document Feedback

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FEATURES

RMS noise: 8.5 nV @ 4.7 Hz (gain = 128)

16 noise free bits @ 2.4 kHz (gain = 128)

Up to 22.5 noise free bits (gain = 1)

Offset drift: 5 nV/°C

Gain drift: 1 ppm/°C

Specified drift over time

2 differential/4 pseudo differential input channels

Automatic channel sequencer

Programmable gain (1 to 128)

Output data rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

4 general-purpose digital outputs

Power supply

AVDD: 4.75 V to 5.25 V

DVDD: 2.7 V to 5.25 V

Current: 6 mA

Temperature range: –40°C to +105°C

Interface

3-wire serial

SPI, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

Qualified for automotive applications

APPLICATIONS

Weigh scales

Strain gauge transducers

Pressure measurement

Temperature measurement

Chromatography

PLC/DCS analog input modules

Data acquisition

Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7190 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise,

24-bit sigma-delta (∑-Δ) analog-to-digital converter (ADC).

The on-chip low noise gain stage means that signals of small

amplitude can be interfaced directly to the ADC.

The device can be configured to have two differential inputs or

four pseudo differential inputs. The on-chip channel sequencer

allows several channels to be enabled, and the AD7190

sequentially converts on each enabled channel. This simplifies

communication with the part. The on-chip 4.92 MHz clock can

be used as the clock source to the ADC or, alternatively, an

external clock or crystal can be used. The output data rate from

the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter

affects the rms noise/noise-free resolution at the programmed

output data rate, the settling time, and the 50 Hz/60 Hz

rejection. For applications that require all conversions to be

settled, the AD7190 includes a zero latency feature.

The part operates with 5 V analog power supply and a digital

power supply from 2.7 V to 5.25 V. It consumes a current of

6 mA. It is housed in a 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

DGND REFIN1(+) REFIN1(–)

AIN1

AIN2

AIN3

AIN4

INCOM

BPDSW

AGND

AD7190

REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

TEMP

SENSOR

CLOCK

CIRCUITRY

DOUT/RDY

DIN

SCLK

SYNC

AGND

Σ-∆

ADC

PGA

MUX

07640-001

Figure 1.

AD7190 Data Sheet

Rev. C | Page 2 of 40

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 7

Circuit and Timing Diagrams ..................................................... 7

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

RMS Noise and Resolution ............................................................ 15

Sinc4 Chop Disabled ................................................................... 15

Sinc3 Chop Disabled ................................................................... 16

Sinc4 Chop Enabled .................................................................... 17

Sinc3 Chop Enabled .................................................................... 18

On-Chip Registers .......................................................................... 19

Communications Register ......................................................... 19

Status Register ............................................................................. 20

Mode Register ............................................................................. 20

Configuration Register .............................................................. 22

Data Register ............................................................................... 24

ID Register ................................................................................... 24

GPOCON Register ..................................................................... 24

Offset Register ............................................................................. 25

Full-Scale Register ...................................................................... 25

ADC Circuit Information .............................................................. 26

Overview ..................................................................................... 26

Filter, Output Data Rate, Settling Time ................................... 26

Digital Interface .......................................................................... 29

Circuit Description......................................................................... 33

Analog Input Channel ............................................................... 33

PGA .............................................................................................. 33

Bipolar/Unipolar Configuration .............................................. 33

Data Output Coding .................................................................. 33

Clock ............................................................................................ 33

Burnout Currents ....................................................................... 34

Reference ..................................................................................... 34

Reference Detect ......................................................................... 34

Reset ............................................................................................. 34

System Synchronization ............................................................ 35

Temperature Sensor ................................................................... 35

Bridge Power-Down Switch ...................................................... 35

Logic Outputs ............................................................................. 35

Enable Parity ............................................................................... 36

Calibration ................................................................................... 36

Grounding and Layout .............................................................. 37

Applications Information .............................................................. 38

Weigh Scales ................................................................................ 38

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

Automotive Products ................................................................. 39

REVISION HISTORY

2/13—Rev. B to Rev. C

Added Automotive Information (Throughout) ........................... 1

Added Automotive Specifications, Table 1 .................................... 3

Changes to Ordering Guide .......................................................... 39

5/09—Rev. A to Rev. B

Changes to Table 3 ............................................................................ 9

5/09—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 3

Changes to Table 3 and Table 4 ....................................................... 9

Changes to Table 5 .......................................................................... 10

Changes to Table 6 and Table 7 ..................................................... 15

Changes to Status Register Section .............................................. 20

Changes to Table 17 ........................................................................ 21

Changes to Table 19 ........................................................................ 23

Changes to Table 20 ....................................................................... 24

Added ID Register Section ............................................................ 24

Changes to Table 21 ....................................................................... 25

Changes to Filter, Output Data Rate, Settling Time Section .... 26

Changes to Continuous Conversion Mode Section ................... 31

Changes to Analog Input Channel and Bipolar/Unipolar

Configuration Sections .................................................................. 33

Changes to Burnout Currents, Reference, Reference Detect, and

Reset Sections .................................................................................. 34

Changes to Temperature Sensor Section ..................................... 35

Changes to Calibration Section .................................................... 36

Changes to Grounding and Layout Section ................................ 37

Changes to Weigh Scales Section ................................................. 38

Changes to Ordering Guide .......................................................... 39

10/08—Revision 0—Initial Version

Data Sheet AD7190

Rev. C | Page 3 of 40

SPECIFICATIONS

AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, REFINx(+) = AVDD , REFINx(−) = AGND, MCLK = 4.92 MHz,

TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter AD7190B Unit Test Conditions/Comments1

ADC

Output Data Rate 4.7 to 4800 Hz nom Chop disabled.

1.17 to 1200 Hz nom Chop enabled, sinc4 filter.

1.56 to 1600 Hz nom Chop enabled, sinc3 filter.

No Missing Codes2 24 Bits min FS > 1, sinc4 filter3.

24 Bits min FS > 4, sinc3 filter3.

Resolution See the RMS Noise and

Resolution section

RMS Noise and Output Data Rates See the RMS Noise and

Resolution section

Integral Nonlinearity

B Grade ±5 ppm of FSR max ±1 ppm typical, gain = 1.

±15 ppm of FSR max ±5 ppm typical, gain > 1.

WB Grade ±7 ppm of FSR max ±1 ppm typical, gain = 1.

±30 ppm of FSR max ±5 ppm typical, gain > 1.

Offset Error4, 5 ±75/gain μV typ Chop disabled.

±0.5 μV typ Chop enabled.

Offset Error Drift vs. Temperature5 ±100/gain nV/°C typ Gain = 1 to 16. chop disabled.

±5 nV/°C typ Gain = 32 to 128. chop disabled.

±5 nV/°C typ Chop enabled.

Offset Error Drift vs. Time 25 nV/1000 hours typ Gain ≥ 32.

Gain Error4

B Grade ±0.005 % max ±0.001 % typical, gain = 1, TA = 25°C,

AVDD = 5 V6.

WB Grade ±0.0075 % max ±0.001 % typical, gain = 1, TA = 25°C,

AVDD = 5 V6.

±0.0075 % typ Gain > 1, post internal full-scale calibration.

Gain Drift vs. Temperature ±1 ppm/°C typ

Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1.

Power Supply Rejection 95 dB typ Gain = 1, VIN = 1 V.

B Grade 100 dB min Gain > 1, VIN = 1 V/gain. 110 dB typical.

WB Grade 95 dB min Gain > 1, VIN = 1 V/gain. 110 dB typical.

Common-Mode Rejection

@ DC 100 dB min Gain = 1, VIN = 1 V2.

110 dB min Gain > 1, VIN = 1 V/gain.

@ 50 Hz, 60 Hz2 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz, 60 Hz2 120 dB min

50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz

(60 Hz output data rate).

Normal Mode Rejection2

Sinc4 Filter

Internal Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

74 dB min

50 Hz output data rate, REJ607 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz.

@ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz.

AD7190 Data Sheet

Rev. C | Page 4 of 40

Parameter AD7190B Unit Test Conditions/Comments1

External Clock

@ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

82 dB min

50 Hz output data rate, REJ607 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz.

@ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz.

Sinc3 Filter

Internal Clock

@ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

60 dB min

50 Hz output data rate, REJ60 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 70 dB min 50 Hz output data rate, 50 ± 1 Hz.

@ 60 Hz 70 dB min 60 Hz output data rate, 60 ± 1 Hz.

External Clock

@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

67 dB min

50 Hz output data rate, REJ607 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 95 dB min 50 Hz output data rate, 50 ± 1 Hz.

@ 60 Hz 95 dB min 60 Hz output data rate, 60 ± 1 Hz.

ANALOG INPUTS

Differential Input Voltage Ranges ±VREF/gain V nom VREF = REFINx(+) − REFINx(−),

gain = 1 to 128.

±(AVDD – 1.25 V)/gain V min/max Gain > 1.

Absolute AIN Voltage Limits2

Unbuffered Mode AGND − 50 mV V min

AVDD + 50 mV V max

Buffered Mode AGND + 250 mV V min

AVDD − 250 mV V max

Analog Input Current

Buffered Mode

Input Current2 ±2 nA max Gain = 1.

±3 nA max Gain > 1.

Input Current Drift ±5 pA/°C typ

Unbuffered Mode

Input Current ±5 μA/V typ Gain = 1, input current varies with input

voltage.

±1 μA/V typ Gain > 1.

Input Current Drift ±0.05 nA/V/°C typ External clock.

±1.6 nA/V/°C typ Internal clock.

REFERENCE INPUT

REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−).

Reference Voltage Range2 1 V min

AVDD V max The differential input must be limited to

± (AVDD – 1.25 V)/gain when gain > 1.

Absolute REFIN Voltage Limits2 AGND – 50 mV V min

AVDD + 50 mV V max

Average Reference Input Current 7 μA/V typ

Average Reference Input Current

Drift

±0.03 nA/V/°C typ External clock.

1.3 nA/V/°C typ Internal clock.

Data Sheet AD7190

Rev. C | Page 5 of 40

Parameter AD7190B Unit Test Conditions/Comments1

Normal Mode Rejection2 Same as for analog inputs

Common-Mode Rejection 95 dB typ

Reference Detect Levels 0.3 V min

0.6 V max

TEMPERATURE SENSOR

Accuracy ±2 °C typ Applies after user calibration at 25°C.

Sensitivity 2815 Codes/°C typ Bipolar mode.

BRIDGE POWER-DOWN SWITCH

RON 10 Ω max

Allowable Current2 30 mA max Continuous current.

BURNOUT CURRENTS

AIN Current 500 nA nom Analog inputs must be buffered and chop

disabled.

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH2 4 V min AVDD = 5V, ISOURCE = 200 μA.

Output Low Voltage, VOL2 0.4 V max AVDD = 5V, ISINK = 800 μA.

Floating-State Leakage Current ±100 nA max

Floating-State Output

Capacitance

10 pF typ

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 4.92 ± 4% MHz min/max

Duty Cycle 50:50 % typ

External Clock/Crystal2

Frequency 4.9152 MHz nom

2.4576/5.12 MHz min/max

Input Low Voltage, VINL 0.8 V max DVDD = 5 V.

0.4 V max DVDD = 3 V.

Input High Voltage, VINH 2.5 V min DVDD = 3 V.

3.5 V min DVDD = 5 V.

Input Current ±10 μA max

LOGIC INPUTS

Input High Voltage, VINH2 2 V min

Input Low Voltage, VINL2 0.8 V max

Hysteresis2 0.1/0.25 V min/V max

Input Currents ±10 μA max

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, VOH2 DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA.

Output Low Voltage, VOL2 0.4 V max DVDD = 3 V, ISINK = 100 μA.

Output High Voltage, VOH2 4 V min DVDD = 5 V, ISOURCE = 200 μA.

Output Low Voltage, VOL2 0.4 V max DVDD = 5 V, ISINK = 1.6 mA.

Floating-State Leakage Current ±10 μA max

Floating-State Output

Capacitance

10 pF typ

Data Output Coding Offset binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V max

Zero-Scale Calibration Limit −1.05 × FS V min

Input Span 0.8 × FS V min

2.1 × FS V max

AD7190 Data Sheet

Rev. C | Page 6 of 40

Parameter AD7190B Unit Test Conditions/Comments1

POWER REQUIREMENTS8

Power Supply Voltage

AVDD − AGND 4.75/5.25 V min/max

DVDD − DGND 2.7/5.25 V min/max

Power Supply Currents

AIDD Current 1 mA max 0.85 mA typical, gain = 1, buffer off.

1.3 mA max 1.1 mA typical, gain = 1, buffer on.

B Grade 4.5 mA max 3.5 mA typical, gain = 8, buffer off.

4.75 mA max 4 mA typical, gain = 8, buffer on.

6.2 mA max 5 mA typical, gain = 16 to 128, buffer off.

6.75 mA max 5.5 mA typical, gain = 16 to 128, buffer on.

WB Grade 5 mA max 3.5 mA typical, gain = 8, buffer off.

5.3 mA max 4 mA typical, gain = 8, buffer on.

6.8 mA max 5 mA typical, gain = 16 to 128, buffer off.

7.4 mA max 5.5 mA typical, gain = 16 to 128, buffer on.

DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V.

0.6 mA max 0.5 mA typical, DVDD = 5 V.

1.5 mA typ External crystal used.

IDD (Power-Down Mode)

B Grade 2 μA max

WB Grade 5 μA max

1 Temperature range: TMIN = −40°C, TMAX = +105°C.

2 Specification is not production tested but is supported by characterization data at initial product release.

3 FS = decimal equivalent of Bit FS9 to Bit FS0 in the mode register.

4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

5 The analog inputs are configured for differential mode.

6 Applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).

7 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.

8 Digital inputs equal to DVDD or DGND.

Data Sheet AD7190

Rev. C | Page 7 of 40

TIMING CHARACTERISTICS

AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless

otherwise noted.

Table 2.

Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments1, 2

t3 100 ns min SCLK high pulse width

t4 100 ns min SCLK low pulse width

READ OPERATION

t1 0 ns min CS falling edge to DOUT/RDY active time

60 ns max DVDD = 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t23 0 ns min SCLK active edge to data valid delay4

ns max

= 4.75 V to 5.25 V

80 ns max DVDD = 2.7 V to 3.6 V

t55, 6 10 ns min Bus relinquish time after CS inactive edge

80 ns max

t6 0 ns min SCLK inactive edge to CS inactive edge

t7 10 ns min SCLK inactive edge to DOUT/RDY high

WRITE OPERATION

t8 0 ns min CS falling edge to SCLK active edge setup time4

ns min

Data valid to SCLK edge setup time

t10 25 ns min Data valid to SCLK edge hold time

t11 0 ns min CS rising edge to SCLK edge hold time

1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2 See Figure 3 and Figure 4.

3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4 The SCLK active edge is the falling edge of SCLK.

5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY

is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the

digital word can be read only once.

CIRCUIT AND TIMING DIAGRAMS

ISINK (1.6mA WIT H DVDD = 5V ,

100µA W ITH DVDD = 3V)

ISOURCE (200µA WI TH DVDD = 5V,

100µA W ITH DVDD = 3V)

1.6V

OUTPUT

PIN 50pF

07640-002

Figure 2. Load Circuit for Timing Characterization

AD7190 Data Sheet

Rev. C | Page 8 of 40

CS (I)

DOUT/RDY ( O)

SCL K ( I)

I = INPUT, O = OUTPUT

MSB LSB

07640-003

Figure 3. Read Cycle Timing Diagram

I = INPUT, O = OUTPUT

CS (I)

SCL K ( I)

DIN ( I) MSB LSB

07640-004

Figure 4. Write Cycle Timing Diagram

Data Sheet AD7190

Rev. C | Page 9 of 40

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND −0.3 V to +6.5 V

DVDD to AGND −0.3 V to +6.5 V

AGND to DGND −0.3 V to +0.3 V

Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V

Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V

Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V

Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V

AIN/Digital Input Current 10 mA

Operating Temperature Range −40°C to +105°C

Storage Temperature Range

−65°C to +150°C

Maximum Junction Temperature 150°C

Lead Temperature, Soldering

Reflow 260°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

24-Lead TSSOP 128 42 °C/W

ESD CAUTION

AD7190 Data Sheet

Rev. C | Page 10 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

MCLK2

SCLK

P1/REFIN2(+)

MCLK1

P0/REFIN2(–)

AINCOM

AIN2

AIN1

DOUT/RDY

SYNC

DVDD

AGND

DGND

AVDD

BPDSW

REFIN1(–)

AIN3

AIN4

REFIN1(+)

DIN

AD7190

TOP VI EW

(No t t o Scal e)

07640-005

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

MCLK2

Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of

a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the

MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-

tinuous clock with the information transmitted to or from the ADC in smaller batches of data.

4 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device.

5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.

6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.

7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be

applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The

nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from

1 V to AVDD.

8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie

anywhere between AGND and AVDD − 1 V.

9 NC No Connect. This pin should be tied to AGND.

10 AINCOM Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo

differential operation.

11 AIN1 Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM.

12 AIN2 Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo differential input when used with AINCOM.

Data Sheet AD7190

Rev. C | Page 11 of 40

Pin No. Mnemonic Description

13 AIN3 Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN4 or as a pseudo differential input when used with AINCOM.

14 AIN4 Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN3 or as a pseudo differential input when used with AINCOM.

REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) −

REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD.

16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V.

17 BPDSW Bridge Power-Down Switch to AGND.

18 AGND Analog Ground Reference Point.

DGND

Digital Ground Reference Point.

20 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD.

21 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD.

22 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using

multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the

calibration control logic are reset and the analog modulator is held in its reset state. SYNC does not affect

the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to

DVDD.

23 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low

to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high

before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,

indicating that valid data is available. With an external serial clock, the data can be read using the

DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on

the SCLK falling edge and is valid on the SCLK rising edge.

24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register selection bits of the communications register identifying the

appropriate register.

AD7190 Data Sheet

Rev. C | Page 12 of 40

TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760

8,388,758

8,388,756

8,388,754

8,388,752

8,388,750

8,388,748

8,388,746 0200 400 600 800 1000

CODE

SAMPLE

07640-106

Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop

Disabled, Sinc4 Filter)

250

200

150

100

8,388,746

8,388,748

8,388,750

8,388,752

8,388,754

8,388,756

8,388,758

8,388,760

FREQUENCY

CODE

07640-107

Figure 7. Noise Distribution Histogram (VREF = 5 V,

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

8,388,950

8,388,900

8,388,800

8,388,750

8,388,650

8,388,600

8,388,850

8,388,700

8,388,550

8,388,500

8,388,450 0200 400 600 800 1000100 300 500 700 900

CODE

SAMPLES

07640-108

Figure 8. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop

Disabled, Sinc4 Filter)

8,388,490

8,388,576

8,388,662

8,388,748

8,388,834

8,388,920

FREQUENCY

CODE

07640-109

Figure 9. Noise Distribution Histogram (VREF = 5 V,

Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)

Data Sheet AD7190

Rev. C | Page 13 of 40

8,388,820

8,388,800

8,388,760

8,388,740

8,388,700

8,388,680

8,388,780

8,388,720

8,388,660

8,388,640

8,388,620 0200 400 600 800 1000100 300 500 700 900

CODE

SAMPLES

07640-110

Figure 10. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop

Disabled, Sinc4 Filter)

8,388,620

8,388,660

8,388,700

8,388,740

8,388,780

8,388,820

FREQUENCY

CODE

07640-111

Figure 11. Noise Distribution Histogram (VREF = 5 V,

Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc4 Filter)

3.0

2.0

1.0

–1.0

–2.0

–3.0

–2.5 –2.0 –1.5 –1.0 –0.5 00.5 1.0 1.5 2.0 2.5

INL (ppm of FSR)

VIN (V)

07640-112

Figure 12. INL (Gain = 1)

–2

–4

–6

–0.020 –0.015 –0.010 –0.005 00.005 0.010 0.015 0.020

INL (ppm of FSR)

(V)

07640-113

Figure 13. INL (Gain = 128)

AD7190 Data Sheet

Rev. C | Page 14 of 40

–60 –40 –20 020 40 60 80 100 120 140

OUTPUT VOLTAGE (µV)

TEMPERATURE (°C)

07640-114

Figure 14. Offset Error (Gain = 1, Chop Disabled)

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–60 –40 –20 020 40 60 80 100 120

OFF SET (µV)

TE M E RATURE (°C)

07640-115

Figure 15. Offset Error (Gain = 128, Chop Disabled)

1.000008

1.000007

1.000006

1.000005

1.000004

1.000003

1.000002

1.000001

1.000000

–60 –40 –20 020 40 60 80 100 120

GAIN

TEMPERATURE (°C)

07640-116

Figure 16. Gain Error (Gain = 1, Chop Disabled)

128.003

128.002

128.001

128.000

127.999

127.998

127.997

127.996

–60 –40 –20 020 40 60 80 100 120

GAIN

TEMPERATURE (°C)

07640-117

Figure 17. Gain Error (Gain = 128, Chop Disabled)

Data Sheet AD7190

Rev. C | Page 15 of 40

RMS NOISE AND RESOLUTION

The AD7190 has a choice of two filter types: sinc4 and sinc3.

In addition, the AD7190 can be operated with chop enabled

or chop disabled.

The following tables show the rms noise of the AD7190 for some

of the output data rates and gain settings with chop disabled

and enabled for the sinc4 and sinc3 filters. The numbers given

are for the bipolar input range with the external 5 V reference.

These numbers are typical and are generated with a differential

input voltage of 0 V when the ADC is continuously converting

on a single channel. The effective resolution is also shown, and

the output peak-to-peak (p-p) resolution, or noise-free resol-

ution, is listed in parentheses. It is important to note that the

effective resolution is calculated using the rms noise, wheras the

p-p resolution is calculated based on peak-to-peak noise. The

p-p resolution represents the resolution for which there is no

code flicker. These numbers are typical and are rounded to the

nearest ½ LSB.

SINC4 CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7 852.5 250 38 21 12 10 8.5

640 7.5 533 310 45 25 16 12 10.5

480 10 400 330 50 30 18 14 11.5

96 50 80 900 125 78 45 33 28

80 60 66.7 970 140 88 52 36 31

32 150 26.7 1460 215 125 75 55 48

300

13.3

1900

285

170

100

5 960 4.17 3000 480 280 175 140 121

2 2400 1.67 5000 780 440 280 220 198

1 4800 0.83 14,300 1920 1000 550 380 295

Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 4.7 852.5 24 (22.5) 24 (22) 24 (22) 24 (22) 24 (21) 23 (20.5)

640 7.5 533 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20)

480

400

24 (22)

24 (21.5)

23.5 (20.5)

22.5 (20)

96 50 80 23.5 (20.5) 23.5 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5)

80 60 66.7 23.5 (20.5) 23 (20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (18.5)

32 150 26.7 22.5 (20) 22.5 (19.5) 22.5 (19.5) 22 (19.5) 21.5 (18.5) 20.5 (18)

16 300 13.3 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (19) 21 (18.5) 20 (17.5)

5 960 4.17 21.5 (19) 21.5 (18.5) 21 (18.5) 21 (18) 20 (17.5) 19.5 (16.5)

2 2400 1.67 21 (18) 20.5 (18) 20.5 (17.5) 20 (17.5) 19.5 (16.5) 18.5 (16)

1 4800 0.83 19.5 (16.5) 19.5 (16.5) 19.5 (16.5) 19 (16.5) 18.5 (16) 18 (15.5)

1 The output peak-to-peak (p-p) resolution is listed in parentheses.

AD7190 Data Sheet

Rev. C | Page 16 of 40

SINC3 CHOP DISABLED

Table 8. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 4.7 639.4 270 42 23 13.5 10.5 9

640 7.5 400 320 50 27 17 13 11.5

480 10 300 350 60 35 19 15 12.5

1000

134

1050

145

32 150 20 1500 225 130 80 58 50

16 300 10 1950 308 175 110 83 73

5 960 3.125 4000 590 330 200 150 133

2 2400 1.25 56,600 7000 3500 1800 900 490

1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450

Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 4.7 639.4 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5)

640 7.5 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20)

480 10 300 24 (22) 24 (21.5) 24 (21.5) 24 (21) 23.5 (20.5) 22.5 (20)

23.5 (20.5)

23 (20.5)

23 (20)

22.5 (20)

22 (19.5)

21.5 (18.5)

80 60 50 23 (20.5) 23 (20.5) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5)

32 150 20 22.5 (20) 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (18.5) 20.5 (18)

16 300 10 22.5 (19.5) 22 (19) 22 (19) 21.5 (18.5) 21 (18) 20 (17.5)

5 960 3.125 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17.5) 19 (16.5)

2400

1.25

17.5 (14.5)

1 4800 0.625 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5)

1 The output peak-to-peak (p-p) resolution is listed in parentheses.

Data Sheet AD7190

Rev. C | Page 17 of 40

SINC4 CHOP ENABLED

Table 10. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.175 1702 177 27 15 8.5 7 6

640 1.875 1067 219 32 18 11.5 8.5 7.5

480 2.5 800 234 36 21 13 10 8.5

96 12.5 160 637 89 55 32 24 20

80 15 133 686 99 63 37 26 22

32 37.5 53 1033 152 89 53 39 34

16 75 26.7 1343 202 120 71 53 48

5 240 8.33 2121 340 198 124 99 86

2 600 3.33 3536 552 311 198 156 140

1 1200 1.67 10,200 1360 707 389 26 209

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 1.175 1702 24 (23) 24 (22.5) 24 (22.5) 24 (22.5) 24 (21.5) 23.5 (21)

640 1.875 1067 24 (22.5) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (20.5)

480 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21) 23 (20.5)

96 12.5 160 24 (21) 24 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19)

80 15 133 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19)

32 37.5 53 23 (20.5) 23 (20) 23 (20) 22.5 (20) 22 (19) 21 (18.5)

16 75 26.7 23 (20) 22.5 (20) 22.5 (19.5) 22 (19.5) 21.5 (19) 20.5 (18)

5 240 8.33 22 (19.5) 22 (19) 21.5 (19) 21.5 (18.5) 20.5 (18) 20 (17)

2 600 3.33 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17) 19 (16.5)

1 1200 1.67 20 (17) 20 (17) 20 (17) 19.5 (17) 19 (16.5) 18.5 (16)

1 The output peak-to-peak (p-p) resolution is listed in parentheses.

AD7190 Data Sheet

Rev. C | Page 18 of 40

SINC3 CHOP ENABLED

Table 12. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

1023 1.56 1282 191 30 16.5 10 8 6.5

640 2.5 800 226 36 19 12 9 8.5

480 3.33 600 248 43 25 14 11 9

96 16.6 120 708 95 61 36 25 21

80 20 100 743 103 68 39 29 23

32 50 40 1061 159 92 57 41 36

16 100 20 1380 218 124 78 59 52

5 320 6.25 2829 418 234 142 106 94

2 800 2.5 40,100 4950 2475 1273 637 347

1 1600 1.25 312,550 38,540 19,800 9900 4950 2440

Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281

1023 1.56 1282 24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (21)

640 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23 (20.5)

480 3.33 600 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5)

16.6

120

24 (21)

23.5 (21)

23.5 (20.5)

23 (20.5)

22.5 (20)

22 (19)

80 20 100 23.5 (21) 23.5 (21) 23 (20.5) 23 (20) 22.5 (19.5) 21.5 (19)

32 50 40 23 (20.5) 23 (20) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5)

16 100 20 23 (20) 22.5 (19.5) 22.5 (19.5) 22 (19) 21.5 (18.5) 20.5 (18)

5 320 6.25 22 (19) 21.5 (19) 21.5 (18.5) 21 (18.5) 20.5 (18) 19.5 (17)

2 800 2.5 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 18 (15)

1 1600 1.25 15 (12) 15 (12.5) 15 (12) 15 (12) 15 (12) 15 (12)

1 The output peak-to-peak (p-p) resolution is listed in parentheses.

Data Sheet AD7190

Rev. C | Page 19 of 40

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described in the following sections. In the

descriptions, set implies a Logic 1 state and cleared implies a

Logic 0 state, unless otherwise noted.

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation and in which register this operation takes

place. For read or write operations, when the subsequent read

or write operation to the selected register is complete, the

interface returns to where it expects a write operation to

the communications register. This is the default state of the

interface and, on power-up or after a reset, the ADC is in this

default state waiting for a write operation to the communi-

cations register. In situations where the interface sequence is

lost, a write operation of at least 40 serial clock cycles with DIN

high returns the ADC to this default state by resetting the entire

part. Table 14 outlines the bit designations for the

communications register. CR0 through CR7 indicate the bit

locations, CR denoting that the bits are in the communications

number in parentheses indicates the power-on/reset default

status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)

Table 14. Communications Register Bit Designations

Bit Location Bit Name Description

CR7 WEN Write enable bit. A 0 must be written to this bit for a write to the communications register to occur. If a 1 is

the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location

until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the

communications register.

CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during

the serial interface communication. See Table 15.

CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data

goes low to indicate that a conversion is complete. The communications register does not have to be

written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written

to the communications register. To disable continuous read, the instruction 01011000 must be written to

the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors

activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset

occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be

written to the device.

CR1 to CR0 These bits must be programmed to Logic 0 for correct operation.

Table 15. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communications register during a write operation 8 bits

0 0 0 Status register during a read operation 8 bits

0 0 1 Mode register 24 bits

0 1 0 Configuration register 24 bits

0 1 1 Data register/data register plus status information 24 bits/32 bits

1 0 0 ID register 8 bits

1 0 1 GPOCON register 8 bits

1 1 0 Offset register 24 bits

1 1 1 Full-scale register 24 bits

AD7190 Data Sheet

Rev. C | Page 20 of 40

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status

register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data

stream. The number in parentheses indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1) ERR(0) NOREF(0) Parity(0) 0(0) CHD2(0) CHD1(0) CHD0(0)

Table 16. Status Register Bit Designations

Bit Location Bit Name Description

SR7 RDY Ready bit for the ADC. Cleared when data is written to the ADC data register. The RDY bit is set

automatically after the ADC data register is read, or a period of time before the data register is updated

with a new conversion result, to indicate to the user that the conversion data should not be read. It is also

set when the part is placed in power-down mode or idle mode or when SYNC is taken low.

The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to

the status register for monitoring the ADC for conversion data.

SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. The ERR bit is set to indicate that the

result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or

underrange or the absence of a reference voltage. The bit is cleared by a write operation to start a conversion.

SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a

voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is

cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled

by setting the REFDET bit in the configuration register to 1.

SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an

odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The

DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set,

the contents of the status register are transmitted along with the data for each data register read.

SR3 0 This bit will be set to 0.

SR2 to SR0 CHD2 to

CHD0

These bits indicate which channel corresponds to the data register contents. They do not indicate which

channel is presently being converted but indicate which channel was selected when the conversion

contained in the data register was generated.

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through

MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The

number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and

filter and sets the RDY bit.

MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16

MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

Sinc3(0) 0 ENPAR(0) 0 Single(0) REJ60(0) FS9(0) FS8(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0)

Data Sheet AD7190

Rev. C | Page 21 of 40

Table 17. Mode Register Bit Designations

Bit Location Bit Name Description

MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7190 (see Table 18).

MR20

DAT_STA

This bit enables the transmission of status register contents after each data register read. When

DAT_STA is set, the contents of the status register are transmitted along with each data register read.

This function is useful when several channels are selected because the status register identifies the

channel to which the data register value corresponds.

MR19 to MR18 CLK1 to CLK0 These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an

external clock can be used. The ability to use an external clock allows several AD7190 devices to be

synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the

AD7190.

CLK1 CLK0 ADC Clock Source

0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2.

0 1 External clock. The external clock is applied to the MCLK2 pin.

1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated.

1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2.

MR17 to MR16

These bits must be programmed with a Logic 0 for correct operation.

MR15 SINC3 Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,

the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time

when chop is disabled. For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC

while the sinc4 filter has a settling time of 4/fADC. The sinc4 filter, due to its deeper notches, gives better

50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no

missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4

filter gives better performance than the sinc3 filter for rms noise and no missing codes.

MR14 This bit must be programmed with a Logic 0 for correct operation.

MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit

in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the

contents of the status register are transmitted along with the data for each data register read.

MR12 This bit must be programmed with a Logic 0 for correct operation.

MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7190 settles in one conversion cycle so

that it functions as a zero latency ADC. This bit has no affect when multiple analog input channels are

enabled or when the single conversion mode is selected.

MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a

filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous

50 Hz/60 Hz rejection.

MR9 to MR0

FS9 to FS0

Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter

cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In

association with the gain selection, it also determines the output noise (and, therefore, the effective

resolution) of the device. (see Table 6 through Table 13)

When chop is disabled and continuous conversion mode is selected, the output data rate equals

Output Data Rate = (fmod/64)/FS

where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023, and

fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this

results in a output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the filter first notch

frequency is equal to the output data rate when converting on a single channel.

When chop is enabled, the output data rate equals

Output Data Rate = (fmod/64)/(N × FS)

where:

FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023.

fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this

results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc

filter’s first notch frequency is equal to N × Output Data Rate. The chopping introduces notches at odd

integer multiples of (Output Data Rate/2).

AD7190 Data Sheet

Rev. C | Page 22 of 40

Table 18. Operating Modes

MD2 MD1 MD0 Mode

0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions

and places the result in the data register. The DOUT/ RDY pin and the RDY bit in the status register go low when a

conversion is complete. The user can read these conversions by setting the CREAD bit in the communications

placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each

conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the

complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are

available at the selected output data rate, which is dependent on filter choice.

0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single

conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then

performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in

the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data

0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are

still provided.

0 1 1 Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered

down. The bridge power-down switch remains active because the user may need to power up the sensor prior to

powering up the AD7190 for settling reasons. The external crystal, if selected, remains active.

1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a

calibration. The measured offset coefficient is placed in the offset register of the selected channel.

1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-

scale error.

System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required

each time the gain of a channel is changed.

1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required

each time the gain of a channel is changed.

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to

configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the

gain, and to select the analog input channel.

Table 19 outlines the bit designations for the configuration register. CON0 through CON23 indicate the bit locations. CON denotes that

the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-

on/reset default status of that bit.

Data Sheet AD7190

Rev. C | Page 23 of 40

CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16

Chop(0) 0(0) 0(0) REFSEL(0) 0(0) 0(0) 0(0) (0)

CON15

CON14

CON13

CON12

CON11

CON10

CON9

CON8

CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

Burn(0) REFDET(0) 0(0) BUF(1) U/B (0) G2(1) G1(1) G0(1)

Table 19. Configuration Register Bit Designations

Bit Location Bit Name Description

CON23 Chop Chop enable bit. When the chop bit is cleared, chop is disabled. When the chop bit is set, chop is

enabled. When chop is enabled, the offset and offset drift of the ADC are continuously minimized.

However, this increases the conversion time and settling time of the ADC. For example, when FS = 96

decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the

settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of

96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms.

However, at low gains, periodic calibrations may be required to remove the offset and offset drift.

CON22, CON21 These bits must be programmed with a Logic 0 for correct operation.

CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits.

REFSEL Reference Voltage

0 External reference applied between REFIN1(+) and REFIN1(−).

1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(-) pins.

CON19 to CON16

These bits must be programmed with a Logic 0 for correct operation.

CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20.

Several channels can be selected, and the AD7190 automatically sequences them. The conversion on

each channel requires the complete settling time.

CON7 Burn When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the

burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and

when chop is disabled.

CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the

external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference

detect circuitry only operates when the ADC is active.

CON5 This bit must be programmed with a Logic 0 for correct operation.

CON4 BUF Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the

power consumption of the device. If set, the analog inputs are buffered, allowing the user to place

source impedances on the front end without contributing gain errors to the system. With the buffer

disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD.

When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be

limited to 250 mV within the power supply rails.

CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar

operation is selected.

CON2 to CON0 G2 to G0 Gain select bits. Written by the user to select the ADC input range as follows:

G2 G1 G0 Gain ADC Input Range (5 V Reference, Bipolar Mode)

0 0 0 1 ±5 V

0 0 1 Reserved

0 1 0 Reserved

0 1 1 8 ±625 mV

1 0 0 16 ±312.5 mV

1 0 1 32 ±156.2 mV

1 1 0 64 ±78.125 mV

1 1 1 128 ±39.06 mV

AD7190 Data Sheet

Rev. C | Page 24 of 40

Table 20. Channel Selection

Channel Enable Bits in the Configuration Register Channel Enabled

Status Register

Bits CHD[2:0]

Calibration

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

Positive Input

AIN(+)

Negative Input

AIN(−)

1 AIN1 AIN2 000 0

1 AIN3 AIN4 001 1

1 Temperature sensor 010 None

1 AIN2 AIN2 011 0

1 AIN1 AINCOM 100 0

1 AIN2 AINCOM 101 1

1 AIN3 AINCOM 110 2

1 AIN4 AINCOM 111 3

DATA REGISTER

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

The conversion result from the ADC is stored in this data

read operation from this register, the RDY pin/bit is set. When

the DAT_STA bit in the mode register is set to 1, the contents of

the status register are appended to each 24-bit conversion. This

is advisable when several analog input channels are enabled

because the three LSBs of the status register (CHD2 to CHD0)

identify the channel from which the conversion originated.

ID REGISTER

RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX4

The identification number for the AD7190 is stored in the ID

GPOCON REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

The GPOCON register is an 8-bit register from which data can

be read or to which data can be written. This register is used to

enable the general-purpose digital outputs.

Table 21 outlines the bit designations for the GPOCON register.

GP0 through GP7 indicate the bit locations. GP denotes that the

bits are in the GPOCON register. GP7 denotes the first bit of

the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Data Sheet AD7190

Rev. C | Page 25 of 40

GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0

0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0)

Table 21. Register Bit Designations

Bit Location Bit Name Description

GP7 0 This bit must be programmed with a Logic 0 for correct operation.

GP 6 BPDSW Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch

BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-

down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.

GP5 GP32EN Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the digital outputs, P3 and P2, are

active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored.

GP4

GP10EN

Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the digital outputs, P1 and P0, are

active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are

ignored. The P1 and P0 pins can be used as a reference input REFIN2 when the REFSEL bit in the

configuration register is set to 1.

GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin.

When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the

GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set.

GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin.

When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the

GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set.

GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin.

When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the

GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set.

GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin.

When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the

GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set.

OFFSET REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The AD7190 has four offset registers; therefore, each channel

has a dedicated offset register. Each of these registers is a 24-bit

read/write register. This register is used in conjunction with its

associated full-scale register to form a register pair. The power-

on reset value is automatically overwritten if an internal or

system zero-scale calibration is initiated by the user. The AD7190

must be placed in power-down mode or idle mode when writing

to the offset register.

FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)

The full-scale register is a 24-bit register that holds the full-scale

calibration coefficient for the ADC. The AD7190 has four full-

scale registers; therefore, each channel has a dedicated full-scale

when writing to the full-scale registers, the ADC must be placed

in power-down mode or idle mode. These registers are configured

at power-on with factory-calibrated, full-scale calibration coef-

ficients, the calibration being performed at gain = 1. Therefore,

every device has different default coefficients. The default value

is automatically overwritten if an internal or system full-scale

calibration is initiated by the user or if the full-scale register is

written to.

AD7190 Data Sheet

Rev. C | Page 26 of 40

ADC CIRCUIT INFORMATION

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

DVDD DGND

AIN1

IN+

IN–

OUT– OUT+ AIN2

AIN3

AIN4

AINCOM

REFIN1(–)

BPDSW

AGND

AD7190

REFIN1(+) REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

TEMP

SENSOR

CLOCK

CIRCUITRY

AVDD

AGND

DOUT/RDY

DIN

SCLK

SYNC

AVDD

AGND

Σ-Δ

ADC

PGA

MUX

07640-012

Figure 18. Basic Connection Diagram

OVERVIEW

The AD7190 is an ultralow noise ADC that incorporates a

∑-∆ modulator, a buffer, PGA, and on-chip digital filtering

intended for the measurement of wide dynamic range signals

such as those in pressure transducers, weigh scales, and strain

gauge applications.

The part can be configured to have two differential inputs or four

pseudo differential inputs that can be buffered or unbuffered.

Figure 18 shows the basic connections required to operate the part.

FILTER, OUTPUT DATA RATE, SETTLING TIME

A ∑-∆ ADC consists of a modulator followed by a digital filter.

The AD7190 has two filter options: a sinc3 filter and a sinc4

filter. The filter is selected using the SINC3 bit in the mode

selected. The sinc3 filter is selected when SINC3 is set to 1.

At low output data rates (<1 kHz), the noise-free resolution is

comparable for the two filter types. However, at the higher

output data rates, the sinc4 filter gives better noise free

resolution.

The sinc4 filter also leads to better 50 Hz and 60 Hz rejection.

While the notch positions are not affected by the order of the

filter, the higher order filter has wider notches, which leads to

better rejection in the band (±1 Hz) around the notches. It also

gives better stop-band attenuation. The benefit of the sinc3 filter

is its lower settling time for the same output data rate.

Chop Disabled

The output data rate (the rate at which conversions are available

on a single channel when the ADC is continuously converting)

is equal to

fADC = fCLK/(1024 × FS[9:0])

where:

fADC is the output data rate.

fCLK = master clock (4.92 MHz nominal).

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The output data rate can be programmed from 4.7 Hz to 4800 Hz;

that is, FS[9:0] can have a value from 1 to 1023.

The previous equation is valid for both the sinc3 and sinc4

filters. The settling time for the sinc4 filter is equal to

tSETTLE = 4/fADC

Whereas the settling time for the sinc3 filter is equal to

tSETTLE = 3/fADC

Figure 19 and Figure 20 show the frequency response of the sinc4

and sinc3 filters, respectively, for an output data rate of 50 Hz.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-013

Figure 19. Sinc4 Filter Response (50 Hz Output Data Rate)

Data Sheet AD7190

Rev. C | Page 27 of 40

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-014

Figure 20. Sinc3 Filter Response (50 Hz Output Data Rate)

The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of

120 dB, assuming a stable master clock, while the sinc3 filter

gives a rejection of 100 dB. The stop-band attenuation is

typically 53 dB for the sinc4 filter but equal to 40 dB for the

sinc3 filter.

The 3 dB frequency for the sinc4 filter is equal to

f3dB = 0.23 × fADC

and for the sinc3 filter is equal to

f3dB = 0.272 × fADC

Chop Enabled

With chop enabled, the ADC offset and offset drift are

minimized. When chop is enabled, the analog input pins are

continuously swapped. Therefore, with the analog input pins

connected in one direction, the settling time of the sinc filter is

allowed to elapse until a valid conversion is available. The analog

input pins are then inverted and another valid conversion is

obtained. Subsequent conversions are then averaged so that the

offset is minimized. This continuous swapping of the analog

input pins and the averaging of subsequent conversions means

that the offset drift is also minimized.

Chopping affects the output data rate and settling time of the

ADC. For the sinc4 filter, the output data rate is equal to

fADC = fCLK/(4 × 1024 × FS[9:0])

For sinc3 filter, the output data rate is equal to

fADC = fCLK/(3 × 1024 × FS[9:0])

where:

fADC is the output data rate.

fCLK = master clock (4.92 MHz nominal).

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The value of FS[9:0] can be varied from 1 to 1023. This results

in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter

and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for

the sinc3 or sinc4 filter is equal to

tSETTLE = 2/fADC

Therefore, with chop enabled, the settling time is reduced for a

given output data rate compared to the chop disabled mode.

However, for a given FS[9:0] value, the output data rate is less

with chop enabled compared with the chop disabled mode.

For either the sinc3 or the sinc4 filter, the cutoff frequency f3dB is

equal to

f3dB = 0.24 × fADC

Figure 21 and Figure 22 show the filter response for the sinc4

and sinc3 filters, respectively, when chop is enabled. As shown

in the plots, the stop-band attenuation is less compared with the

chop disabled modes.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-015

Figure 21. Sinc4 Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-016

Figure 22. Sinc3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)

AD7190 Data Sheet

Rev. C | Page 28 of 40

50 Hz/60 Hz Rejection

Normal mode rejection is one of the main functions of the

digital filter. With chop disabled, 50 Hz rejection is obtained

when the output data rate is set to 50 Hz, whereas 60 Hz

rejection is achieved when the output data rate is set to 60 Hz.

Simultaneous 50 Hz/60 Hz rejection is obtained when the

output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz

rejection can also be achieved using the REJ60 bit in the mode

the REJ60 bit is set to 1, notches are placed at both 50 Hz and

60 Hz.

Figure 23 and Figure 24 show the frequency response of the

sinc4 and sinc3 filters, respectively, when the output data rate is

programmed to 50 Hz and REJ60 is set to 1.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-017

Figure 23. Sinc4 Filter Response (50 Hz Output Data Rate, REJ60 = 1)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-018

Figure 24. Sinc3 Filter Response (50 Hz Output Data Rate, REJ60 = 1)

Again, the sinc4 filter provides better 50 Hz/60 Hz rejection

than the sinc3 filter. In addition, better stop-band attenuation is

achieved with the sinc4 filter.

When chop is enabled, lower output data rates must be used to

achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output

data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection

when the sinc4 filter is selected, whereas an output data rate of

16.7 Hz gives simultaneous 50 Hz/ 60 Hz rejection when the sinc3

filter is used. Figure 25 and Figure 26 show the filter response for

both output data rates when REJ60 is set to 1.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-125

Figure 25. Sinc4 Filter Response (12.5 Hz Output Data Rate,

Chop Enabled, REJ60 = 1)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 025 50 75 100 125 150

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-126

Figure 26. Sinc3 Filter Response (16.7 Hz Output Data Rate,

Chop Enabled, REJ60 = 1)

Zero Latency

Zero latency is enabled by setting the SINGLE bit in the mode

allowed for each conversion. Therefore,

fADC = 1/tSETTLE

Zero latency means that the output data rate is constant

irrespective of the number of analog input channels enabled;

the user does not need to consider the effects of channel

changes on the output data rate. The disadvantages of zero

latency are the increased noise for a given output data rate

compared with the nonzero latency mode. For example, when

zero latency is not enabled, the AD7190 has a noise-free

resolution of 18.5 bits when the output data rate is 50 Hz and

the gain is set to 128. When zero latency is enabled, the ADC

has a resolution of 17.5 bits peak-to-peak when the output data

rate is 50 Hz. The filter response also changes. Figure 19 shows

the filter response for the sinc4 filter when the output data rate

is 50 Hz (zero latency disabled). Figure 27 shows the filter

response when zero latency is enabled and the output data rate

Data Sheet AD7190

Rev. C | Page 29 of 40

is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The

ADC needs to operate with an output data rate of 12.5 Hz to

obtain 50 Hz rejection when zero latency is enabled. To obtain

simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode

The stop-band attenuation is considerably reduced also (3 dB

compared with 53 dB in the nonzero latency mode).

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 010050 200 300 400 500150 250 350 450 550 600

FILTER GAIN (dB)

FRE QUENCY ( Hz )

07640-020

Figure 27. Sinc4 Filter Response (50 Hz Output Data Rate, Zero Latency)

Channel Sequencer

The AD7190 includes a channel sequencer, which simplifies

communications with the device in multichannel applications.

The sequencer also optimizes the channel throughput of the

device as the sequencer switches channels at the optimum rate

rather than waiting for instructions via the SPI interface.

Bits CH0 to Bit CH7 in the configuration register are used to

enable the required channels. In continuous conversion mode,

the ADC selects each of the enabled channels in sequence and

performs a conversion on the channel. The RDY pin goes low

when a valid conversion is available on each channel. When

several channels are enabled, the contents of the status register

should be attached to the 24-bit word so that the user can

identify the channel that corresponds to each conversion. To

attach the status register value to the conversion, Bit DAT_STA

in the mode register should be set to 1.

When several channels are enabled, the ADC must allow the

complete settling time to generate a valid conversion each time

that the channel is changed. The AD7190 takes care of this:

when a channel is selected, the modulator and filter are reset

and the RDY pin is taken high. The AD7190 then allows the

complete settling time to generate the first conversion.

RDY only goes low when a valid conversion is available. The

AD7190 then selects the next enabled channel and converts on

that channel. The user can then read the data register while the

ADC is performing the conversion on the next channel.

The time required to read a valid conversion from all enabled

channels is equal to

tSETTLE × Number of Enabled Channels

For example, if the sinc4 filter is selected, chop is disabled and

zero latency is disabled, conversions are available at 1/fADC when

converting on a single channel, where fADC is equal to the output

data rate. The settling time is equal to

tSETTLE = 4/fADC

The time required to sample N channels is

4/(fADC × N)

RDY

CONVERSIONS CHANNEL A CHANNEL B

1/f

ADC

CHANNEL C

07640-019

Figure 28. Channel Sequencer

DIGITAL INTERFACE

As indicated in the On-Chip Registers section, the programmable

functions of the AD7190 are controlled using a set of on-chip

registers. Data is written to these registers via the serial interface

of the part. Read access to the on-chip registers is also provided

by this interface. All communication with the part must start with

a write to the communications register. After power-on or reset,

the device expects a write to its communications register. The data

written to this register determines whether the next operation is a

read operation or a write operation and also determines which

access to any of the other registers on the part begins with a write

operation to the communications register, followed by a write to

the selected register. A read operation from any other register

(except when continuous read mode is selected) starts with a write

to the communications register, followed by a read operation from

the selected register.

The serial interface of the AD7190 consists of four signals: CS,

DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer

data into the on-chip registers, whereas DOUT/RDY is used for

accessing data from the on-chip registers. SCLK is the serial clock

input for the device, and all data transfers (either on DIN or

DOUT/RDY) occur with respect to the SCLK signal.

The DOUT/ RDY pin functions as a data ready signal also, the

line going low when a new data-word is available in the output

data register to indicate when not to read from the device, to

ensure that a data read is not attempted while the register is being

updated. CS is used to select a device. It can be used to decode the

AD7190 in systems where several components are connected to

the serial bus.

AD7190 Data Sheet

Rev. C | Page 30 of 40

Figure 3 and Figure 4 show timing diagrams for interfacing to the

AD7190, with CS being used to decode the part. Figure 3 shows

the timing for a read operation from the output shift register of

the AD7190, and Figure 4 shows the timing for a write operation

to the input shift register. It is possible to read the same word

from the data register several times even though the DOUT/RDY

line returns high after the first read operation. However, care

must be taken to ensure that the read operations have been com-

pleted before the next output update occurs. In continuous read

mode, the data register can be read only once.

The serial interface can operate in 3-wire mode by tying CS low.

In this case, the SCLK, DIN, and DOUT/RDY lines are used to

communicate with the AD7190. The end of the conversion can be

monitored using the RDY bit or pin. This scheme is suitable for

interfacing to microcontrollers.

If CS is required as a decoding signal, it can be generated from a

port pin. For microcontroller interfaces, it is recommended that

SCLK idle high between data transfers.

The AD7190 can be operated with CS used as a frame synchron-

ization signal. This scheme is useful for DSP interfaces. In this

case, the first bit (MSB) is effectively clocked out by CS because

CS normally occurs after the falling edge of SCLK in DSPs. The

SCLK can continue to run between data transfers, provided the

timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s to the

DIN input. If a Logic 1 is written to the AD7190 DIN line for at

least 40 serial clock cycles, the serial interface is reset. This ensures

that the interface can be reset to a known state if the interface gets

lost due to a software error or some glitch in the system. Reset

returns the interface to the state in which it is expecting a write to

the communications register. This operation resets the contents of

all registers to their power-on values. Following a reset, the user

should allow a period of 500 µs before addressing the serial

interface.

The AD7190 can be configured to continuously convert or to

perform a single conversion. See Figure 29 through Figure 31.

Single Conversion Mode

In single conversion mode, the AD7190 is placed in power-

down mode after conversions. When a single conversion is

initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,

in the mode register, the AD7190 powers up, performs a single

conversion, and then returns to power-down mode. The

on-chip oscillator requires 1 ms approximately to power up.

DOUT/RDY goes low to indicate the completion of a conversion.

When the data word has been read from the data register,

DOUT/RDY goes high. If CS is low, DOUT/RDY remains high

until another conversion is initiated and completed. The data

DOUT/RDY has gone high.

If several channels are enabled, the ADC sequences through the

enabled channels and performs a conversion on each channel.

When a conversion is started, DOUT/RDY goes high and

remains high until a valid conversion is available. As soon as the

conversion is available, DOUT/RDY goes low. The ADC then

selects the next channel and begins a conversion. The user can

read the present conversion while the next conversion is being

performed. As soon as the next conversion is complete, the data

which to read the conversion. When the ADC has performed a

single conversion on each of the selected channels, it returns to

power-down mode.

If the DAT_STA bit in the mode register is set to 1, the contents

of the status register are output along with the conversion each

time that the data read is performed. The four LSBs of the status

DIN

SCLK

DOUT/RDY

0x08 0x58

DATA

0x280060

07640-021

Figure 29. Single Conversion

Data Sheet AD7190

Rev. C | Page 31 of 40

Continuous Conversion Mode

Continuous conversion is the default power-up mode. The

AD7190 converts continuously, the RDY bit in the status

low, the DOUT/RDY line also goes low when a conversion is

completed. To read a conversion, the user writes to the com-

munications register, indicating that the next operation is a read

of the data register. When the data word has been read from the

data register, DOUT/RDY goes high. The user can read this

ensure that the data register is not being accessed at the

completion of the next conversion or else the new conversion

word is lost.

When several channels are enabled, the ADC continuously

loops through the enabled channels, performing one conversion

on each channel per loop. The data register is updated as soon

as each conversion is available. The DOUT/RDY pin pulses low

each time a conversion is available. The user can then read the

conversion while the ADC converts on the next enabled channel.

If the DAT_STA bit in the mode register is set to 1, the contents

of the status register are output along with the conversion each

time that the data read is performed. The status register indicates

the channel to which the conversion corresponds.

DIN

SCLK

DOUT/RDY

0x58 0x58

DATA DATA

07640-022

Figure 30. Continuous Conversion

AD7190 Data Sheet

Rev. C | Page 32 of 40

Continuous Read

Rather than write to the communications register each time a

conversion is complete to access the data, the AD7190 can be

configured so that the conversions are placed on the DOUT/

RDY line automatically. By writing 01011100 to the commun-

ications register, the user need only apply the appropriate

number of SCLK cycles to the ADC, and the conversion word

is automatically placed on the DOUT/RDY line when a

conversion is complete. The ADC should be configured for

continuous conversion mode.

When DOUT/RDY goes low to indicate the end of a conversion,

sufficient SCLK cycles must be applied to the ADC; the data

conversion is then placed on the DOUT/RDY line. When the

conversion is read, DOUT/RDY returns high until the next

conversion is available. In this mode, the data can be read only

once. Also, the user must ensure that the data-word is read

before the next conversion is complete. If the user has not read

the conversion before the completion of the next conversion,

or if insufficient serial clocks are applied to the AD7190 to

read the word, the serial output register is reset when the next

conversion is complete and the new conversion is placed in

the output serial register.

To exit the continuous read mode, the instruction 01011000

must be written to the communications register while the

RDY pin is low. While in the continuous read mode, the ADC

monitors activity on the DIN line so that it can receive the

instruction to exit the continuous read mode. Additionally, a

reset occurs if 40 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is to be written to the device.

When several channels are enabled, the ADC continuously

steps through the enabled channels and performs one con-

version on each channel each time that it is selected. DOUT/

RDY pulses low when a conversion is available. When the user

applies sufficient SCLK pulses, the data is automatically placed

on the DOUT/RDY pin. If the DAT_STA bit in the mode

along with the conversion. The status register indicates the

channel to which the conversion corresponds.

DIN

SCLK

DOUT/RDY

0x5C

DATA DATA DATA

07640-023

Figure 31. Continuous Read

Data Sheet AD7190

Rev. C | Page 33 of 40

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7190 has two differential/four pseudo differential analog

input channels which can be buffered or unbuffered. In buffered

mode (the BUF bit in the configuration register is set to 1), the

input channel feeds into a high impedance input stage of the

buffer amplifier. Therefore, the input can tolerate significant

source impedances and is tailored for direct connection to

external resistive-type sensors such as strain gauges or resistance

temperature detectors (RTDs).

When BUF = 0, the part is operated in unbuffered mode. This

results in a higher analog input current. Note that this unbuffered

input path provides a dynamic load to the driving source.

Therefore, resistor/capacitor combinations on the input pins

can cause gain errors, depending on the output impedance of

the source that is driving the ADC input. Table 22 shows the

allowable external resistance/capacitance values for unbuffered

mode at a gain of 1 such that no gain error at the 20-bit level is

introduced.

Table 22. External R-C Combination for No 20-Bit Gain Error

C (pF) R (Ω)

1.4 k

100 850

500 300

1000 230

5000 30

The absolute input voltage range in buffered mode is restricted

to a range between AGND + 250 mV and AVDD – 250 mV. Care

must be taken in setting up the common-mode voltage so that

these limits are not exceeded. Otherwise, there is degradation in

linearity and noise performance.

The absolute input voltage in unbuffered mode includes the

range between AGND – 50 mV and AVDD + 50 mV. T h e

negative absolute input voltage limit does allow the possibility

of monitoring small true bipolar signals with respect to AGND.

PGA

When the gain stage is enabled, the output from the buffer is

applied to the input of the programmable gain array (PGA).

The presence of the PGA means that signals of small amplitude

can be gained within the AD7190 while still maintaining excel-

lent noise performance. For example, when the gain is set to

128, the rms noise is 8.5 nV, typically, when the output data rate

is 4.7 Hz, which is equivalent to 23 bits of effective resolution or

20.5 bits of noise-free resolution.

The AD7190 can be programmed to have a gain of 1, 8, 16, 32,

64, and 128 using Bit G2 to Bit G0 in the configuration register.

Therefore, with an external 2.5 V reference, the unipolar ranges

are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar

ranges are from ±19.53 mV to ±2.5 V.

The analog input range must be limited to (AVDD − 1.25 V)/gain

because the PGA requires some headroom. Therefore, if AVDD =

5 V, t h e maximum analog input that can be applied to the

AD7190 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/ gain

in bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7190 can accept either unipolar or

bipolar input voltage ranges. A bipolar input range does not

imply that the part can tolerate negative voltages with respect

to system AGND. In pseudo-differential mode, signals are

referenced to AINCOM while in differential mode, signals are

referenced to the negative input of the differential pair. For

example, if AINCOM is 2.5 V and the AD7190 AIN1 analog

input is configured for unipolar mode with a gain of 2, the input

voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V

reference is used. If AINCOM is 2.5 V and the AD7190 AIN1

analog input is configured for bipolar mode with a gain of 2, the

analog input range on AIN1 is 1.25 V to 3.75 V.

The bipolar/unipolar option is chosen by programming the U/B

bit in the configuration register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00...00, a midscale voltage resulting

in a code of 100...000, and a full-scale input voltage resulting in

a code of 111...111. The output code for any analog input voltage

can be represented as

Code = (2N × AIN × gain)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000...000, a zero differential input voltage resulting

in a code of 100...000, and a positive full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

Code = 2N – 1 × [(AIN × gain/VREF) + 1]

where:

AIN is the analog input voltage.

gain is the PGA setting (1 to 128).

N = 24.

CLOCK

The AD7190 includes an internal 4.92 MHz clock on-chip. This

internal clock has a tolerance of ±4%. Either the internal clock

or an external crystal/clock can be used as the clock source to

the AD7190. The clock source is selected using the CLK1 and

CLK0 bits in the mode register. When an external crystal is

used, it must be connected across the MCLK1 and MCLK2

pins. The crystal manufacturer recommends the load capaci-

tances required for the crystal. The MCLK1 and MCLK2 pins of

the AD7190 have a capacitance of 15 pF, typically. If an external

AD7190 Data Sheet

Rev. C | Page 34 of 40

clock source is used, the clock source must be connected to the

MCLK2 pin and the MCLK1 pin must be left floating.

The internal clock can also be made available at the MCLK2

pin. This is useful when several ADCs are used in an application

and the devices need to be synchronized. The internal clock

from one device can be used as the clock source for all ADCs

in the system. Using a common clock, the devices can be syn-

chronized by applying a common reset to all devices, or the

SYNC pin can be pulsed.

BURNOUT CURRENTS

The AD7190 contains two 500 nA constant current generators,

one sourcing current f rom AVDD to AIN(+) and one sinking

current from AIN(−) to AGND, where AIN(+) is the positive

analog input terminal and AIN(−) is the negative analog input

terminal in differential mode and AINCOM in pseudo-

differential mode. The currents are switched to the selected

analog input pair. Both currents are either on or off, depending

on the burnout current enable (burn) bit in the configuration

transducer remains operational before attempting to take

measurements on that channel. After the burnout currents are

turned on, they flow in the external transducer circuit, and a

measurement of the input voltage on the analog input channel

can be taken. It will take some time for the burnout currents to

detect an open circuit condition as the currents will need to

charge any external capacitors

There are several reasons why a fault condition can be detected.

The front-end sensor may be open circuit. It could also mean

that the front-end sensor is overloaded, or the reference may be

absent and the NOREF bit in the status register is set, thus

clamping the data to all 1s. The user needs to check these three

cases before making a judgment. If the voltage measured is 0 V,

it may indicate that the transducer has short circuited. The

current sources work over the normal absolute input voltage

range specifications when the analog inputs are buffered and

chop is disabled.

REFERENCE

The ADC has a fully differential input capability for the refer-

ence channel. In addition, the user has the option of selecting

one of two external reference options (REFIN1(x) or REFIN2(x)).

The reference source for the AD7190 is selected using the

REFSEL bit in the configuration register. The REFIN2(x) pins

are dual purpose: they can function as two general-purpose

output pins or as reference pins. When the REFSEL bit is set

to 1, these pins automatically function as reference pins.

The common-mode range for these differential inputs is from

AGND to AVDD. The reference input is unbuffered; therefore,

excessive R-C source impedances introduce gain errors. The

reference voltage REFIN (REFINx(+) − REFINx(−)) is AVDD

nominal, but the AD7190 is functional with reference voltages

from 1 V to AVDD. In applications where the excitation (voltage

or current) for the transducer on the analog input also drives

the reference voltage for the part, the effect of the low frequency

noise in the excitation source is removed because the application is

ratiometric. If the AD7190 is used in a nonratiometric applica-

tion, use a low noise reference.

Recommended 2.5 V reference voltage sources for the AD7190

include the ADR421 and ADR431, which are low noise

references. Also note that the reference inputs provide a high

impedance, dynamic load. Because the input impedance of each

reference input is dynamic, resistor/capacitor combinations on

these inputs can cause dc gain errors, depending on the output

impedance of the source driving the reference inputs.

Reference voltage sources like those previously recommended

(for example, ADR431) typically have low output impedances

and are, therefore, tolerant to having decoupling capacitors on

REFINx(+) without introducing gain errors in the system.

Deriving the reference input voltage across an external resistor

means that the reference input sees a significant external source

impedance. External decoupling on the REFINx pins is not

recommended in this type of circuit configuration.

REFERENCE DETECT

The AD7190 includes on-chip circuitry to detect whether the

part has a valid reference for conversions or calibrations. This

feature is enabled when the REFDET bit in the configuration

and REFINx(–) pins is between 0.3 V and 0.6 V, the AD7190

detects that it no longer has a valid reference. In this case, the

NOREF bit of the status register is set to 1. If the AD7190 is

performing normal conversions and the NOREF bit becomes

active, the conversion result is all 1s. Therefore, it is not

necessary to continuously monitor the status of the NOREF bit

when performing conversions. It is only necessary to verify its

status if the conversion result read from the ADC data register

is all 1s. If the AD7190 is performing either an offset or full-

scale calibration and the NOREF bit becomes active, the

updating of the respective calibration registers is inhibited to

avoid loading incorrect coefficients to these registers, and the

ERR bit in the status register is set. If the user is concerned

about verifying that a valid reference is in place every time a

calibration is performed, check the status of the ERR bit at the

end of the calibration cycle.

RESET

The circuitry and serial interface of the AD7190 can be reset

by writing consecutive 1s to the device; 40 consecutive 1s are

required to perform the reset. This resets the logic, the digital

filter, and the analog modulator, whereas all on-chip registers

are reset to their default values. A reset is automatically

performed on power-up. When a reset is initiated, the user

must allow a period of 500 µs before accessing any of the

on-chip registers. A reset is useful if the serial interface loses

synchronization due to noise on the SCLK line.

Data Sheet AD7190

Rev. C | Page 35 of 40

SYSTEM SYNCHRONIZATION

The SYNC input allows the user to reset the modulator and the

digital filter without affecting any of the setup conditions on the

part. This allows the user to start gathering samples of the analog

input from a known point in time, that is, the rising edge of

SYNC. SYNC needs to be taken low for four master clock cycles

to implement the synchronization function.

If multiple AD7190 devices are operated from a common master

clock, they can be synchronized so that their data registers are

updated simultaneously. A falling edge on the SYNC pin resets

the digital filter and the analog modulator and places the AD7190

into a consistent, known state. While the SYNC pin is low, the

AD7190 is maintained in this state. On the SYNC rising edge,

the modulator and filter are taken out of this reset state and, on

the next clock edge, the part starts to gather input samples again.

In a system using multiple AD7190 devices, a common signal to

their SYNC pins synchronizes their operation. This is normally

done after each AD7190 has performed its own calibration or

has had calibration coefficients loaded into its calibration

registers. The conversions from the AD7190s are then

synchronized.

The part is taken out of reset on the master clock falling edge

following the SYNC low-to-high transition. Therefore, when

multiple devices are being synchronized, the SYNC pin should

be taken high on the master clock rising edge to ensure that all

devices begin sampling on the master clock falling edge. If the

SYNC pin is not taken high in sufficient time, it is possible to

have a difference of one master clock cycle between the devices;

that is, the instant at which conversions are available differs

from part to part by a maximum of one master clock cycle.

The SYNC pin can also be used as a start conversion command.

In this mode, the rising edge of SYNC starts conversion, and the

falling edge of RDY indicates when the conversion is complete.

The disadvantage of this scheme is that the settling time of the

filter has to be allowed for each data register update. This means

that the rate at which the data register is updated is reduced. For

example, if the ADC is configured to use the sinc4 filter, zero

latency is disabled and chop is disabled, the data register update

takes four times longer.

TEMPERATURE SENSOR

Embedded in the AD7190 is a temperature sensor. This is

selected using the CH2 bit in the configuration register. When

the CH2 bit is set to 1, the temperature sensor is enabled. When

the temperature sensor is selected and bipolar mode is selected,

the device should return a code of 0x800000 when the temper-

ature is 0 K. A one-point calibration is needed to get the optimum

performance from the sensor. Therefore, a conversion at 25°C

should be recorded and the sensitivity calculated. The sensitivity

is approximately 2815 codes/°C. The equation for the temperature

sensor is

Temp (K) = (Conversion – 0x800000)/2815 K

Temp (°C) = Temp (K) – 273

Following the one point calibration, the internal temperature

sensor has an accuracy of ±2 °C, typically.

BRIDGE POWER-DOWN SWITCH

In bridge applications such as strain gauges and load cells, the

bridge itself consumes the majority of the current in the system.

For example, a 350 Ω load cell requires 15 mA of current when

excited with a 5 V supply. To minimize the current consumption

of the system, the bridge can be disconnected (when it is not

being used) using the bridge power-down switch. Figure 18

shows how the bridge power-down switch is used. The switch

can withstand 30 mA of continuous current, and it has an on

resistance of 10 Ω maximum.

LOGIC OUTPUTS

The AD7190 has four general-purpose digital outputs, P0, P1,

P2, and P3. These are enabled using the GP32EN and GP10EN

bits in the GPOCON register. The pins can be pulled high or

low using the P0DAT to P3DAT bits in the GPOCON register;

that is, the value at the pin is determined by the setting of the

P0DAT to P3DAT bits. The logic levels for these pins are

determined by AVDD rather than by DVDD. When the GPOCON

value at the pins. This is useful for short-circuit detection.

These pins can be used to drive external circuitry, for example,

an external multiplexer. If an external multiplexer is used to

increase the channel count, the multiplexer logic pins can be

controlled via the AD7190 general-purpose output pins. The

general-purpose output pins can be used to select the active

multiplexer pin. Because the operation of the multiplexer is

independent of the AD7190, the AD7190 modulator and filter

should be reset using the SYNC pin each time that the multi-

plexer channel is changed.

AD7190 Data Sheet

Rev. C | Page 36 of 40

ENABLE PARITY

The AD7190 also has a parity check function on-chip that

detects 1-bit errors in the serial communications between the

ADC and the microprocessor. When the ENPAR bit in the

mode register is set to 1, parity is enabled. The contents of the

status register must be transmitted along with each 24-bit

conversion when the parity function is enabled. To append the

contents of the status register to each conversion read, the

DAT_STA bit in the mode register should be set to 1. For each

conversion read, the parity bit in the status register is

programmed so that the overall number of 1s transmitted in the

24-bit data-word is even. Therefore, for example, if the 24-bit

conversion contains eleven 1s (binary format), the parity bit is

set to 1 so that the total number of 1s in the serial transmission is

even. If the microprocessor receives an odd number of 1s, it

knows that the data received has been corrupted.

The parity function only detects 1-bit errors. For example, two

bits of corrupt data can result in the microprocessor receiving an

even number of 1s. Therefore, an error condition is not detected.

CALIBRATION

The AD7190 provides four calibration modes that can be pro-

grammed via the mode bits in the mode register. These modes

are internal zero-scale calibration, internal full-scale calibration,

system zero-scale calibration, and system full-scale calibration.

A calibration can be performed at any time by setting the MD2

to MD0 bits in the mode register appropriately. A calibration

should be performed when the gain is changed. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The offset calibration coefficient is subtracted from the result

prior to multiplication by the full-scale coefficient.

To start a calibration, write the relevant value to the MD2 to

MD0 bits. The DOUT/RDY pin and the RDY bit in the status

calibration is complete, the contents of the corresponding

calibration registers are updated, the RDY bit in the status

and the AD7190 reverts to idle mode.

During an internal zero-scale or full-scale calibration, the res-

pective zero input and full-scale input are automatically connected

internally to the ADC input pins. A system calibration, however,

expects the system zero-scale and system full-scale voltages to

be applied to the ADC pins before initiating the calibration

mode. In this way, errors external to the ADC are removed.

From an operational point of view, treat a calibration like

another ADC conversion. A zero-scale calibration, if required,

must always be performed before a full-scale calibration. Set the

system software to monitor the RDY bit in the status register or

the DOUT/RDY pin to determine the end of calibration via a

polling sequence or an interrupt-driven routine.

With chop disabled, both an internal zero-scale calibration and

a system zero-scale calibration require a time equal to the

settling time, tSETTLE, (4/fADC for the sinc4 filter and 3/fADC for the

sinc3 filter).

With chop enabled, an internal zero-scale calibration is not

needed because the ADC itself minimizes the offset continuously.

However, if an internal zero-scale calibration is performed, the

settling time, tSETTLE, (2/fADC) is required to perform the calibra-

tion. Similarly, a system zero-scale calibration requires a time of

tSETTLE to complete.

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. For a gain of 1, the time required for an

internal full-scale calibration is equal to tSETTLE. For higher gains,

the internal full-scale calibration requires a time of 2 × tSETTLE.

A full-scale calibration is recommended each time the gain of a

channel is changed to minimize the full-scale error.

A system full-scale calibration requires a time of tSETTLE. With

chop disabled, the zero-scale calibration (internal or system

zero-scale) should be performed before the system full-scale

calibration is initiated.

An internal zero-scale calibration, system zero-scale calibration

and system full-scale calibration can be performed at any output

data rate. An internal full-scale calibration can be performed at

any output data rate for which the filter word FS[9:0] is divisible

by 16, FS[9:0] being the decimal equivalent of the 10-bit word

written to Bit FS9 to Bit FS0 in the mode register. Therefore,

internal full-scale calibrations can be performed at output data

rates such as 10 Hz or 50 Hz when chop is disabled. Using these

lower output data rates results in better calibration accuracy.

The offset error is, typically, 100 µV/gain. If the gain is changed,

it is advisable to perform a calibration. A zero-scale calibration

(an internal zero-scale calibration or system zero-scale

calibration) reduces the offset error to the order of the noise.

The gain error of the AD7190 is factory calibrated at a gain of 1

with a 5 V power supply at ambient temperature. Following this

calibration, the gain error is 0.001%, typically, a t 5 V. Table 23

shows the typical uncalibrated gain error for the different gain

settings. An internal full-scale calibration reduces the gain error

to 0.001%, typically, when the gain is equal to 1. For higher

gains, the gain error post internal full-scale calibration is

0.0075%, typically. A system full-sale calibration reduces the

gain error to the order of the noise.

Table 23. Typical Precalibration Gain Error vs. Gain

Gain Precalibration Gain Error (%)

8 −0.11

16 −0.20

32 −0.23

64 −0.29

128 −0.39

Data Sheet AD7190

Rev. C | Page 37 of 40

The AD7190 gives the user access to the on-chip calibration

registers, allowing the microprocessor to read the calibration

coefficients of the device and also to write its own calibration

coefficients from prestored values in the EEPROM. A read of

the registers can be performed at any time. However, the ADC

must be placed in power-down or idle mode when writing to

the registers. The values in the calibration registers are 24-bits

wide. The span and offset of the part can also be manipulated

using the registers.

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs are differential,

most of the voltages in the analog modulator are common-

mode voltages. The high common-mode rejection of the part

removes common-mode noise on these inputs. The analog and

digital supplies to the AD7190 are independent and separately

pinned out to minimize coupling between the analog and

digital sections of the device. The digital filter provides

rejection of broadband noise on the power supplies, except at

integer multiples of the modulator sampling frequency.

Connect an R-C filter to each analog input pin to provide

rejection at the modulator sampling frequency. A 100 Ω

resistor in series with each analog input, a 0.1 μF capacitor

between the analog inputs along with a 0.01 μF capacitor from

each analog input to AGND is advised. The digital filter also

removes noise from the analog and reference inputs provided

these noise sources do not saturate the analog modulator. As a

result, the AD7190 is more immune to noise interference than a

conventional high resolution converter. However, because the

resolution of the AD7190 is so high and the noise levels from

the converter so low, care must be taken with regard to grounding

and layout.

The printed circuit board (PCB) that houses the ADC must be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes because it

gives the best shielding.

Although the AD7190 has separate pins for analog and digital

ground, the AGND and DGND pins are tied together internally

via the substrate. Therefore, the user must not tie these two

pins to separate ground planes unless the ground planes are

connected together near the AD7190.

In systems in which the AGND and DGND are connected

somewhere else in the system (that is, the power supply of the

system), they should not be connected again at the AD7190

because a ground loop results. In these situations, it is

recommended that ground pins of the AD7190 be tied to the

AGND plane.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all currents are as close

as possible to the paths the currents took to reach their destin-

ations. Avoid forcing digital currents to flow through the AGND.

Avoid running digital lines under the device because this

couples noise onto the die and allow the analog ground plane to

run under the AD7190 to prevent noise coupling. The power

supply lines to the AD7190 must use as wide a trace as possible

to provide low impedance paths and reduce the effects of

glitches on the power supply line. Shield fast switching signals

like clocks with digital ground to prevent radiating noise to

other sections of the board, and never run clock signals near the

analog inputs. Avoid crossover of digital and analog signals.

Run traces on opposite sides of the board at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best but is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes,

whereas signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs.

Decouple all analog supplies with 10 μF tantalum in parallel with

0.1 μF capacitors to AGND. To achieve the best from these

decoupling components, place them as close as possible to the

device, ideally right up against the device. Decouple all logic chips

with 0.1 μF ceramic capacitors to DGND. In systems in which a

common supply voltage is used to drive both the AVDD and DVDD

of the AD7190, it is recommended that the system AVDD supply

be used. For this supply, place the recommended analog supply

decoupling capacitors between the AVDD pin of the AD7190 and

AGND and the recommended digital supply decoupling

capacitor between the DVDD pin of the AD7190 and DGND.

AD7190 Data Sheet

Rev. C | Page 38 of 40

APPLICATIONS INFORMATION

The AD7190 provides a low-cost, high resolution analog-to-

digital function. Because the analog-to-digital function is

provided by a ∑-∆ architecture, it makes the part more

immune to noisy environments, making it ideal for use in

sensor measurement and industrial and process control

applications.

WEIGH SCALES

Figure 32 shows the AD7190 being used in a weigh scale

application. The load cell is arranged in a bridge network and

gives a differential output voltage between its OUT+ and OUT–

terminals. Assuming a 5 V excitation voltage, the full-scale

output range from the transducer is 10 mV when the sensitivity

is 2 mV/V. The excitation voltage for the bridge can be used to

directly provide the reference for the ADC because the reference

input range includes the supply voltage.

A second advantage of using the AD7190 in transducer-based

applications is that the bridge power-down switch can be fully

utilized to minimize the power consumption of the system. The

bridge power-down switch is connected in series with the cold

side of the bridge. In normal operation, the switch is closed and

measurements can be taken. In applications in which current

consumption is being minimized, the AD7190 can be placed in

standby mode, thus significantly reducing the power consumed

in the application. In addition, the bridge power-down switch

can be opened while in standby mode, thus avoiding unnecessary

power consumption by the front-end transducer. When the part

is taken out of standby mode and the bridge power-down switch

is closed, the user should ensure that the front-end circuitry is

fully settled before attempting a read from the AD7190.

For simplicity, external filters are not included in Figure 32.

However, an R-C antialias filter should be included on each

analog input. This is required because the on-chip digital filter

does not provide any rejection around the modulator sampling

frequency or multiples of this frequency. Suitable values are a

100 Ω resistor in series with each analog input, a 0.1 μF capa-

citor between the analog inputs and 0.01 μF capacitors from

each analog input pin to AGND.

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

DVDD DGND

AIN1

IN+

IN–

OUT– OUT+ AIN2

AIN3

AIN4

AINCOM

REFIN1(–)

BPDSW

AGND

AD7190

REFIN1(+) REFERENCE

DETECT

SERIAL

INTERFACE

AND

CONTROL

LOGIC

TEMP

SENSOR

CLOCK

CIRCUITRY

AGND

DOUT/RDY

DIN

SCLK

SYNC

AGND

Σ-Δ

ADC

PGA

MUX

07640-024

Figure 32. Typical Application (Weigh Scale)

Data Sheet AD7190

Rev. C | Page 39 of 40

OUTLINE DIMENSIONS

24 13

121

6.40 BSC

4.50

4.40

4.30

PIN 1

7.90

7.80

7.70

0.15

0.05

0.30

0.19

0.65

BSC 1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models1, 2 Temperature Range Package Description Package Option

AD7190BRUZ –40°C to +105°C 24-Lead TSSOP RU-24

AD7190BRUZ-REEL –40°C to +105°C 24-Lead TSSOP RU-24

AD7190WBRUZ –40°C to +105°C 24-Lead TSSOP RU-24

AD7190WBRUZ-RL –40°C to +105°C 24-Lead TSSOP RU-24

EVAL-AD7190EBZ Evaluation Board

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD7190W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

AD7190 Data Sheet

Rev. C | Page 40 of 40

registered trademarks are the property of their respective owners.

D07640-0-2/13(C)

NOTES