1. General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It gener ates the drive signals for any static or
multiplexed LCD cont aining up to four backplan es and up to 40 segments . It can be easily
cascaded for larger LCD applications. The PCF8576D is compatible with most
microcontrollers and communica tes via the two-li ne bidirectio nal I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and du p lex dr ive
modes).
PCF8576DT/2 shou ld not be use d fo r new design-ins. Replacement part is
PCF85176T/1 for industrial applications
PCF8576DT/S400/2 should not be used for new design-ins. Replacement part is
PCA85176T/Q900/1 for automotive applications
2. Features and benefits
AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
Selectable display bias configuration: static, 12, or 13
Internal LCD bias generation with voltage-follower buffers
40 s eg m en t dr ive s:
Up to 20 7-segment numeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 elements
40 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 6.5 V for high-threshold twisted nematic LCDs
Low power consum ption
400 kHz I2C-bus in te r f ac e
PCF8576D
Universal LCD driver for low multiplex rates
Rev. 14 — 10 June 2013 Product data sheet
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 2 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
May be cascaded for large LCD applications (up to 2560 elements possible)
No external components required
Compatible with chip-on-glass and chip-on-board technology
Manufactured in silicon gate CMOS process
3. Ordering information
[1] Not to be used for new designs. Replacement part is PCF85176T/1 for industrial applications.
[2] Not to be used for new designs. Replacement part is PCA85176T/Q900/1 for automotive applications.
3.1 Ordering options
4. Marking
Table 1. Ordering information
Product type number Package
Name Description Version
PCF8576DT/2[1] T SSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm SOT364-1
PCF8576DT/S400/2[2] TSSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm SOT364-1
PCF8576DU/DA/2 wire bond die 59 bonding pads PCF8576DU/DA
PCF8576DU/2DA/2 bare die 59 bumps PCF8576DU/2DA
Tabl e 2. Or dering options
Product type number Sales item (12NC) Orderable part number IC
revision Delivery form
PCF8576DT/2 935276166118 PCF8576DT/2,118 2 tape and reel, 13 inch
PCF8576DT/S4 00/2 935287131118 PCF8576DT/S400/2,1 2 tape and reel, 13 inch
PCF8576DU/DA/2 935276239026 PCF8576DU/DA/2,026 2 chips in tray
PCF8576DU/2DA/2 935276249026 PCF8576DU/2DA/2,02 2 chips in tray
Table 3. Marking codes
Product type number Marking code
PCF8576DT/2 PCF8576DT
PCF8576DT/S400/2 PCF8576DT/S400
PCF8576DU/DA/2 PC8576D-2
PCF8576DU/2DA/2 PC8576D-2
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Product data sheet Rev. 14 — 10 June 2013 3 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
5. Block diagram
Fig 1. Block diagram of PCF8576D
40
001aai900
LCD BIAS
GENERATOR
LCD
VOLTAGE
SELECTOR
PCF8576D
BACKPLANE
OUTPUTS
DISPLAY
CONTROLLER
COMMAND
DECODER WRITE DATA
CONTROL
DISPLAY RAM
40 × 4-BIT
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
REGISTER
DISPLAY SEGMENT
OUTPUTS
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
CLOCK SELECT
AND TIMING
OSCILLATOR
INPUT
FILTERS
BLINKER
TIMEBASE
POWER-ON
RESET
I2C-BUS
CONTROLLER
BP0 BP2 BP1 BP3
A2A1A0SA0
SDA
SCL
VDD
OSC
SYNC
CLK
VSS
VLCD
S0 to S39
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Product data sheet Rev. 14 — 10 June 2013 4 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
Top view. For mechanical details, see Figure 25.
Fig 2. Pinning diagram for PCF8576DT (TSSOP56)
PCF8576DT
BP2 BP0
BP1 VLCD
BP3 VSS
S0 SA0
S1 A2
S2 A1
S3 A0
S4 OSC
S5 VDD
S6 CLK
S7 SYNC
S8 SCL
S9 SDA
S10 S39
S11 S38
S12 S37
S13 S36
S14 S35
S15 S34
S16 S33
S17 S32
S18 S31
S19 S30
S20 S29
S21 S28
S22 S27
S23 S26
S24 S25
001aaf646
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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Product data sheet Rev. 14 — 10 June 2013 5 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 26
and Figure 27.
Fig 3. Pinning diagram for PCF8576DU (bare die)
S25
S26
S27
S28
S29
S30
S31
S32
S33
C2
S4
S6
S5
S7
S9
S10
S8
S11
S12
S13
S15
S14
S16
S17
OSC
A0
SYNC
SCL
CLK
SDA
SDA
SDA
SCL
S39
S38
S36
S37
S35
S34
A2
A1
C1
SA0
VSS
BP2
BP0
VLCD
BP1
BP3
S0
S2
S1
S3
PCF8576DU
VDD
001aag424
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
52
53
54
55
56
57
58
59
1
2
3
4
5
6
7
8
43
44
45
46
47
48
49
S18
S19
S20
S21
S22
S23
S24
36
37
38
39
40
41
42
50
51
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Product data sheet Rev. 14 — 10 June 2013 6 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6.2 Pin description
[1] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
Tabl e 4. Pin description
Symbol Pin Description
PCF8576DT PCF8576DU
SDA 44 1, 58, 59 I2C-bus serial data input and output
SCL 45 2, 3 I2C-bus serial clock input
CLK 47 5 external clock input or output
VDD 48 6 supply voltage
SYNC 46 4 cascade synchronization input or output
OSC 49 7 internal oscillator enable input
A0 to A2 50 to 52 8 to 10 subaddress inputs
SA0 53 11 I2C-bus address input; bit 0
VSS 54 12[1] ground supply voltage
VLCD 55 13 LCD supply voltage
BP0, BP2,
BP1, BP3 56, 1, 2, 3 14 to 17 LCD backplane outputs
S0 to S39 4 to 43 18 to 57 LCD segment outputs
n.c. - - not connected
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Product data sheet Rev. 14 — 10 June 2013 7 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8576D is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
40 segments.
The possible display configurations of the PCF8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 5. All
of these configurations can be implemented in the typical system shown in Figure 5.
[1] 7 segment display has 8 elements including the decimal point.
[2] 14 segment display has 16 elements including decimal point and accent dot.
Fig 4. Example of displays suitable for PCF8576D
Table 5. Selection of possi ble display configurations
Number of
Backplanes Icons Digits/Characters Dot matrix/
Elements
7-segment[1] 14-segment[2]
4 160 20 10 160 (4 40)
3 120 15 7 120 (3 40)
28010580 (2 40 )
1405240 (1 40)
7-segment with dot 14-segment with dot and accent
013aaa312
dot matrix
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Product data sheet Rev. 14 — 10 June 2013 8 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated inte rn ally.
The only other connections required to complete the system are to the po we r su pp lies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8576D resets to the following starting conditions:
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 13 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 12)
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 12bias voltage level for the 1:2 multiplex drive mode configuration is
selected. The LCD voltage can be temperature compensated externally using the supply
to pin VLCD.
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO ) track resistance, each supply line
must be routed separately between the chip and the connector.
Fig 5. Typical system configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
tr
2CB
SDA
SCL
OSC
40 segment drives
4 backplanes
LCD PANEL
(up to 160
elements)
PCF8576D
A0 A1 A2 SA0
VDD
VSS
VSS
VDD VLCD
mdb079
R
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Product data sheet Rev. 14 — 10 June 2013 9 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coord ina te s th e mu ltiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of o per ation , to gether with the biasing cha racteri stics as functions o f
VLCD and the resulting discrimination ratios (D) are given in Table 6.
Discrimination is a term which is defined as the ratio of the on a nd off RMS volt age across
a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold volt age (Vth(off)) , typically when the LCD exhibits appr oximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3V
th(off).
Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by , where the values for a are
a = 1 for 12 bias
a = 2 for 13 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
Table 6. Biasing characteristics
LCD drive
mode Number of: LCD bias
configuration
Backplanes Levels
static 1 2 static 0 1
1:2 multiplex 2 3 120.354 0.791 2.236
1:2 multiplex 2 4 130.333 0.745 2.236
1:3 multiplex 3 4 130.333 0.638 1.915
1:4 multiplex 4 4 130.333 0.577 1.732
Voff RMS
VLCD
-------------------------
Von RMS
VLCD
------------------------
DVon RMS
Voff RMS
-------------------------=
Von RMS a22a n++
n1a+
2
------------------------------
VLCD
=
Voff RMS a22an+
n1a+
2
------------------------------
VLCD
=
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Product data sheet Rev. 14 — 10 June 2013 10 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
12bias is and the discrimination for an L CD drive mode of 1:4 multiple x with
12bias is .
The advanta ge of these LCD drive modes is a reduction of the LCD full scale volta ge VLCD
as follows:
1:3 multiplex (12 bias):
1:4 multiplex (12 bias):
These compare with when 13 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative tran sm iss i on (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are af fected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
DVon RMS
Voff RMS
-----------------------a22a n++
a22an+
---------------------------==
3 1.732=
21
3
---------- 1.528=
VLCD 6V
off RMS
2.449Voff RMS
==
VLCD 43
3
----------------------2.309Voff RMS
==
VLCD 3Voff RMS
=
Von RMS
Vth on
Voff RMS
Vth off
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Product data sheet Rev. 14 — 10 June 2013 11 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 6. Electro-optical characteristic: relative transmission curve of the liquid
VRMS [V]
100 %
90 %
10 %
OFF
SEGMENT GREY
SEGMENT ON
SEGMENT
Vth(off) Vth(on)
Relative T ransmission
013aaa494
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Product data sheet Rev. 14 — 10 June 2013 12 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 7.
(1) Vstate1(t) = VSn(t) VBP0(t).
(2) Von(RMS) = VLCD.
(3) Vstate2(t) = VSn+1(t) VBP0(t).
(4) Voff(RMS) = 0 V.
Fig 7. Static drive mode wavefo rms
mgl745
VSS
VLCD
VSS
VLCD
VSS
VLCD
VLCD
VLCD
VLCD
VLCD
state 1 0 V
BP0
Sn
Sn+1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
Tfr
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Product data sheet Rev. 14 — 10 June 2013 13 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mo de is used when two b ackplanes are pr ovided in the LCD. This
mode allows fractional LCD bias voltages of 12 bias or 13 bias as shown in Figure 8 and
Figure 9.
(1) Vstate1(t) = VSn(t) VBP0(t).
(2) Von(RMS) = 0.791VLCD.
(3) Vstate2(t) = VSn+1(t) VBP1(t).
(4) Voff(RMS) = 0.354VLCD.
Fig 8. W aveforms for the 1:2 multiplex drive mode with 12 bias
mgl746
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD / 2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD / 2
VLCD / 2
VLCD / 2
VLCD
VLCD
VLCD / 2
VLCD / 2
Sn
Sn+1
Tfr
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Product data sheet Rev. 14 — 10 June 2013 14 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
(1) Vstate1(t) = VSn(t) VBP0(t).
(2) Von(RMS) = 0.745VLCD.
(3) Vstate2(t) = VSn+1(t) VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 9. W aveforms for the 1:2 multiplex drive mode with 13 bias
mgl747
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
VLCD
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
Sn
Sn+1
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
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Product data sheet Rev. 14 — 10 June 2013 15 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies
(see Figure 10).
(1) Vstate1(t) = VSn(t) VBP0(t).
(2) Von(RMS) = 0.638VLCD.
(3) Vstate2(t) = VSn+1(t) VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:3 multiplex drive mode with 13 bias
mgl748
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
(a) Waveforms at driver.
BP2
Sn
Sn+1
Sn+2
Tfr
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
0 V
VLCD
2VLCD / 3
2VLCD / 3
VLCD / 3
VLCD / 3
VLCD
VSS
VLCD
2VLCD / 3
VLCD / 3
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Product data sheet Rev. 14 — 10 June 2013 16 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are pr ovided in the LCD, the 1:4 multiple x drive mode applies (see
Figure 11).
(1) Vstate1(t) = VSn(t) VBP0(t).
(2) Von(RMS) = 0.577VLCD.
(3) Vstate2(t) = VSn+1(t) VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 11. Waveforms for the 1:4 multiplex drive mode with 13 bias
mgl749
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
T
fr
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
0 V
V
LCD
2V
LCD
/ 3
2V
LCD
/ 3
V
LCD
/ 3
V
LCD
/ 3
V
LCD
0 V
V
LCD
2V
LCD
/ 3
2V
LCD
/ 3
V
LCD
/ 3
V
LCD
/ 3
V
LCD
V
SS
V
LCD
2V
LCD
/ 3
V
LCD
/ 3
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Product data sheet Rev. 14 — 10 June 2013 17 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
7.5.2 External clock
Pin CL K is ena ble d as an ext er nal cloc k inpu t by conn e ctin g pin OSC to VDD. The LCD
frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includ es the
transfer of display dat a from the display RAM to the display seg ment outputs. In cascaded
applications, the correct timing relationship betwe en each PCF8576D in the system is
mainta ined by the synchronization signal at pin SYNC. The timing also genera tes the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock: .
7.7 Display register
The display latch holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 40 segment output s S0 to S39 which should be
connected dir ec tly to the LC D. Th e segm e nt output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 40 segment output s are required, the unused segment output s should be left
open-circuit.
ffr fclk
24
-------
=
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Product data sheet Rev. 14 — 10 June 2013 18 of 57
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Universal LCD driver for low multiplex rates
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-c ircu it.
In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, there fore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the
same signals and may also be paired to increase the drive capabilities.
In static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 40 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
the bits in the RAM bitmap and the LCD elements
the RAM columns and the se gm e nt outp u ts
the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a log ic 0 indicat es th e off-state.
The display RAM bit map, Figure 12, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
When display data is transmitted to the PCF8576D, the receive d display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and depending o n the current multip lex drive mode the bits are stored singular ly,
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 12. Display RAM bit map
0
0
1
2
3
1 2 3 4 35 36 37 38 39
display RAM addresses (columns)/segment outputs (S)
display RAM bits
(rows)/
backplane outputs
(BP)
mbe525
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NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 13; the RAM filling organization
depicted applies equally to other LCD types.
The following applies to Figure 13:
In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
In 1:3 multiplex drive mode the eight bits are pla ce d in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be t aken to avoid overwriting adjace nt data because al ways full bytes are
transmitted (see Section 7.10.3).
In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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Universal LCD driver for low multiplex rates
x = data bit unchanged.
Fig 13. Relationship betwee n LCD layout, drive mode, display RAM filling order and display data transmit ted over the I2C-bus
001aaj646
acbDPfegd
MSB LSB
bDPcadgfe
MSB LSB
abfgecdDP
MSB LSB
cbafgedDP
MSB LSB
drive mode
static
1:2
multiplex
1:3
multiplex
1:4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
BP0
BP0
BP1
BP0
BP1 BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
rows
display RAM
rows/backplane
outputs (BP)
byte1
columns
display RAM address/segment outputs (s)
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n + 1 n + 2 n + 3
byte1 byte2
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n + 1 n + 2
byte1 byte2 byte3
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
n + 1
n
a
c
b
DP
0
1
2
3
f
e
g
d
byte1 byte2 byte3 byte4 byte5
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
Sn+2
Sn+3
Sn+1
Sn
DP
a
fb
g
ec
d
Sn+2
Sn+1
Sn+7
Sn
Sn+3
Sn+5
Sn+6
Sn+4
DP
a
fb
g
ec
d
Sn
Sn+1
Sn+2
DP
a
fb
g
ec
d
Sn+1
Sn
DP
a
fb
g
ec
d
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Universal LCD driver for low multiplex rates
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display da t a byte, or a series of display dat a bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 13). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 13. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddr ess applied to A0, A1, and A2. The subaddress co unter value is defined
by the device-select command (see Table 14). If the content of the subaddress counter
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented a s if data stor age had t ake n place. The su baddress co unter is also
incremented when the data pointer overflows.
The storage arrange men ts described lead to extremely ef ficien t data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subadd ress must not be changed while the device is b eing accessed on the
I2C-bus interface.
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 13 as
well).
Table 7. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elemen ts on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM address es (columns)/segment outpu ts (Sn)
0123456789:
0a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2a5 a2 - b5 b2 - c5 c2 - d5 :
3----------:
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Universal LCD driver for low multiplex rates
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 8.
In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
In the first write to the RAM, bits a7 to a0 are written.
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF8576D is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF8576D is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
7.10.5 Output bank selector
The output bank selector (see Table 15) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
In 1:2 multiplex mode, rows 0 and 1 are selected
In static mode, row 0 is selected
The PCF8576D includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
Table 8. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM address es (columns)/segment outpu ts (Sn)
0123456789:
0a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :
1a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :
2a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :
3----------:
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Universal LCD driver for low multiplex rates
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.10.6 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display dat a can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using th e bank-select command (see
Table 15). The inp ut bank selector functions independently to the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF8576D are very versatile. The whole display
can blink at frequen cie s selected by the blink-select command (see Table 16). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 16).
An additional feature is for an arbitrary select ion of LCD eleme nts to blink. This applies to
the static and 1:2 multiplex drive mo de s and ca n be imple m en te d witho ut any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 12).
[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator
frequency (fclk) of 1536 Hz (see Section 12).
Table 9. Blinking frequ en cies
Blink mode Normal operating mode ratio Nominal blink frequency[1]
off - blinking off
12 Hz
21 Hz
3 0.5 Hz
fclk
768
----------
fclk
1536
-------------
fclk
3072
-------------
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7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands availa ble to th e PC F85 7 6D ar e de fin ed in Table 10.
[1] Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 19. When this bit is set logic 1, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that
the command byte is the last in the transfer . Further bytes will be regarded as display data
(see Table 11).
Table 10. Definition of PCF8576D commands
Command Operation code Reference
Bit 76543210
mode-set C 1 0 -[1] E B M[1:0] Table 12
load-data-pointer C 0 P[5:0] Table 13
device-select C1100A[2:0] Table 14
bank-select C 1 1 1 1 0 I O Table 15
blink-select C 1 1 1 0 AB BF[1:0] Table 16
Tabl e 11. C bit description
Bit Symbol Value Description
7C continue bit
0 last control byte in the transfer; next byte w ill be re ga rded
as display data
1 control bytes continue; next byte will be a command too
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Universal LCD driver for low multiplex rates
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Default value.
[3] The display is disabled by setting all backplane and segment outputs to VLCD.
[4] Not applicable for static drive mode.
[1] Default value.
[1] Default value.
Table 12. Mode-set command bit description
Bit Symbol Value Description
7C0, 1see Table 11
6, 5 - 10 fixed value
4 - - unused
3E display status[1]
0[2] disabled (blank)[3]
1 enabled
2B LCD bias configuration[4]
0[2] 13 bias
112 bias
1 to 0 M[1:0] LCD drive mode selection
01 static; BP0
10 1:2 multiplex; BP0, BP1
11 1:3 multiplex; BP0, BP1, BP2
00[2] 1:4 multiplex; BP0, BP1, BP2, BP3
Table 13. Load-data-pointer command bit description
See Section 7.10.1.
Bit Symbol Value Description
7C0, 1see Table 11
6 - 0 fixed value
5 to 0 P[5:0] 000000[1] to
100111 6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Table 14. Device-select command bit de scription
See Section 7.10.2.
Bit Symbol Value Description
7C0, 1see Table 11
6 to 3 - 1100 fixed value
2 to 0 A[2:0] 000[1] to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware suba ddresses
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Universal LCD driver for low multiplex rates
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2] Default value.
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Default value.
[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display dat a into the display RAM in the correct filling order.
Table 15. Bank-select command bit description
See Section 7.10.5 and Section 7.10.6.
Bit Symbol Value Description
Static 1:2 multiplex[1]
7 C 0, 1 see Table 11
6 to 2 - 11110 fixed value
1I input bank selection; storage of arriving display data
0[2] RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
0O output bank sele c tion ; retrieval of LCD display data
0[2] RAM row 0 RAM rows 0 and 1
1 RAM row 2 RAM rows 2 and 3
Table 16. Blink-select command bit description
See Section 7.11.
Bit Symbol Value Description
7C0, 1see Table 11
6 to 3 - 1110 fixed value
2AB blink mode selection
0[2] normal blinking[1]
1 alternate RAM bank blinking[3]
1 to 0 BF[1:0] blink frequency selection
00[2] off
01 1
10 2
11 3
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Universal LCD driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidire ctional, two-line communication between dif ferent ICs or modules.
The two lines are a Serial DAt a line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 14).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the dat a line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P.
The START and STOP conditions are illustrated in Figure 15.
8.2 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 16.
Fig 14. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 15. Definitio n of START and STOP condition s
mbc622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
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Universal LCD driver for low multiplex rates
8.3 Acknowledge
The number of data bytes tran sf er re d be tween the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge af ter the reception of e ach byte that
has been clocke d ou t of th e sl av e tra n sm i tte r.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter mus t leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 17.
Fig 16. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig 17. Acknowledgement of the I2C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
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Universal LCD driver for low multiplex rates
8.4 I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8576 D are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.5 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF8576D. The entir e I 2C-bus slave address byte is shown in Table 17.
The PCF8576D is a write-only device and will not respond to a read access, therefore bit
0 should always be logic 0. Bit 1 of the slave address byte that a PCF8576D will respond
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
Up to 16 PCF8576D for very large LCD applications
The use of two types of LCD multiplex drive
The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D
slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
Table 17. I2C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
011100SA0R/W
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Universal LCD driver for low multiplex rates
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8576D.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 19). The command bytes are also acknowledged by all add ressed
PCF8576D on the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data p ointer and subadd ress counter are auto matically updated
and the data directed to the intended PCF8576D device.
An acknowledgement after each byte is asserted only by the PCF8576Ds that are
addressed via address lines A0, A1, and A2. After the last display byte, the I2C-bus
master asserts a STOP condition (P). Alternately a START may be asserted to restart an
I2C-bus access.
Fig 18. I2C-bus protocol
Fig 19. Format of co mman d by te
mdb078
S
A
0
S011100 0AC COMMAND A P
ADISPLAY DATA
slave address R/W
acknowledge by
all addressed
PCF8576Ds
acknowledge
by A0, A1 and A2
selected
PCF8576D only
1 byte
update data pointers
and if necessary,
subaddress counter
n 1 byte(s) n 0 byte(s)
msa833
REST OF OPCODE
C
MSB LSB
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Universal LCD driver for low multiplex rates
9. Internal circuitry
Fig 20. Device protection circuits
SA0
VDD VDD
VSS VSS
VLCD
VSS
SDA
mdb076
VSS
SCL
VSS
CLK
VDD
VSS
OSC
VDD
VSS
SYNC
VDD
VSS
A0, A1 A2
VDD
VSS
BP0, BP1,
BP2, BP3
VLCD
VSS
S0 to S39
VLCD
VSS
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Universal LCD driver for low multiplex rates
10. Limiting values
[1] Pass level; Human Body Model (HBM) according to Ref. 8 “JESD22-A114.
[2] Pass level; Machine Model (MM), according to Ref. 9 “JESD22-A115.
[3] Pass level; Charged-Device Model (CDM), according to Ref. 10 “JESD22-C101.
[4] Pass level; latch-up testing according to Ref. 11 “JESD78 at maximum ambient temperature (Tamb(max)).
[5] According to the store and transport requirements (see Ref. 14 “UM10569) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.5 V
VLCD LCD supply voltage 0.5 +7.5 V
VIinput voltage on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
0.5 +6.5 V
VOoutput voltage on each of the pins S0 to
S39, BP0 to BP3 0.5 +7.5 V
IIinput current 10 +10 mA
IOoutput current 10 +10 mA
IDD supply current 50 +50 mA
IDD(LCD) LCD supply current 50 +50 mA
ISS ground supply current 50 +50 mA
Ptot total power dissipation - 400 mW
Pooutput power - 100 mW
VESD electrostatic discharge
voltage HBM [1] -5000 V
MM [2] -200 V
CDM [3] -1500 V
Ilu latch-up current [4] - 200 mA
Tstg storage temperature [5] 65 +150 C
Tamb ambient temperature operating device 40 +85 C
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Product data sheet Rev. 14 — 10 June 2013 33 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
11. Static characteristics
[1] VLCD > 3 V for 13 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3] The I2C-bus interface of PCF8576D is 5 V tolerant.
[4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 18.
[5] Propagation delay of driver between clock (CLK) and LCD driving signals.
[6] Periodically sampled, not 100 % tested.
[7] Outputs measured one at a time.
Table 19. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 1.8 - 5.5 V
VLCD LCD supply voltage [1] 2.5 - 6.5 V
IDD supply current fclk(ext) = 1536 Hz [2] -3.57A
VDD =3.0V;
Tamb =25C-2.7-A
IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [2] -1825A
VDD(LCD) =3.0V;
Tamb =25C-13-A
Logic[3]
VP(POR) power-on reset supply voltage 1.0 1.3 1.6 V
VIL LOW-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS -0.3V
DD V
VIH HIGH-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
[4][5] 0.7VDD -V
DD V
IOL LOW-level output current output sink current;
VOL = 0.4 V; VDD =5V
on pins CLK and SYNC 1- - mA
on pin SDA 3 - - mA
IOH(CLK) HIGH-level output current on pin CLK output source current;
VOH =4.6V; V
DD =5V 1- - mA
ILleakage current VI=V
DD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
1- +1A
IL(OSC) leakage current on pin OSC VI=V
DD 1- +1A
CIinput capacitance [6] --7pF
LCD outputs
VOoutput voltage variation on pins BP0 to BP3 and
S0 to S39 100 - +100 mV
ROoutput resistance VLCD = 5 V [7]
on pins BP0 to BP3 - 1.5 - k
on pins S0 to S39 - 6.0 - k
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Product data sheet Rev. 14 — 10 June 2013 34 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
Table 20. Dy namic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
fclk(int) internal clock frequency [1] 1440 1850 2640 Hz
fclk(ext) external clock fre quency 960 - 2640 Hz
tclk(H) HIGH-level clock time 60 - - s
tclk(L) LOW-level clock time 60 - - s
Synchronization
tPD(SYNC_N) SYNC propagation delay - 30 - ns
tSYNC_NL SYNC LOW time 1 - - s
tPD(drv) driver propagation delay VLCD = 5 V [2] --30s
I2C-bus[3]
Pin SCL
fSCL SCL clock frequency - - 400 kHz
tLOW LOW period of the SCL clock 1.3 - - s
tHIGH HIGH period of the SCL clock 0.6 - - s
Pin SDA
tSU;DAT data set-up time 100 - - ns
tHD;DAT data hold ti me 0 - - ns
Pins SCL and SDA
tBUF bus free time between a STOP and
START condition 1.3 - - s
tSU;STO set-up time for STOP condition 0.6 - - s
tHD;STA hold time (repeated) START condition 0.6 - - s
tSU;STA set-up time for a repeated START
condition 0.6 - - s
trrise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s
fSCL < 125 kHz - - 1.0 s
tffall time of both SDA and SCL signals - - 0.3 s
Cbcapacitive load for each bus line - - 400 pF
tw(spike) spike pulse width on the I2C-bus--50ns
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Product data sheet Rev. 14 — 10 June 2013 35 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 21. Driver timing waveforms
Fig 22. I2C-bus timing waveforms
001aai163
tPD(drv)
tSYNC_NL
tPD(SYNC_N)
CLK
SYNC
BP0 to BP3,
and S0 to S39
tclk(H) tclk(L)
1 / fCLK
0.7 VDD
0.3 VDD
0.7 VDD
0.3 VDD
0.5 V
(VDD = 5 V)
0.5 V
SDA
mga728
SDA
SCL
tSU;STA tSU;STO
tHD;STA
tBUF tLOW
tHD;DAT tHIGH
tr
tf
tSU;DAT
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Product data sheet Rev. 14 — 10 June 2013 36 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0).
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded
PCF8576Ds contribute additional segment outputs but their backplane outputs are left
open-circuit (see Figure 23).
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed
on all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in Figure 24.
Table 21. Addressing cascaded PCF8576D
Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device
100000
0011
0102
0113
1004
1015
1106
1117
210008
0019
01010
01111
10012
10113
11014
11115
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Product data sheet Rev. 14 — 10 June 2013 37 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 22.
The PCF8576D can be cascaded with the PCF8562. This allows optimal drive selection
for a given number of pixels to display. Figure 21 and Figure 22 show the timing o f the
synchronization signals.
Table 22. SYNC contact resistance
Number of devices Maximum contact resist ance
26 k
3 to 5 2.2 k
6 to 10 1.2 k
10 to 16 700
Fig 23. Cascaded PCF8576D configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1, 58, 59
2, 3
4
5
7
89
6
8 9 10 11 12
13
10 11 12
40 segment drives
4 backplanes
40 segment drives
LCD PANEL
(up to 2560
elements)
PCF8576DU
A0 A1 A2 SA0
VDD
VLCD
DD
VLCD
V
mdb077
SDA
SCL
SYNC
CLK
OSC
1, 58, 59
613
2, 3
4
5
7BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 VSS
VSS
VSS
VDD VLCD
PCF8576DU
BP0 to BP3
Rtr
2CB
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Product data sheet Rev. 14 — 10 June 2013 38 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
14. Test information
The following quality information corresponds with the product type: PCF8576DT/S400/2
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
Fig 24. Synchronization of the cascade for the various PCF8576D drive modes
Tfr =ffr
1
BP0
SYNC
BP0
(1/2 bias)
SYNC
BP0
(1/3 bias)
(a) static drive mode.
(b) 1:2 multiplex drive mode.
(c) 1:3 multiplex drive mode.
(d) 1:4 multiplex drive mode.
BP0
(1/3 bias)
SYNC
SYNC
BP0
(1/3 bias)
mgl755
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Product data sheet Rev. 14 — 10 June 2013 39 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
15. Package outline
Fig 25. Package outline SOT364-1 (TSSOP56)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT364-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
128
56 29
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 14.1
13.9 6.2
6.0 0.5 1
8.3
7.9 0.50
0.35 0.5
0.1
0.080.25
0.8
0.4
p
EvMA
A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
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Product data sheet Rev. 14 — 10 June 2013 40 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
16. Bare die outline
Fig 26. B are die outl ine PCF8576DU/DA (fo r dime ns i ons see Table 23)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
PCF8576DU/DA
pcf8576du_da_do
08-12-10
10-12-20
Notes
1. Marking code: PC8576D-2
Wire bond die; 59 bonding pads PCF8576DU/DA
0 0.5 1 mm
scale
A
e
X
(1)
00y
x
D
E
C2 59 152 8 C1
2235
36
51 9
21
detail X
P2
P1
P4P3
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Product data sheet Rev. 14 — 10 June 2013 41 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Fig 27. Bare die outline PCF8576DU/2DA (for dimensions see Table 24)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
PCF8576DU/2DA
pcf8576du_2da_do
08-12-10
10-12-20
Bare die; 59 bumps PCF8576DU/2DA
e
X
(1)
00y
x
D
E
C2 59 152 8 C1
2235
36
51 9
21
detail X
b
L
Notes
1. Marking code: PC8576D-2
0 0.5 1 mm
scale
Y
detail Y
A1
A2
A
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Product data sheet Rev. 14 — 10 June 2013 42 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
[1] Dimension not drawn to scale.
[2] Pad size.
[3] Passivation opening.
[1] Dimension not drawn to scale.
Table 23. Dimensions of PCF8576DU/DA
Original dimensions are in mm.
Unit (mm) A D E e[1] P1[2] P2[3] P3[2] P4[3]
max--------
nom 0.38 2.2 2.0 - 0.09 0.08 0.066 0.056
min - - - 0.072 - - - -
Table 24. Dimensions of PCF8576DU/2DA
Original dimensions are in mm.
Unit (mm) A A1A2b D E e[1] L
max-0.012------
nom 0.40 0.015 0.381 0.052 2.2 2.0 - 0.077
min - 0.018 - - - - 0.072 -
Table 25. Bonding pad location for PCF8576DU/x
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 3, Figure 26 and Figure 27).
Symbol Pad X (m) Y (m) Description
SDA 1 34.38 876.6 I2C-bus serial data input/output
SCL 2 109.53 876.6 I2C-bus serial clock input
SCL 3 181.53 876.6
SYNC 4 365.58 876.6 cascade synchronization input/output
CLK 5 469.08 876.6 external clock input/output
VDD 6 577.08 876.6 supply voltage
OSC 7 740.88 876.6 internal oscillator enable input
A0 8 835.83 876.6 subaddress inputs
A1 9 1005.48 630.9
A2 10 1005.48 513.9
SA0 11 1005.48 396.9 I2C-bus address input; bit 0
VSS 12 1005.48 221.4 ground supply voltage
VLCD 13 1005.48 10.71 LCD supply voltage
BP0 14 1005.48 156.51 LCD backplane outputs
BP2 15 1005.48 232.74
BP1 16 1005.48 308.97
BP3 17 1005.48 385.2
S0 18 1005.48 493.2 LCD segment outputs
S1 19 1005.48 565.2
S2 20 1005.48 637.2
S3 21 1005.48 709.2
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Product data sheet Rev. 14 — 10 June 2013 43 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
S4 22 347.22 876.6 LCD segment outp uts
S5 23 263.97 876.6
S6 24 180.72 876.6
S7 25 97.47 876.6
S8 26 14.22 876.6
S9 27 69.03 876.6
S10 28 152.28 876.6
S11 29 235.53 876.6
S12 30 318.78 876.6
S13 31 402.03 876.6
S14 32 485.28 876.6
S15 33 568.53 876.6
S16 34 651.78 876.6
S17 35 735.03 876.6
S18 36 1005.5 625.59
S19 37 1005.5 541.62
S20 38 1005.5 458.19
S21 39 1005.5 374.76
S22 40 1005.5 291.33
S23 41 1005.5 207.9
S24 42 1005.5 124.47
S25 43 1005.5 41.04
S26 44 1005.5 42.39
S27 45 1005.5 125.8
S28 46 1005.5 209.3
S29 47 1005.5 292.7
S30 48 1005.5 376.1
S31 49 1005.5 459.5
S32 50 1005.5 543
S33 51 1005.5 625.6
S34 52 735.03 876.6
S35 53 663.03 876.6
S36 54591.03 876.6
S37 55 519.03 876.6
S38 56 447.03 876.6
S39 57 375.03 876.6
SDA 58 196.38 876.6 I2C-bus serial data input/output
SDA 59 106.38 876.6
Table 25. Bonding pad location for PCF8576DU/x …continued
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip (see Figure 3, Figure 26 and Figure 27).
Symbol Pad X (m) Y (m) Description
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Product data sheet Rev. 14 — 10 June 2013 44 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent
standards.
Table 26. Alignment marks
All x/y coordinates represent the position of the center of each alignment mark with respect to the
center (x/y = 0) of the chip (see Figure 3, Figure 26 and Figure 27).
Symbol Location Dimension
X (m) Y (m) Diameter (m)
C1 930.42 870.3 72
C2 829.98 870.3 72
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Product data sheet Rev. 14 — 10 June 2013 45 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
18. Packing information
18.1 Tray information
Fig 28. Tray details
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;
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0
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-
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[
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PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 46 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
18.2 Carrier tape information
Table 27. Description of tray details
Tray details are shown in Figure 28.
Tray details
Dimensions
ABCDEFGHJKLMNUnit
3.6 3.6 2.36 2.11 50.8 45.72 39.6 5.6 5.6 39.6 3.96 2.18 2.49 mm
Number of pockets
x direction y direction
12 12
Fig 29. Tray alignment
DDD
PDUNLQJFRGH
Fig 30. Tape details
001aaj314
direction of feed
K04A0
P1
B0
W
pin 1 index
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Product data sheet Rev. 14 — 10 June 2013 47 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Table 28. Carrier ta pe dimensions
Symbol Description Value Unit
A0 pocket width in x direction 8.6 mm
B0 pocket width in y direction 14.5 mm
K0 pocket height 1.8 mm
P1 sprocket hole pitch 12 mm
W t ape width in y direction 24 mm
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Product data sheet Rev. 14 — 10 June 2013 48 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
19. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
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Product data sheet Rev. 14 — 10 June 2013 49 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
19.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low en ough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 29 and 30
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
Table 29. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Packag e reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 30. Lead-free proce ss (from J-STD-020D)
Package thickness (mm) Packag e reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 14 — 10 June 2013 50 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
20. Abbreviations
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 31. Abbreviations
Acronym Description
CDM Charged-Device Mode l
CMOS Complementary Metal-Oxide Semiconductor
HBM Huma n Body Model
ITO Indium Tin Oxide
LCD Liquid Crystal Display
LSB Least Significant Bit
MM Machine Model
MSB Most Significant Bit
MSL Moisture Sensitivity Level
PCB Printed Circu i t Boa r d
RAM Random Access Memory
RMS Root Mean Square
SCL Serial CLock line
SDA Serial DAta line
SMD Surface Mount Device
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 51 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
21. References
[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2] AN10365 — Surface mount reflow soldering description
[3] AN10706 — Handling bare die
[4] AN10853 — ESD and EMC sensitivity of IC
[5] IEC 60 13 4 Rating syst ems for electronic tubes and valves and analogous
semiconductor devices
[6] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[7] IPC/JEDEC J-STD-020D — Moisture/R eflow Sensitivity Classific ation for
Nonhermetic Solid State Surface Mount Devices
[8] JESD 22 -A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9] JESD 22 -A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[10] JESD 22 -C10 1 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[11] JESD78 — IC Latch-Up Test
[12] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[13] UM10204 — I2C-bus specification and user manual
[14] UM10569 — Store and transport requirements
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 52 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
22. Revision history
Table 32. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8576D v.14 2013 0610 Product data sheet - PCF8576D v.13
Modifications: Added improved IDD and IDD(LCD) val ues (Table 19)
Added bump height tolerance
Changed tray information (Section 18.1)
PCF8576D v.13 2012 0510 Product data sheet - PCF8576D v.12
PCF8576D v.12 2012 0413 Product data sheet - PCF8576D v.11
PCF8576D v.11 20110 627 Product data sheet PCF8576D v.10
PCF8576D v.10 20110214 Product data sheet - PCF8 576D_9
PCF8576D_9 20090825 Product data sheet - PCF8576D_8
PCF8576D_8 20090319 Product data sheet - PCF8576D_7
PCF8576D_7 20081218 Product data sheet - PCF8576D_6
PCF8576D_6 20081202 Product data sheet - PCF8576D_5
PCF8576D_5 20041222 Product specification - PCF8576D_4
PCF8576D_4 20041008 Product specification - PCF8576D_3
PCF8576D_3 20040617 Product specification - PCF8576D_2
PCF8576D_2 20030623 Product specification - PCF8576D_1
PCF8576D_1 20030401 Objective specification - -
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 53 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
23. Legal information
23.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
23.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe propert y or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains dat a from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 54 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive appl ications beyond NXP Semiconductors’
standard warrant y and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English version s.
Bare die — All die are tested on compliance with their related tech nical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditione d upon and sub ject to the custo mer enter ing into a
written die sale agreement with NXP Semiconductors through its legal
department.
23.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 55 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
25. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 5. Selection of possible display configurations. . . .7
Table 6. Biasing characteristics . . . . . . . . . . . . . . . . . . . .9
Table 7. Standard RAM filling in 1:3 multiplex drive
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 8. Entire RAM filling by rewriting in 1:3 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 9. Blinking frequencies . . . . . . . . . . . . . . . . . . . . .23
Table 10. Definition of PCF8576D commands . . . . . . . .24
Table 11. C bit description . . . . . . . . . . . . . . . . . . . . . . . .24
Table 12. Mode-set command bit description . . . . . . . . .25
Table 13. Load-data-pointer command bit description . . .25
Table 14. Device-select command bit description . . . . . .25
Table 15. Bank-select command bit description . . . . . . .2 6
Table 16. Blink-select command bit description . . . . . . . .2 6
Table 17. I2C slave address byte . . . . . . . . . . . . . . . . . . .29
Table 18. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .33
Table 20. Dynamic characteristics . . . . . . . . . . . . . . . . . .34
Table 21. Addressing cascaded PCF8576D . . . . . . . . . .36
Table 22. SYNC contact resistance . . . . . . . . . . . . . . . . .37
Table 23. Dimensions of PCF8576DU/DA . . . . . . . . . . . .42
Table 24. Dimensions of PCF8576DU/2DA . . . . . . . . . . .42
Table 25. Bonding pad location for PCF8576DU/x . . . . .42
Table 26. Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .44
Table 27. Description of tray details . . . . . . . . . . . . . . . . .46
Table 28. Carrier tape dimensions . . . . . . . . . . . . . . . . . .47
Table 29. SnPb eutectic process (from J-STD-020D) . . .49
Table 30. Lead-free process (from J-STD-020D) . . . . . .49
Table 31. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 32. Revision history . . . . . . . . . . . . . . . . . . . . . . . .52
PCF8576D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 14 — 10 June 2013 56 of 57
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
26. Figures
Fig 1. Block diagram of PCF8576D . . . . . . . . . . . . . . . . .3
Fig 2. Pinning diagram for PCF8576DT (TSSOP56). . . .4
Fig 3. Pinning diagram for PCF8576DU (bare die) . . . . .5
Fig 4. Example of displays suitable for PCF8576D . . . . .7
Fig 5. Typical system configuration . . . . . . . . . . . . . . . . .8
Fig 6. Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . .11
Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .12
Fig 8. Waveforms for the 1:2 multiplex drive mode
with 12 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 9. Waveforms for the 1:2 multiplex drive mode
with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 10. Waveforms for the 1:3 multiplex drive mode
with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 11. Waveforms for the 1:4 multiple x drive mode
with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Fig 12. Display RAM bit map. . . . . . . . . . . . . . . . . . . . . .18
Fig 13. Relationship between LCD layout, drive mode,
display RAM filling order and display data
transmitte d ove r th e I 2C-bus . . . . . . . . . . . . . . . .2 0
Fig 14. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Fig 15. Definition of START and STOP conditions. . . . . .27
Fig 16. System configuration. . . . . . . . . . . . . . . . . . . . . .28
Fig 17. Acknowledgement of the I2C-bus . . . . . . . . . . . .2 8
Fig 18. I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .30
Fig 19. Format of command byte. . . . . . . . . . . . . . . . . . .30
Fig 20. Device protection circuits. . . . . . . . . . . . . . . . . . .31
Fig 21. Driver timing waveforms . . . . . . . . . . . . . . . . . . .35
Fig 22. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .35
Fig 23. Cascaded PCF8576D configuration . . . . . . . . . .37
Fig 24. Synchronization of the cascade for the vari ous
PCF8576D drive modes . . . . . . . . . . . . . . . . . . .38
Fig 25. Package outline SOT364-1 (TSSOP56) . . . . . . .39
Fig 26. Bare die outline PCF8576DU/DA (for dimension s
see Table 23). . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Fig 27. Bare die outline PCF8576DU/2DA (for dimensions
see Table 24). . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Fig 28. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Fig 29. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Fig 30. Tape details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Fig 31. Temperature profi les for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 June 2013
Document identifier: PCF8576D
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
27. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Functional description . . . . . . . . . . . . . . . . . . . 7
7.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 8
7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8
7.3 LCD voltage select or . . . . . . . . . . . . . . . . . . . . 8
7.3.1 Electro-optical performance . . . . . . . . . . . . . . 10
7.4 LCD drive mode waveforms. . . . . . . . . . . . . . 12
7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12
7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 16
7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.7 Display register. . . . . . . . . . . . . . . . . . . . . . . . 17
7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17
7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18
7.10 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.10.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.10.2 Subaddre s s counter . . . . . . . . . . . . . . . . . . . . 21
7.10.3 RAM writing in 1:3 multiplex drive mode . . . . . 21
7.10.4 Writing over the RAM address boundary . . . . 22
7.10.5 Output bank selector . . . . . . . . . . . . . . . . . . . 22
7.10.6 Input bank selector. . . . . . . . . . . . . . . . . . . . . 23
7.11 Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.12 Command decoder. . . . . . . . . . . . . . . . . . . . . 24
7.13 Display controller . . . . . . . . . . . . . . . . . . . . . . 26
8 Characteristics of the I2C-bus . . . . . . . . . . . . 27
8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1.1 START and STOP conditions . . . . . . . . . . . . . 27
8.2 System configuration . . . . . . . . . . . . . . . . . . . 27
8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 29
8.5 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 29
9 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 31
10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Static characteristics . . . . . . . . . . . . . . . . . . . 33
12 Dynamic characteristics. . . . . . . . . . . . . . . . . 34
13 Application information . . . . . . . . . . . . . . . . . 36
13.1 Cascaded operation. . . . . . . . . . . . . . . . . . . . 36
14 Test information . . . . . . . . . . . . . . . . . . . . . . . 38
14.1 Quality information. . . . . . . . . . . . . . . . . . . . . 38
15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 39
16 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 40
17 Handling information . . . . . . . . . . . . . . . . . . . 44
18 Packing information . . . . . . . . . . . . . . . . . . . . 45
18.1 Tray information. . . . . . . . . . . . . . . . . . . . . . . 45
18.2 Carrier tape information . . . . . . . . . . . . . . . . . 46
19 Soldering of SMD pa ckages. . . . . . . . . . . . . . 48
19.1 Introduction to soldering. . . . . . . . . . . . . . . . . 48
19.2 Wave and reflow soldering. . . . . . . . . . . . . . . 48
19.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 48
19.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 49
20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50
21 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 52
23 Legal information . . . . . . . . . . . . . . . . . . . . . . 53
23.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 53
23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
23.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53
23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54
24 Contact information . . . . . . . . . . . . . . . . . . . . 54
25 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
26 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57