Features
•Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
•3.3V Output Capability
•5V Tolerant I/O Pins
•Program Support using the Atmel ATDH2200E System or Industry Third-party
Programmers
•In-System Programmable (ISP) via 2-wire Bus
•Simple Interface to SRAM FPGAs
•Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices,
Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs,
Motorola® MPA1000 FPGAs
•Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
•Low-power CMOS FLASH Process
•Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC and 44-lead TQFP Packages
•Emulation of Atmel’s AT24CXXX Serial EEPROMs
•Low-power Standby Mode
•Single Device Capable of Holding 4-bit Stream Files Allowing Simple System
Reconfiguration
•Fast Serial Download Speeds up to 33 MHz
•Endurance: 5,000 Write Cycles Typical
•Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17F Series Packages
Package AT17F040 AT17F080
8-lead LAP Yes Yes
20-lead PLCC Yes Yes
44-lead TQFP – Yes
FPGA
Configuration
Flash Memory
AT17F040
AT17F080
3039K–CNFG–2/08
2
3039K–CNFG–2/08
AT17F040/080
2. Pin Configuration
8-lead LAP
20-lead PLCC
20-lead PLCC (Virtex Pinout)(1)(2)
Notes: 1. 20-lead PLCC (Virtex pinout) is only available in the AT17F040.
2. Virtex pinout is compatible with the XC17V and XC18V Series PROM.
8
7
6
5
1
2
3
4
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
4
5
6
7
8
18
17
16
15
14
CLK
NC
RESET/OE
PAGESEL1
CE
NC
SER_EN
PAGE_EN
READY
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
PAGESEL0
NC
NC
NC
DATA
NC
VCC
NC
4
5
6
7
8
18
17
16
15
14
NC
NC
NC
NC
RESET/OE
SER_EN
NC
NC
READY
NC
3
2
1
20
19
9
10
11
12
13
NC
CE
GND
NC
CEO (A2)
CLK
NC
DATA
VCC
NC
3
3039K–CNFG–2/08
AT17F040/080
44 TQFP
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
4
3039K–CNFG–2/08
AT17F040/080
3. Block Diagram
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
5
3039K–CNFG–2/08
AT17F040/080
5. Pin Description
5.1 DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2 CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3 PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
Table 5-1. Pin Description
Name I/O
AT17F040 AT17F080
8
LAP
20
PLCC
20 PLCC
(Virtex)
8
LAP
20
PLCC
44
TQFP
DATA I/O1211240
CLK I2432443
PAGE_ENI–16– –1639
PAGESEL0 I – 11 – – 11 14
PAGESEL1I–7––719
RESET/OEI3683613
CE I4 8104 815
GND –5101151018
CEO O6141361421
A2 I
READY O–1515–1523
SER_EN I 7 17 18 7 17 35
VCC – 8 20 20 8 20 38
6
3039K–CNFG–2/08
AT17F040/080
5.4 PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-2. When
SER_EN is Low (ISP mode) these pins have no effect.
5.5 RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver.
5.6 CE(1)
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7 GND
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
5.8 CEO
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value
is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the
4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the
address maximum value is the highest address in the device, see Table 5-2 on page 6. In a
daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE
input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will
then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is
read again.
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
Table 5-2. Address Space
Paging Decodes AT17F040 (4 Mbits) AT17F080 (8 Mbits)
PAGESEL = 00, PAGE_EN = 1 00000 – 0FFFFh 00000 – 1FFFFh
PAGESEL = 01, PAGE_EN = 1 10000 – 1FFFFh 20000 – 3FFFFh
PAGESEL = 10, PAGE_EN = 1 20000 – 2FFFFh 40000 – 5FFFFh
PAGESEL = 11, PAGE_EN = 1 30000 – 3FFFFh 60000 – 7FFFFh
PAGESEL = XX, PAGE_EN = 0 00000 – 3FFFFh 00000 – 7FFFFh
7
3039K–CNFG–2/08
AT17F040/080
5.9 A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming
Specification available on the Atmel web site for additional details.
5.10 READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7 kΩ pull-up on this pin if used).
5.11 SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing
SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
5.12 VCC
+3.3V (±10%).
Notes: 1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
8
3039K–CNFG–2/08
AT17F040/080
6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17F Serial Configuration PROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are sim-
ple and self-explanatory.
• The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
• The CEO output of any AT17F Series Configurator drives the CE input of the next
Configurator in a cascade chain of configurator devices.
•SER_EN
must be connected to VCC (except during ISP).
• The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
• PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs
must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL
pins must be set to High or Low such that the desired page is selected, see Table 5-2 on
page 6.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the 2-wire serial bus. The programming is done at VCC supply only. Programming
super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal.
Refer to the AT17F Programming Specification available on the Atmel web site
(www.atmel.com) for more programming details. AT17F devices are supported by the Atmel
ATDH2200 programming system along with many third party programmers.
9
3039K–CNFG–2/08
AT17F040/080
10. Standby Mode
The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High
and CE is asserted High. In this mode, the AT17F Configurator consumes less than 1 mA of cur-
rent at 3.3V. The output remains in a high-impedance state regardless of the state of the OE
input.
11. Absolute Maximum Ratings*
Operating Temperature................................... -40°C to +85°C*NOTICE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature .................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +4.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
Symbol Description
AT17F Series Configurator
UnitsMin Max
VCC
Commercial Supply voltage relative to GND
-0°C to +70°C2.97 3.63 V
Industrial Supply voltage relative to GND
-40°C to +85°C2.97 3.63 V
13. DC Characteristics
Symbol Description
AT17F040 AT17F080
UnitsMin Max Min Max
VIH High-level Input Voltage 2.0 VCC 2.0 VCC V
VIL Low-level Input Voltage 0 0.8 0 0.8 V
VOH High-level Output Voltage (IOH = -2.5 mA) Commercial 2.4 2.4 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 V
VOH High-level Output Voltage (IOH = -2 mA) Industrial 2.4 2.4 V
VOL Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 V
ICCA Supply Current, Active Mode 20 20 mA
ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 µA
ICCS Supply Current, Standby Mode Commercial 1 1 mA
Industrial 1 1 mA
10
3039K–CNFG–2/08
AT17F040/080
14. AC Characteristics
15. AC Characteristics when Cascading
CE
RESET/OE
CLK
DATA
TSCE
TLC THC
TCAC
TOE
TCE
TOH
THOE
TSCE THCE
TDF
TOH
CE
RESET/OE
CLK
DATA
CEO
T
CDF
T
OCK
T
OCE
T
OCE
T
OOE
LAST BIT FIRST BIT
11
3039K–CNFG–2/08
AT17F040/080
Notes: 1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
4. See the AT17F Programming Specfication for procedural information.
16. AC Characteristics
Symbol Description
AT17F040/080
UnitsMin Max
TOE(2) OE to Data Delay Commercial 50 ns
Industrial(1) 55 ns
TCE(2) CE to Data Delay Commercial 55 ns
Industrial(1) 60 ns
TCAC(2) CLK to Data Delay Commercial 3 30 ns
Industrial(1) 30 ns
TOH Data Hold from CE, OE, or CLK Commercial 0 ns
Industrial(1) 0ns
TDF(3) CE or OE to Data Float Delay Commercial 15 ns
Industrial(1) 15 ns
TLC CLK Low Time Commercial 15 ns
Industrial(1) 15 ns
THC CLK High Time Commercial 15 ns
Industrial(1) 15 ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
Commercial 20 ns
Industrial(1) 25 ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
Commercial 0 ns
Industrial(1) 0ns
THOE
RESET/OE Low Time
(guarantees counter is reset)
Commercial 20 ns
Industrial(1) 20 ns
FMAX
Maximum Input Clock Frequency
SEREN = 0
Commercial 10 MHz
Industrial(1) 10 MHz
FMAX
Maximum Input Clock Frequency
SEREN = 1
Commercial 33 MHz
Industrial(1) 33 MHz
TWR Write Cycle Time(4) Commercial 12 µs
Industrial(1) 12 µs
TEC Erase Cycle Time(4) Commercial 13 s
Industrial(1) 13 s
12
3039K–CNFG–2/08
AT17F040/080
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
16.1 AC Characteristics When Cascading
Symbol Description
AT17F040 AT17F080
UnitsMin Max Min Max
TCDF(3) CLK to Data Float Delay Commercial 60 50 ns
Industrial 60 50 ns
TOCK(2) CLK to CEO Delay Commercial 55 50 ns
Industrial 60 55 ns
TOCE(2) CE to CEO Delay Commercial 55 35 ns
Industrial 60 40 ns
TOOE(2) RESET/OE to CEO Delay Commercial 40 35 ns
Industrial 45 35 ns
FMAX Maximum Input Clock Frequency Commercial 33 33 MHz
Industrial 33 33 MHz
13
3039K–CNFG–2/08
AT17F040/080
Note: 1. Airflow = 0 ft/min.
17. Thermal Resistance Coefficients
Package Type AT17F040 AT17F080
8CN4 Leadless Array Package (LAP)
θJC [°C/W] –
θJA [°C/W](1) –
20J Plastic Leaded Chip Carrier (PLCC)
θJC [°C/W] –
θJA [°C/W](1) –
44A Thin Plastic Quad Flat Package (TQFP)
θJC [°C/W] – 17
θJA [°C/W](1) –62
14
3039K–CNFG–2/08
AT17F040/080
Notes: 1. For the -30BJC and -30BJI packages, customers may migrate to the AT17F32-30BJU.
2. For the -30JC and -30JI packages, customers may migrate to the AT17Fxxx-30JU.
18. Ordering Information
Memory Size Ordering Code Package(1)(2) Operation Range
4-Mbit
AT17F040-30VJC 20J - 20 PLCC Commercial
(0°C to 70°C)
AT17F040-30VJI 20J - 20 PLCC Industrial
(-40°C to 85°C)
8-Mbit
AT17F080-30TQC 44A - 44 TQFP Commercial
(0°C to 70°C)
AT17F080-30TQI 44A - 44 TQFP Industrial
(-40°C to 85°C)
19. Green Package Options (Pb/Halide-free/RoHS Compliant)
Memory Size Ordering Code Package Operation Range
4-Mbit
AT17F040-30CU 8CN4 - 8 LAP
Industrial
(-40°C to 85°C)
AT17F040-30JU 20J - 20 PLCC
8-Mbit
AT17F080-30CU 8CN4 - 8 LAP
AT17F080-30JU 20J - 20 PLCC
Package Type
8CN4 8-lead, 6 mm x 6 mm x 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead
SOIC/VOIC Packages
20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)
44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
15
3039K–CNFG–2/08
AT17F040/080
20. Packaging Information
20.1 8CN4 – LAP
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8CN4DMH D
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
2/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
b 0.45 0.50 0.55 1
D 5.89 5.99 6.09
E 5.89 5.99 6.09
e 1.27 BSC
e1 1.10 REF
L 0.95 1.00 1.05 1
L1 1.25 1.30 1.35 1
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
16
3039K–CNFG–2/08
AT17F040/080
20.2 20J – PLCC
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE DRAWING NO. REV.
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 9.779 – 10.033
D1 8.890 – 9.042 Note 2
E 9.779 – 10.033
E1 8.890 – 9.042 Note 2
D2/E2 7.366 – 8.382
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1
D2/E2
B
e
E1 E
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B
20J
10/04/01
17
3039K–CNFG–2/08
AT17F040/080
20.3 44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
18
3039K–CNFG–2/08
AT17F040/080
21. Revision History
Revision Level – Release Date History
J – March 2006 Added last-time buy for AT17FXXX-30CC and AT17FXXX-30CI.
K – February 2008 Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering
information.
3039K–CNFG–2/08
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Product Contact
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Technical Support
configurator@atmel.com
Sales Contact
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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