Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
5V or 12V Single Output PWM Controller with PFM
Features
• Operating with Single 5~12V Supply Voltage or
Two Supply Voltages
• ±0.6% 0.5V Reference
- Over Line, Load Regulation, and Operating Temp.
• Drive Dual Low Cost N-Channel MOSFETs
- Adaptive Shoot-Through Protection
• Power-On-Reset Monitoring on VCC Pin
• High Efficiency at Light Load
• Constant-On-Time Control Scheme
- Switching Frequency Compensation for PWM
Operation
• 300kHz Constant Switching Frequency
• Integrated MOSFET Drivers and Bootstrap Diode
• Internal Integrated Soft-Start
• Built-In Ultrasonic Mode Control Scheme with PFM
• Adaptive Dead-Time Control
• Power Good Monitoring
• 70% Under-Voltage Protection
• 125% Pre-Over-Voltage and Over-Voltage
Protection
• Adjustable Current-Limit Protection
- Using Low-Side MOSFET’s RDS(ON)
• Over-Temperature Protection
• 3mmx3mm TDFN-10 (TDFN3x3-10) Package
• Lead Free and Green Devices Available
(RoHS Compliant)
General Description
The APW7190 is a single-phase, constant-on-time, syn-
chronous PWM controller, which drives N-channel MOS-
FETs. The APW7190 allows wide input voltage that is
either a single 5~12V or two supply voltage(s) for various
applications. An internal 0.5V temperature-compensated
reference voltage with high accuracy is designed to meet
the requirement of low output voltage applications.
The APW7190 is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On-Reset function monitors the voltage on VCC
to prevent wrong operation during power-on. The
APW7190 has a 4ms digital soft-start to ramp up the
output voltage with programmable slew rate to reduce
the start-up current. A soft-stop function actively dis-
charges the output capacitors with controlled reverse in-
ductor current.
The APW7190 is available in TDFN3x3-10 package.
The PWM controller operates fixed 300kHz pseudo-con-
stant frequency PWM with an adaptive constant-on-time
control. The device provides excellent transient response
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW7190 pro-
vides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. The device
works in ultrasonic mode with PFM at no load. The unique
ultrasonic mode maintains the switching frequency above
20kHz, which eliminates noise in audio applications.
Applications
• Mother Board
• Low Cost PC
• 5V or 12V-Input DC/DC Regulators
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw2
Ordering and Marking Information
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
= Thermal Pad (connected to the GND plane for better heat
dissipation)
Simplified Application Circuit
VOUT
LOUT
Q2
EN/EXTREF
APW7190
VIN
VCC=5Vor 12V
Q1
COUT
ROCSET
UGATE
PHASE
LGATE/OCSET
POK
TDFN3x3-10
Top View
PHASE 3
10 EN/EXTREFBOOT 1
UGATE 2
LGATE/OCSET 5
9 POK
7 FB
8 VOUT
GND 4 6 VCC
APW7190
Handling Code
Package Code
XXXXX -Date Code
Temperature Range
Assembly Material
APW
7190
XXXXX
APW7190 QB :
Package Code
QB : TDFN3x3-10
Temperature Range
I : -40 to 85 °C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw3
Symbol Parameter Rating Unit
VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V
VBOOT-GND BOOT Supply Voltage (BOOT to GND ) -0.3 ~ 30 V
VBOOT BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V
FB, EN/EXTREF and VOUT to GND -0.3 ~ 7 V
POK to GND -0.3 ~ VCC+0.3 V
UGATE Voltage (UGATE to PHASE)
<400ns pulse width
>400ns pulse width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3 V
LGATE/OCSET Voltage (LGATE to GND)
<400ns pulse width
>400ns pulse width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3 V
VPHASE PHASE Voltage (PHASE to GND)
<400ns pulse width
>400ns pulse width
-10 ~ 30
-0.3 ~ 16 V
TJ Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Thermal Characteristics
Symbol
Parameter Typical Value Unit
θJA Thermal Resistance -Junction to Ambient (Note 2) TDFN3x3-10 55 °C/W
θJC Thermal Resistance -Junction to Case (Note 3) TDFN3x3-10 5 °C/W
Note 2 : θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed
pad of package is soldered directly on the PCB.
Note 3 : The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-10 package.
Recommended Operating Conditions (Note 4)
Symbol Parameter Range Unit
VIN Converter Input Voltage 2.2 ~ 13.2 V
VCC VCC, PVCC Supply Voltage 4.5 ~ 13.2 V
VOUT Converter Output Voltage 0.5 ~ 3.3 V
IOUT Converter Output Current 0 ~ 40 A
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Note 4 : Refer to the typical application circuit.
Absolute Maximum Ratings (Note 1)
Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw4
Electrical Characteristics
These specifications apply for TA = -40°C to +85°C, unless otherwise stated. All typical specifications TA= +25°C, VIN= 12V, VCC = 12V.
APW7190
Symbol Parameter Test Conditions Min.
Typ. Max.
Unit
SUPPLY CURRENT
IVCC-PWM
VCC Input Bias Current
at PWM Mode
UGATE and LGATE Open - 1.7 2.5 mA
IVCC-PFM
VCC Input Bias Current at
PFM Mode
UGATE and LGATE Open - 350 550 µA
IVCC_SHDN VCC Shutdown Current - - 70 µA
FEEDBACK VOLTAGE
VREF Reference Voltage -
0.5
- V
Regulation Accuracy TA = -40 oC ~ 85 oC -0.6 - +0.6 %
Line and Load Regulation 0A < IOUT < 40A; 4V < VCC < 13.2V -0.2 - +0.2 %
IFB FB Input Bias Current VFB=0.5V -0.5 - +0.5 µA
PWM CONTROLLERS
TON(MIN) Minimum on Time of UGATE Over Temperature and VCC - 100 - ns
TOFF(MIN) Minimum off Time of UGATE Over Temperature and VCC - 350 - ns
TSS Internal Soft-Start Time From VFB=0V to POK Rises Up 3 4 5 ms
Zero Crossing Voltage
Threshold -3 0 +3 mV
PWM to PFM Debounce Time - 20 - µs
PFM to PWM Debounce Time - 20 - µs
PFM/PWM On Time Ratio PFM On Time / PWM On Time - 1.2 -
GATE DRIVER
UGATE Source Resistance VBOOT=12V, ISOURCE=100mA - 1.8 2.7 Ω
UGATE Sink Resistance VBOOT=12V, ISINK=100mA - 2.2 3.3 Ω
LGATE Source Resistance VCC=12V, ISOURCE=100mA - 1.2 1.8 Ω
LGATE Sink Resistance VCC=12V, ISINK=100mA - 1.4 2.1 Ω
UGATE Source Resistance VBOOT=5V, ISOURCE=100mA - 2.4 3.75 Ω
UGATE Sink Resistance VBOOT=5V, ISINK=100mA - 3 4.5 Ω
LGATE Source Resistance VCC=5V, ISOURCE=100mA - 1.8 2.7 Ω
LGATE Sink Resistance VCC=5V, ISINK=100mA - 1.8 2.7 Ω
Dead Time (Note 5) 20 25 60 ns
VCC POWER-ON-RESET (POR) THRESHOLD
VVCC_THR Rising VCC POR Threshold
Voltage 3.9 4.1 4.3 V
VCC POR Hysteresis 0.1 0.2 0.3 V
OSCILLATOR
FSW Switching Frequency in PWM
Mode DC Output Current,
VCC=4.5V~13.2V 270 300 330 kHz
Minimum Ultrasonic Operating
Frequency VCC=4.5V ~ 13.2V 20 25 - kHz
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw5
Electrical Characteristics (Cont.)
These specifications apply for TA = -40°C to +85°C, unless otherwise stated. All typical specifications TA= +25°C, VIN= 12V, VCC = 12V.
APW7190
Symbol Parameter Test Conditions Min.
Typ. Max.
Unit
CONTROL INPUTS
Shutdown Threshold,
EN/EXTREF Falling - - 0.4 V
External Reference, VOUT=VEN/EXTREF 0.5 - 3.3 V
EN/EXTREF Input Voltage
PWM on Logic High Threshold,
EN/EXTREF Rising 3.5 - - V
EN/EXTREF Leakage Current VEN/EXTREF=0V -0.1 - 0.1 µA
POWER OK INDICATOR (POK)
VFB is from low to target value
(POK Goes High) 93 95 97 %
~3µs noise filter, VFB Falling
(POK Goes Low) 65 70 75 %
VPOK POK Threshold
~3µs noise filter, VFB Rising
(POK Goes Low) 120 125 130 %
IPOK POK Leakage Current VPOK=5V - 0.1 1.0 µA
VPOK POK Output Low Voltage IPOK=-4mA - 0.5 1 V
PROTECTION
IOCSET IOCSET Source Current IOCSET Sourcing 9 10 11 µA
VOCSET_MAX
Built-in Maximum Current-Limit
Threshold Voltage 230 250 270 mV
VUV Under-Voltage Protection
Threshold 65 70 75 %
Under-Voltage Protection
Debounce Interval - 2 - µs
VOVR Over-Voltage Protection Rising
Threshold 120 125 130 %
Over-Voltage Protection Falling
Threshold 100 105 110 %
Over-Voltage Protection
Debounce Interval - 2 - µs
TOTR Over-Temperature Protection
Rising Threshold (Note 5) - 150 - oC
Over-Temperature Protection
Hysteresis (Note 5) - 20 - oC
Note 5 : Guaranteed by design.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw6
Typical Operating Characteristics
Input Voltage,VIN (V)
Switching Frequnecy vs. Input Voltage
Switching Frequency, FSW (kHz)
270
280
290
300
310
320
330
2 4 6 8 10 12 Outupt Current,IOUT (A)
Switching Frequnecy vs. Output Current
Switching Frequency, FSW (kHz)
0
50
100
150
200
250
300
350
0 5 10 15 20 25 30 35 40
Junction Temperature,TJ (oC)
Switching Frequency Over Temperature
Switching Frequency, FSW (kHz)
270
280
290
300
310
320
330
-40 -20 0 20 40 60 80 100
Reference Voltage,VREF (V)
Referece Voltage vs. Output Current
0.497
0.498
0.499
0.5
0.501
0.502
0.503
-40 -20 020 40 60 80 100
Junction Temperature,TJ (oC )
Efficiency vs. Output Current
Efficiency (%)
Output Current,IOUT (A)
11
0
H-Side:IPD090N03LGx1,
L-Side:IPD060N03LGx2
H-Side:IPD090N03LGx2,
L-Side:IPD060N03LGx2
H-Side:BSC090N03LSGx1,
L-Side:NTMFS4839NH-Dx2
H-Side:BSC090N03LSGx2,
L-Side:NTMFS4839NH-Dx2
VIN=12V, VCC=12V, L=1µH,VOUT=1.1V
0.1 100
101
0
10
20
30
40
50
60
70
80
90
100
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw7
Operating Waveforms
Enable at Zero Initial Voltage of VOUTEnable before End of Soft-Stop
CH1: VEN/EXTREF (5V/div)
CH2: VOUT (1V/div)
CH3: VPHASE (10V/div)
CH4: VPOK (10V/div)
Time: 5ms/div
CH1: VEN/EXTREF (5V/div)
CH2: VOUT (1V/div)
CH3: VPHASE (10V/div)
CH4: VPOK (10V/div)
Time: 10ms/div
Shutdown at IOUT=20AShutdown with Soft-Stop at No Load
CH1: VEN/EXTREF (5V/div)
CH2: VOUT (1V/div)
CH3: VPHASE (10V/div)
CH4: VPOK (10V/div)
Time: 20µs/div
CH1: VEN/EXTREF (5V/div)
CH2: VOUT (1V/div)
CH3: VPHASE (10V/div)
CH4: VPOK (10V/div)
Time: 50ms/div
1
2
3
4
VEN/EXTREF
VOUT
VPHASE
VPOK
1
2
3
4
VEN/EXTREF
VOUT
VPHASE
VPOK
1
2
3
4
VEN/EXTREF
VOUT
VPHASE
VPOK
1
2
3
4
VEN/EXTREF
VOUT
VPHASE
VPOK
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw8
Operating Waveforms (Cont.)
Mode Change
(External Mode <=> Internal Mode)Mode Transient of PWM to PFM
CH1: VEN/EXTREF (1V/div)
CH2: VOUT (1V/div)
Time: 10ms/div
CH1: VEN/EXTREF (1V/div)
CH2: VOUT (1V/div)
Time: 20ms/div
Load Transient
0A->10ALoad Transient
10A->0A
CH1: VPHASE (10V/div)
CH2: VLGATE (10V/div)
CH3: VOUT (AC, 50mV/div)
CH4: IL (10A/div)
Time: 10µs/div
CH1: VPHASE (10V/div)
CH2: VLGATE (10V/div)
CH3: VOUT (AC, 50mV/div)
CH4: IL (10A/div)
Time: 10µs/div
1
2
VEN/EXTREF
VOUT
1
2
VEN/EXTREF
VOUT
1
2
3
4
VPHASE
VLGATE
VOUT
IL
1
2
3
4
VPHASE
VLGATE
VOUT
IL
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw9
Operating Waveforms (Cont.)
Current-Limit and UV Protections
CH1: VPHASE (20V/div)
CH2: VLGATE (20V/div)
CH3: VOUT (500mV/div)
CH4: IL (10A/div)
Time: 200µs/div
Short Circuit Test
CH1: VPHASE (20V/div)
CH2: VLGATE (20V/div)
CH3: VOUT (500mV/div)
CH4: IL (10A/div)
Time: 10µs/div
Operating at UTRASONIC Mode
CH1: VPHASE (10V/div)
CH2: VLGATE (10V/div)
CH3: VOUT (AC,50mV/div)
CH4: IL (5A/div)
Time: 10µs/div
Operating at PFM Mode
CH1: VPHASE (10V/div)
CH2: VLGATE (10V/div)
CH3: VOUT (AC,50mV/div)
CH4: IL (5A/div)
Time: 2µs/div
1
2
3
4
VPHASE
VLGATE
VOUT
IL
1
2
3
4
VPHASE
VLGATE
VOUT
IL
1
2
3
4
VPHASE
VLGATE
VOUT
IL
1
2
3
4
VPHASE
VLGATE
VOUT
IL
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw10
Pin Description
PIN
NO. NAME FUNCTION
1 BOOT This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap
circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level
N-channel MOSFET.
2 UGATE Connect this pin to the high-side N-channel MOSFET’s gate. This pin provides gate drive for the
high-side MOSFET.
3 PHASE The pin provides return path for the high-side MOSFET driver’s pull-low current. Connect this pin
to the high-side MOSFET’s source.
4 GND The GND terminal provides return path for the IC’s bias current and the low-side MOSFET
driver’s pull-low current. Connect the pin to the system ground via very low impedance layout on
PCBs.
5 LGATE/OCSET
Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for
low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in
“Function Description” for detail.
6 VCC Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry
and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset
(POR) purpose.
7 FB Output Voltage Feedback pin. This pin is connected to the resistive divider that set the desired
output voltage. The PGOOD, UVP, and OVP circuits detect this signal to report output voltage
status.
8 VOUT The VOUT pin makes a direct measurement of the converter output voltage. The VOUT pin
should be connected to the top feedback resistor at the converter output.
9 POK POK is an open drain output used to indicate the status of the output voltage. Connect the POK
pin to +5V or +12V through a pull-high resistor.
10 EN/EXTREF
Enable/Shutdown Pin or External Reference Selection of The PWM Controller.
Operating Waveforms (Cont.)
Operating at PWM Mode
CH1: VPHASE (10V/div)
CH2: VLGATE (10V/div)
CH3: VOUT (AC,50mV/div)
CH4: IL (5A/div)
Time: 2µs/div
1
2
3
4
VPHASE
VLGATE
VOUT
IL
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw11
Block Diagram
FB
Error
Comparator
OV
UV
70% VREF
125% VREF
VREF
POR
VCC
EN/EXTREF
Digital
Soft-Start
PWM Signal Controller
VCC
BOOT
UGATE
PHASE
LGATE/OCSET
Thermal
Shutdown
GND
POK VOUT
Fault
Latch
Logic
On-Time
Generator
VREF x 95% /70%
VREF x125%
ZC
PHASE
Current-Limit
Debounce
Time
VCC
Sample
and Hold
VOCSET To LGATE/OCSET
10µA
VOCSET
Sense Low-Side
Ocillator
VOUT
VOUT
300kHz
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw12
Typical Application Circuit
EN/EXTREF
POK
VCC
GND
UGATE
BOOT
PHASE
LGATE/OCSET
VOUT
FB
RPOK
RVCC
CVCC
COUT
RTOP
RGND
Q1
Q2
LOUT
CBOOT
APW7190
CIN
VPOK VIN
VOUT
10K
2.2
1µF1.1K,1%
1K, 1%
CFB-VOUT
10nF
820µF x 3
1µH
2.2V ~ 13.2V
0.1µF
APM4350
APM4354
ROCSET
15K, 1%
5VBUS 12V
820µF x 2
5V
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw13
Function Description
Constant-On-Time PWM Controller with Input Feed-
Forward
The constant-on-time control architecture is a pseudo-
fixed frequency with input voltage feed-forward. This ar-
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
erator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
is more outstanding than a conventional constant-on-
time controller, which has large switching frequency varia-
tion over input voltage, output current, and temperature.
Both in PFM and PWM, the on-time generator, which
senses input voltage on PHASE pin, provides a very fast
on-time response to input line transients.
Another one-shot sets a minimum off-time (typical:
350ns). The on-time one-shot is triggered if the error com-
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
shot has timed out.
Pulse-Frequency Modulation (PFM)
In PFM mode, an automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point).
The on-time of PFM mode is designed at 1.2 time of the
nominal on-time of PWM mode. The on-time of PFM is
given by:
Where FSW is the nominal switching frequency of the con-
verter in PWM mode.
This design provides a hysteresis of converter output
current to prevent wrong or repeatedly PFM/PWM handoff
with constant output current. The load current at handoff
from PFM to PWM mode is given by:
The load current at handoff from PWM to PFM mode is
given by:
Therefore, the ILOAD(PFM to PWM) is 1.2 time of the ILOAD(PWM to PFM).
In this case, APW7190 operates in ultrasonic mode with
PFM when the load is zero. The ultrasonic mode is
illustrated as below description.
Ultrasonic Mode
The ultrasonic mode activates an unique PFM mode with
a minimum switching frequency of 20kHz. The minimum
frequency 20kHz of ultrasonic mode eliminates audio-
frequency interference in light load condition. It will transit
to an unique PFM mode when output loading makes the
frequency bigger than ultrasonic frequency.
In ultrasonic mode, the controller automatically transits
to fixed-frequency PWM operation when the load reaches
the same critical conduction point (ILOAD(PFM to PWM)).
When the controller detects that no switching has oc-
curred within about 40µs (Typical), an ultrasonic pulse
will be occurred. The ultrasonic controller turns on the
low-side MOSFET firstly to reduce the output voltage. Af-
ter feedback voltage drops below the internal reference
voltage, the controller turns off the low-side MOSFET and
triggers a constant-on-time. When the constant-on-time
has expired, the controller turns on the low-side MOSFET
again until the inductor current is below the zero-cross-
ing threshold. The behavior is the same as PFM mode.
IN
OUT
SW
PFMON V
V
x
F2.1
T=
−
IN
OUT
SW
OUTIN
PFM-ON
OUTIN
PWM) to LOAD(PFM
V
V
x
F
1.2
x
2L
V-V
xT
LV-V
x
2
1
I
=
=
IN
OUT
SW
OUTIN
PWM-ON
OUTIN
PFM) to LOAD(PWM
V
V
x
F1
x
2L
V-V
xT
LV-V
x
2
1
I
=
=
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw14
Function Description (Cont.)
Power-On-Reset (POR)
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.1V, typical), the POR signal goes
high and the chip initiates soft-start operations. When
this voltage drop lower than 3.9V (typical), the POR dis-
ables the chip.
EN/EXTREF Pin Control
The voltage (VEN/EXTREF) applied to EN/EXTREF pin se-
lects either enable-shutdown or adjustable external
reference. When VEN/EXTREF is above the EN high thresh-
old (3.5V, typical), the PWM is enabled. When VEN/EXTREF is
from 0.5V to 3.3V, the output voltage can be programmed
as same as VEN/EXTREF voltage. When VEN/EXTREF is below
the EN low threshold (0.4V, typical), the chip is in the
shutdown and only low leakage current is taken from
VCC.
Digital Soft-Start
The APW7190 integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
regulation setpoint at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
start process. The figure 1 shows soft-start sequence.
When the EN/EXTREF pin is pulled above the rising EN
threshold voltage, the VOCSET voltage is equal to 10µA x
ROCSET. When VCC rising POR threshold is triggered, the
device starts to sample and hold the current-limit setting
threshold. The sample time is as below:
During soft-start stage before the POK pin is ready, the
under-voltage protection is prohibited. The over-voltage
and over-current protection functions are enabled. If the
output capacitor has residue voltage before startup, both
low-side and high-side MOSFETs are in off-state until the
internal digital soft start voltage equal the VFB voltage.
This will ensure the output voltage starts from its existing
voltage level.
In the event of under-voltage, over-voltage, over-tempera-
ture or shutdown, the chip enables the soft-stop function.
The soft-stop function discharges the output voltage to
GND through an internal 20Ω switch. Cycling the EN/
EXTREF enable signal or VCC power-on-reset signal can
reset the latch.
Power OK Indicator
The APW7190 features an open-drain POK pin to indi-
cate output regulation status. In normal operation,when
the output voltage rises 95% of its target value, the POK
goes high. When the output voltage outruns 70% or 125%
of the target voltage, POK signal will be pulled low
immediately.
Since the FB pin is used for both feedback and monitor-
ing purposes, the output voltage deviation can be coupled
directly to the FB pin by the capacitor in parallel with the
voltage divider as shown in the typical applications. In
order to prevent false POK drop, capacitors need to par-
allel at the output to confine the voltage deviation with
severe load step transient and the POK comparator has
a built-in 3µs noise filter.
TSS = t2-t1 = 4ms
EN
VOUT
VCC
VPOK
t1t2
95% x VREF
V
t
t0
When current-limit setting action has finished, the device
initiates a soft-start process to ramp up the output voltage.
The soft-start interval, TSS, is about 4ms (typical value).
IOCSET(µA) x ROCSET(kΩ) x 5 x 10-3 sec.
Figure 1. Soft-Start Sequence
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw15
Function Description (Cont.)
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, the over-voltage protection compara-
tor designed with a 2µs noise filter will force the low-side
MOSFET gate driver fully turn on. This action actively pulls
down the output voltage. When the FB voltage decreases
below 105%, the OVP comparator is disengaged and
both high-side and low-side drivers turn off.
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can only be reset by toggling EN/EXTREF enable signal
or VCC power-on-reset signal.
Current-Limit
Figure 2. Current-Limit Algorithm
When the junction temperature increases above the ris-
ing threshold temperature TOTR , the IC will enter the over-
temperature protection state that suspends the PWM,
which forces the UGATE and LGATE gate drivers output
low. The thermal sensor allows the converters to start a
start-up process and regulate the output voltage again
after the junction temperature cools by 20oC. The OTP is
designed with a 20oC hysteresis to lower the average TJ
during continuous thermal overload conditions, which
increases lifetime of the APW7190.
Over-Temperature Protection (OTP)
Under-Voltage Protection (UVP)
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When the load current is
bigger than current-limit threshold value, the output volt-
age will fall out of the required regulation range. The un-
der-voltage protection circuit continually monitors the VFB
after soft-start is completed. If a load step is strong enough
to pull the output voltage lower than the under-voltage
threshold, the device starts to soft-stop process to shut
down the output gradually. The under-voltage threshold
is 70% of the normal output voltage. The under-voltage
comparator has a built-in 2µs noise filter to prevent the
chip from wrong UVP shutdown caused by noise. Cy-
cling the EN/EXTREF enable signal or VCC power-on-
reset signal can reset the latch.
The current-limit circuit employs a “valley” current-sens-
ing algorithm (See Figure 2). The APW7190 uses the
low-side MOSFET RDS(ON) of the synchronous rectifier as
a current-sensing element. If the magnitude of the cur-
rent-sense signal at PHASE pin is above the current-limit
threshold, the PWM is not allowed to initiate a new cycle.
The actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic
and maximum load capability are the functions of the
sense resistance, inductor value, and input voltage.
A resistor (ROCSET), connected from the LGATE/OCSET to
GND, programs the current-limit threshold. Before the IC
initiates a soft-start process, an internal current source,
IOCSET (10µA typical), flowing through the ROCSET develops
a voltage (VOCSET) across the ROCSET. The device holds
VOCSET and stops the current source, IOCSET, during normal
operation. The relationship between the sampled volt-
age VOCSET and the current-limit threshold ILIMIT is given by:
10µA x ROCSET = ILIMIT x RDS(ON)
ILIMIT can be expressed as IOUT minus half of peak-to-peak
inductor current.
The APW7190 has an internal current-limit voltage
(VOCSET_MAX), and the value is 0.25V typical. When the ROCSET
x IOCSET exceeds 0.25V or the ROCSET is floating or not
connected, the over current threshold will be the internal
default value 0.25V.
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
bined with the under-voltage protection circuit, this cur-
rent-limit method is effective in almost every circumstance.
Time
INDUCTOR CURRENT
0
IPEAK
IOUT
ILIMIT
ΔI
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw16
Application Information
Where 0.5 is the reference voltage, RTOP is the resistor
connected from converter’s output to FB, and RGND is the
resistor connected from FB to GND. Suggested RGND is in
the range from 1K to 20kΩ. To prevent stray pickup, lo-
cate resistors RTOP and RGND close to APW7190. Similarly,
when VEN/EXTREF is from 0.5V to 3.3V, the output voltage
can be programmed as same as VEN/EXTREF voltage.
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
IN
OUT
V
V
D=
IN
OUT
SW
OUTIN
RIPPLE V
V
LF V- V
I×
×
=
Output Capacitor Selection
The inductor value (L) determines the inductor ripple
current, IRIPPLE, and affects the load transient response.
Higher inductor value reduces the inductor’s ripple cur-
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
ESR
RIPPLEESR
SWOUT
RIPPLE
OUTC
RIVF8C
I
V
×=∆
=∆
Output Voltage Setting
The output voltage is adjustable from 0.5V to 3.3V with a
resistor-divider connected with FB, GND, and converter’s
output or the voltage (VEN/EXTREF) applied to EN/EXTREF
pin selects adjustable external reference. Using 1% or
better resistors for the resistor-divider is recommended.
The output voltage is determined by:
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
lator load transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW) also reduces
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
been chosen, selecting an inductor which is capable of
carrying the required peak current without going into
saturation. In some types of inductors, especially core
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This results in a larger output
ripple voltage. Besides, the inductor needs to have low
DCR to reduce the loss of efficiency.
Output voltage ripple, the transient voltage deviation and
the stability issue are factors which have to be taken into
consideration when selecting an output capacitor. Higher
capacitor value and lower ESR reduce the output ripple
and the load transient drop. Generally, selecting high per-
formance low ESR capacitors is recommended for
switching regulator applications. In addition to high fre-
quency noise related to MOSFET turn-on and turn-off, the
output voltage ripple includes the capacitance voltage
drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC
peak-to-peak inductor’s current. These two voltages can
be represented by:
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level.
Nevertheless, the constant-on-time (COT) control archi-
tecture relies on the output capacitor’s ESR to act as a
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. For stability issue, the output
ripple also need to be considered. By stability experi-
mentation result, suggesting the feedback ripple is about
25mV to 50mV.
To support a load transient that is faster than the switch-
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
+×= GND
TOP
OUT R
R
10.5V
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw17
Application Information
aspect of the capacitor selection is that the total AC cur-
rent going through the capacitors has to be less than the
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
Output Capacitor Selection (Cont.)
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select-
ing the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is
recommended. The capacitors must be connected be-
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impeadance PCB layout.
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reversing transfer capaci-
tance (CRSS) and maximum output current requirement.
The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side
and low-side MOSFETs, the losses are approximately
given by the following equations:
Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D)
Layout Consideration
During turn-off, current stops flowing in the MOSFET and
is freewheeling by the low side MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates a
large voltage spike during the switching interval. In
general, using short and wide printed circuit traces should
minimize interconnecting impedances and the magni-
tude of voltage spike. Besides, signal and power grounds
are to be kept separating and finally combined using
ground plane construction or single point grounding. Fig-
ure 3 illustrates the layout, with bold lines indicating high
current paths; these traces must be short and wide. Com-
ponents along the bold lines should be placed lose
together. Below is a checklist for your layout:
Where
IOUT is the load current
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition
loss. The switching interval, tSW, is the function of the re-
verse transfer capacitance CRSS. The (1+TC) term is a
factor in the temperature dependency of the RDS(ON) and
can be extracted from the “RDS(ON) vs. Temperature” curve
of the power MOSFET.
= Keep the switching nodes (UGATE, LGATE/OCSET,
BOOT, and PHASE) away from sensitive small signal
nodes since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as pos-
sible and there should be no other weak signal traces
in parallel with theses traces on any layer.
= The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATE and LGATE/OCSET) should
be short and wide.
= Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of
the node. In addition, the large layout plane between
the drain of the MOSFETs (VIN and PHASE nodes) can
get better heat sinking.
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at higher
frequency, the resulting current transient will cause volt-
age spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider the
turn-off transition of the PWM MOSFET. Before turn-off
condition, the MOSFET is carrying the full load current.
= Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the
drain of the high-side MOSFET as close as possible.)
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw18
= Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATE, LGATE/OCSET, BOOT, and PHASE).
= The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-
tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
Application Information (Cont.)
Layout Consideration (Cont.)
= The ROCSET resistance should be placed near the IC
as close as possible.
Close to IC
VCC
BOOT
PHASE
UGATE
LGATE/OCSET
VIN
VOUT
L
O
A
D
APW7190
ROCSET
Figure 3.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw19
Package Information
TDFN3x3-10
D
E
Pin 1
A
A1
A3
b
Pin 1
Corner
D2
E2L
e
0.70
0.069
0.028
0.002
0.50 BSC 0.020 BSC
0.20 0.008
K
2.90 3.10 0.114 0.122
2.90 3.10 0.114 0.122
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.18 0.30
2.20 2.70
0.05
1.40
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN3x3-10
0.30 0.50
1.75
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.087 0.106
0.055
0.012 0.020
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw20
Application
A H T1 C d D W E1 F
178.0±
2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN3x3-10
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.35±0.20
3.35±0.20
1.30±0.20
(mm)
Carrier Tape & Reel Dimensions
Devices Per Unit
Package Type Unit Quantity
TDFN3x3-10 Tape & Reel 3000
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw21
Taping Direction Information
t
TDFN3x3-10
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw22
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
ESD MIL-STD-883-3015.7 VHBM≧2KV, VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Reliability Test Program
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Mar., 2009
APW7190
www.anpec.com.tw23
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
