REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline Y, add vendor CAGE code 18324. 90-03-08 W. Heckman B Corrected supply voltage in 1.3 absolute max ratings. Technical changes to table I. Add new footnote 3/ to table I. Editorial changes throughout. 92-03-16 Monica Poelking C Update boilerplate to current MIL-PRF-38535 requirements. - CFS 06-02-08 Thomas M. Hess REV SHEET REV C C C C C C C C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Todd D. Creek STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Ray Monnin APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Michael A. Frye DRAWING APPROVAL DATE 04 April 1989 AMSC N/A REVISION LEVEL C DSCC FORM 2233 APR 97 MICROCIRCUIT, DIGITAL, CMOS, DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET 1 OF 5962-89532 34 5962-E131-06 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89532 01 Q X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 02 88C681, 2692 88C681, 2692 03 68C681 Circuit function Dual asynchronous receiver/transmitter (DUART) Dual asynchronous receiver/transmitter (DUART) with 7-bit input and 8-bit output ports Dual asynchronous receiver/transmitter (DUART) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Q X U Y Descriptive designator Terminals GDIP1-T40 or CDIP2-T40 GDIP1-T28 or CDIP2-T28 CQCC1-N44 See figure 1. 40 28 44 52 Package style Dual-in-line Dual-in-line Square leadless chip carrier Flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range................................................................................................................. -0.5 V dc to +7.0 V dc Storage temperature range ....................................................................................................... -65C to +150C Maximum power dissipation (PD)............................................................................................... 1.0 W Lead temperature (soldering, 5 seconds).................................................................................. +300C Maximum junction temperature (TJ) .......................................................................................... +175C Thermal resistance, junction-to-case (JC): Cases X, Q, and U ............................................................................................................. See MIL-STD-1835 Case Y ............................................................................................................................... 20C/W 1.4 Recommended operating conditions. Supply voltage (VCC) ................................................................................................................. 4.5 V dc to 5.5 V dc Minimum high level input voltage (VIH): Logic inputs........................................................................................................................ 2.0 V dc X1/CLK input...................................................................................................................... 4.0 V dc Maximum low level input voltage (VIL) ....................................................................................... 0.8 V dc Maximum high level output current (IOH).................................................................................... -400 A Maximum low level output current (IOL) ..................................................................................... 2.4 mA Case operating temperature range (TC) .................................................................................... -55C to +125C STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 3 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type 1, 2, 3 All Limits Min Unit Max Input low voltage VIL Input high voltage (except X1/CLK) VIH 2.0 V Input high voltage (X1/CLK) VIH 4.0 V Output low voltage VOL IOL = 2.4 mA, VCC = 4.5 V Output high voltage (except open collector outputs) VOH IOH = -400 A, VCC = 4.5 V 2.4 Input leakage current IIL VI = 0 V to VCC -25 10 A Data bus three-state leakage current IOZL, IOZH VO = 0.4 V to VCC -10 10 A X1/CLK low input current IIL (X1) VI = 0 V, X2 grounded -6.0 0.0 mA X1/CLK high input current IIH (X1) VI = VCC, X2 grounded -1.0 1.0 mA X2 low input current IIL (X2) VI = 0 V, X1/CLK floated -100 0.0 A IIH (X2) VI = VCC, X1/CLK floated 0.0 100 A Open collector output leakage current IOH VO = 0.4 V to VCC -10 10 A Power supply current ICC VCC = 5.5 V 15 mA Input capacitance CIN VIN = 0 V, FC = 1 MHz See 4.3.1c 20 pF X2 high input current 3/ 3/ Functional tests 0.8 V 0.4 4 See 4.3.1d V V 7, 8 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics - Continued. Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Reset pulse width tRES See figure 4. A0-A3 setup time to RDN, WRN low Test Group A subgroups Device type 9, 10, 11 01, 02 Limits Min 4/ Unit Max 1.0 ns tAS 10 ns A0-A3 hold time from RDN, WRN low tAH 100 ns CEN setup time to RDN, WND low tCS 0 ns CEN hold time from RDN, WRN high tCH 0 ns WRN, RDN pulse width tRW 225 ns Data valid after RDN low tDD 175 ns Data bus floating after RDN high tDF 110 ns Data setup time before WRN high tDS 100 ns Data hold time after WRN high tDH 20 ns High time between READS and/or WRITES 5/ 6/ tRWD 200 ns Port input setup time before RDN low tPS 0 ns Port input hold time after RDN high tPH 0 ns Port output valid after WRN high tPD 400 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Limits Min INTRN (or OP3-OP7 when used as interrupts) negated from: Read RHR (RxRDY/FFULL interrupt) tIR1 Write THR (TxRDY interrupt See figure 4. Unit Max 4/ 9, 10, 11 01, 02 325 ns tIR2 325 ns Reset command (delta break interrupt) tIR3 325 ns Stop C/T command (counter interrupt) tIR4 325 ns Read IPCR (input port change interrupt) tIR5 325 ns Write IMR (clear of interrupt mask bit) tIR6 325 ns X1/CLK high or low time tCLK 100 X1/CLK frequency fCLK 2.0 CTCLK (IP2) high or low time tCTC 100 CTCLK (IP2) frequency 7/ fCTC 0 RxC high or low time tRX 220 fRX 0 2.0 MHz fRX 0 1.0 MHz tTX 220 fTX 0 2.0 MHz fTX 0 1.0 MHz 350 ns RxC frequency (16X) RxC frequency (1X) 7/ 7/ TxC high or low time TxC frequency (16X) TxC frequency (1X) 7/ 7/ TxD output delay from TxC low tTXD ns 4.0 MHz ns 4.0 MHz ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics - Continued. Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Output delay from TxC low to TxD data output tTCS See figure 4. RxD data setup time to RxC high tRXS 240 ns RxD data hold time from RxC high tRXH 200 ns RESETN pulse width tRES 1.0 s A1-A4 setup to CSN low tAS 10 ns A1-A4 hold time from CSN high tAH 0 ns R/WN setup time to CSN high tRWS 0 ns R/WN holdup time to CSN high tRWH 0 ns CSN high pulse width tCSW 90 ns CSN or IACKN high from DTACKN low 9/ tCSD 20 ns Data valid from CSN or IACKN low tDD 175 ns Data bus floating from CSN or IACKN high tDF 100 ns Data setup time to CLK high tDS 100 ns Data hold time from CSN high tDH 0 ns DTACKN low from read data tDAL 0 ns DTACKN low (read cycle) from CLK high tDCR 125 ns DTACKN low (write cycle) from CLK high tDCW 125 ns DTACKN high from CSN or IACKN high tDAH 100 ns DTACKN high impedance from CSN or IACKN high tDAT 125 ns Test 8/ 4/ Group A subgroups Device type 9, 10, 11 01, 02 03 Limits Unit Min Max 0 150 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 8 TABLE I. Electrical performance characteristics - Continued. Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified CSN or IACKN setup time to clock high 10/ tCSC See figure 4. Port input setup to CSN low Test Group A subgroups Device type 9, 10, 11 03 Limits Min 4/ Unit Max 90 ns tPS 0 ns Port input hold time CSN high tPH 0 ns Port output valid from CSN high tPD 400 ns 325 ns INTRN, or OP3-OP7 when used as interrupts, negated from: Read RHR (RxRDY/FFULL interrupts) tIR1 Write THR (TxRDY interrupt) tIR2 325 ns Reset command (delta break interrupt) tIR3 325 ns Stop C/T command (counter interrupts) tIR4 325 ns Read IPCR (input port change interrupt) tIR5 325 ns Write IMR (clear of interrupt mask bit) tIR6 325 ns X1/CLK high or low time tCLK 100 X1/CLK frequency fCLK 2.0 CTCLK high or low time tCTC 100 CTCLK frequency fCTC 0 RxC high or low time tRX 220 RxC frequency (16X) fRX 0 2.0 MHz RxC frequency (1X) fRX 0 1.0 MHz 9, 10, 11 03 ns 4.0 MHz ns 4.0 MHz ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 9 TABLE I. Electrical performance characteristics - Continued. Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified TxC high or low time tTX See figure 4. TxC frequency (16X) fTX 0 2.0 MHz TxC frequency (1X) fTX 0 1.0 MHz TxD output delay from TxC low tTXD 350 ns Output delay from TxC low to TxD data output tTCS 0 150 ns RxD data setup time to RxC high tRXS 240 ns RxD data hold time from RxC high tRXH 200 ns Test Group A subgroups Device type 9, 10, 11 03 Limits Min 4/ Unit Max 220 ns 1/ All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a transition time of < 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements referenced at input voltages of 0.8 V and 2.0 V as appropriate. 2/ Test condition for outputs: CL = 150 pF tied to ground, except interrupt outputs. Test condition for interrupt outputs: CL = 50 pF tied to ground, RL = 2.7 k to VCC. 3/ For CMOS technology: IIL(X2) X1/CLK = VCC, IIH(X2) X1/CLK = 0.0 V. 4/ Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the "strobing" input. In this case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are AND'ed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 5/ If CEN is used as the "strobing" input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must be negated for tRWD to guarantee that any status register changes are valid. 6/ Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 7/ Minimum frequencies may not be tested, but are guaranteed by design. 8/ This specification will impose maximum 68000 CPU CLK to 6 MHz. Higher CPU CLK can be used if repeating bus reads are not performed. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 9/ This specification imposed a lower bound on CSN and IACKN low, guaranteeing that it will be low for at least 1 CLK period. This requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part. 10/ This specification is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram, not to guarantee operation of the part. If the setup time is violated, DTACKN may be asserted as shown, or may be asserted one clock cycle later. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 10 Case Y Symbol A b c D E E1 e L Q S S1 Inches Min Max .045 .100 .015 .026 .008 .015 --1.330 .620 .660 .488 .498 .050 BSC .250 .370 .054 .066 --.045 .005 --- Millimeters Min Max 1.14 2.54 0.38 0.66 0.20 0.38 --33.78 15.75 16.76 12.40 12.65 1.27 BSC 6.35 9.40 1.37 1.68 --1.14 0.13 --- Notes 7 7 4 5 6 NOTES: 1. Dimensions are in inches. 2. Metric equivalents are for general information only. 3. A lead tap (enlargement) or index dot is located within the shaded area shown at pin 1. Other pin numbers proceed sequentially from pin 1 counterclockwise (as viewed from the top of the device). 4. This dimension allows for off-center lid, meniscus, and glass overrun. 5. The reference pin spacing is .050 (1.27 mm) between centerlines. Each pin centerline is located within .005 (0.13 mm) of its longitudinal position relative to the first and last pin numbers. 6. This dimension is measured at the point of exit of the lead body. 7. Lead dimensions include .003 inch allowance for hot solder dip lead finish. FIGURE 1. Case outlines. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 11 Device type: Case outline: Terminal Terminal number symbol 1 A0 2 A1 3 A2 4 A3 5 WRN 6 RDN 7 RxDB 8 TxDB 9 OP1 10 D1 11 D3 12 D5 13 D7 14 GND Device type: Case outline: Terminal Terminal number symbol 1 A0 2 IP3 3 A1 4 IP1 5 A2 6 A3 7 IP0 8 WRN 9 RDN 10 RxDB 11 TxDB 12 OP1 13 OP3 14 OP5 15 OP7 16 D1 17 D3 18 D5 19 D7 20 GND 01 X Terminal number 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Terminal symbol INTRN D6 D4 D2 D0 OP0 TxDA RxDA X1/CLK X2 RESET CEN IP2 VCC 02 Q Terminal number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Terminal symbol INTRN D6 D4 D2 D0 OP6 OP4 OP2 OP0 TxDA RxDA X1/CLK X2 RESET CEN IP2 IP6 IP5 IP4 VCC FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 12 Device type: Case outline: Terminal Terminal number symbol 1 NC 2 A0 3 IP3 4 A1 5 IP1 6 A2 7 A3 8 IP0 9 WRN 10 RDN 11 RxDB Terminal number 12 13 14 15 16 17 18 19 20 21 22 Terminal symbol NC TxDB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND Terminal number 23 24 25 26 27 28 29 30 31 32 33 02 U Terminal symbol NC INTRN D6 D4 D2 D0 OP6 OP4 OP2 OP0 TxDA Terminal number 34 35 36 37 38 39 40 41 42 43 44 Terminal symbol NC RxDA X1/CLK X2 RESET CEN IP2 IP6 IP5 IP4 VCC Terminal number 27 28 29 30 31 32 33 34 35 36 37 38 39 02 Y Terminal symbol INTRN D6 D4 D2 D0 NC NC NC OP6 OP4 OP2 OP0 TxDA Terminal number 40 41 42 43 44 45 46 47 48 49 50 51 52 Terminal symbol RxDA X1/CLK X2 RESET CEN NC NC NC IP2 IP6 IP5 IP4 VCC NC = No connection. Device type: Case outline: Terminal Terminal number symbol 1 A0 2 IP3 3 A1 4 IP1 5 A2 6 A3 7 NC 8 NC 9 NC 10 IP0 11 WRN 12 RDN 13 RxDB Terminal number 14 15 16 17 18 19 20 21 22 23 24 25 26 Terminal symbol TxDB OP1 OP3 OP5 OP7 NC NC NC D1 D3 D5 D7 GND NC = No connection. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 13 Device type: Case outline: Terminal Terminal number symbol 1 A1 2 IP3 3 A2 4 IP1 5 A3 6 A4 7 IP0 8 R/WN 9 DTACKN 10 RxDB 11 TxDB 12 OP1 13 OP3 14 OP5 15 OP7 16 D1 17 D3 18 D5 19 D7 20 GND Device type: Case outline: Terminal Terminal number symbol 1 NC 2 A1 3 IP3 4 A2 5 IP1 6 A3 7 A4 8 IP0 9 R/WN 10 DTACKN 11 RxDB Terminal number 12 13 14 15 16 17 18 19 20 21 22 Terminal symbol NC TxDB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND 03 Q Terminal number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Terminal number 23 24 25 26 27 28 29 30 31 32 33 Terminal symbol INTRN D6 D4 D2 D0 OP6 OP4 OP2 OP0 TxDA RxDA X1/CLK X2 RESETN CSN IP2 IACKN IP5 IP4 VCC 03 U Terminal symbol NC INTRN D6 D4 D2 D0 OP6 OP4 OP2 OP0 TxDA Terminal number 34 35 36 37 38 39 40 41 42 43 44 Terminal symbol NC RxDA X1/CLK X2 RESETN CSN IP2 IACKN IP5 IP4 VCC NC = No connection. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 14 Device types 01 and 02 NOTE: Device type 01 does not have 7-bit input port and 8-bit output port (see 6.7 pin descriptions). FIGURE 3. Functional block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 15 Device type 03 FIGURE 3. Functional block diagram - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 16 Device types 01 and 02 FIGURE 4. Timing waveforms and test circuits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 17 Device types 01 and 02 NOTES: 1. INTRN or OP3 - OP7 when used as interrupt outputs. 2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of the response is referenced from the midpoint of the switching signal, VM, to a point 0.5 V above VOL. This point represents the noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 18 Device types 01 and 02 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 19 Device types 01 and 02 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 20 Device type 03 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 21 Device type 03 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 22 Device type 03 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 23 Device type 03 NOTES: 1. INTRN or OP3 - OP7 when used as interrupt outputs. 2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of the response is referenced from the midpoint of the switching signal, VM, to a point 0.5 V above VOL. This point represents the noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 24 Device type 03 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 25 Device type 03 FIGURE 4. Timing waveforms and test circuits - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 26 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005) Subgroups (in accordance with MIL-STD-883, method 5005, table I) 1 1*, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which may affect capacitance. A minimum sample size of five devices with zero rejects shall be required. d. Subgroups 7 and 8 shall include verification of the instruction set. The instruction set forms a part of the vendors test tape and shall be maintained and available from the approved sources of supply. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 27 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Pin descriptions. The pin descriptions for the device types herein are as defined in table III as follows: STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 28 TABLE III. Pin descriptions. For device types 01 and 02. Mnemonic 28 01 Package Number of pins: 40 44 Device: 02 02 52 Name and function Type 02 D0 - D7 X X X X I/O CEN X X X X I Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on D0 - D7 as controlled by the WRN, RDN, and A0 - A3 inputs. When high, places the D0 - D7 lines in three-state condition. WRN X X X X I Write Strobe: When low and CEN is also low, the contents of the data bus are loaded into the addressed register. The transfer occurs on the rising edge of the signal. RDN X X X X I Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. A0 - A3 X X X X I Address Inputs: Selects the DUART internal registers and ports for read/write operations. RESET X X X X I Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0 - OP7 in the high state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high) state. INTRN X X X X O Interrupt Request: Active low, open drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. X1/CLK X X X X I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see figure 4 herein). X2 X X X X RxDA X X X X I Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is high, "space" is low. RxDB X X X X I Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is high, "space" is low. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see figure 4 herein). SIZE 5962-89532 A REVISION LEVEL C SHEET 29 TABLE III. Pin descriptions - Continued. For device types 01 and 02. Mnemonic 28 01 Package Number of pins: 40 44 Device: 02 02 52 Type Name and function 02 TxDA X X X X O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle, or when operating in local loopback mode. "Mark" is high, "space" is low. TxDB X X X X O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle, or when operating in local loopback mode. "Mark" is high, "space" is low. OPO X X X X O Output 0: General purpose output, or channel A request to send (RTSAN, active low). Can be deactivated automatically on receive or transmit. OP1 X X X X O Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be deactivated automatically on receive or transmit. OP2 X X X O Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output. OP3 X X X O Output 3: General purpose output, or open drain, active low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. OP4 X X X O Output 4: General purpose output, or channel A open drain, active low, RxRDYA/FFULLA output. OP5 X X X O Output 5: General purpose output, or channel B open drain, active low, RxRDYB/FFULLB output. OP6 X X X O Output 6: General purpose output, or channel A open drain, active low, TxRDYA output. OP7 X X X O Output 7: General purpose output, or channel B open drain, active low, TxRDYB output. IP0 X X X I Input 0: General purpose input, or channel A clear to send active low input (CTSAN). IP1 X X X I Input 1: General purpose input, or channel B clear to send active low input (CTSBN). X X X I Input 2: General purpose input, or counter/timer external clock input. IP2 X STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 30 TABLE III. Pin descriptions - Continued. For device types 01 and 02. Mnemonic 28 01 Package Number of pins: 40 44 Device: 02 02 52 Type Name and function 02 IP3 X X X I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. IP4 X X X I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 X X X I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. IP6 X X X I Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. VCC X X X X I Power Supply: +5 V supply input. GND X X X X I Ground: Ground. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 31 TABLE III. Pin descriptions - Continued. For device type 03. Mnemonic Pin number 1/ Name and function Type 25, 16, 24, 17, 23, 18, 22, 19 I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. CSN 35 I Chip Select: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on D0 - D7 as controlled by the R/WN and A1 - A4 inputs. When high, places the D0 - D7 lines in the three-state condition. R/WN 8 I Read/Write: A high input indicates a read cycle and a low input indicates a write cycle, when a cycle is initiated by assertion of the CSN input. A1 - A4 1, 3, 5, 6 I Address Inputs: Selects the DUART internal registers and ports for read/write operations. RESETN 34 I Reset: A low clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts OP0 - OP7 in the high state, stops the counter/timer, and puts channel A and B in the inactive state, with the TxDA and TxDB outputs in the "mark" (high) state. DTACKN 9 O Data Transfer Acknowledge: Three-state active low output asserted in write, read, or interrupt cycles to indicate proper transfer of data between the CPU and the DUART. INTRN 21 O Interrupt Request: Active low, open drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true. IACKN 37 I Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. In response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending. X1/CLK 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. If a crystal is used, a capacitor must be connected from this pin to ground (see figure 4 herein). X2 33 I Crystal 2: Connection for other side of the crystal. If a crystal is used, a capacitor must be connected from this pin to ground (see figure 4 herein). If an external clock is used, this pin should be grounded. RxDA 31 I Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is high, "space" is low. RxDB 10 I Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is high, "space" is low. D0 - D7 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 32 TABLE III. Pin descriptions - Continued. For device type 03. Mnemonic Pin number 1/ Name and function Type TxDA 30 O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle, or when operating in local loopback mode. "Mark" is high, "space" is low. TxDB 11 O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle, or when operating in local loopback mode. "Mark" is high, "space" is low. OPO 29 O Output 0: General purpose output, or channel A request to send (RTSAN, active low). Can be deactivated automatically on receive or transmit. OP1 12 O Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be deactivated automatically on receive or transmit. OP2 28 O Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output. OP3 13 O Output 3: General purpose output, or open drain, active low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. OP4 27 O Output 4: General purpose output, or channel A open drain, active low, RxRDYA/FFULLA output. OP5 14 O Output 5: General purpose output, or channel B open drain, active low, RxRDYB/FFULLB output. OP6 26 O Output 6: General purpose output, or channel A open drain, active low, TxRDYA output. OP7 15 O Output 7: General purpose output, or channel B open drain, active low, TxRDYB output. IP0 7 I Input 0: General purpose input, or channel A clear to send active low input (CTSAN). IP1 4 I Input 1: General purpose input, or channel B clear to send active low input (CTSBN). IP2 36 I Input 2: General purpose input, or channel B receiver external clock input (RxCB), or counter/timer external clock input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 33 TABLE III. Pin descriptions - Continued. For device type 03. Mnemonic 1/ Pin number 1/ Name and function Type IP3 2 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. IP4 39 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 38 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. VCC 40 I Power Supply: +5 V supply input. GND 20 I Ground: Ground. All pin numbers are for dual-in-line package except 52 pin flat package. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89532 A REVISION LEVEL C SHEET 34 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-02-08 Approved sources of supply for SMD 5962-89532 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8953201XA 0C7V7 2692/BXA 3/ XR88C681YA883C 0C7V7 2692/BQA 3/ XR88C681QA883C 0C7V7 2692/BUA 3/ XR88C681XC883C 5962-8953202YA 0C7V7 2692/BYA 5962-8953203QA 3/ XR68C681QA883C 5962-8953203UA 3/ XR68C681X883C 5962-8953202QA 5962-8953202UA 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply Vendor CAGE number 0C7V7 Vendor name and address QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.