Dual N-Channel JFET Switch
U401 – U406
FEATURES
••Minimum System Error and Calibration
••Low Drift With Temperature
••Operates From Low Powe r Supp ly Voltage s
••High Outp ut Impeda nce
ABSOLUTE M AXIM UM R A T INGS
(TA = 25oC unless oth erw ise specified)
Gate- Dr ain or Gate -So urce Voltage . . . . . . . . . . . . . . . . . 50V
Gate Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Stor age Temper at ure R a nge. . . . . . . . . . . . . -65oC t o +200oC
Oper at ing Temper atur e Ra nge . . . . . . . . . . . - 55oC t o +150oC
Lead Temperatu re (So ld erin g, 10sec). . . . . . . . . . . . . +300oC
On e Side Both Si des
Power Dissipation (TA = 8 5oC) 300mW 500mW
Derate above 25oC2.6mW/
oC5mW/
oC
NOTE: Str esses above those listed under "Abso lute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the sp ecifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affec t device reliability.
ORDERING INFORMATION
Part Package Temperat ure Range
U401-6 Herm etic T O- 71 -55 oC to +150oC
XU401-6 Sort ed Chips in Carr iers -55 oC to +150oC
CORPORATION
PIN CONFIGUR ATI O N
S2 G1 D2 D1G2 S1
TO-71
CJ2
ELECTRICA L CHARACTERI STIC S (TA = 2 5oC unle ss otherwise sp ecif ie d)
SYMBOL PARAMETER U401 U402 U403 U404 U405 U406 UNITS TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
BVGSS Gate-Source
Breakdown Voltage -50 -50 -50 -50 -50 -50 V VDS = 0, IG = -1µA
IGSS Gate Reverse Current
(Note 2) -25 -25 -25 -25 -25 -25 pA VDS = 0, VGS = -30V
VGS(off) Gate-Source Cutoff
Voltage -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 VVDS = 15V, ID = 1nA
VGS(on) Gate-Source Voltage
(on) -2.3 -2.3 -2.3 -2.3 -2.3 -2.3 VDG = 15V, ID = 200µA
IDSS Saturation Drain
Current (Note 3) 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 mA VDS = 10V, VGS = 0
IGOperating Gate
Curr ent (Note 2) -15 -15 -15 -15 -15 -15 pA VDG = 15V, ID = 200µA
-10 -10 -10 -10 -10 -10 nA TA = 125oC
BVG1-G2 Gate-Gate
Breakdown Voltage ±50 ±50 ±50 ±50 ±50 ±50 VVDS = 0, VGS = 0,
IG = ±1µA
gfs
Common-Source
Forward
Transconductance
(Note 3)
2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
µS
VDS = 10V,
VGS = 0 f = 1kHz
gos Common-Source
Output Conductance 20 20 20 20 20 20
gfs Common-Source
Forward
Transconductance 1000 2000 1000 2000 1000 2000 1000 2000 1000 2000 1000 2000
VDG = 1 5V,
ID = 200µA
f = 1kHz
gos Common-Source
Output Conductance 2.0 2.0 2.0 2.0 2.0 2.0
Ciss Common-Source
Input Capacitance
(Note 6) 8.0 8.0 8.0 8.0 8.0 8.0
pF f = 1MHz
Crss Common-Source
Reverse Transfer
Capa cita nce (N ote 6) 3.0 3.0 3.0 3.0 3.0 3.0
enEquivalent
Short-Circuit Input
Noise V oltage 20 20 20 20 20 20 nV
√Hz VDS = 15V,
VGS = 0 f = 10Hz
(Note 6)
CMRR Common-Mode
Rejection Ratio 95 95 95 95 90 dB VDG = 10 to 20V,
ID = 200µA (Note 5, 6)
| VGS1 −VGS2 | Differential
Gate-Source Voltage 5 1010152040mV
VDG = 10V, ID = 200µA
| ∆VGS1 −VGS2 |
∆T
Gate-Source Voltage
Differential Drift (Note
4) 10 10 25 25 40 80 µV/oCVDG = 10V,
ID = 200µA
TA = -55oC
TB = +25oC
TC = +125oC
NOTES: 1. Per transistor.
2. Approximately doubles for every 10oC increas e in T A.
3. Pulse test duration = 300µs; duty c y cle ≤3%.
4. Measured at end points TA, TB, TC.
5. CMRR = 20 log10
∆VDD
∆ | VGS1 −VGS2 |
, ∆VDD = 10V.
6. For design reference only, not 100% tested.
U401 – U406
CORPORATION
