M27C322-100F1 - STMicroelectronics

1/13April 2000

M27C322

32 Mbit (2Mb x16) UV EPROM and OTP EPROM

■5V ± 10% SUPPLY VO LTAGE in READ

OPERATION

■ACCESS TIME: 80ns

■WORD-WIDE CONFIGURABLE

■32 Mbit MASK ROM REPLACEMENT

■LOW POWER CONSUMPTI ON

– Active Current 50mA at 5MHz

– Stand-by Current 100µA

■PROGRAMMING VOLTAGE: 12V ± 0.25V

■PROGRAMMING TIME: 50µs /word

■ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Device Code: 0034h

DESCRIPTION

The M 27C322 is a 32 Mbit EP ROM offered i n the

UV range (ultra violet erase). It is ideally suited for

microprocessor systems requiring large data or

program storage. It is organised as 2 MWords of

16 bit. The pin-out is compatible with a 32 Mbit

Mask ROM.

The FDIP42W (window ceramic frit-seal package)

has a transparent lid which all ows the user to ex-

pose the chip to ultr aviolet light to erase the bit pat-

tern. A new pattern can then be written rapidly to

the device by following the programming proce-

dure.

For applications where the content is programmed

only one time and erasure is not required, the

M27C322 is offered in PDIP42 pac kage.

FDIP42W (F) PDIP42 (P)

Figure 1. Logic Diagram

AI02156

A0-A20

GVPP

Q0-Q15

VCC

M27C322

VSS

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M27C322

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Figure 2A. DIP Connections

GVPP

VSS

A13

VSS

A14

A15

A12

A16

A20

Q15

Q5Q2

Q3 VCC

Q11 Q4

Q14

A8A17

A18 A19

AI02157

M27C322

Q13

A11

A10

Q10

Q12

from E to output (tELQV). Data is available at the

output af ter a delay of tGLQV from the f alling edge

of GVPP, assuming that E has been low and the

addresses have been stable for at least tAVQV-

tGLQV.

Standby Mo de

The M27C322 has a standby mode whi ch reduces

the supply current from 50mA to 100µA. The

M27C322 is placed in the standby mode by apply-

ing a CMOS high signal to the E input.When in the

standby mode, the outputs are in a high imped-

ance state, independen t of the GVPP input.

Two Li ne Ou tp ut C on t rol

Because EPROMs are usually used in larger

memory arrays, this pr oduct features a 2 line con-

trol function which accom mo dates the use of m ul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, whil e G VPP should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that al l deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

Table 1. Sign al Names

A0-A20 Address Inputs

Q0-Q15 Data Outputs

EChip Enable

GVPP Output Enable / Program Supply

VCC Supply Voltage

VSS Ground

DEVICE OPERATION

The operati ng m odes of the M27C322 are listed i n

the Operating Modes Table. A single power supply

is required in the read mode. All inputs are TTL

compatib le except for V PP and 1 2V on A 9 fo r t he

Electronic Signa ture.

Read Mode

The M27C322 has a word-wide organization. Chip

Enable (E) is the power control and should be

used for device selection. Output Enable (G) is the

output control and shoul d be used to gate data to

the output pins independent of device selection.

Assuming that the addresses are stable, the ad-

dress access time (tAVQV) is equal to the delay

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M27C322

Table 2. Absolute M axim um Ratings (1)

Note: 1. Exc ept for th e rating " Operat i ng Temperatur e Range" , stresses above those lis ted in the Tabl e " A bsolu te Maximum Rati ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above thos e ind i cated in the Operating section s of thi s specifica tion i s not im plied. Expo sure t o Abso l ute Maxi m um R at i ng condi-

tions for extended pe riods may aff ect device re liab ility. Refer also to t he STMicroelectronics SURE Program and other relevant qual-

i ty do cu m ent s .

2. Minimum DC voltage on Inpu t or O utput is –0.5V with possibl e undershoot to –2.0V fo r a period les s than 20ns. Maximu m DC

voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period les s than 20ns.

3. Depends on range.

Table 3. Operating Modes

No te: X = VIH or VIL, VID = 12V ± 0. 5V .

Table 4. El ectroni c Signa ture

Note: Output s Q15-Q8 are set to '0'.

Symbol Parameter Value Unit

TAAmbient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Mode E GVPP A9 Q15-Q0

Read VIL VIL X Data Out

Output Disable VIL VIH X Hi-Z

Program VIL Pulse VPP X Data In

Program Inhibit VIH VPP X Hi-Z

Standby VIH X X Hi-Z

Electronic Signature VIL VIL VID Codes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 00100000 20h

Device Code VIH 00110100 34h

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M27C322

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Table 5. AC Measu remen t Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 6. Capaci tance (1) (TA = 2 5 °C, f = 1 MHz)

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 10 pF

COUT Output Capacitance VOUT = 0V 12 pF

put control and by properly selected decoupling

capacitors. It is r ecommended that a 0. 1µF ceram-

ic capacitor is used on every device bet ween VCC

and VSS. This should be a hi gh frequency type of

low inherent inductance and shou ld be placed as

close as possible to the device. In addition, a

4.7µF electrolytic capacitor should be used be-

tween V CC and VSS for every eight devices. This

capacitor should be mounted near the power sup-

ply connection point. The purpose of t his capacitor

is to overcom e th e volt age d rop c aused by the in-

ductive effects of PCB t races .

System Con siderations

The power switching characteristics of Advanced

CMOS EPROMs require careful dec oupling of the

supplies to the devices. The supply current ICC

has three segments of importance to the system

designer: the standby current, the active current

and the transient peaks th at are produced by the

falling and rising edges of E. The magnitude of the

transient current peaks is dependent on the ca-

pacitive and inductive loading of the device out-

puts. The associated transi ent voltage peaks can

be suppressed by complyi ng with the two line out -

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M27C322

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)

Note: 1. VCC must be applied si m ul taneously with or before VPP and rem oved simultaneously or aft er VPP.

2. Max imum DC vol t age on Ou tp ut is VCC +0. 5V.

Table 8. Read Mode AC Characteri stics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)

Note: 1. VCC must be applied si m ul taneously with or before VPP and rem oved simultaneously or aft er VPP

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement co ndition s.

Symbol Parameter Test Cond ition Min Max Unit

ILI Input Leakage Current 0v ≤ VIN ≤ VCC ±1 µA

ILO Output Leak age Curren t 0V ≤ VOUT ≤ VCC ±10 µA

ICC Supply Curre nt

E = VIL, GVPP = VIL, IOUT = 0mA,

f = 8MHz 70 mA

E = VIL, GVPP = VIL, IOUT = 0mA,

f = 5MHz 50 mA

ICC1Supply Current (Standby) TTL E = VIH 1mA

CC2Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH O utput High Volta ge TTL IOH = –400µA 2.4 V

Symbol Alt Parameter Test Condition

M27C322

Unit

-80 (3 ) -100

Min Max Min Max

tAVQV tACC Address Valid to Output Valid E = VIL, GVPP = VIL 80 100 ns

tELQV tCE Chip Enable Low to Output Valid GVPP = VIL 80 100 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL 40 50 ns

tEHQZ (2) tDF Chip Enable High to Output Hi-Z GVPP = VIL 0 40 0 40 ns

tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 40 0 40 ns

tAXQX tOH Address Transition to Output

Transition E = VIL, GVPP = VIL 55ns

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Figure 5. Read Mode AC Waveforms

AI02207

tAXQX

tEHQZ

A0-A20

GVPP

Q0-Q15

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

Table 9. Progra m ming Mode DC Char acteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

Note: 1. VCC must be applied si m ul taneously with or before VPP and rem oved simultaneously or aft er VPP.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.4 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –2.5mA 3.5 V

VID A9 Volta ge 11.5 12 .5 V

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M27C322

Table 10. MARGIN MODE AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

Note: 1. VCC must be applied si m ul taneously with or before VPP and rem oved simultaneously or aft er VPP.

Table 11. Progr amming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

Note: 1. VCC must be applied si m ul taneously with or before VPP and rem oved simultaneously or aft er VPP.

2. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition Min Max Unit

tA9HVPH tAS9 VA9 High to VPP High 2µs

tVPHEL tVPS VPP High to Chip Enable Low 2µs

A10HEH tAS10 VA10 High to Chip Enable High (Set) 1µs

A10LEH tAS10 VA10 Low to Chip Enable High (Reset) 1µs

EXA10X tAH10 Chip Enable Transition to VA10 Transition 1µs

EXVPX tVPH Chip Enable Transition to VPP Transition 2µs

VPXA9X tAH9 VPP Transition to VA9 Transition 2µs

Symb ol Alt Parameter Test Cond ition Min Max Unit

tAVEL tAS Address Valid to Chip Enable Low 1 µs

tQVEL tDS Input Valid to Chip Enable Low 1 µs

tVCHEL tVCS VCC High to Chip Enable Low 2µs

VPHEL tOES VPP High to Chip Enable Low 1µs

VPLVPH tPRT VPP Rise Time 50 ns

tELEH tPW Chip Enable Program Pulse Width (Initial) 45 55 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tEHVPX tOEH Chip Enable High to VPP Transition 2µs

VPLEL tVR VPP Low to Chip Enable Low 1µs

ELQV tDV Chip Enable Low to Output Valid 1 µs

tEHQZ (2) tDFP Chip Enable High to Output Hi-Z 0 130 ns

tEHAX tAH Chip Enable High to Address Transition 0 ns

Programming

When delivered (and after each erasure for UV

EPROM), all bits of the M27C322 are in the "1"

state. Data is introduced by selectively program-

ming "0"s into the desired bit locations. Although

only "0"s will be programmed, both "1"s and "0"s

can be present in the data word. The on ly way to

change a "0" to a "1" is by die exposition to ultravi-

olet light (UV EPROM). The M27C322 is in the

programming mode when VPP input is at 12.V,

GVPP is at VIH and E is pu lsed t o VIL. T he data t o

be pro grammed is applied to 16 b its in parallel to

the data output pins. The levels required for the

address and data inputs are TTL. VCC is specified

to be 6.25V ± 0.25V.

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Figure 6. MARGIN MODE AC Waveforms

Note: A 8 High level = 5V; A9 High level = 12V.

Figure 7. Program mi ng and Verify Modes AC Wavefor m s

Note: BYTE = VIH.

AI00736B

tA9HVPH tVPXA9X

GVPP

A10 Set

VCC

tVPHEL

tA10LEH

tEXVPX

tA10HEH

A10 Reset

tEXA10X

tAVEL

VALID

AI02205

A0-A20

Q0-Q15

VCC

DATA IN DATA OUT

tQVEL

tVCHEL

tVPHEL

tEHQX

tEHVPX tELQV

tELEH

tEHQZ

tVPLEL

PROGRAM VERIFY

GVPP

tEHAX

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M27C322

PRES TO II I Programm i ng Algorithm

The PRESTO III Programming Algorithm allows

the whole array to be programed with a guaran-

teed margin in a typical time of 100 seconds. Pro-

gramming with PRESTO I II con sists of applying a

sequence of 50µs program pulses to each word

until a correct verify occurs (see Figure 8). During

programing and verify operation a MARGIN

MODE circuit must be activated to guarantee that

each cell is programed with enough margin. No

overprogram pulse is applied since the verify in

MARGIN MODE provides the nec essary margin to

each programmed cell.

Program Inhibit

Programming of multiple M27C322s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs incl uding GVPP of the par-

allel M27C322 may be co mmon. A TTL low level

pulse applie d to a M27C322's E i nput and VPP at

12V, will program that M27C322. A high le vel E in-

put inhibits the other M27C322s from being pro-

grammed.

Program Verify

A verify (read) should be performed on the pro-

grammed bits to det ermine that they were correct-

ly programmed. The verify is accomplished with

Figure 8. Programming Flowchart

AI02206

n = 0

Last

Addr

VERIFY

E = 50µs Pulse

++n

= 25 ++ Addr

VCC = 6.25V, VPP = 12V

FAIL

CHECK ALL WORDS

1st: VCC = 6V

2nd: VCC = 4.2V

YES

SET MARGIN MODE

RESET MARGIN MODE

GVPP at VIL. Data should be verified wit h tELQV af -

ter the falling edge of E .

On-Boa rd Progra mming

The M27C 322 can be directly programmed in the

application circuit. See the relevant Application

Note AN620.

Electronic Sign atur e

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer an d type. This mode

is intended for use b y programmin g equipment to

automaticall y match the device to be programmed

with its corresponding programming algorithm.

The ES mode is functional in the 25°C ± 5°C am-

bient temperature range that is required when pro-

gramming the M27C322. To activate the ES

mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the

M27C322, with VPP = VCC = 5V. Two identifier

bytes may then be sequenced from the device out-

puts by toggling address line A0 from VIL to VIH. All

other address lines must be held at VIL during

Electronic Signa ture mode.

Byte 0 (A0 = VIL) represents the manufacturer

code and byte 1 (A0 = VIH) the device identifier

code. For the STMicroelectronics M27C322, these

two identifier bytes are given in Table 4 and can be

read-out on outputs Q0 to Q7.

ERASU RE OPERAT ION ( appli es to UV E PROM)

The erasure characteristics of the M27C322 is

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that

sunlight and some type of fluoresce nt lamps have

wavelengths in the 3000-400 0 Å range . Research

shows that constant exposure to room level fluo-

rescent lighting could erase a typical M 27C322 in

about 3 years, whi le it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If t he M27C322 is to be expos ed to these

types of lighting conditi ons for extended periods of

time, it is suggested that opaque labels be put over

the M27C322 window to prevent unint entional era-

sure. The recommended erasure procedure for

M27C322 is exposure to short wave ultraviolet

light which has a wavelength of 2537 Å . The inte-

grated dose (i.e. UV intensi ty x exposure time) for

erasure should be a minimum of 30 W-sec/cm2.

The erasure time with this dosage is approximate-

ly 30 to 40 minutes using an ultraviolet lamp with

12000 µW/cm2 power rating. The M27C322

should be placed within 2.5cm (1 inch) of t he l amp

tubes during the erasure. Some lamps have a filter

on their tubes which should be removed before

erasure.

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M27C322

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Table 12. Ordering Information Scheme

No te : 1. High Speed, see AC Characteris tics sec tion for f urther in f ormat i on.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the STMicroelectronics Sales Office nearest to you.

Example: M27C322 -80 F 1

Device Type

M27

Supply Voltag e

C = 5V ±10%

Device Function

322 = 32 Mbit (2Mb x16)

Speed

-80 (1) = 80 ns

-100 = 100 ns

Package

F = FDIP42W

P = PDIP42

Temperature Range

1 = 0 to 70 °C

3 = –40 to 125 °C

6 = –40 to 85 °C

Table 13. Revision History

Date Revision Details

July 1999 First Issue

02/24/00 Programming Time changed

Programming Flowchart changed (Figure 8)

Presto III Programming Algorithm paragraph changed

04/04/00 –40 to 85 °C and –40 to 125 °C temperature ranges added (Table 7, 8 and 12)

80ns speed class in High Speed AC measurement conditions

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M27C322

Table 14. FDI P42 W - 42 pin Ceramic Frit-seal DIP with windo w, Packa ge Mechan ical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 5.72 0.225

A1 0.51 1.40 0.020 0.055

A2 3.91 4.57 0.154 0.180

A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022

B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 54.41 54.86 2.142 2.160

D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –

E1 14.50 14.90 0.571 0.587

e 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 16.18 18.03 0.637 0.710

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

K 8.00 – – 0.315 – –

K1 16.00 – – 0.630 – –

α4° 11° 4° 11°

N42 42

Figure 9. FDIP42W - 42 pin Ceramic Frit-seal DIP with window, Package Outline

Not e: Drawing is not to scale.

FDIPW-b

B1 B e1

E1 E

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Table 15. PDIP 42 - 42 pin Plastic DIP, 600 mil s width, Package Mechan ic al Data

Symbol mm inches

Typ Min Max Typ Min Max

A– 5.08 – 0.200

A1 0.25 – 0.010 –

A2 3.56 4.06 0.140 0.160

B 0.38 0.53 0.015 0.021

B1 1.27 1.65 0.050 0.065

C 0.20 0.36 0.008 0.014

D 52.20 52.71 2.055 2.075

D2 50.80 – – 2.000 – –

E 15.24 – – 0.600 – –

E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135

S 0.86 1.37 0.034 0.054

α0° 10° 0° 10°

N42 42

Figure 10. PDIP42 - 42 pin Plastic DIP, 600 mils width, Packag e Outline

Not e: Drawing is not to scale.

PDIP

B1 B e1

E1 E

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M27C322

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