TISP4125M3BJ THRU TISP4200M3BJ - Power Innovations

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

Information is curre nt as of publication date . Products conform to specifications in accordance

with the terms of Power Innovations standard warranty. Production processing does not

necessarily incl ude tes ting of all parameters .

TELECOMMUNICATION SYSTEM 50 A 10/1000 OVERVOLTAGE PROTECTORS

●4 kV 10/700, 100 A 5/310 ITU-T K20/21 rating

●Ion-Implanted Breakdown Region

Precise and Stable Voltage

Low Voltage Overshoot under Surge

●Rated for International Surge Wave Shapes

●Low Differential Capacitance . . . 43 pF max.

●UL Recognized, E132482

DEVICE VDRM

V(BO)

‘4070 58 70

‘4080 65 80

‘4095 75 95

‘4125 100 125

‘4145 120 145

‘4165 135 165

‘4180 145 180

‘4200 155 200

‘4240 180 240

‘4265 200 265

‘4300 230 300

‘4350 275 350

‘4400 300 400

WAV E SHAP E STANDARD ITSP

2/10 µs GR-1089-CORE 300

8/20 µs IEC 61000-4-5 220

10/160 µs FCC Part 68 120

10/700 µs ITU-T K20/21 100

10/560 µs FCC Part 68 75

10/1000 µs GR-1089-CORE 50

description

These devices are designed to limit ov ervoltages on the telephone line. Overvoltages are normally caused by

a.c. power system or ligh tni ng f las h dis tu rbanc es whi ch ar e ind uc ed or co nducted o n to the tel eph one li ne. A

single dev ice provide s 2-point protection and is typically u sed for the protec tion of 2 -wire telec ommunicatio n

equipmen t (e.g. between the Ri ng and Tip wires for telephone s and mod ems). Combi nations of devices ca n

be used for multi-point protection (e.g. 3-point protection between Ring, Tip and Ground).

The protector consists of a symmetrical voltage-triggered bidirectional thyristor. Overvoltages are initially

clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to

crowbar into a low-voltage on state. This low-voltage on state causes the current resulting from the

over voltage to be safely diver ted through the device. The high crowbar holdin g current prevents d.c. latc hup

as the diverted current subsides.

device symbol

RSD4XAA

Te rmin als T and R correspond to the

alternative line designators of A and B

T(A)R(B)

SMBJ PACKAGE

(TOP VIEW )

MDXXBG

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

This TISP4xxxM3BJ range consists of thirteen voltage variants to meet various maximum system voltage

levels (58 V to 275 V). They are guaranteed to voltage limit and withstand the listed international lightning

surges in both polarities. These medium (M) current protection devices are in a plastic package SMBJ

(JEDEC DO- 214A A with J-be nd l ead s) an d s uppl ie d in embosse d tap e reel pa ck. For altern ati ve vo ltage and

hold ing cur rent values, consult the factor y. For higher ra ted im pulse c urren ts in t he SM B pa ckage, the 100 A

10/1000 TISP4xxxH3BJ series is available.

absolute maximum ratings, TA = 25°C (unless otherwise noted)

RATING SYMBOL VALUE UNIT

Repetitive peak off-state voltage, (see Note 1)

‘4070

‘4080

‘4095

‘4125

‘4145

‘4165

‘4180

‘4200

‘4240

‘4265

‘4300

‘4350

‘4400

VDRM

± 58

± 65

± 75

±100

±120

±135

±145

±155

±180

±200

±230

±275

±300

Non-repetitive peak on-state pulse current (see Notes 2, 3 and 4)

ITSP A

2/10 µs (GR-1089-CORE, 2/10 µs voltage wave shape) 300

8/20 µs (IEC 61000-4-5, combination wave generator, 1.2/50 voltage, 8/20 current) 220

10/160 µs (FCC P art 68, 10/160 µs voltage wave shape) 120

5/200 µs (VDE 0433, 10/700 µs voltage wave shape) 110

0.2/310 µs (I3124, 0.5/700 µs voltage wave shape) 100

5/310 µs (ITU-T K20/21, 10/700 µs voltage wave shape) 100

5/310 µs (FTZ R12, 10/700 µs voltage wave shape) 100

10/560 µs (FCC P art 68, 10/560 µs voltage wave shape) 75

10/1000 µs (GR-1089-CORE, 10/1000 µs voltage wave shape) 50

Non-repetitive peak on-state current (see Notes 2, 3 and 5)

ITSM

2.1 A

20 ms (50 Hz) full sine wave

16.7 ms (60 Hz) full sine wa ve

1000 s 50 Hz/60 Hz a.c.

Initial rate of rise of on-state current, Exponential current ramp , Maximum ramp v alue < 100 A di T/dt 300 A/µs

Junction temperature TJ-40 to +150 °C

Storage temperature range Tstg -65 to +150 °C

NOTES: 1. See Applications Info rmation and Figure 10 for voltage values at lower temperatures.

2. Initially the TISP4xxxM3BJ must be in thermal equilibrium with TJ= 25°C.

3. The surge may be repeated after the TISP4xxxM3BJ returns to its initial conditions.

4. See Applications Information and Figure 11 for current ratings at other temperatures.

5. EIA/JESD51-2 environment and EIA/JESD 51-3 PCB with standard footprint dimensions connected with 5 A rated printed w iring

trac k widths . See Figure 8 for the current ratings at other durations . Derate current v alues at -0. 61 %/°C for ambient temper atures

above 25 °C

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

electri cal character istics for the T and R terminals, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IDRM Repetitive peak off-

state current VD = VDRM TA = 25°C

TA = 85°C ±5

±10 µA

V(BO) Breakover voltage dv/dt = ±750 V/ms , RSOURCE = 300 Ω

‘4070

‘4080

‘4095

‘4125

‘4145

‘4165

‘4180

‘4200

‘4240

‘4265

‘4300

‘4350

‘4400

±70

±80

±95

±125

±145

±165

±180

±200

±240

±265

±300

±350

±400

V(BO) Impulse breakover

voltage

dv/dt ≤±1000 V/µs, Linear voltage ramp,

Maximum ramp value = ±500 V

di/dt = ±20 A/µs, Linear current ramp,

Maximum ramp value = ±10 A

‘4070

‘4080

‘4095

‘4125

‘4145

‘4165

‘4180

‘4200

‘4240

‘4265

‘4300

‘4350

‘4400

±78

±88

±102

±132

±151

±171

±186

±207

±247

±272

±308

±359

±410

I(BO) Break over current dv/dt = ±750 V/ms, RSOURCE = 300 Ω±0.15 ±0.6 A

VTOn-state voltage IT=±5A, t

W= 100 µs ±3 V

IHHolding current IT= ±5 A, di/dt = +/-30 mA /ms ±0.15 ±0.6 A

dv/dt Critical rate of rise of

off-state voltage Linear voltage ramp, Maximum ramp value < 0.85VDRM ±5 kV/µs

IDOff-state current VD=±50V T

A = 85°C ±10 µA

Coff Off-state capacitance

f = 100 kHz, Vd=1V rms, V

D=0,

f = 100 kHz, Vd=1V rms, V

D=-1V

f = 100 kHz, Vd=1V rms, V

D=-2V

f = 100 kHz, Vd=1V rms, V

D=-50V

f = 100 kHz, Vd=1V rms, V

D= -100 V

(see Note 6)

‘4070 thru ‘4095

‘4125 thru ‘4200

‘4240 thru ‘4400

‘4070 thru ‘4095

‘4125 thru ‘4200

‘4240 thru ‘4400

‘4070 thru ‘4095

‘4125 thru ‘4200

‘4240 thru ‘4400

‘4070 thru ‘4095

‘4125 thru ‘4200

‘4240 thru ‘4400

‘4125 thru ‘4200

‘4240 thru ‘4400

110

NOTE 6: To avoid possible voltage clipping, the ‘4125 is tested with VD=-98V.

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

thermal characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RθJA Junction to free air thermal resistance

EIA/JESD5 1-3 PC B, IT = ITSM(1000),

TA = 25 °C, (see Note 7) 115 °C/W

265 mm x 210 mm populated line card,

4-layer PCB, IT = ITSM(1000), TA = 25 °C 52

NOTE 7: EIA/JESD51-2 environment and PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.

PARAMETER MEASUREM ENT INFORMAT ION

Figure 1. VOLTAGE-CURRENT CHARACTERISTIC FOR T AND R TERMINALS

ALL MEASUREMENTS ARE REFERENCED TO THE R TERMINAL

-v VDRM

IDRM

ITSM

ITSP

V(BO)

I(BO)

Qua drant I

Switching

Characteristic

V(BO)

I(BO)

ITSM

ITSP

-i

Quadrant III

Switching

Characteristic PMXXAAB

VDRM

IDRM

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

TYPICAL CHARACTERISTICS

Figure 2. Figure 3.

Figure 4. Figure 5.

OFF-STATE CURRENT

JUNCTION TEMPERATURE

TJ - Junction Temp erature - °C

-25 0 25 50 75 100 125 150

|ID| - Off-State Current - µA

0·001

0·01

0·1

100 TCMAG

VD = ±50 V

NORMALISED BREAKOVER VOLTAGE

JUNCTION TEMPERATURE

TJ - Junction Temperature - °C

-25 0 25 50 75 100 125 150

Normali sed Breakover Voltage

0.95

1.00

1.05

1.10 TC4MAF

ON-STATE CURRENT

ON-STATE VOLTAGE

VT - On-State V o ltage - V

0.7 1.5 2 3 4 5 7110

IT - On-State Cu rrent - A

1.5

100 TA = 25 °C

tW = 100 µs

TC4MAC

'4070

THRU

'4095

'4240

THRU

'4400

'4125

THRU

'4200

NORMALISED HOLDING CURRENT

JUNCTION TEMPERATURE

TJ - Junction Temperature - °C

-25 0 25 50 75 100 125 150

Normal ise d Holdi ng Current

0.4

0.5

0.6

0.7

0.8

0.9

1.5

2.0

1.0

TC4MAD

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

TYPICAL CHARACTERISTICS

Figure 6. Figure 7.

NORMALISED CAPACITANCE

OFF-STATE VOLTAGE

VD - Off-state V o l tage - V

0.5 1 2 3 5 10 20 30 50 100150

Capacitance Normali sed to VD = 0

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

'4070 THRU ' 4095

TJ = 25°C

Vd = 1 Vrms

TC4MAB

'4240 THRU ' 4400

'4125 THRU ' 4200

TCMAE

DIFFERENTIAL OFF-STATE CAPACITANCE

RATED REPETITIVE PEAK OFF-STATE VOLTAGE

VDRM - Repetitive Peak Off-State Voltage - V

50 60 70 80 90 150 200 250 300100

∆

∆∆

∆C - Differenti al Off -S tate Capacit anc e - pF

∆

∆∆

∆C = Coff(-2 V) - Coff(-50 V)

'4265

'4300

'4350

'4400

'4240

'4125

'4145

'4165

'4180

'4200

'4070

'4080

'4095

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

RATING AND THERMAL INFORMATION

Figure 8. Figure 9.

Figure 10. Figure 11.

NON-REPETITIVE PEAK ON-STATE CURRENT

CURRENT DURATION

t - Current Duration - s

0·1 1 10 100 1000

ITSM(t) - Non-Repeti ti ve Peak On -S tate Current - A

1.5

TI4MAC

VGEN = 600 Vrms, 50/60 Hz

RGEN = 1.4*VGEN/ITSM(t)

EIA/JESD51-2 ENVIRONMENT

EIA/JESD51-3 PCB

TA = 25 °C

THERMAL IMPEDANCE

POWER DURATION

t - Power Du ration - s

0·1 1 10 100 1000

Zθ

θθ

θJA(t) - Transient Thermal Impedance - °C/W

150

100

TI4MAE

ITSM(t) APPLIED FOR T IME t

EIA/JESD51-2 ENVIRONMENT

EIA/JESD51-3 PCB

TA = 25 °C

VDRM DERATING FACTOR

MINIMUM AMBIENT TEMPERATURE

TAMIN - Minimum A mb ient Temperature - °C

-35 -25 -15 -5 5 15 25-40 -30 -20 -10 0 10 20

Derating Factor

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00 TI4MAD

'4070 THRU '4095

'4125 THRU '4200

'4240 THRU '4400

IMPULSE RATING

AMBIENT TEMPERATURE

TA - Ambient Temperature - °C

-40-30-20-100 1020304050607080

Impulse Current - A

100

120

150

200

250

300

400

IEC 1.2/50, 8/20

ITU-T 10/700

FCC 10/560

BELLCORE 2/10

BELLCOR E 10/1000

FCC 10/160

TC4MAA

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

APPLICATIONS INFORMATION

deployment

These devices are two terminal overvoltage protectors. They may be used either singly to limit the voltage

between two conductors (Figure 12) or in multiples to limit the voltage at sev eral points in a circuit (Figure 13).

In Figure 12, protector Th1 limits the maximum voltage between the two conductors to ±V(BO). This

configu ration is nor ma lly used to protect ci rcuits wit hout a ground re fer ence, such as modems. In Figure 1 3,

protec tors Th2 and Th3 l imit the maxi mum voltage be tween each cond uctor and ground to the ±V (BO) of the

individual protector. Protector Th1 limits the maximum voltage between the two conductors to its ±V(BO)

value. If the equipment being protected has all its vulnerable components connected between the conductors

and ground, then protector Th1 is not required.

impulse testing

To ve rify the withst and capa bilit y and safety of the equipm ent, stan dards req uire that the equi pment is tested

with various impulse wave forms. The table below shows some common values.

If the impulse generator current e xceeds the protectors current rating then a series resistance can be used to

reduce the curren t to the prot ectors rat ed value and so preve nt possi ble failure. Th e required value of se rie s

resistance for a given waveform is given by the following calculations. First, the minimum total circuit

impedance is found by dividing the impulse generators peak voltage by the protectors rated current. The

impuls e generators fictive impedan ce (generator s peak voltage divi ded by peak shor t circuit current) is then

subtracted from the minimum total circuit impedance to give the required value of series resistance.

For the FCC Part 68 10/560 waveform the following values result. The minimum total circuit impedance is

800/75 = 10.7 Ω and the generators fictive impedance is 800/100 = 8 Ω. This gives a minimum series

resistan ce value of 10.7 - 8 = 2.7 Ω. Afte r allowing for tolerance, a 3 Ω ±10% res istor would be s uitable. The

10/160 waveform needs a standard resistor value of 5.6 Ω per conductor. These would be R1a and R1b in

Figure 12. TWO POINT PROTECTION Figure 13. MULTI-POINT PROTECTION

STANDARD PEAK VOLTAGE

SETTING

VOL TAGE

WAVE FORM

µs

PEAK CURRENT

VALUE

CURRENT

WAVE FORM

µs

TISP4xxxM3

25 °C RATING

SERIE S

RESISTANCE

Ω

GR-1089-CORE 2500 2/10 500 2/10 300 11

1000 10/1000 100 10/1000 50

FCC Part 68

(March 1998)

1500 10/160 200 10/160 120 2x5.6

800 10/560 100 10/560 75 3

1500 9/720 † 37.5 5/320 † 100 0

1000 9/720 † 25 5/320 † 100 0

I3124 1500 0.5/700 37.5 0.2/310 100 0

ITU-T K20/K21 1500

4000 10/700 37.5

100 5/310 100 0

† FCC Part 68 terminology for the waveforms produced by the ITU-T recommendation K21 10/700 impulse generator

Th1

Th3

Th2

Th1

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

Figure 15 and Figure 16. FCC Part 68 allows the equipment to be non-operational after the 10/160 (conductor

to ground) and 10/ 560 (inter-condu ctor) impuls es. The ser ies resistor value may be reduced to zero to pa ss

FCC Part 6 8 in a non- operation al mode e.g. Fi gure 14. In s ome cas es th e equi pment w ill req uire verifi catio n

over a temperature range. By using the rated waveform values from Figure 11, the appropriate series resistor

value can be calculated for ambient temperatures in the range of -40 °C to 85 °C.

a.c. power testing

The protec tor can withs tand curre nts applied for times n ot ex ceeding thos e shown in Figure 8 . Currents tha t

exceed these times must be terminated or reduced to avoid protector failure. Fuses, PTC (Positive

Temperature Coefficient) resistors and fusible resistors are overcurrent protection devices which can be used

to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere. In

some cases it may be necessary to add some extra series resistance to prevent the fuse opening during

impulse testing. The current versus time characteristic of the overcurrent protector must be below the line

shown in Figure 8. In some cases there may be a further time limit imposed by the test standard (e.g. UL

1459 wiring simulator failure).

capacitance

The protector characteristic off-state capacitance values are given for d.c. bias voltage, VD, values of 0, -1 V,

-2 V and -50 V. Whe re pos sible values are al so gi ven for -100 V. Values for othe r voltages m ay be calcul ated

by multiplying the VD= 0 capacit ance value by the fac tor given in Figure 6. Up t o 10 MHz the ca pacitanc e is

essentially independent of frequency. Above 10 MHz the effective capacitance is strongly dependent on

connection inductance. In many applications, such as Figure 15 and Figure 17, the typical conductor bias

voltages wi ll be ab out - 2 V a nd -50 V. Figure 7 sh ows the di fferential (line unba la nce) capa ci tanc e c aus ed by

biasing one protector at -2 V and the other at -50 V.

normal system voltage levels

The protector should not clip or limit the voltages that occur in normal system operation. For unusual

conditions, such as ringing without the line connected, some degree of clipping is permissible. Under this

condition about 10 V of clipping is normally possible without activating the ring trip circuit.

Figure 10 allows the calculation of the protector VDRM value at temperatures below 25 °C. The calculated

value should not be less than the maximum normal system voltages. The TISP4265M3BJ, with a VDRM of

200 V, can be used for the protection of ring generators producing 100 V rms of ring on a battery voltage of

-58 V (Th2 and Th3 in Figure 17). The peak ring voltage will be 58 + 1.414*100 = 199.4 V. Howe v er, this is the

open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. In the

extreme case of an unconnected line, clipping the peak voltage to 190 V should not activate the ring trip. This

level of clipping would occur at the temp erature when the VDRM has reduce d to 190/200 = 0.95 of its 25 °C

value. Figure 10 shows that this condition will occur at an ambient temperature of -28 °C. In this example, the

TISP4265M3BJ will allow normal equipment operation provided that the minimum expected ambient

temperature does not fall below -28 °C.

JESD51 thermal measurement method

To standardise thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51

standard. P art 2 of the standard (JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft3)

cube which contains the test PCB (Printed Circuit Board) horizontally mounted at the centre. Part 3 of the

standar d (JESD51- 3, 1996) defines two test PCBs for surface mount compon ents; one for packages small er

than 27 m m on a side and the othe r for packages up to 48 mm. The SMBJ me asureme nts used th e small er

76.2 mm x 114.3 mm (3.0 “ x 4.5 “) PCB. The JESD51-3 PCBs are designed to have low effective thermal

conducti vity (hi gh ther mal res istance) and represen t a worse case c ondition . The PCBs used in the ma jor ity

of applic ations will a chieve lower values of ther ma l resistan ce and so c an dissipat e higher power levels than

indicated by the JESD51 values.

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

typical circuits

Figure 14. MODEM INTER-WIRE PROTECTION Figure 15. PROTECTION MODULE

Figure 16. ISDN PROTECTION

Figure 17. LINE CARD RING/TEST PROTECTION

FUSE

TISP4350

AI6XBMA

RING DETECTOR

HOOK SWITCH

D.C. SINK

SIGNAL

MODEM

RING

TIP

R1a

R1b

RING

WIRE

TIP

WIRE

Th3

Th2

Th1

PROTECTED

EQUIPMENT

E.G. LINE CARD

AI6XBK

R1a

R1b

Th3

Th2

Th1

AI6XBL

SIGNAL

D.C.

TEST

RELAY RING

RELAY SLIC

RELAY

TEST

EQUIP-

MENT RING

GENERATOR

S1a

S1b

R1a

R1b

RING

WIRE

TIP

WIRE

Th3

Th2

Th1

Th4

Th5

SLIC

PROTECTION

RING/TEST

PROTECTION

OVER-

CURRENT

PROTECTION

S2a

S2b

S3a

S3b

VBAT

220 n F

AI6XBJ

TISP6xxxx,

TISPPBLx,

½TISP6NTP2

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

MECHANICAL DATA

SMBJ (DO-214AA)

plastic surface mount diode package

This sur face m ount pa ckage consist s of a circ uit moun ted on a lea d frame and en caps ulated within a pl astic

compound. The compound will withstand soldering temperature with no deformation, and circuit performance

characteristics will remain stable when operated in high humidity conditions. Leads require no additional

cleaning or processing when used in soldered assembly.

SMB

ALL LINEAR DIMENSIONS IN MILLIMETERS

MDXXBHA

5,59

5,21

2,40

2,00

2,10

1,90

1,52

0,76

4,57

4,06

3,94

3,30 2

Index

Mark

(if needed )

2,32

1,96

0,20

0,10

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

MECHANICAL DATA

recommended printed wiring footprint .

device symbolization code

Devices will be coded as below. As the de vice parameters are symmetrical, terminal 1 is not identified.

car rier in fo r m a t io n

Devices are shipped in one of the carriers below. Unless a specific method of shipment is specified by the

customer, devices will be shipped in the most practical carrier. For production quantities the carrier will be

embossed tape reel pack. Evaluation quantities may be shipped in bulk pack or embossed tape.

DEVICE SYMOBLIZATION

CODE

TISP4070M3BJ 4070M3

TISP4080M3BJ 4080M3

TISP4095M3BJ 4095M3

TISP4125M3BJ 4125M3

TISP4145M3BJ 4145M3

TISP4165M3BJ 4165M3

TISP4180M3BJ 4180M3

TISP4200M3BJ 4200M3

TISP4240M3BJ 4240M3

TISP4265M3BJ 4265M3

TISP4300M3BJ 4300M3

TISP4350M3BJ 4350M3

TISP4400M3BJ 4400M3

CARRIER ORDER #

Embossed Tape Reel Pack TISP4xxxM3BJR

Bulk Pack TISP4xxxM3BJ

SMB Pad Size

ALL LINEAR DIMENSIONS IN MILLIMETERS

2.40

2.16

2.54

MDXXBI

NOVEMBER 1997 - REVISED MA RCH 1999

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

PRODUCT INFORMATION

MECHANICAL DATA

tape dimensions

SMB Package Single-Sprocket Tape

ALL LINEAR DIMENSIONS IN MILLIMETERS

Direction of Feed

0,40 MAX.

4,5 MAX.

0 MI N.

12,30

11,70

1,65

1,55

4,10

3,90

2,05

1,95

ø 1,5 MI N.

7,90

8,10

Embossment

Carrier Tape

5,55

5,45

1,85

1,65

Cover

Tape

8,20

MAX.

NOTES: A. The clearance between the component and the cavity must be within 0,05 mm MIN. to 0,65 mm MAX. so that the

component cannot rotate more than 20° within the determined cavity.

B. Taped devices are supplied on a reel of the following dimensions:-

Reel di am et e r: 330 ±3, 0 mm

Reel hub diameter 75 mm MIN.

Reel axial hole: 13,0 ±0,5 mm

3000 devices are on a reel.

MDXXBJ

20°

Typic al com pon ent

cavity centre line

Max imi um com ponent

rotation

Typic al com pon ent

centre line

Index

Mark

(if needed )

TISP4070M3BJ THRU TISP4095M3BJ, TISP4125M3BJ THRU TISP4200M3BJ,

TISP4240M3BJ THRU TISP4400M3BJ

BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS

NOV EM BER 1997 - REVISED MARCH 1999

PRODUCT INFORMATION

IMPORTANT NOTICE

Power I nnovatio ns Li mi te d ( PI ) r e se rves t he right t o ma ke ch an g es to it s pro d uc ts or t o disc on t inu e any s em ico nd uc t or p r odu ct

or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is

current.

PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with

PI's sta nda rd warranty. Testing and ot her quality c on trol techn iqu es are uti lize d t o th e extent PI deems ne ce ss ary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by gover nment

requirements.

PI assumes no liability for applications assistance, customer product design, software perfor mance, or infringement of patents

or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design

right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used.

PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORISED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.