MR25H256 256Kb Serial SPI MRAM FEATURES * * * * * * * * * * No write delays Unlimited write endurance Data retention greater than 20 years Automatic data protection on power loss Block write protection Fast, simple SPI interface with up to 40 MHz clock rate 2.7 to 3.6 Volt power supply range Low current sleep mode Industrial temperatures Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant packages. * Direct replacement for serial EEPROM, Flash, FeRAM * AEC-Q100 Grade 1 option DFN Small Flag DFN INTRODUCTION The MR25H256 is a 262,144-bit magnetoresistive random access memory (MRAM) device organized as 32,768 words of 8 bits. The MR25H256 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. RoHS Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H256 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. The MR25H256 is available in either a 5 mm x 6 mm 8-pin DFN package or a 5 mm x 6 mm 8-pin DFN Small Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products. The MR25H256 provides highly reliable data storage over a wide range of temperatures. The product is offered with industrial (-40 to +85 C) and AEC-Q100 Grade 1 (-40C to +125 C) operating temperature range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 3 2. SPI COMMUNICATIONS PROTOCOL...................................................... 4 3. ELECTRICAL SPECIFICATIONS................................................................. 10 4. TIMING SPECIFICATIONS.......................................................................... 14 5. ORDERING INFORMATION....................................................................... 16 6. MECHANICAL DRAWING.......................................................................... 17 7. REVISION HISTORY...................................................................................... 18 How to Reach Us.......................................................................................... 18 Copyright (c) Everspin Technologies 2013 1 MR25H256 Rev. 9, 4/2013 MR25H256 1. DEVICE PIN ASSIGNMENT Overview The MR25H256 is a serial MRAM with memory array logically organized as 32Kx8 using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral interface (SPI) bus. Serial MRAM implements a subset of commands common to today's SPI EEPROM and Flash components allowing MRAM to replace these components in the same socket and interoperate on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and more reliable data retention compared to available serial memory alternatives. Figure 1.1 Block Diagram WP CS HOLD SCK Instruction Decode Clock Generator Control Logic Write Protect 32KB MRAM ARRAY Instruction Register 15 Address Register Counter 8 Data I/O Register SI SO 4 Nonvolatile Status Register System Configuration Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are common among devices. Each device requires CS and HOLD pins to be driven separately. Figure 1.2 System Configuration SCK MOSI MISO SO SPI Micro Controller SI SCK EVERSPIN SPI MRAM 1 HOLD CS SO SI SCK EVERSPIN SPI MRAM 2 CS HOLD CS1 HOLD 1 CS2 HOLD 2 MOSI = Master Out Slave In MISO = Master In Slave Out Copyright (c) Everspin Technologies 2013 2 MR25H256 Rev. 9, 4/2013 MR25H256 DEVICE PIN ASSIGNMENT Figure 1.3 Pin Diagrams (Top View) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI 8-Pin DFN or 8-Pin DFN Small Flag Packages Table 1.1 Pin Functions Signal Name Pin I/O Function Description CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a common set of data pins by using a unique chip select for each memory. SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status Register. VSS 4 Supply Ground Power supply ground pin. SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 40 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task. When HOLD is low, the current operation is suspended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts. Copyright (c) Everspin Technologies 2013 3 MR25H256 Rev. 9, 4/2013 MR25H256 2. SPI COMMUNICATIONS PROTOCOL MR25H256 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. Depending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Table 2.1 Command Codes Instruction Description Binary Code Hex Code Address Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 WRDI Write Disable 0000 0100 04h 0 0 RDSR Read Status Register 0000 0101 05h 0 1 WRSR Write Status Register 0000 0001 01h 0 1 READ Read Data Bytes 0000 0011 03h 2 1 to WRITE Write Data Bytes 0000 0010 02h 2 1 to SLEEP Enter Sleep Mode 1011 1001 B9h 0 0 WAKE Exit Sleep Mode 1010 1011 ABh 0 0 Status Register and Block Write Protection The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the memory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable writes to status register bits. The fast writing speed of MR25H256 does not require write status bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set from the factory to the "0" state. Table 2.2 Status Register Bit Assignments Bit 7 SRWD Bit 6 Don't Care Bit 5 Don't Care Copyright (c) Everspin Technologies 2013 Bit 4 Don't Care Bit 3 BP1 4 Bit 2 BP0 Bit 1 WEL Bit 0 Don't Care MR25H256 Rev. 9, 4/2013 MR25H256 SPI COMMUNICATIONS PROTOCOL Table 2.3 Block Memory Write Protection Status Register BP1 BP0 0 0 0 1 1 0 1 1 Memory Contents Protected Area None Upper Quarter Upper Half All Unprotected Area All Memory Lower Three-Quarters Lower Half None Table 2.4 Memory Protection Modes WEL 0 1 1 1 SRWD WP Protected Blocks Unprotected Blocks X 0 1 1 X X Low High Protected Protected Protected Protected Protected Writable Writable Writable Status Register Protected Writable Protected Writable When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and BP1. Read Status Register (RDSR) The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be read at any time to check the status of write enable latch bit, status register write protect bit, and block write protect bits. For MR25H256, the write in progress bit (bit 0) is not written by the memory because there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and then driving CS high. Figure 2.1 RDSR CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI Mode 3 Mode 0 0 0 0 0 0 1 0 1 MSB Status Register Out SO High Impedance 7 6 5 4 3 2 1 0 High Z MSB Copyright (c) Everspin Technologies 2013 5 MR25H256 Rev. 9, 4/2013 MR25H256 SPI COMMUNICATIONS PROTOCOL Write Enable (WREN) The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The WEL bit must be set prior to writing in the status register or the memory. The WREN command is entered by driving CS low, sending the command code, and then driving CS high. Figure 2.2 WREN CS Mode 3 SCK 0 1 2 3 4 5 6 Mode 3 7 Mode 0 Mode 0 Instruction (06h) SI 0 0 0 0 0 1 1 0 High Impedance SO Write Disable (WRDI) The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending the command code, and then driving CS high. The WEL bit is reset to 0 on power-up or completion of WRDI. Figure 2.3 WRDI CS Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (04h) SI 0 SO 0 0 0 0 1 0 0 High Impedance Write Status Register (WRSR) The Write Status Register (WRSR) command allows new values to be written to the Status Register. The WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN command while pin WP and bit SRWD correspond to values that make the status register writable as seen in table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0 upon power cycling. Copyright (c) Everspin Technologies 2013 6 MR25H256 Rev. 9, 4/2013 MR25H256 SPI COMMUNICATIONS PROTOCOL The WRSR command is entered by driving CS low, sending the command code and status register write data byte, and then driving CS high. Figure 2.4 WRSR CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 Mode 3 14 SCK Mode 0 Instruction (01h) SI 0 0 0 0 0 Status Register In 0 0 1 7 6 5 4 3 2 1 0 MSB High Impedance SO Read Data Bytes (READ) The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are read out sequentially from memory until the read operation is terminated by bringing CS high The entire memory can be read in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is terminated by bring CS high. Figure 2.5 READ CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction (03h) SI 0 0 0 0 0 0 16-Bit Address 1 1 X 14 13 3 2 1 0 MSB SO Data Out 1 High Impedance 7 6 5 4 3 Data Out 2 2 1 0 7 MSB Copyright (c) Everspin Technologies 2013 7 MR25H256 Rev. 9, 4/2013 MR25H256 SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are written sequentially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in memory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory making it ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Figure 2.6 WRITE CS 0 1 2 3 4 5 6 7 8 9 20 10 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction (02h) SI 0 0 0 0 0 16-Bit Address 0 1 0 14 X 13 3 2 1 MSB 0 7 6 5 4 3 2 1 0 MSB High Impedance SO CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 3 47 SCK Mode 0 Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 MSB Data Byte N 2 1 0 7 6 5 4 3 2 1 0 MSB High Impedance SO Copyright (c) Everspin Technologies 2013 8 MR25H256 Rev. 9, 4/2013 MR25H256 SPI COMMUNICATIONS PROTOCOL Enter Sleep Mode (SLEEP) The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 3 A typical. The SLEEP command is entered by driving CS low, sending the command code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid command following SLEEP mode entry is a WAKE command. Figure 2.7 SLEEP CS t DP 0 1 2 3 4 5 6 Mode 3 7 SCK Mode 0 Instruction (B9h) SI 1 0 1 1 1 0 0 1 Active Current Standby Current Sleep Mode Current SO Exit Sleep Mode (WAKE) The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over. Figure 2.8 WAKE CS t RDP 0 1 2 3 4 5 6 7 SCK Mode 3 Mode 0 Instruction (ABh) SI 1 0 1 0 1 0 1 Sleep Mode Current 1 Standby Current SO Copyright (c) Everspin Technologies 2013 9 MR25H256 Rev. 9, 4/2013 MR25H256 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Table 3.1 Absolute Maximum Ratings 1 Symbol Parameter Conditions Value Unit VDD Supply voltage 2 All -0.5 to 4.0 V VIN Voltage on any pin 2 All -0.5 to VDD + 0.5 V IOUT Output current per pin All 20 mA PD Package power dissipation 3 All 0.600 W Industrial -45 to 95 C AEC-Q100 Grade 1 -45 to 135 C TBIAS Temperature under bias Tstg Storage Temperature All -55 to 150 C TLead Lead temperature during solder (3 minute max) All 260 C Hmax_write Maximum magnetic field (Write) During Write 12,000 A/m Hmax_read Maximum magnetic field (Read or Standby) During Read or Standby 12,000 A/m 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. 3 Power dissipation capability depends on package characteristics and use environment. Copyright (c) Everspin Technologies 2013 10 MR25H256 Rev. 9, 4/2013 MR25H256 ELECTRICAL SPECIFICATIONS Table 3.2 Operating Conditions Symbol Parameter Grade Min Typical Max Unit Industrial 2.7 - 3.6 V AEC-Q100 Grade1 3.0 - 3.6 V VDD Power supply voltage VIH Input high voltage All 2.2 - VDD + 0.3 V VIL Input low voltage All -0.5 - 0.8 V TA Temperature under bias Industrial -40 - 85 C AEC-Q100 Grade 1 1 -40 125 C 1 AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years out of 20-year life.) Table 3.3 DC Characteristics Symbol Parameter Conditions Min Typical Max Unit ILI Input leakage current All - - 1 A ILO Output leakage current All - - 1 A VOL Output low voltage IOL = +4 mA - - 0.4 V IOL = +100 A - - VSS + 0.2v V VOH Output high voltage 2.4 - - V VDD - 0.2 - - V IOH = -4 mA IOH = -100 A Table 3.4 Power Supply Characteristics Symbol Parameter 1 IDDR Active Read Current IDDW Active Write Current Conditions Typical Max Unit @ 1 MHz 2.5 3 mA @ 40 MHz 6 10 mA @ 1 MHz 8 13 mA @ 40 MHz 23 27 mA ISB Standby Current CS High 1 90 115 A IZZ Standby Sleep Mode Current CS High 7 30 A ISB current is specified with CS high and the SPI bus inactive. Copyright (c) Everspin Technologies 2013 11 MR25H256 Rev. 9, 4/2013 MR25H256 4. TIMING SPECIFICATIONS Table 4.1 Capacitance1 Symbol 1 Parameter Typical Max Unit CIn Control input capacitance - 6 pF CI/O Input/Output capacitance - 8 pF = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 4.2 AC Measurement Conditions Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V 0 or 3.0 V 2 ns Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters See Figure 4.1 Output load for all other timing parameters See Figure 4.2 Figure 4.1 Output Load for Impedance Parameter Measurements ZD= 50 Output RL = 50 VL = 1.5 V Figure 4.2 Output Load for all Other Parameter Measurements 3.3 V 590 Output 30 pF 435 Copyright (c) Everspin Technologies 2013 12 MR25H256 Rev. 9, 4/2013 MR25H256 TIMING SPECIFICATIONS Power-Up Timing The MR25H256 is not accessible for a start-up time, tPU= 400 s after power up. Users must wait this time from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up sequence. Table 4.3 Power-Up Symbol Parameter Min Typical Max Unit VWI Write Inhibit Voltage 2.2 - 2.7 V tPU Startup Time 400 - - s Figure 4.3 Power-Up Timing VDD VDD(max) Chip Selection not allowed VDD(min) Reset state of the device t PU Normal Operation VWI Time Copyright (c) Everspin Technologies 2013 13 MR25H256 Rev. 9, 4/2013 MR25H256 TIMING SPECIFICATIONS Synchronous Data Timing Symbol Parameter Table 4.4 AC Timing Parameters 1 Conditions Min Max Unit fSCK SCK Clock Frequency 0 40 MHz tRI Input Rise Time - 50 ns tRF Input Fall Time - 50 ns tWH SCK High Time 11 - ns tWL SCK Low Time 11 - ns Synchronous Data Timing (See figure 4.4) tCS CS High Time 40 - ns tCSS CS Setup Time 10 - ns tCSH CS Hold Time 10 - ns tSU Data In Setup Time 5 - ns tH Data In Hold Time 5 - ns 0 10 ns 0 9 ns 0 10 ns 0 - ns Output Valid Industrial Grade tV Output Valid Industrial Grade Output Valid AEC-Q100 Grade 1 tHO VDD = 2.7 to 3.6v. VDD = 3.0 to 3.6v. VDD = 3.0 to 3.6v. Output Hold Time HOLD Timing (See figure 4.5) tHD HOLD Setup Time 10 - ns tCD HOLD Hold Time 10 - ns tLZ HOLD to Output Low Impedance - 20 ns tHZ HOLD to Output High Impedance - 20 ns Other Timing Specifications 1 tWPS WP Setup To CS Low 5 - ns tWPH WP Hold From CS High 5 - ns tDP Sleep Mode Entry Time 3 - s tRDP Sleep Mode Exit Time 400 - s tDIS Output Disable Time 12 - ns Over the Operating Temperature Range and CL= 30 pF Copyright (c) Everspin Technologies 2013 14 MR25H256 Rev. 9, 4/2013 MR25H256 TIMING SPECIFICATIONS Figure 4.4 Synchronous Data Timing CS tCS V IH V IL tCSS SCK tCSH V IH tWH V IL tSU SI SO tWL tH V IH V IL V IH tV tHO tDIS High Impedance V IL Figure 4.5 HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ tLZ SO Copyright (c) Everspin Technologies 2013 15 MR25H256 Rev. 9, 4/2013 MR25H256 5. ORDERING INFORMATION Figure 5.1 Part Numbering System MR 25H 256 C DC Package Options DC 8 Pin DFN on Tray DCR 8 Pin DFN on Tape and Reel DF 8 pin DFN Small Flag on Tray DFR 8 pin DFN Small Flag on Tape and Reel Temperature Range C -40 to +85 C ambient (Industrial) M -40 to +125 C ambient (AEC-Q100 Grade 1) Memory Density 256 256Kb Interface 25H High Speed Serial SPI Family Product Type MR Magnetoresistive RAM Table 5.1 Available Parts Grade Temperature Package 8-DFN Industrial -40 to +85 C 8-DFN Small Flag 8-DFN AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag Copyright (c) Everspin Technologies 2013 16 Shipping Container Trays Tape and Reel Trays Tape and Reel Trays Tape and Reel Trays Tape and Reel Order Part Number MR25H256CDC MR25H256CDCR MR25H256CDF MR25H256CDFR MR25H256MDC MR25H256MDCR MR25H256MDF MR25H256MDFR MR25H256 Rev. 9, 4/2013 MR25H256 6. MECHANICAL DRAWINGS Figure 6.1 DFN Package Exposed metal Pad. Do not connect anything except VSS 8 A 5 DAP Size 4.4 x 4.4 J B I L G H M Pin 1 Index C Detail A D Max. Min. K N E Detail A A B C D E 5.10 4.90 6.10 5.90 1.00 0.90 1.27 BSC 0.45 0.35 Dimension 1 4 F F 0.05 0.00 G H 0.35 Ref. 0.70 0.50 I 4.20 4.00 J 4.20 4.00 K 0.261 0.195 L C0.35 M R0.20 N 0.05 0.00 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229-E Copyright (c) Everspin Technologies 2013 17 MR25H256 Rev. 9, 4/2013 MR25H256 6. MECHANICAL DRAWINGS Figure 6.2 DFN Small Flag Package A 2X Exposed metal Pad. Do not connect anything except VSS 0.10 C 8 5 2X J B I G L H M C Pin 1 Index Detail A D Dimension Max Min 1 4 F 0.10 C K N E Detail A A B C D E F G H I J K L M 5.10 4.90 6.10 5.90 0.90 0.80 1.27 BSC 0.45 0.35 0.05 0.00 1.60 1.20 0.70 0.50 2.10 1.90 2.10 1.90 .210 .196 C0.45 R0.20 N 0.05 0.00 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229-E Copyright (c) Everspin Technologies 2013 18 MR25H256 Rev. 9, 4/2013 MR25H256 7. REVISION HISTORY Revision Date Description of Change 1 Jan 15, 2010 Preliminary Information Release 2 Apr 8, 2010 Corrected READ and WRITE addressing from 24-bit to 15-bit. Removed commercial option. 3 Mar 3, 2011 Clarified language on status register WEL bit. Removed automotive option to seperate datasheet. 4 May 14, 2011 Datasheet released to production. Corrected various typos. Clarified block and status register protection description. Specified maximum Power Supply Characteristics for production parts. 5 Aug 11, 2011 Revised Power Supply Specification Table 3.4 6 Sept 1, 2011 Added AEC Q100 Grade 1 ordering option. Revised Table 3.1, Table 3.2, Table 4.4 Note 2, Figure 5.1 and Table 5.1. Corrected VOL in Table 3.3 to read VOL Max = VSS + 0.2v. Operating Conditions Power Supply 7 8 November 18, 2011 October 19, 2012 Voltage for AEC-Q100 Grade1revised to 3.0-3.6v. Table 4.4: Output Valid tV specifications revised to include VDD ranges for Industrial and AEC-Q100 Grade 1 options. Corrected SI waveform in Figure 2.8. New Small Flag DFN package option added to Page 1 Features and available parts Table 5.1. DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Package, cleaned up with better quality drawing and dimension table. Reformatted parametric tables. Table 5.1 Available Parts Revised: Removed MDF and MDFR options. MDC and MDCR options are now fully qualified. Added DFN illustrations. Revised 8-DFN package drawing to show correct proportion for flag and package. Corrected VDD range for AEC-Q100 tV parameter. 9 April 17, 2013 Added Automotive Grade AEC-Q100 Grade 1 for Small Flag DFN package as qualified mass production product. Copyright (c) Everspin Technologies 2013 19 MR25H256 Rev. 9, 4/2013 MR25H256 Everspin Technologies, Inc. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Canada/South and Central America Everspin Technologies 1347 N. Alma School Road, Suite 220 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Japan support.japan@everspin.com Asia Pacific support.asia@everspin.com Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright (c) Everspin Technologies, Inc. 2013 Copyright (c) Everspin Technologies 2013 20 MR25H256 Rev. 9, 4/2013