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ATTENUATORS - DIGITAL - SMT
4
HMC629LP4 / 629LP4E
v08 .0112
3 dB LSB GaAs MMIC 4-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)
must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in
the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired
states the LE is pulsed. See timing diagram below for reference.
Timing Diagram (Latched Parallel Mode)
Bias Voltage
Vdd (Vdc) Idd (Typ.) (mA)
52.0
Control Voltage Input Attenuation State
D3 D2 D1 D0
High High High High Reference
I.L.
High High High Low 3 dB
High High Low High 6 dB
High Low High High 12 dB
Low High High High 24 dB
Any combination of the above states will provide an attenuation
approximately equal to the sum of the bits selected.
Truth Table
PUP Truth Table
LE PUP1 PUP2 Attenuation State
0 0 0 45 dB
0 1 0 45 dB
0 0 1 45 dB
011Insertion Loss
1X X 0 to 45 dB
Note: Power-Up with LE= 1 provides direct parallel operation with
D0 - D3.
Parameter Typ.
Min. serial period, tSCK 100 ns
Control set-up time, tCS 20 ns
Control hold-time, tCH 20 ns
LE setup-time, tLN 10 ns
Min. LE pulse width, tLEW 10 ns
Min LE pulse spacing, tLES 630 ns
Serial clock hold-time from LE, tCKN 10 ns
Hold Time, tPH. 0 ns
Latch Enable Minimum Width, tLEN 10 ns
Setup Time, tPS 2 ns
Control Voltage Table
State Vdd = +3V Vdd = +5V
Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA
High 2 to 3V @ <1 µA 2 to 5V @ <1 µA
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D3-D0 determines
the power-up state of the part per truth table. The
attenuator latches in the desired power-up state
approximately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND