CDCM7005RGZT - Texas Instruments - Datasheet.Directory

FEATURES

PIN ASSIGNMENTS (TOP VIEW)

P0022-01

CP_OUTREF_SELPRI_REF

GND GND GND GND GND GND GND

SEC_REF

GND AVCC AVCC AVCC AVCC AVCC

STATUS_

REFor

PRI_SEC_

CLK

GND GND GND GND GND VCC

STATUS_

VCXO

VCXO_IN

GND VCC VCC VCC VCC VCC VCC

Y0A GND GND GND GND GND VCC Y4B

Y0B VCC VCC VCC VCC VCCVCC Y4A

PD Y1A Y1B Y2A Y2B Y3A Y3B

RESET

HOLD

1 2 3 4 5 6 7 8

I_REF_CP

PLL_LOCK

VBB

VCC_CP CTRL_LE CTRL_CLK CTRL_

DATA

VCXO_IN

P0023-01

1 2 3 4 5 6 7 8 9 10 11 12

36 35 34 33 32 31 30 29 28 27 26 25

ThermalPad

mustbe

solderedtoGND

STATUS_REFor

PRI_SEC_CLK

STATUS_VCXOor

I_REF_CP

RESET

HOLD

VCC

Y1A

Y1B

VCC

Y2A

Y2B

VCC

Y3A

Y3B

PRI_REF

REF_SEL

VCC_CP

AVCC

CP_OUT

AVCC

CTRL_LE

CTRL_CLK

AVCC

CTRL_DATA

PLL_LOCK

GND

VCC

Y4B

Y4A

VCC

SEC_REF

AVCC

VBB

VCC

VCXO_IN

VCC

Y0A

Y0B

VCC

VCXO_IN

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

•High Performance LVPECL and LVCMOS PLLClock Synchronizer

•Two Reference Clock Inputs (Primary andSecondary Clock) for Redundancy SupportWith Manual or Automatic Selection•Accepts LVCMOS Input Frequencies Up to 200MHz

•VCXO_IN Clock is Synchronized to One of theTwo Reference Clocks•VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)•Outputs Can Be a Combination of LVPECL andLVCMOS (Up to Five Differential LVPECLOutputs or Up to 10 LVCMOS Outputs)•Output Frequency is Selectable by x1, /2, /3, /4,/6, /8, /16 on Each Output Individually•Efficient Jitter Cleaning From Low PLL LoopBandwidth

•Low Phase Noise PLL Core•Programmable Phase Offset (PRI_REF andSEC_REF to Outputs)•Wide Charge Pump Current Range From200 µA to 3 mA•Dedicated Charge Pump Supply (VCC_CP) forWide Tuning Voltage Range VCOs•Presets Charge Pump to VCC_CP/2 for FastCenter-Frequency Setting of VC(X)O•Analog and Digital PLL Lock Indication•Provides VBB Bias Voltage Output forSingle-Ended Input Signals (VCXO_IN)•Frequency Hold-Over Mode Improves Fail-SafeOperation

•Power-Up Control Forces LVPECL Outputs to3-State at V

< 1.5 V•SPI Controllable Device Setting•3.3-V Power Supply•Packaged in 64-Pin BGA (0,8 mm Pitch – ZVA)or 48-Pin QFN (RGZ)•Industrial Temperature Range – 40 ° C to 85 ° C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2005 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

DESCRIPTION

CDCM7005

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes aVCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the tworeference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to thefrequency ratio of the reference clock to VC(X)O:•VC(X)O_IN / PRI_REF = (N x P) / M or•VC(X)O_IN / SEC_REF = (N x P) / M

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components,the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequencyhold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of theCDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOSoutputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, … ), so that each pair has the samefrequency. But each output can be separately inverted and disabled. The built in synchronization latches ensurethat all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable bySPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from – 40 ° C to 85 ° C.

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B0057-01

PECL

LVCMOS

Progr.Delay

PECL

INPUT

CTRL_LE

CTRL_DATA

CTRL_CLK

VCXO_IN

CP_OUT

PLL_LOCK

STATUS_VCXO/

STATUS_REF/

PRI_SEC_CLK

I_REF_CP

RESET or

HOLD

BiasGenerator

V 1.3V

CC –

VBB

VCC_CP

VCC AVCC

GND

PRI_REF

SEC_REF

REF_SEL

REF_M UX

LVCMOS

FB_MUX

CMOS

Y0B

Y0A

CMOS

PECL

CMOS

Y1B

Y1A

CMOS

PECL

CMOS

Y2B

Y2A

CMOS

PECL

CMOS

Y3B

Y3A

CMOS

PECL

CMOS

Y4B

Y4A

CMOS

PECL

SPILOGIC

Manual&

Automatic

CLKSelect

Current

Reference

Clock

SelectedREFSignal

Progr.Divider

N 212

P Divider

÷3

÷4

÷6

÷8

÷16

÷1

÷2

÷4

÷8

90o

LOCK

Charge

Pump

PFD

Y0_MUX

HOLD

P16-Div

freq.Detect

>2Mhz

freq.Detect

>2Mhz

Progr.Delay

Progr.Divider

M210

Feedback

Clock

Y1_MUXY2_MUXY3_MUX

Y4_MUX

CDCM7005

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FUNCTIONAL BLOCK DIAGRAM

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CDCM7005

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Table 1. PIN ASSINGMENT

TERMINAL

I/O DESCRIPTIONNAME BGA QFN

D7, E3, 2, 5, 6,E4, E5, 9, 10,E6, E7, 13, 15,

3.3-V supply. V

and AV

should have always same supply voltage. It isVCC E8, F7, 18, 19, Power

recommended that AV

use its own supply filter.G2, G3, 20, 21,G4, G5, 41, 44,G6, G7 45; 48B2, B3,B4, B5,B6, B7,B8, C2,

ThermalD2, D3,GND pad and Ground GroundD4, D5,

pin 24D6, E2,F2, F3,F4, F5,

F6C3, C4, 27, 30,

Analog 3.3-V analog power supply. There is no internal connection between AV

andAVCC C5, C6, 32, 38,

Power V

. It is recommended that AV

use its own supply filter.C7 39

This is the charge pump power supply pin used to have the same supply as theVCC_CP A3 33 Power

external VCO. It can be set from 2.3 V to 3.6 V.LVCMOS input, control latch enable for serial programmable Interface (SPI), withCTRL_LE A5 29 I hysteresis. Unused or floating inputs must be tied to proper logic level. It isrecommended to use a 20k Ωor larger pullup resistor to VCCLVCMOS input, serial control clock input for SPI, with hysteresis. Unused orCTRL_CLK A6 28 I floating inputs must be tied to proper logic level. It is recommended to use a 20k Ωor larger pullup resistor to VCCLVCMOS input, serial control data input for SPI, with hysteresis. Unused orCTRL_DATA A7 26 I floating inputs must be tied to proper logic level. It is recommended to use a 20k Ωor larger pullup resistor to VCCLVCMOS input, asynchronous power down (PD) signal. This pin is low active andcan be activated external or by the corresponding bit in the SPI register (in case oflogic high, the SPI setting is valid). Switches the device into power-down mode.Resets M- and N-Divider, 3-states charge pump, STATUS_REF, orPRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pinPD H1 1 I

and all Yx outputs. Sets the SPI register to default value; has internal 150-k Ωpullup resistor.

It is recommended to ramp up the PD with the same time as V

and AV

orlater. The ramp up rate of the PD should not be faster than the ramp up rate ofV

and AV

.This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESETis the default function. This pin is low active and can be activated external or viathe corresponding bit in the SPI register. In case of RESET, the charge pump (CP)is switched to 3-state and all counters (N, M, P) are reset to zero (the initial dividersettings are maintained in SPI registers). The LVPECL outputs are static low andhigh respectively and the LVCMOS outputs are all low or high if inverted. RESETRESET or

is not edge triggered and should have a pulse duration of at least 5 ns.H8 14 IHOLD

When in HOLD, the CP is switched in to 3-state mode only. After HOLD isreleased and with the next valid reference clock cycle the charge pump isswitched back in to normal operation (CP stays in 3-state as long as no referenceclock is valid). During HOLD, the P divider and all outputs Yx are at normaloperation. This mode allows an external control of the frequency hold-over mode.The input has an internal 150-k Ωpullup resistor.VCXO_IN E1 43 I VCXO LVPECL inputVCXO_IN D1 42 I Complementary VCXO LVPECL inputLVCMOS input for the primary reference clock, with an internal 150-k ΩpullupPRI_REF A1 36 I

resistor and input hysteresis.LVCMOS input for the secondary reference clock, with an internal 150-k ΩpullupSEC_REF B1 37 I

resistor and input hysteresis.

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Table 1. PIN ASSINGMENT (continued)

TERMINAL

I/O DESCRIPTIONNAME BGA QFN

LVCMOS reference clock selection input. In the manual mode the REF_SELsignal selects one of the two input clocks:REF_SEL A2 35 I REF_SEL [1]: PRI_REF is selected;REF_SEL [0]: SEC_REF is selected;The input has an internal 150-k Ωpullup resistor.CP_OUT A4 31 O Charge pump outputBias voltage output to be used to bias unused complementary input VCXO_IN forVBB C1 40 O single ended signals. The output of VBB is V

– 1.3 V. The output current islimited to about 1.5 mA.This output can be programmed (SPI) to provide either the STATUS_REF orPRI_SEC_CLK information. This pin is set high if one of the STATUS conditions isvalid. STATUS_REF is the default setting.STATUS_REF or In case of STATUS_REF, the LVCMOS output provides the Status of theC8 23 OPRI_SEC_CLK Reference Clock. If a reference clock with a frequency above 2 MHz is provided toPRI_REF or SEC_REF STATUS_REF will be set high.In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primaryclock [high] or the secondary clock [low] is selected.This LVCMOS output can be programmed (SPI) to provide either theSTATUS_VCXO information or serve as current path for the charge pump (CP).STATUS_VCXO is the default setting.In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXOSTATUS_VCXO

D8 22 O input (frequencies above 2 MHz are interpreted as valid clock; active high).or I_REF_CP

In case of I_REF_CP, it provides the current path for the external referenceresistor (12 k Ω± 1%) to support an accurate charge pump current, optional. Do notuse any capacitor across this resistor to prevent noise coupling via this node. Ifthe internal 12 k Ωis selected (default setting), this pin can be left open.LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is inlock (see feature description). This output can be programmed to be digital lockdetect or analog lock detect (see feature description).The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REFclock and VCXO_IN clock at the phase frequency detector (PFD) are inside thelock detect window for a predetermined number of successive clock cycles.PLL_LOCK A8 25 I/O

The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF orSEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detectwindow or if a cycle-slip occurs.Both, the lock detect window and the number of successive clock cycles are userdefinable (via SPI).Y0A:Y0B F1, G1, 46, 47,

The outputs of the CDCM7005 are user definable and can be any combination ofY1A:Y1B H2, H3, 3, 4,

up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs areY2A:Y2B H4, H5, 7, 8, O

selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs areY3A:Y3B H6, H7, 11,12,

LVPECL.Y4A:Y4B G8, F8 16, 17

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ABSOLUTE MAXIMUM RATINGS

Package Thermal Resistance for RGZ (QFN) Package

(1) (2)

Package Thermal Resistance for ZVA (BGA) Package

(1)

RECOMMENDED OPERATING CONDITIONS

CDCM7005

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over operating free-air temperature range (unless otherwise noted)

(1)

VALUE / UNIT

, A

VCC

, V

CC_CP

Supply voltage range

(2)

– 0.5 V to 4.6 VV

Input voltage range

(3)

– 0.5 V to V

+ 0.5 VV

Output voltage range

(3)

– 0.5 V to V

+ 0.5 VOutput current for LVPECL/LVCMOS outputsI

OUT

± 50 mA(0 < V

< V

Input current (V

< 0, V

> V

) ± 20 mAT

stg

Storage temperature range – 65 ° C to 150 ° CT

Maximum junction temperature 125 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute – maximum – rated conditions for extended periods may affect device reliability.(2) All supply voltages have to be supplied at the same time.(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

Airflow (lfm) θ

( ° C/W) θ

( ° C/W)

(3)

( ° C/W)

0 29.9 22.4 1.5 0.2150 24.7 0.2250 23.2 0.2500 21.5 0.3

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).(2) Connected to GND with nine thermal vias (0,3 mm diameter).(3) θ

(junction pad) is used for the QFN package, because the main heat flow is from the junction to the GND pad of the QFN.

Airflow (m/s) θ

( ° C/W) θ

( ° C/W)

(2)

( ° C/W)

0 m/s 53.9 28.3 38.6 0.71 m/s 49.8 0.72 m/s 48.5 0.8

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).(2) θ

(junction board) is used for the BGA package, because the main heat flow is from junction to the board.

MIN NOM MAX UNIT

, AV

3 3.3 3.6Supply voltage VV

CC_CP

2.3 V

Low-level input voltage LVCMOS, see

(1)

0.3 V

High-level input voltage LVCMOS, see

(1)

0.7 V

High-level output current LVCMOS (includes all status pins) – 8 mAI

Low-level output current LVCMOS (includes all status pins) 8 mAV

Input voltage range LVCMOS 0 3.6 VV

INPP

Input amplitude LVPECL (V

VCXO_IN

– V

VCXO_IN

)

(2)

0.5 1.3 VV

Common-mode input voltage LVPECL 1 V

– 0.3 VT

Operating free-air temperature – 40 85 ° C

(1) V

and V

are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling toV

/2 is provided.(2) V

INPP

minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V

INPPof 150 mV.

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TIMING REQUIREMENTS

DEVICE CHARACTERISTICS

CDCM7005

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over recommended ranges of supply voltage, load and operating free air temperature

PARAMETER MIN TYP MAX UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

REF_IN

LVCMOS primary or secondary reference clock frequency

(1) (2)

0 200 MHzt

/ t

Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of V

4 nsdutyREF Duty cycle of PRI_REF or SEC_REF at V

/2 40% 60%

VCXO_IN, VCXO_IN REQUIREMENTS

VCXO_IN

VCXO clock frequency

(3)

0 2200 MHzt

/ t

Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz

(4)

3 nsdutyVCXO Duty cycle of VCXO clock 40% 60%

SPI/CONTROL REQUIREMENTS (see Figure 14 )

CTRL_CLK

CTRL_CLK frequency 20 MHzt

su1

CTRL_DATA to CTRL_CLK setup time 10 nst

CTRL_DATA to CTRL_CLK hold time 10 nst

CTRL_CLK high duration 25 nst

CTRL_CLK low duration 25 nst

su5

CTRL_LE to CTRL_CLK setup time 10 nst

su6

CTRL_CLK to CTRL_LE setup time 10 nst

CTRL_LE pulse width 20 nst

/ t

Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of V

4 ns

PD, RESET, HOLD, REF_SEL REQUIREMENTS

/ t

Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of V

4 ns

(1) At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets theSTATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.(2) f

REF_IN

can be up to 250 MHz in typical operating mode (25 ° C / 3.3-V V

).(3) If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequencydetection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. Thiseffects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!(4) Use a square wave for lower frequencies ( < 80 MHz).

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

OVERALL

VCXO

= 245.76 MHz,f

REF_IN

= 30.72 MHz,I

CC_LVPECL

PFD = 240 kHz, I

= 2 mA, all outputs 210 260 mAare LVPECL and Div-by-8 (load, seeSupply current (I

over frequency see

Figure 13 )Figure 1 through Figure 4 )

VCXO

= 245.76 MHz,f

REF_IN

= 30.72 MHz,I

CC_LVCMOS

120 150 mAPFD = 240 kHz, I

= 2 mA, All outputsare LVCMOS and Div-by-8 (load, 10 pF)

= 0 MHz, V

= 3.6 V, AV

= 3.6 V,I

CCPD

Power-down current V

CC_CP

= 3.6 V, 100 300 µ AV

= 0 V or V

– 0.8 V ± 40 µ AHigh-impedance state output currentI

for Yx outputs

= 0 V or V

± 100 µ A

Voltage on I_REF_CP (external current 12 k Ωto GND at pin D8 (BGA), pin 22V

I_REF_CP

1.21 Vpath for accurate charge pump current) (QFN)

Output reference voltage V

= 3 V – 3.6 V; I

= – 0.2 mA V

– 1.3 V

Output capacitance for Yx V

= 3.3 V, V

= 0 V or V

2 pF

(1) All typical values are at V

= 3.3 V, temperature = 25 ° C.

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DEVICE CHARACTERISTICS (continued)over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Input capacitance at PRI_REF and

= 0 V or V

, V

= 0 V or V

2.7SEC_REFC

pFInput capacitance at CTRL_LE,

= 0 V or V

2CTRL_CLOCK, CTRL_DATA

LVCMOS

Output frequency, see

(2)

(3)

,Figure 6 , Load = 5 pF to GND, 1 k Ωto V

, 1 k Ωf

clk

250 MHzand Figure 7 to GND

LVCMOS input clamp voltage V

= 3 V, I

= – 18 mA – 1.2 V

LVCMOS input current for CTRL_LE,I

= 0 V or V

, V

= 3.6 V ± 5 µ ACTRL_CLK, CTRL_DATA

LVCMOS input current for PD, RESET,I

HOLD, REF_SEL, PRI_REF, V

= V

, V

= 3.6 V 5 µ ASEC_REF, (see

(4)

)

LVCMOS input current for PD, RESET,I

HOLD, REF_SEL, PRI_REF, V

= 0 V, V

= 3.6 V – 15 – 35 µ ASEC_REF, (see

(4)

)

= min to max,

– 0.1I

= – 100 µAHigh-level output voltage for LVCMOSV

Voutputs V

= 3 V, I

= – 6 mA 2.4

= 3 V, I

= – 12 mA 2

= min to max,

0.1I

= 100 µALow-level output voltage for LVCMOSV

Voutputs V

= 3 V, I

= 6 mA 0.5

= 3 V, I

= 12 mA 0.8

High-level output current V

= 3.3 V, V

= 1.65 V – 30 mA

Low-level output current V

= 3.3 V, V

= 1.65 V 33 mA

VREF_IN = V

/2, Y = V

/2,tpho Phase offset (REF_IN to Y output)

(5)

1.8 nssee Figure 11 , Load = 10 pF

sk(p)

LVCMOS pulse skew, see Figure 10 Crosspoint to V

/2 load, see Figure 12 150 ps

pd(LH)

Crosspoint to V

/2,Propagation delay from VCXO_IN to

Load = 10 pF, see Figure 12 (PLL 2 2.5 3 nsYx, see Figure 10t

pd(HL)

bypass mode)

All outputs have the same divider ratio 55LVCMOS single-ended output skew,t

sk(o)

pssee

(6)

and Figure 10

Outputs have different divider ratios 70

Duty cycle LVCMOS V

/2 to V

/2 49% 51%

20% to 80% of swing (loadt

slew-rate

Output rise/fall slew rate 2.4 3.5 V/nssee Figure 12 )

LVPECL

clk

Output frequency, see

(7)

and Figure 5 Load, see Figure 13 0 1500 MHz

LVPECL input current V

= 0 V or V

± 20 µ A

LVPECL high-level output voltage Load, See Figure 13 V

– 1.18 V

– 0.81 V

LVPECL low-level output voltage Load, See Figure 13 V

– 2 V

– 1.55 V

| Differential output voltage See Figure 9 and load, see Figure 13 500 mV

VREF_IN = V

/2 to cross point of Y,t

pho

Phase offset (REF_IN to Y output)

(6)

– 200 100 pssee Figure 11

pd(LH)

Propagation delay time, VCXO_IN to Cross point-to-cross point, load

340 490 640 psYx, see Figure 10 see Figure 13t

pd(HL)

(2) f

clk

can be up to 400 MHz in the typical operating mode (25 ° C / 3.3-V V

). The total power consumption limit of 700 mW for the BGApackage can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4 ).(3) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the outputsignal swing may no longer meet the output specification.(4) These inputs have an internal 150-k Ωpullup resistor.(5) This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay Mand VCXO delay N).(6) The t

sk(o)

specification is only valid for equal loading of all outputs.(7) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the outputsignal swing may no longer meet the output specification.

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DEVICE CHARACTERISTICS (continued)over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Cross point-to-cross point, loadt

sk(p)

LVPECL pulse skew, see Figure 10 10 pssee Figure 13

Load see Figure 13 , all outputs have the

20same divider ratiot

sk(o)

LVPECL output skew

(6)

psLoad see Figure 13 , outputs have

50different divider ratios

/ t

Rise and fall time 20% to 80% of V

OUTPP

, see Figure 9 120 170 220 ps

Input capacitance at VCXO_IN,C

1.5 pFVCXO_IN

LVCMOS-TO-LVPECL

Output skew between LVCMOS and Cross point to V

/2; load,t

sk(P_C)

1.7 2 2.4 nsLVPECL outputs, see

(8)

and Figure 10 see Figure 12 and Figure 13

PLL ANALOG LOCK

High-level output current V

= 3.6 V, V

= 1.8 V – 110 µ A

Low-level output current V

= 3.6 V, V

= 1.8 V 110 µ A

High-impedance state output currentI

OZH LOCK

= 3.6 V ( PD is set low) 45 65 µ Afor PLL LOCK output

(9)

High-impedance state output currentI

OZL LOCK

= 0 V ( PD is set low) ± 5 µ Afor PLL LOCK output

(9)

IT+

Positive input threshold voltage V

= min to max V

× 0.55 V

IT –

Negative input threshold voltage V

= min to max V

× 0.35 V

PHASE DETECTOR

CPmax

Maximum charge pump frequency Default PFD pulse width delay 100 MHz

CHARGE PUMP

Charge pump sink/source currentI

= 0.5 V

CC_CP

± 0.2 ± 3 mArange

(10)

CP3St

Charge pump 3-state current 0.5 V < V

< V

CC_CP

– 0.5 V 10 nA

= 0.5 V

CC_CP

, internal reference

10%resistor, SPI default settingsI

CPA

ICP absolute accuracy

= 0.5 V

CC_CP

, external referenceresistor 12 k Ω(1%) at I_REF_CP, SPI 5%default settings

0.5 V < V

< V

CC_CP

– 0.5 V, SPII

CPM

Sink/source current matching 2.5%default settings

VCPM

ICP vs VCP matching 0.5 V < V

< V

CC_CP

– 0.5 V 5%

(8) The phase of LVCMOS is lagging in reference to the phase of LVPECL.(9) Lock output has an 80-k Ωpulldown resistor.(10) Defined by SPI settings.

Product Folder Link(s) :CDCM7005

TYPICAL CHARACTERISTICS

VCXO_IN Input Frequency − MHz

110

130

150

170

190

210

230

250

50 250 450 650 850 1050 1250 1450 1650 1850 2050

VCC = 3.3 V

TA = 25°C

ICC − Supply Current − mA

All Output Pairs Active (4 div-by-8 / 1 div-by-3)

All Output Pairs Active (div-by-1)

All Output Pairs Active (div-by-8)

∆ for div-by-2/4/8/16

One Output Pair Active (div-by-8)

∆ For 1 Output Pair

∆ For div-by-3/6

G001

No Output Active

150

250

350

450

550

650

750

50 250 450 650 850 1050 1250 1450 1650 1850 2050

VCXO_IN Input Frequency − MHz

VCC = 3.3 V

TA = 25°C

PDEV − Device Power Consumption − mW

All Output Pairs Active (4 div-by-8 / 1 div-by-3)

All Output Pairs Active (div-by-1)

All Output Pairs Active (div-by-8)

One Output Pair Active (div-by-8)

G002

No Output Active

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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LVPECL SUPPLY CURRENT

vsNUMBER OF ACTIVE OUTPUTS

A. If div-by-2/4/8/16 is activated for one or more outputs, ' Δfor div-by-2/4/8/16 ' has to be added to I

of div-by-1. If div-by-3 or div-by-6is activated, ' Δfor div-by-2/4/8/16 ' and ' Δfor div-by3/6 ' has to be added to I

of div-by-1.Figure 1.

LVPECL DEVICE POWER CONSUMPTION

vsNUMBER OF ACTIVE OUTPUTS

Figure 2.

Product Folder Link(s) :CDCM7005

100

150

200

50 100 150 200 250 300

Output Frequency − MHz

Icc − Supply Current − mA

100

200

300

400

500

600

700

800

PDEV − Power Device Consumption

− mW

Vcc = 3.3V

load = 5 pF

for 1 output for 1 output pair

no output active one output active div−by−1

one output pair active div−by−1

all outputs active div−by−1

all outputs active div−by−3

for div−by−3/6

TA = 255C

D D

100

150

200

250

40 60 80 100 120 140 160 180 200 220 240 260 280 300

Output Frequency − MHz

Icc − Supply Current − mA

100

200

300

400

500

600

700

800

900

PDEV − Device Power

Consumption − mW

for 1 output for 1 output pair

no output active one output active div−by−1

one output pair active div−by−1

all outputs active div−by−1

all outputs active div−by−3

for div−by−3/6

VCC = 3.3 V

TA = 255C

Load = 10 pF

D D

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

TYPICAL CHARACTERISTICS (continued)LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTIONvsNUMBER OF ACTIVE OUTPUTS (Load = 5 pF)

A. To estimate I

with different P-divider settings use ' Δfor div-by-2/4/8/16 ' and ' Δfor div-by-3/6 ' of Figure 1 .B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at T

85 ° C.Figure 3.

LVCMOS SUPPLY CURRENT / DEVICE POWER CONSUMPTIONvsNUMBER OF ACTIVE OUTPUTS (Load = 10 pF)

A. To estimate I

with different P-divider settings use ' Δfor div-by-2/4/8/16 ' and ' Δfor div-by-3/6 ' of Figure 1 .B. It is not recommended to exceed power dissipation of 700 mW for the BGA package at T

85 ° C.Figure 4.

Product Folder Link(s) :CDCM7005

fOut − Output Frequency − MHz

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

50 250 450 650 850 1050 1250 1450 1650 1850

VCC = 3.3 V

TA = 25°C

Termination = 50 W to VCC − 2 V

VOD − Differential Output Voltage − V

G005

f − Frequency − MHz

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

50 100 150 200 250 300 350 400 450 500

LVCMOS Output Swing − V

G006

TA = 25°C

Load = 5 pF (See Figure 12)

VCC = 3 V

VCC = 3.6 V

VCC = 3.3 V

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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TYPICAL CHARACTERISTICS (continued)DIFFERENTIAL LVPECL OUTPUT VOLTAGEvsOUTPUT FREQUENCY

Figure 5.

LVCMOS OUTPUT SWINGvsFREQUENCY

Figure 6.

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f − Frequency − MHz

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

50 100 150 200 250 300 350 400 450 500

LVCMOS Output Swing − V

G007

VCC = 3 V

VCC = 3.6 V

VCC = 3.3 V

TA = 25°C

Load = 10 pF (See Figure 12)

I − Load − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−5 0 5 10 15 20 25 30 35

VCC = 3.3 V

TA = 25°C

VBB − Output Reference Voltage − V

G008

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

TYPICAL CHARACTERISTICS (continued)LVCMOS OUTPUT SWINGvsFREQUENCY

Figure 7.

OUTPUT REFERENCE VOLTAGE (VBB)vs

LOAD

Figure 8.

Product Folder Link(s) :CDCM7005

PARAMETER MEASUREMENT INFORMATION

VOH

VOL

80%

20%

trtf

VOD

VOUTpp

T0058-01

CDCM7005

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Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time

Product Folder Link(s) :CDCM7005

YxA

YxB

YxA

YxB

VCXO_IN

/VCXO_IN

YxA

LVPECL

LVCMOS

YxA/B

VCXO_IN

/VCXO_IN

LVCMOS

YxA/B

LVPECL

LVCMOS

tpd(LH) / tpd(HL); tsk(p) = | tpd(HL) − tpd(LH) |

LVPECL

tsk(o)LVPECL

tskp_c

tpd(LH); tsk(p) = | tpd(HL) − tpd(LH) |

tsk(o)LVCMOS

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

PARAMETER MEASUREMENT INFORMATION (continued)

A. Output skew, t

sk(o),

is calculated as the greater of:The difference between the fastest and the slowest t

(LH)n (n = 0...4)The difference between the fastest and the slowest t

(HL)n (n = 0...4)B. Pluse skew, t

sk(p)

, is calculated as the magnitude of the absolute time difference between the high-to-low (t

(HL)) andthe low-to-high (t

(LH)) propagation delays when a single switching input causes one or more outputs to switch,t

sk(p)

= |t

(HL) – t

(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew.

Figure 10. Output Skew

Product Folder Link(s) :CDCM7005

T0060-01

VIH

VIL

VOH

VOL

VOH

VOL

REF_IN

YxB

YxA

LVCMOS

LVPECL

tpho LVPECL

50%VCC

tpho LVCMOS

S0079-01

CDCM7005

LVCMOS

1kW

1kW10pF

S0078-01

VCC

VEE

VT =VCC – 2V

CDCM7005

Driver

LVPECL

Receiver

Z =50

50W50W

Z =50

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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PARAMETER MEASUREMENT INFORMATION (continued)

Figure 11. Phase Offset

Figure 12. LVCMOS Output Loading During Device Test

Figure 13. LVPECL Output Loading During Device Test

Product Folder Link(s) :CDCM7005

SPI CONTROL INTERFACE

T0061-01

CTRL_DATA

CTRL_LE

CTRL_CLK

th2

tsu5 tsu6

tsu1

Bit31(MSB) Bit2 Bit1 Bit0

Bit30

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

PARAMETER MEASUREMENT INFORMATION (continued)

The serial interface of the CDCM7005 is a simple SPI-compatible interface for writing to the registers of thedevice and consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wideregisters, which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted wordmust have 32 bits, starting with MSB first. Each word can be written separately. Bit 7, 8, 10, and Bit 12 to 31 ofWord 3 are reserved for factory test purposes and must be filled with zeros. The transfer is initiated with thefalling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low datacan be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge ofCTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, thenew word is asynchronously transferred to the internal register (e.g., N, M, P, ...). Each word has to beseparately transmitted by this procedure. Unused or floating inputs must be tied to proper logic level. It isrecommended to use a 20k Ωor larger pullup resistor to VCC

Figure 14. Timing Diagram SPI Control Interface

The SPI serial protocol accepts word Write operation only. There is neither a read, acknowledge, nor ahandshake operation.

The following four words include the register settings of the programmable functions of the CDCM7005. It can bemodified to the customer application by changing one or more bits. It comes up with a default register settingafter power up or if the power down ( PD) control signal is applied. The default setting is shown in column five ofthe following words.

It is recommended to program Word 0, Word 1, Word 2 and Word 3 right after power up and PD becomes HIGH.

A low active function is shown as [0] and a high active function is shown as [1].

Product Folder Link(s) :CDCM7005

Word 0

CDCM7005

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PARAMETER MEASUREMENT INFORMATION (continued)

PIN AFFECTEDPOWER UPBIT BIT NAME DESCRIPTION/FUNCTION

CONDITION

BGA QFN

0 C0 Register Selection 01 C1 Register Selection 02 M0 Reference Divider M Reference Divider M Bit 0 13 M1 Reference Divider M Bit 1 14 M2 Reference Divider M Bit 2 15 M3 Reference Divider M Bit 3 16 M4 Reference Divider M Bit 4 17 M5 Reference Divider M Bit 5 18 M6 Reference Divider M Bit 6 19 M7 Reference Divider M Bit 7 010 M8 Reference Divider M Bit 8 011 M9 Reference Divider M Bit 9 012 N0 VC(X)O Divider N

(1)

VCXO Divider N Bit 0 113 N1 VCXO Divider N Bit 1 114 N2 VCXO Divider N Bit 2 115 N3 VCXO Divider N Bit 3 116 N4 VCXO Divider N Bit 4 117 N5 VCXO Divider N Bit 5 118 N6 VCXO Divider N Bit 6 119 N7 VCXO Divider N Bit 7 020 N8 VCXO Divider N Bit 8 021 N9 VCXO Divider N Bit 9 022 N10 VCXO Divider N Bit 10 023 N11 VCXO Divider N Bit 11 024 DLYM0 Progr. Delay M Reference Phase Delay M Bit 0 025 DLYM1 Reference Phase Delay M Bit 1 026 DLYM2 Reference Phase Delay M Bit 2 027 DLYN0 Progr. Delay N Feedback Phase Delay N Bit 0 028 DLYN1 Feedback Phase Delay N Bit 1 029 DLYN2 Feedback Phase Delay N Bit 2 030 MANAUT Manual or Auto Ref. Manual Reference Clock Selection [0] 0 A1, B1 36, 37Automatic Reference Clock Selection [1]31 REFDEC Freq. Detect Reference Frequency Detection on [0], off [1]

(2)

0 C8 23

(1) The frequency applied to the Divider N must be smaller than 300 MHz. A sufficient P Divider must be selected with the FB_MUX tomaintain this criteria.(2) If set to low, STATUS_REF will be in normal operation. If set to high, STATUS_REF will be high, even if no valid clock isdetected ( < 2 MHz). This is useful for reference inputs frequencies less than 2 MHz where the frequency detection circuitry normallyresets the STATUS_REF signal to low.

Product Folder Link(s) :CDCM7005

Word 1

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

PIN AFFECTEDPOWER UPBIT BIT NAME DESCRIPTION/FUNCTION

CONDITION

BGA QFN

0 C0 Register Selection 11 C1 Register Selection 02 OUTSEL0 Output (Yx) For Output Y0A, Y0B: 1 F1, G1 46, 47Signaling Selection LVPECL = enabled [1]; LVCMOS = enabled [0];3 OUTSEL1 For Outputs Y1A, Y1B: 1 H2, H3 3, 4LVPECL = enabled [1]; LVCMOS = enabled [0];4 OUTSEL2 For Outputs Y2A, Y2B: 1 H4, H5 7, 8LVPECL = enabled [1]; LVCMOS = enabled [0];5 OUTSEL3 For Outputs Y3A, Y3B: 1 H6, H7 11, 12LVPECL = enabled [1]; LVCMOS = enabled [0];6 OUTSEL4 For Outputs Y4A, Y4B: 1 G8, F8 16,17LVPECL = enabled [1]; LVCMOS = enabled [0];7 OUT0A0 Output Y0 Mode Output Y0A Mode Bit 0 0 F1 468 OUT0A1 Output Y0A Mode Bit 1 0 F1 469 OUT0B0 Output Y0B Mode Bit 0 0 G1 4710 OUT0B1 Output Y0B Mode Bit 1 0 G1 4711 OUT1A0 Output Y1 Mode Output Y1A Mode Bit 0 0 H2 312 OUT1A1 Output Y1A Mode Bit 1 0 H2 313 OUT1B0 Output Y1B Mode Bit 0 0 H3 414 OUT1B1 Output Y1B Mode Bit 1 0 H3 415 OUT2A0 Output Y2 Mode Output Y2A Mode Bit 0 0 H4 716 OUT2A1 Output Y2A Mode Bit 1 0 H4 717 OUT2B0 Output Y2B Mode Bit 0 0 H5 818 OUT2B1 Output Y2B Mode Bit 1 0 H5 819 OUT3A0 Output Y3 Mode Output Y3A Mode Bit 0 0 H6 1120 OUT3A1 Output Y3A Mode Bit 1 0 H6 1121 OUT3B0 Output Y3B Mode Bit 0 0 H7 1222 OUT3B1 Output Y3B Mode Bit 1 0 H7 1223 OUT4A0 Output Y4 Mode Output Y4A Mode Bit 0 0 G8 1624 OUT4A1 Output Y4A Mode Bit 1 0 G8 1625 OUT4B0 Output Y4B Mode Bit 0 0 F8 1726 OUT4B1 Output Y4B Mode Bit 1 0 F8 1727 SREF Status Ref. Displays the status of the reference clock at the 0 C8 23STATUS_REF output [0]Displays the selected clock (high for PRI_REF andlow for SEC_REF clock) at the STATUS_REFoutput [1]28 SXOIREF Status VCXO or Selects STATUS_VCXO [0] 0 D8, A8 22, 25I_REF_CP

Selects I_REF_CP [1] which enable externalreference resistor used for charge pump current andanalog PLL lock detect output current.29 ADLOCK Analog or Digital Selects Digital PLL_LOCK [0] 0 A8 25Lock Selects Analog PLL_LOCK [1]30 90DIV4 90 degree shift 90 degree output phase shift in div-4 mode on [1]; 0 Yx Yxdiv-4 off [0]

(1)

31 90DIV8 90 degree shift 90 degree output phase shift in div-8 mode on [1]; 0 Yx Yxdiv-8 off [0]

(1)

(1) The P 16-Div has to be selected to obtain the 90 degree phase shift. If bit 30 or bit 31 is set, the Div-by-16 mode is no longer available.The outputs are switched in pairs. Only one bit can be set at a time. If both bits set to [1] at the same time, no 90 degree phase shiftmode is selected (equal to off-mode setting).

Product Folder Link(s) :CDCM7005

Word 2

CDCM7005

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POWER UP PIN AFFECTEDBITBIT DESCRIPTION/FUNCTION CONDITIONAME

BGA QFNN

0 C0 Register Selection 01 C1 Register Selection 12 CP_DIR CP Direction Determines in which direction CP current regulates (Reference 0 A4 31Clock leads to Feedback Clock – see Figure 23 )– positive CP output current [0];– negative CP output current [1];3 PRECP Preset charge pump output voltage to VCC_CP/2, on [1], off [0] 0 A4 314 CP0 CP Current CP Current Setting Bit 0 0 A4 315 CP1 CP Current Setting Bit 1 1 A4 316 CP2 CP Current Setting Bit 2 0 A4 317 CP3 CP Current Setting Bit 3 1 A4 318 PFD0 PFD Pulse PFD Pulse Width PFD Bit 0 0 A4 31Width9 PFD1 PFD Pulse Width PFD Bit 1 0 A4 3110 FBMUX0 FB_MUX Feedback MUX Select Bit 0 111 FBMUX1 Feedback MUX Select Bit 1 012 FBMUX2 Feedback MUX Select Bit 2 113 Y0MUX0 Y0_MUX Output Y0x Select Bit 0 1 F1, G1 46, 4714 Y0MUX1 Output Y0x Select Bit 1 0 F1, G1 46, 4715 Y0MUX2 Output Y0x Select Bit 2 1 F1, G1 46, 4716 Y1MUX0 Y1_MUX Output Y1x Select Bit 0 1 H2, H3 3, 417 Y1MUX1 Output Y1x Select Bit 1 0 H2, H3 3, 418 Y1MUX2 Output Y1x Select Bit 2 1 H2, H3 3, 419 Y2MUX0 Y2_MUX Output Y2x Select Bit 0 1 H4, H5 7, 820 Y2MUX1 Output Y2x Select Bit 1 0 H4, H5 7, 821 Y2MUX2 Output Y2x Select Bit 2 1 H4, H5 7, 822 Y3MUX0 Y3_MUX Output Y3x Select Bit 0 1 H6, H7 11, 1223 Y3MUX1 Output Y3x Select Bit 1 0 H6, H7 11, 1224 Y3MUX2 Output Y3x Select Bit 2 1 H6, H7 11, 1225 Y4MUX0 Y4_MUX Output Y4x Select Bit 0 1 G8, F8 16, 1726 Y4MUX1 Output Y4x Select Bit 1 0 G8, F8 16, 1727 Y4MUX2 Output Y4x Select Bit 2 1 G8, F8 16, 1728 PD Power Down mode on [0], off [1] 1 Yx Yx29 RESHOL RESET or HOLD Pin definition: RESET [0] or HOLD [1] 0 H8 1430 RESET Resets all dividers [0] - (equal to RESET pin function) 131 HOLD 3-state charge pump [0] - (equal to HOLD pin function) 1 A4 31

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Word 3

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

PIN AFFECTEDBIT POWER UPBIT DESCRIPTION/FUNCTIONNAME CONDITION

BGA QFN

0 Register selection 11 Register selection 12 LOCKW 0 Lock Window Lock-detect window Bit 0 1 A8 253 LOCKW 1 Lock-detect window Bit 1 0 A8 254 LOCKC0 Lock Cycles Number of coherent lock events Bit 0 0 A8 255 LOCKC1 Number of coherent lock events Bit 1 1 A8 256 CSLIP Cycle Slip Cycle slip mode only for out-of-lock detection on [1] or 0 A8 25off [0]

(1)

7 RES RESERVED 0 RES RES8 RES RESERVED 0 RES RES9 HOLDF HOLD Function Enables the frequency hold-over function on [1], off [0] 010 RESERVED 0 RES RESHOLD function always activated [1];

(2)

Triggered by analog PLL lock detect outputs [0] (ifHOLD Trigger11 HOLDTR analog PLL Lock signal is set then HOLD is activated; 0Condition

if analog PLL lock signal is reset then HOLD isde-activated).12 RES RESERVED 0 RES RES13 RES RESERVED 0 RES RES14 RES RESERVED 0 RES RES15 RES RESERVED 0 RES RES16 GTME General Test Mode Enable. Test Mode is only 0enabled if this bit is set to 1.17 RES RESERVED 0 RES RES18 RES RESERVED 0 RES RES19 RES RESERVED 0 RES RES20 RES RESERVED 0 RES RES21 RES RESERVED 0 RES RES22 RES RESERVED 0 RES RES23 RES RESERVED 0 RES RES24 RES RESERVED 0 RES RES25 RES RESERVED 0 RES RES26 RES RESERVED 0 RES RES27 RES RESERVED 0 RES RES28 PFDFC PFD Frequency Control. Data provided to the PFD 0 D8 22are feed through to the corresponding STATUSpins

(3)

29 RES RESERVED 0 RES RES30 RES RESERVED 0 RES RES31 RES RESERVED 0 RES RES

(1) If Cycle Slip mode only for out-of-lock detection is on, the selected lock detect window is valid for lock detect. Independent from this, outof lock is detected if a cycle slip occurs.(2) HOLD function always activated is recommended for test purposes only.(3) The maximum frequency for the STATUS_VCXO pin is 100 MHz.

Product Folder Link(s) :CDCM7005

FUNCTIONAL DESCRIPTION OF THE LOGIC

Reference Divider M (Word 0)

(4)

VC(X)O Feedback Divider N (Word 0)

(1) (2)

CDCM7005

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M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by Default

00000000001000000000120000000010300000000114•

•

•0001111111128 Yes•

•

•111111110110221111111110102311111111111024

(4) If the divider value is Q, then the code will be the binary value of (Q – 1).

N11 N10 N0 N8 N7 N6 N5 N4 N3 N2 N1 N0 Div by Default

000000000000 1000000000001 2000000000010 3000000000011 4•

•

•0 0 0 0 0 1 1 1 1 1 1 1 128 Yes•

•

•1 1 1 1 1 1 1 1 1 1 0 1 40941 1 1 1 1 1 1 1 1 1 1 0 40951 1 1 1 1 1 1 1 1 1 1 1 4096

(1) If the divider value is Q, then the code will be the binary value of (Q – 1).(2) The frequency applied to the Divider N must be smaller than 300 MHz. A sufficient P Divider must be selected with the FB_MUX tomaintain this criteria.

Product Folder Link(s) :CDCM7005

Output Mode Selection for LVCMOS and LVPECL Outputs: Y0A, Y0B, Y1A … Y4B (Word 1)

(1)

Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment (Word 0)

(1)

PFD Pulse Width Delay (Word 2)

Lock-Detect Window (Word 3)

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

OUTSELx OUTxB1 OUTxB0 LVCMOS OUTxA1 OUTxA0 LVCMOS Default[YxB] [YxA]

LVCMOS 0 0 0 Active 0 0 Active0 0 1 3-state 0 1 3-state0 1 0 Inverting 1 0 Inverting0 1 1 Low 1 1 Low

OUTSELx OUTxB1 OUTxB0 OUTxA1 OUTxA0 LVCMOS Default[YxA]

LVPECL 1 x x x 0 Active Yx1 x x x 1 3-state

(1) If the differential LVPECL output e.g. Y0A:Y0B is selected (bit 2 of word 1), then only bit 7 of word 1 defines the output mode forY0A:Y0B. The settings of bit 8, bit 9, and bit 10 of word 1 are therefore not relevant to the Y0A:Y0B. This applies for the other LVPECLoutputs as well.

DLYM2 / DLYN2 DLYM1 / DLYN1 DLYM0 / DLYN0 Phase Offset Default

0 0 0 0 ps Yes0 0 1 ± 160 ps0 1 0 ± 320 ps0 1 1 ± 480 ps1 0 0 ± 830 ps1 0 1 ± 1130 ps1 1 0 ± 1450 ps1 1 1 ± 1750 ps

(1) If Progr. Delay M is set, all Yx outputs are lagging to the reference clock according to the value set. If Progr. If Delay N is set; all Yxoutputs are leading to the reference clock according to the value set. Above are typical values at V

= 3.3 V, Temp = 25 ° C,PECL-output relate to Div4 mode.

PFD1

(1)

PFD0

(1)

PFD Pulse Width

(1) (2)

Default

(1)

0 0 1.5 ns Yes0 1 3 ns1 0 4.5 ns1 1 6 ns

(1) The PFD pulse width delay gets around the dead zone of the PFD transfer function and reduces phase noise and reference spurs.(2) Typical values at V = 3.3 V

, Temp = 25 ° C .

LOCKW1 LOCKW0 Phase-Offset at PFD Input

(1)

Default

0 0 3.5 ns0 1 8.5 ns Yes1 0 18.5 ns1 1 Cycle slip

(2)

(1) Typical Values at V

= 3.3 V, Temp = 25 ° C.(2) Cycle slip occurs when the phase shift at the PFD is greater than one period of the frequency. It is a complete (integer number) cyclejump, i.e., cause by a loss-of-lock of the PLL.

Product Folder Link(s) :CDCM7005

Number of Successive Lock Events Inside the Lock Detect Window (Word 3)

Charge Pump Current (Word 2)

FB_MUX Selection (Word 2)

Yx_MUX – Output Divider Selection for Y0, Y1, Y2, Y3, Y4 (Word 2)

CDCM7005

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LOCKC1

(1)

LOCKC0

(1)

No. of Successive Lock Events

(1)

Default

(1)

0 0 10 1 161 0 64 Yes1 1 256

(1) This does not apply to Out-of-Lock condition.

CP3 CP2 CP1 CP0 Typical Charge Pump Current Default

0 0 0 0 0 µ A (3-state)0 0 0 1 200 µ A0 0 1 0 400 µ A0 0 1 1 600 µ A0 1 0 0 800 µ A0 1 0 1 1 mA0 1 1 0 1.2 mA0 1 1 1 1.4 mA1 0 0 0 1.6 mA1 0 0 1 1.8 mA1 0 1 0 2.0 mA Yes1 0 1 1 2.2 mA1 1 0 0 2.4 mA1 1 0 1 2.6 mA1 1 1 0 2.8 mA1 1 1 1 3 mA

FBMUX2 FBMUX1 FBMUX0 Selected VC(X)O Signal for the DefaultPhase Discriminator

0 0 0 Div by 10 0 1 Div by 20 1 0 Div by 30 1 1 Div by 41 0 0 Div by 61 0 1 Div by 8 Yes1 1 0 Div by 16

(1)

1 1 1 Div by 8

(1) This divider setting depends on the selected P-divider mode for the “ Div-by-16 ” divider. In the default mode (after power up), Div-by-16is selected. But if bit 30 or bit 31 of word 1 is set to [1], then the Div-by-4 and 90 degree phase shift or Div-by-8 and 90 degree phaseshift is selected.

YxMUX2 YxMUX1 YxMUX0 Selected Divided V(C)XO Signal for the DefaultYx Outputs

0 0 0 Div by 10 0 1 Div by 20 1 0 Div by 30 1 1 Div by 41 0 0 Div by 61 0 1 Div by 8 all Yx

Product Folder Link(s) :CDCM7005

FEATURE DESCRIPTION

Automatic/Manual Reference Clock Switching

T0062-01

PRI_REF

SEC_REF

STATUS_REF

PRI_SEC_CLK

1 2 34

Internal

ReferenceClock

PrimaryClock SecondaryClock PrimaryClock

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

YxMUX2 YxMUX1 YxMUX0 Selected Divided V(C)XO Signal for the DefaultYx Outputs

1 1 0 Div by 16

(1)

1 1 1 Div by 8

The CDCM7005 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clockinput, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by thededicated SPI register bit (Word 0, Bit 30).

In the manual mode, the external REF_SEL signal selects one of the two input clocks:REF_SEL [1] -> primary clock is selectedREF_SEL [0] -> secondary clock is selected

In the automatic mode, the primary clock is selected by default even if both clocks are available. In case theprimary clock is not available or fails, then the input switches to the secondary clock as long until the primaryclock is back. Figure 15 shows the automatic clock selection.

NOTE: PRI_REF is the preferred clock input.

Figure 15. Behavior of STATUS_REF and PRI_SEC_CLK

In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. Thephase of the clock signal can be any.

The clock input circuitry is design to suppress glitches during switching between the primary and secondary clockin the manual and automatic mode. This avoids an undefined switching of the following circuitries.

The phase of the output clock slowly follows the new input phase. There will be no phase-jump at the output.How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of< 100 Hz; the phase adjustment can take several ms. There is no phase build-out function supported (like inSONET/SDH applications).

Product Folder Link(s) :CDCM7005

T0063-01

PRI_REF

SEC_REF

Internal

ReferenceClock

YxOutput

PRI_SEC_CLK

234

PrimaryClock SecondaryClock PrimaryClock

PLL Lock for Analog and Digital Detect

T0064-01

t(lockdetect)

SelectedREFatPFD

(clockfedthroughMDividerandMDelay)

VCXO_INatPFD

(clockfedthroughNDividerandNDelay)

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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Figure 16. Phase Approach of Output to New Reference Clock

The CDCM7005 supports two PLL lock indications: the digital lock signal or the analog lock signal. Both signalsindicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.

PLL Lock/Out-of-Lock Definition

The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) andFeedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detectwindow, or if no cycle-slip appears, for a pre-defined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) andFeedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a cycle-slipappears.

Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6).

Figure 17. Lock Detect Window

The lock detect window describes the maximum allowed time difference for lock detect between the rising edgeof PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. Therising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lockdetect window if there is a phase displacement of more than +0.5 × t

(lockdetect)

or -0.5 x t

(lockdetect)

Product Folder Link(s) :CDCM7005

S0080-01

Power_Down

Lock_Out

Lock_In

80kW

5pF

PLL_LOCK

Output

CDCM7005

Lock

DigitalLockDetection

V =0.55V

high CC

V =0.35V

low CC

Out-of-Lock

VOut

S0081-01

Power_Down

Lock_Out

Lock_In

100 A

(Lock)

100 A

(Out-of-Lock)

80kW

5pF

PLL_LOCK

Output

Lock

V =0.55V

high CC

VCC

V =0.35V

low CC

Out-of-Lock

VOut

V =1/C I t

Out ´ ´

Example:

forI=110 A,C=10nF,V =3.3V,

andV =V =0.55 Vcc=1.8V

t=164 s

³ m

high out

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

Digital vs Analog Lock

Figure 18 and Figure 19 show the circuit for the digital and analog lock. The analog lock operates with anexternal load capacitor.

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out oflock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window andhigh number of successive clock cycles. PLL_LOCK returns to out of lock if just one cycle is outside the lockdetect window or a cycle slip occurs.

Figure 18. Digital Lock-Detect

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110- µ Acurrent source until logic high-level is reached. Therefore, more time is needed to detect logic high level, butjittering of PLL_LOCK will be suppressed in case of digital lock. The time PLL_LOCK needs to return to out oflock depends on the level of V

Out

, when the current source starts to unload the external capacitor.

Figure 19. Analog Lock-Detect

Product Folder Link(s) :CDCM7005

Differential LVPECL Outputs and Single-Ended LVCMOS Outputs

B0058-01

PECL

Input

VCXO_IN

P Divider

÷3

÷4

÷6

÷8

÷16

÷1

÷2

÷4

÷8

90o

P16-Div

T0065-01

ReferenceClock

VCXOClock

Y-Outputdiv4

(90degshift)

Y-Outputdiv8

(90degshift)

90deg 90deg

Y-Outputdiv8

90deg

LVCMOSOutputs LVPECL Outputs

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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The CDCM7005 supports up to 5 × LVPECL outputs or 10 × LVCMOS/LVTTL outputs or any combination ofthese. The single-ended LVCMOS outputs are arranged in pairs which mean both outputs of a LVCMOS pairhave the same frequency but can separately be disabled or inverted. The power up output arrangement is fiveLVPECL (default setting).

The LVPECL outputs are designed to terminate in to a 50- Ωload to V

– 2 V. The LVCMOS outputs supportsthe standard LVCMOS load (see Figure 12 ). The LVPECL and LVCMOS outputs can be enabled (normaloperation) or disabled (3-state).

In addition, the output phase can be shifted by 90 degrees when using the additional div-by-4 or div-by-8 modeof the P16-Div (see Figure 20 ). In the default mode (after power up), the div-by-16 mode of the P16-Div is active.To change it to a 90 degree phase shift, bit 30 or bit 31 of word 1 has to be programmed accordingly. The P16-Div has to be selected via the dedicated YxMUX to obtain the 90 degree phase shift. The outputs areswitched in pairs. When selecting the 90 degree phase shift mode, the div-by-16 functions will no longer beavailable. The 90 degree phase shifted signal is lagging to the non-shifted signal.

Figure 20. 90 Degree Phase Shift Option of P-Divider

The following diagram shows the LVCMOS and LVPECL output signal when 90 degree phase shift is on.

Figure 21. Output Switching Diagram

Product Folder Link(s) :CDCM7005

Frequency Hold-Over Mode

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

In addition, the LVCMOS supports disabled-to-low and 180 degree output phase shift for each output individually.When selecting the 180 degree phase shift together with the 90 degree phase shift, the respective outputs has atotal phase shift of 270 degree (see Table 2 ).

Table 2. LVCMOS Phase Shift Options

Phase P-Divider 180 ° Phase-Shift P16-Div - Function

0 ° Any P-Divider No div-by-1690 ° P16-Div No div-by-4 or div-by-8180 ° Any P-Divider Yes div-by-16270 ° P16-Div Yes div-by-4 or div-by-8

If the P16-Div is selected by the FB_MUX and div-by-4 or div-by-8 is active, the 90 degree phase shifted clockwill be synchronized to PRI_REF or SEC_REF. This means all outputs Yxx, which are switched to div-by-4 ordiv-by-8, are in phase to PRI_REF or SEC_REF. All other outputs are 90 degree phase shifted with leadingphase.

The HOLD function is a useful feature which helps the designer to improve the system reliability. The HOLDfunction holds the output frequency in case the input reference clock fails or is disrupted. During HOLD, thecharge pump is switched off (3-state) freezing the last valid output frequency. The hold function will be releasedafter a valid reference clock is back. For proper HOLD function, the analog PLL lock detect mode has to beactive.

The following register settings are involved with the HOLD function:•Lock Detect Window (Word 3, Bit 2, 3, 6): Defines the window in ns inside the lock is valid. The size is3.5 ns, 8.5 ns, 18.5 ns, or a complete cycle-slip. Lock is set if reference clock and the feedback clock areinside this predefined lock-detect window for a pre-selected number of successive cycles or if a cycle-slip nolonger occurs.•Out-of-Lock: Defines the out-of-lock condition: If the reference clock and the feedback clock at the PFD areoutside the predefined Lock Detect Window or if a cycle-slip occurs.•Cycle-Slip (Word 3, Bit 6): Cycle-slip occurs when the phase shift at the PFD is greater than one period of thefrequency. It is a complete (integer number) cycle jump, i.e. caused by an out-of-lock of the PLL. Cycle-slip isequivalent to the PLL pull-in time.•Number of Clock Cycles (Word 3, Bit 4, 5): Defines the number of successive PFD cycles which have tooccur inside the lock window to set Lock detect. This applies not for out-of-lock condition.•Hold-Function (Word 3, Bit 9): Selects HOLD function (see more details below).•Hold-Trigger (Word 3, Bit 11): Defines whether the HOLD function is always activated (Bit 11 = [1]) or whetherit is dependent on the state of the analog PLL lock detect output (Bit 11 = [0]). In the latter case, HOLD isactivated, if lock is set (high) and de-activated if Lock is reset (low).•Analog PLL Lock Detect (Word 1, Bit 29): Analog lock output charges or discharges an external capacitor withevery valid lock cycle. The time constant for Lock detect can be set by the value of the capacitor.

The CDCM7005 supports two types of HOLD functions, one external controllable HOLD mode and one internalmode, HOLD.

With the external HOLD function the charge pump can directly be switched into 3-state (pin H8 [BGA] or pin 14[QFN] can be programmed for HOLD [Word 2, Bit 29]). This function is also available via SPI register (Word 2,Bit 31).

If logic low is applied to the HOLD pin, the charge pump will be switched to 3-state. After the HOLD pin isreleased, the charge pump is switched back in to normal operation with the next valid reference clock cycle atPRI_REF or SEC_REF and the next valid feedback clock cycle at the PFD. During HOLD, the P divider and alloutputs Yx are at normal operation.

HOLD-Over-Function: The PLL has to be in lock to start the HOLD function. It switches the charge pump in to3-State when an out-of-lock event occurs. It leaves the 3-state charge pump state when the reference clock isback. Then it starts a locking sequence of 64 cycles before it goes back to the beginning of the HOLD-over loop.The dedicated looking sequence and a digital phase alignment enable a fast lock.

Product Folder Link(s) :CDCM7005

F0004-01

PLL

Out-of-Lock?

PLL-Lock

Output

Set?

3-StateCharge-Pump

ReferenceClock

Back?

64PFD

Lock-Cycles

Yes

Charge-Pumpisswitchedinto3-State.

P-dividerand Yxoutputareatnormaloperation.

TheCharge-Pumpremainsin3-State

untiltheReferenceClockisback. The1st

validReferenceClockatthePFDreleases

theCharge-Pump.

ThePLL acquire64lockcyclestophase

aligntotheinputclock.

FrequencyHold-OverFunctionworksin

combinationwiththe AnalogLock-Detect

functiononly!

Start

PLL isout-of-lockifthephase

differenceofReferenceClockand

FeedbackClockatPFDareoutsidethe

predefinedLock-Detect-Windoworifa

Cycle-Slipoccurs.

PLL hastobeinLOCKtostart

HOLD-Function.

(The AnalogLockoutputisnotresetbythefirstOut-of-

Lockevent.Itstays‘High’ dependingontheanalogtime

delay(outputC-load). Thetimedelaymustbelongenough

toassureproperHOLDfunction)

(The‘PLL-LockOutputSet?’ enquirycanbebypassedby

settingtheHOLDTRbitto[1](Word3,Bit11)

Charge Pump Preset to VCC_CP/2

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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Figure 22. Frequency HOLD-Over Function

The preset charge pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O afterpowerup or reset. The adequate control voltage for the VC(X)O will be provided to the charge-pump output by aninternal voltage divider of 1 k Ω/1 k Ωto VCC_CP and GND (VCC_CP/2).

This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) orOBSAI (Open Base Station Architecture Initiative).

The preset charge pump to VCC_CP/2 can be set and reset by SPI register (word 2, bit 3). This feature must bedisabled for PLL locking.

Product Folder Link(s) :CDCM7005

Charge Pump Current Direction

T0076-01

PFDPulse

WidthDelay

PFDPulse

WidthDelay

0V

VCC

PRI_REForSEC_REF

ClockFedThroughthe

MDividerandDelay

VCXO_INClockFedThrough

theNDividerandDelay

CP_DIR(Bit2ofWord2=0,

DefaultState)

CP_DIR(Bit2ofWord2=1)

V (InternalSignal)

(PFD1)

V (InternalSignal)

(PFD2)

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

The direction of the charge pump (CP) current pulse can be changed by the SPI register (word 2, bit 2). Itdetermines in which direction the CP current regulates (reference clock leads to feedback clock). Mostapplications use the positive CP output current (power-up condition) because of the use of a passive loop filter.The negative CP current is useful when using an active loop filter concept with inverting operational amplifier.Figure 23 shows the internal PFD signal and the corresponding CP current.

NOTE: The purpose of the PFD pluse width delay is to improve spurious suppression.

Figure 23. Charge Pump Current Direction (VCXO and VCO Support)

Product Folder Link(s) :CDCM7005

APPLICATION INFORMATION

Phase Noise Reference Circuit

S0082-01

VCXO Low-PassFilter

CDCM7005

245.76MHz

Gain=21.3kHz/V

PECL_OUT_B

PRI_REF

VCXO_IN YnA

YnB

VCXO_IN

CTRL_DATA

CTRL_LE

CTRL_CLK

V_CTRL

CP_OUT

PLL_LOCK

STATUS_REF

STATUS_VCXO

PECL_OUT

SPI

VOC VOC

130W

82W

150W

50W

82W

150WR

50W

160W

130W

4.7kWC2

100nF

22 Fm

10nF

100nF

Measurement

Equipment

PhaseNoiseReferenceCircuit(SeetheEVM)

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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Figure 24. Typical Applications Diagram With Passive Loop Filter

Product Folder Link(s) :CDCM7005

Phase Noise Performance

f − Frequency − Hz

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

10 100 1k 100k 10M1M10k

L(f) − dB

G009

CDCM7005 in PLL−Closed Loop

CDCM7005 EVM

REF_IN: AgilentE8257C−61.44MHz

VCXO: Toyocom TCO−2111 245.76MHz

CDCM7005 Out is Y0A: 61.44MHz

Loop bandwidth ~ 30Hz

Date: 30. Mar 2005

Phase-Noise

Analyzer

E5052A

CDCM7005

Ref_Clk

LPF

VCXO

Phase Jitter (rms) − 1kHz − 10MHz

LVPECL

61.44MHz (282fs)

Input−Clk

61.44MHz (769fs)

VXCO

245.76MHz (581fs)

LVCMOS

61.44MHz

(230fs)

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

REF_IN PHASE VCXO PHASE Yx PHASE NOISENOISE NOISE AT 30.72 MHzPARAMETER

(1)

TEST CONDITIONS UNITAT 30.72 MHz AT 245.76 MHz

LVCMOS LVPECL

TYP

(2)

TYP

(2)

phn10 Phase noise at 10 Hz – 109 – 75 – 104 – 100 dBc/Hzphn100 Phase noise at 100 Hz – 125 – 97 – 116 – 116 dBc/HzY = 30.72 MHz; f

PFD

= 200phn1k Phase noise at 1 kHz – 134 – 117 – 140 – 140 dBc/HzkHz, Loop BW = 20 Hz,phn10k Phase noise at 10 kHz Feedback Divider = 8 x 128 – 136 – 138 – 153 – 152 dBc/Hz(N x P), f

REF_IN

= 30.72 MHz,phn100k Phase noise at 100 kHz – 138 – 148 – 156 – 153 dBc/HzM-Divider = 128, I

= 2 mAphn1Mk Phase noise at 1 MHz – 144 – 148 – 156 – 153 dBc/Hzphn10M Phase noise at 10 MHz – 144 – 148 – 156 – 153 dBc/Hz

PLL Stabilization Time

tstabi PLL stabilization time

(3)

Y = 30.72 MHz, f

PFD

= 200 400 mskHz, Loop BW = 20 Hz,Feedback Divider = 8 x 128(N x P), f

REF_IN

= 30.72 MHz,M-Divider = 128, I

= 2 mA

(1) Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor. The phase noise performance of theBGA and the QFN package is equal. The phase noise measurements were taken with the CDCM7005 EVM and CDCM7005 SPI defaultsettings.

(2) The typical stabilization time is based on the above application example. The stabilization criterion was a stable high level ofPLL_LOCK.

(3) For further explanations, as well as phase noise/jitter test results using various VCXOs, see application note SCAA067 .

Figure 25. Phase Noise (61.44-MHz REF_IN and 61.44-MHz Output Frequency)

Product Folder Link(s) :CDCM7005

In-Band Noise Performance

APPLICATION INFORMATION ON THE CLOCK GENERATION FOR INTERPOLATING DACS

B0064-01

LO1

(PLL)

16-Bit

DAC

16-Bit

DAC

DAC5687

FIRFIR

DDC

DUC

14-Bit

ADC

ADS5423

3.84MHz

VCXO

491.52MHz

61.44MHz

491.52MHz

122.88MHz

Duplexer

LO1

IF1

LNA

FIRFIR

From

GC5016

THS4509

TRF3750

(PLL)

TRF3702

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

in-band

In-band phase noise test conditions – 95 dBc/HzY = 900 MHz, f

PFD

= 400 kHz, Looppn

f400

Phase noise floor at 400 kHz f

PFD

, in-band – 162 dBc/HzBW = 27 kHz, Feedback Divider = 8 x 282noise – 20log(feedback div)

(1)

(N x P), f

REF_IN

= 10 MHz; M-Divider = 25, I

=pn

Phase noise floor at 1 Hz f

PFD

, in-band – 218 dBc/Hz3 mAnoise – 20log(feedback div) – 10log(f

PFD

)

(2)

(1) The synthesizer phase noise floor can be estimated by measuring the in-band noise at the output of the CDCM7005 and subtracting20log(Feedback Divider) N (in case of CDCM7005 it is the N+P divider). The calculated phase noise floor still based on the PFD updatefrequency, in the above specification, is 400 kHz.(2) The in-band noise can also be normalized to a comparison frequency of 1 Hz. The resulting phase noise floor is: pnfloor = PNmeasured- 20log(N+P) - 10log(f

PFD

)where:

pnNfloor = normalized phase noise floor in dBc/HzPNmeasured = in-band phase noise measurement in dBc/Hz20log(N+P) = divider ratio of feedback loop10log(f

PFD

) = PFD update frequency in Hz

WITH THE CDCM7005The CDCM7005, with its specified phase noise performance, is an ideal sampling clock generator for high speedADCs and DACs. The CDCM7005 is especially of interest for the new high speed DACs, which have integratedinterpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can typically not besupported from the digital side driving the DAC (e.g., DUC, digital up-converter). Therefore, one approach tointerface the DUC to the DAC is the integration of an interpolation filter within the DAC to reduce the data rate atthe digital input of the DAC. In 3G systems, for example, a common sampling rate of a high speed DAC is491.52 MSPS. With a four times interpolation of the digital data, the required input data rate results into122.88 MSPS, which can be supported easily from the digital side. The DUC GC5016, which supports up to fourWCDMA carriers, provides a maximum output data rate of 150 MSPS. An example is shown in Figure 26 , wherethe CDCM7005 supplies the clock signal for the DUC/DDC and ADC/DAC.

Figure 26. CDCM7005 as a Clock Generator for High Speed ADCs and DACs

Product Folder Link(s) :CDCM7005

AC-Coupled Interface to ADC/DAC

DAC

CDCM7005

YxA

YxB

LVPECL

Driver

150 W150 W

130 W

83 W

VCC

CDCM7005

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....................................................................................................................................................... SCAS793D – JUNE 2005 – REVISED AUGUST 2009

The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DACcan be done in different ways. The recommended way is to use the CDCM7005, which generates the fastsampling clock for the DAC from the data input clock signal. The DAC5687 demands that the edges of the twoinput clocks must be phase aligned within ± 500 ps for latching the data properly. This phase alignment is wellachieved with the CDCM7005, which assures a maximum skew of 70 ps of the different different outputs to eachother.

Another advantage of this clock solution is that the ADC or DAC can be driven directly in an ac-coupling interfaceas shown in Figure 27 , with an external termination in a differential configuration. There is no need for atransformer to generate a differential signal from a single-ended clock source.

Figure 27. Driving DAC or ADC With PECL Output of the CDCM7005

Product Folder Link(s) :CDCM7005

CDCM7005

SCAS793D – JUNE 2005 – REVISED AUGUST 2009 .......................................................................................................................................................

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Revision History

Changes from Original (June 2005) to Revision A ......................................................................................................... Page

•Changed data sheet from Product Preview to Production data............................................................................................. 1

Changes from Revision A (June 2005) to Revision B .................................................................................................... Page

•Added minor updates. ............................................................................................................................................................ 1

Changes from Revision B (October 2005) to Revision C ............................................................................................... Page

•Changed N2, From: 1 To: 0 ................................................................................................................................................. 22•Changed N3, From: 1 To: 0 ................................................................................................................................................. 22•Changed N3, From: 1 To: 0 ................................................................................................................................................. 22•Changed N2, From: 1 To: 0 ................................................................................................................................................. 22

Changes from Revision C (December 2007) to Revision D ........................................................................................... Page

•Changed The VCC pin text - From: There is no internal connection between V

and AV

To: V

and AV

CCshould have always same supply voltage.............................................................................................................................. 4•Added to the CTRL_LE - Unused or floating inputs must be tied to proper logic level. It is recommended to use a20k Ωor larger pullup resistor to VCC. ................................................................................................................................... 4•Added to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. It is recommended to usea 20k Ωor larger pullup resistor to VCC. ................................................................................................................................ 4•Added to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. It is recommended touse a 20k Ωor larger pullup resistor to VCC. ......................................................................................................................... 4•Added to the PD pin text - It is recommended to ramp up the... ........................................................................................... 4•Added to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level. It isrecommended to use a 20k Ωor larger pullup resistor to VCC. ........................................................................................... 17•Added to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2 andWord 3 right after power up and PD becomes HIGH. ” ........................................................................................................ 17•Changed From: RES To: GTME .......................................................................................................................................... 21•Changed From: RES To: PFDFC ........................................................................................................................................ 21

Product Folder Link(s) :CDCM7005

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CDCM7005RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS &

no Sb/Br) Call TI Level-3-260C-168 HR

CDCM7005RGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS &

no Sb/Br) Call TI Level-3-260C-168 HR

CDCM7005RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS &

no Sb/Br) Call TI Level-3-260C-168 HR

CDCM7005RGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS &

no Sb/Br) Call TI Level-3-260C-168 HR

CDCM7005ZVA ACTIVE BGA ZVA 64 348 Pb-Free

(RoHS) SNAGCU Level-3-260C-168 HR

CDCM7005ZVAR ACTIVE BGA ZVA 64 1000 Pb-Free

(RoHS) SNAGCU Level-3-260C-168 HR

CDCM7005ZVAT ACTIVE BGA ZVA 64 250 Pb-Free

(RoHS) SNAGCU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CDCM7005 :

•Space: CDCM7005-SP

NOTE: Qualified Version Definitions:

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

PACKAGE OPTION ADDENDUM

www.ti.com 8-Dec-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CDCM7005RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

CDCM7005RGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

CDCM7005ZVAR BGA ZVA 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1

CDCM7005ZVAT BGA ZVA 64 250 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CDCM7005RGZR VQFN RGZ 48 2500 336.6 336.6 28.6

CDCM7005RGZT VQFN RGZ 48 250 336.6 336.6 28.6

CDCM7005ZVAR BGA ZVA 64 1000 336.6 336.6 28.6

CDCM7005ZVAT BGA ZVA 64 250 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2012

Pack Materials-Page 2

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