ISL88021, ISL88022 (R) Data Sheet September 18, 2006 Triple Voltage Monitor with Adjustable Power-On-Reset and Undervoltage/ Overvoltage Monitoring Capability The ISL88021 and ISL88022 family of devices are customizable triple voltage-monitoring supervisors that assert a reset if any of the monitored voltages becomes non-compliant. They offer popular functions such as Power-On-Reset timing control with both RESET and RESET outputs, Supply Voltage Supervision, both under or overvoltage detection, and Manual Reset assertion. By offering these features in a small 8 Ld MSOP package, the ISL88021 and ISL88022 can lower system cost, reduce board space requirements and increase the reliability of systems. Applying a voltage to VDD activates the Power-On-Reset circuit which holds RESET low for an adjustable period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VDD detection circuitry protects the user's system from low voltage conditions, resetting the system when VDD falls below its minimum preset voltage threshold VTH1. Reset remains asserted until VDD returns to its proper operating level and stabilizes. Two additional voltage monitoring inputs, V2MON (preset) and V3MON (adjustable), monitor other supplies to provide reliable system operation. The ISL88021 V3MON input monitors for undervoltage (UV) conditions whereas the ISL88022 V3MON input allows monitoring for overvoltage (OV) conditions. The monitored voltage on V3MON on either device is compared via a resistor divider to a 600mV internal reference. Hence, any voltage more or less positive than this reference can be accurately monitored to meet specific system level requirements or to fine-tune the threshold for applications requiring higher precision. These devices also let users increase the Power-On-Reset time-out delay by connecting a capacitor between CPOR and ground. This lengthens the period of an internal clock counter thereby increasing the time between voltage compliance and reset outputs signaling. FN8226.1 Features * Triple Voltage Monitor and Reset Assertion * Low VDD Detection and Reset Assertion - Adjustable Reset Threshold Voltages - 0.6V 6mV Over -40C to +85C - Reset Signal Valid to VDD = 1V * 140ms Minimum Reset Pulse Delay that is Customizable Using an External Capacitor * Both RST and RST Outputs Available * Undervoltage/Overvoltage Monitoring Capability * Low 20A Consumption * Small 8 Ld MSOP Package * Pb-Free Plus Anneal Available (RoHS Compliant) Applications * Process Control Systems * Intelligent Instruments * Embedded Control Systems * Computer Systems * Portable/Battery-Powered Equipment * Multi-Voltage Systems Pinout ISL88021, ISL88022 (8 LD MSOP) TOP VIEW MR 1 8 RST VDD 2 7 RST V2MON 3 6 CPOR GND 4 5 V3MON A manual reset input provides debounce circuitry for minimum reset component count. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL88021, ISL88022 Ordering Information PART NUMBER Ordering Information (See Notes) PART VDD V2MO V3MON MARKING VTRIP1 VTRIP2 TYPE PACKAGE PART NUMBER (See Notes) (Continued) PART VDD V2MO V3MON MARKING VTRIP1 VTRIP2 TYPE PACKAGE ISL88021IU8FAZ ANM 3.09V 1.69V UV 8 Ld MSOP ISL88022IU8HAZ 4.64V 1.69V OV 8 Ld MSOP ISL88021IU8FCZ ANL 3.09V 2.32V UV 8 Ld MSOP ISL88022IU8HCZ 4.64V 2.32V OV 8 Ld MSOP ISL88021IU8FEZ 3.09V 2.92V UV 8 Ld MSOP ISL88022IU8HEZ ANO 4.64V 2.92V OV 8 Ld MSOP ISL88021IU8FFZ 3.09V 3.09V UV 8 Ld MSOP ISL88022IU8HFZ ANN 4.64V 3.09V OV 8 Ld MSOP ISL88021IU8HAZ 4.64V 1.69V UV 8 Ld MSOP NOTES: ISL88021IU8HCZ 4.64V 2.32V UV 8 Ld MSOP ISL88021IU8HEZ ANK 4.64V 2.92V UV 8 Ld MSOP ISL88021IU8HFZ ANJ 4.64V 3.09V UV 8 Ld MSOP ISL88022IU8FAZ ANQ 3.09V 1.69V OV 8 Ld MSOP ISL88022IU8FCZ ANP 3.09V 2.32V OV 8 Ld MSOP ISL88022IU8FEZ 3.09V 2.92V OV 8 Ld MSOP ISL88022IU8FFZ 3.09V 3.09V OV 8 Ld MSOP 1. Standard versions are shown in bold. For non-standard versions, please contact factory for availability. 2. Add "-TK" suffix for Tape and Reel. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagrams VDD VDD RST RST RST RST POR POR V2MON CPOR V2MON CPOR MR V3MON MR V3MON PB VREF PB VREF GND GND ISL88022 ISL88021 Pin Descriptions ISL88021 ISL88022 NAME 1 1 MR Active-Low Open Drain Manual Reset Input 2 2 VDD Power Supply Input 3 3 V2MON 4 4 GND 5 FUNCTION Second Undervoltage Monitor Input Ground V3MON Undervoltage Monitor Input 5 V3MON Overvoltage Monitor Input 6 6 CPOR Set Power-On-Reset Timeout Delay 7 7 RST Active-Low Open Drain Reset Output 8 8 RST Active-High Push-Pull Reset Output 2 FN8226.1 September 18, 2006 ISL88021, ISL88022 Absolute Maximum Ratings Thermal Information Temperature Under Bias . . . . . . . . . . . . . . . . . . . . -40 C to +85 C Voltage on Any Pin with Respect to GND . . . . . . . . . . . -1.0V to +7V D.C. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Thermal Resistance (Typical, Note 1) JA (C/W) MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C (MSOP - Lead Tips Only) Recommended Operating Conditions Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications SYMBOL Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MAX UNITS 5.5 V 12.5 15 A V2MON = 3.3V 5.5 6 A V3MON = 1.0V 19 100 nA VDD Supply Voltage Range IDD1 VDD Supply Current VDD = 5.0V IDD2 V2MON Input Current IDDA V3MON Input Current MIN TYP 2.0 VOLTAGE THRESHOLDS VTH1 VTH1HYST VTH2 VTH2HYST VTH3 VREFHYST Fixed Voltage Trip Point for VDD Hysteresis of VTH1 Fixed Voltage Trip Point for V2MON Hysteresis of VTH2 V3MON Threshold Voltage ISL88021/22IU8HxZ 4.565 4.649 4.733 V ISL88021/22IU8FxZ 3.029 3.085 3.141 V VTH1 = 4.64V 46 mV VTH1 = 3.09V 37 mV ISL88021/22IU8xFZ 3.034 3.090 3.146 V ISL88021/22IU8xEZ 2.894 2.947 3.000 V ISL88021/22IU8xCZ 2.290 2.332 2.374 V ISL88021/22IU8xAZ 1.660 1.690 1.720 V VTH2 = 3.09V 37 mV VTH2 = 2.92V 29 mV VTH2 = 2.32V 23 mV VTH2 = 2.19V 22 mV VTH2 = 1.69V 17 mV VTH for V3MON on ISL88021 0.594 0.605 0.616 V VTH for V3MON on ISL88022 0.587 0.595 0.603 V Hysteresis Voltage 3 mV RESET VOL VOH Reset Output Voltage Low RST Output Voltage High tRPD VTH to Reset Asserted Delay tPOR POR Timeout Delay CLOAD Load Capacitance on Reset Pins 3 VDD 3.3V, Sinking 2.5mA 0.05 0.40 V VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V VDD 3.3V, Sourcing 2.5mA VDD-0.6 VDD-0.4 V VDD < 3.3V, Sourcing 1.5mA VDD-0.6 VDD-0.4 V 10 s 200 ms 5 pF CPOR is open 140 FN8226.1 September 18, 2006 ISL88021, ISL88022 Electrical Specifications SYMBOL Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 0.8 V MANUAL RESET VMRL MR Input Voltage Low VMRH MR Input Voltage High tMR MR Minimum Pulse Width RPU Internal Pull-Up Resistor VDD-0.6 V 550 ns 20 k Functional Description Power-On-Reset (POR) The ISL88021 and ISL88022 devices incorporate such features as Power-On-Reset control, Supply Voltage Supervision, Undervoltage or Overvoltage Monitoring, and Manual Reset Assertion. Applying power to the ISL88021 and ISL88022 devices activates a POR circuit which holds the RESET pin low once VDD > 1V. This signal provides several benefits: The ISL88021 and ISL88022 devices provide common preset threshold voltages on both VDD and V2MON and for an optional resistor divider network on V3MON to provide custom voltage monitoring of voltages greater than 0.6V. An optional capacitor can be connected between the CPOR pin and GND to increase the nominal 200ms tPOR delay. Figure 7 illustrates operational functionality with a timing diagram. Voltage Monitoring During normal operation, the ISL88021 and ISL88022 monitor the voltage levels on VDD, V2MON and V3MON. The ISL88021 asserts reset if any one of these voltages fall below their respective voltage trip points and in the case of ISL88022 above the voltage trip point on the V3MON input. The reset signal effectively prevents the microprocessor from operating during a power failure, brownout or over voltage condition. This signal remains active until all monitored voltages meet all voltage threshold requirements for the reset time delay period tPOR. Note that both RESET and RESET signals are provided for design flexibility. Figure 1 illustrates the VDD, V2MON and V3MON input threshold voltages for the various available options. 4.500 Vth = 4.64V * It prevents the processor from operating prior to stabilization of the oscillator. * It ensures that the monitored device is held out of operation until internal registers are properly loaded. * It allows time for an FPGA to download its configuration prior to initialization of the circuit. When all of the monitored voltages meet their respective input voltage requirements for the specified reset timeout delay tPOR, the POR circuit simultaneously pulls the RST output low and releases the RST output to allow the system to begin operation. Adjusting tPOR On the ISL88021 and ISL88022, users can adjust the Power-On-Reset timeout delay (tPOR) to many times the nominal tPOR. Figure 2 illustrates the effect of capacitance on the CPOR pin to ground, showing changing tPOR with a graph normalized to 175ms for an open CPOR pin. The maximum recommended capacitance that should be placed on the CPOR pin is 50pF. NOTE: Care should be taken in PCB layout and capacitor placement in order to eliminate stray capacitance as much as possible, which contributes to tPOR error. 4.000 3.500 Vth = 3.09V 3.000 10 Vth = 2.92V 2.500 2.000 Vth = 2.32V 1.500 Vth = 1.69V Normalized t POR VDD, V2MON, V3MON Vth (V) 5.000 * It prevents the system microprocessor from starting to operate with insufficient voltage. 1.000 0.500 0.000 Vth = 0.60V -40 25 85 TEMPERATURE (C) FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP 8 6 4 2 0 1 5 9 13 17 21 25 29 33 37 41 45 CPOR (pF) FIGURE 2. NORMALIZED tPOR vs CPOR GRAPH 4 FN8226.1 September 18, 2006 ISL88021, ISL88022 Manual Reset The manual reset input (MR) allows the user to trigger a reset by using a push-button switch or by signaling that pin low. The MR input is an active low debounced input. By connecting a push-button directly from MR to ground, the designer adds manual system reset capability. Reset is asserted if the MR pin is pulled low to less than 100mV for 1s or longer while the push-button is closed or a reset is signaled. After MR is released, the reset outputs remain asserted for tPOR. MR input has an internal 20k pull up resistor provided. ISL88021IU8HFZ Figure 3 illustrates a typical application diagram for either IC showing both reset outputs being used along with both a manual and signalled reset configuration. The VDD and V2MON thresholds are preset whereas the V3MON is capable of UV (ISL88021) or OV (ISL88022) monitoring of a voltage greater than or less than 0.6V, respectively. TO DISPLAY 3.3V - 5V VDD TO P RST RST ISL88022IU8HFZ V2MON MR 1.8V - 3.3V ISL88021 ISL88022 RESET SIGNAL CPOR V3MON VMON > 0.6V PB GND FIGURE 3. TYPICAL APPLICATION DIAGRAM Application Considerations Follow good decoupling practices to prevent transients from causing unwanted reset signaling due to switching noises and short duration droops. When using the CPOR pin, reduce layout stray capacitance on this pin to minimize effect on tPOR timing. If no PCB CPOR pad is patterned, the tPOR can be 160ms. FIGURE 4. ISL88021_22EVAL1 SCHEMATIC AND PHOTO MONITORED VOLTAGE RISING AND FALLING RAMP THROUGH THE PROGRAMMED UV AND OV THRESHOLDS Using the ISL88021_22EVAL1 Platform The ISL88021_22EVAL1 board is designed to provide both immediate functional assessment and flexibility to the user. Both ICs are the `HF' variant having a VDD Vth of 4.64V, a V2MON Vth of 3.09V and V3MON Vth of 0.6V. The top IC position is the ISL88021 and is configured to monitor for undervoltage (UV) compliance of a 5V, 3.3V and a 2.5V and signaling the RESET and RESET outputs. The bottom position is the ISL88022 variant, which is configured to measure a 3.3V overvoltage (OV) in addition to UV on both the 5V and 3.3V supplies. RESET and RESET is asserted for at least tPOR when these voltage go out of range. In both cases V3MON interfaces with the monitored supply via a simple resistor divider for comparison to the internal 0.6V reference. A Manual Reset (MR) input is provided on both ICs and is invoked by pulling this input LOW. 5 RESET# RESPONDING TO MONITORED VOLTAGE. CPOR PIN IS OPEN, tPOR = 150ms FIGURE 5. ISL88022EVAL1 3.3V UV AND OV DETECTION FN8226.1 September 18, 2006 ISL88021, ISL88022 3.3V RISING EDGE 100ms/DIV ISL88022 tPOR = 150ms CPOR = OPEN ISL88021 tPOR = 390ms CPOR = 10pF FIGURE 6. ISL88021_22EVAL1 tPOR COMPARISON Operational Timing Diagrams VTH1 VDD 1V V2MON or V3MON (ISL88021) VTH2 or VREF >tMR MR tPOR tRPD tPOR tRPD tPOR tPOR RST RST <tMD FIGURE 7. ISL88021 AND ISL88022 TIMING DIAGRAM 6 FN8226.1 September 18, 2006 ISL88021, ISL88022 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X L1 SEATING PLANE C 0.20 (0.008) C a CL E1 C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C 0.20 (0.008) MIN A L1 -A- SIDE VIEW SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o -B- Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN8226.1 September 18, 2006