FINAL Advanced Micro Devices Am27X256 256 Kilobit (32,768 x 8-Bit) CMOS ExpressROM Device DISTINCTIVE CHARACTERISTICS As an OTP EPROM alternative: -- Factory optimized programming -- Fully tested and guaranteed As a Mask ROM alternative: -- Shorter leadtime -- Lower volume per code Fast access time -- 55 ns Single +5 V power supply Compatible with JEDEC-approved EPROM pinout 10% power supply tolerance High noise immunity Low power dissipation -- 20 A typical CMOS standby current Available in Plastic Dual In-Line Package (PDIP), Plastic Leaded Chip Carrier (PLCC), and Thin Small Outline Package (TSOP) Latch-up protected to 100 mA from -1 V to VCC +1 V Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions GENERAL DESCRIPTION The Am27X256 is a factory programmed and tested OTP EPROM. It is programmed after packaging prior to final test. Every device is rigorously tested under AC and DC operating conditions to your stable code. It is organized as 32,768 by 8 bits and is available in plastic dual in-line (PDIP), plastic leaded chip carrier (PLCC), and thin small outline (TSOP) packages. ExpressROM devices provide a board-ready memory solution for medium to high volume codes with short leadtimes. This offers manufacturers a cost-effective and flexible alternative to OTP EPROMs and mask programmed ROMs. Access times as fast as 55 ns allow operation with highperformance microprocessors with reduced WAIT states. The Am27X256 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 W in standby mode. BLOCK DIAGRAM Data Outputs DQ0-DQ7 VCC VSS OE CE A0-A14 Address Inputs Output Enable Chip Enable Output Buffers Y Decoder Y Gating X Decoder 262,144-Bit Cell Matrix 12082E-1 Publication# 12082 Rev. E Issue Date: May 1995 Amendment /0 4-27 AMD PRODUCT SELECTOR GUIDE Am27X256 Family Part No. Ordering Part No: VCC 5% -255 VCC 10% -55 -70 -90 -120 -150 -200 Max Access Time (ns) 55 70 90 120 150 200 250 CE (E) Access (ns) 55 70 90 120 150 200 250 OE (G) Access (ns) 35 40 40 50 50 50 50 CONNECTION DIAGRAMS Top View PDIP PLCC A12 2 27 A14 A7 3 26 A13 A6 5 29 A8 A6 4 25 A8 A5 6 28 A9 A5 5 24 A9 A4 A3 7 8 27 26 NC A2 9 25 OE (G) A1 10 24 A10 6 23 A11 A3 7 22 OE (G) A2 8 21 A10 A1 9 20 CE (E) A0 10 19 DQ7 2 1 32 31 30 A11 A0 11 23 CE (E) NC 12 22 DQ0 13 DQ7 DQ6 21 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 DQ4 DQ5 DQ6 DQ3 18 DU 11 VSS DQ0 14 15 16 17 18 19 20 DQ1 DQ2 A4 4 3 A14 A13 VCC VCC 28 VPP DU 1 A7 A12 VPP 12082E-2 12082E-3 Note: 1. JEDEC nomenclature is in parentheses. TSOP* OE (G) A11 A9 A8 A13 NC A14 VCC VPP NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout *Contact local AMD sales office for package availability 4-28 Am27X256 NC A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 NC A0 A1 A2 12082E-4 AMD PIN DESIGNATIONS A0-A14 CE (E) DQ0-DQ7 DU NC OE (G) = = = = = = VCC = VCC Supply Voltage VPP = Program Voltage Input VSS = Ground LOGIC SYMBOL Address Inputs Chip Enable Input Data Inputs/Outputs No External Connection (Do Not Use) No Internal Connection Output Enable Input 15 8 A0-A14 DQ0-DQ7 CE (E) OE (G) 12082E-5 Am27X256 4-29 AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of: AM27X256 -55 J C XXXXX e. CODE DESIGNATION Assigned by AMD d. TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) c. PACKAGE TYPE P = 28-Pin Plastic Dual In-Line Package (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TS 032) b. SPEED OPTION See Product Selector Guide and Valid Combinations a. DEVICE NUMBER/DESCRIPTION Am27X256 256 Kilobit (32,768 x 8-Bit) CMOS ExpressROM Device Valid Combinations AM27X256-55 AM27X256-70 AM27X256-90 AM27X256-120 AM27X256-150 AM27X256-200 AM27X256-255 4-30 JC, PC PC, JC, PI, JI, EC, EI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am27X256 AMD FUNCTIONAL DESCRIPTION Read Mode The Am27X256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC-tOE. Standby Mode The Am27X256 has a CMOS standby mode which reduces the maximum VCC current to 100 A. It is placed in CMOS-standby when CE is at VCC 0.3 V. The Am27X256 also has a TTL-standby mode which reduces the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Output OR-Tieing To accommodate multiple memory connections, a twoline control function is provided to allow for: Low memory power dissipation Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on ExpressROM device arrays, a 4.7-F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Pins CE OE VPP Outputs VIL VIL X DOUT Output Disable X VIH X Hi-Z Standby (TTL) VIH X X Hi-Z VCC 0.3 V X X Hi-Z Mode Read Standby (CMOS) Note: 1. X = Either VIH or VIL Am27X256 4-31 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature OTP Products . . . . . . . . . . . . . . . -65C to +125C Commercial (C) Devices Ambient Temperature (TA) . . . . . . . 0C to +70C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Industrial (I) Devices Ambient Temperature (TA) . . . . . -40C to +85C Voltage with Respect to VSS All pins except VCC . . . . . . . -0.6 V to VCC + 0.6 V Supply Read Voltages VCC for Am27X256-255 . . . . . . +4.75 V to +5.25 V VCC . . . . . . . . . . . . . . . . . . . . . . . -0.6 V to +7.0 V VCC for all other valid combinations . . . . . . . . . +4.50 V to +5.50 V Note: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for periods up to 20 ns. Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 4-32 Am27X256 AMD DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2 and 4) Parameter Symbol Parameter Description Test Conditions Min 2.4 VOH Output HIGH Voltage IOH = - 400 A VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage ILI Input Load Current ILO Max Unit V 0.45 V 2.0 VCC + 0.5 V -0.5 +0.8 V VIN = 0 V to +VCC 1.0 A Output Leakage Current VOUT = 0 V to +VCC 1.0 A ICC1 VCC Active Current (Note 3) CE = VIL, f = 10 MHz, IOUT = 0 mA 25 mA ICC2 VCC TTL Standby Current CE = VIH 1.0 mA ICC3 VCC CMOS Standby Current CE = VCC 0.3 V 100 A Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. Caution: the Am27X256 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 30 30 25 25 Supply Current in mA Supply Current in mA 4. Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 20 15 10 1 2 3 4 5 6 7 8 9 10 20 15 10 -75 -50 -25 0 25 50 75 100 125 150 Temperature in C Frequency in MHz Figure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25C Figure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz 12082E-6 Am27X256 12082E-7 4-33 AMD CAPACITANCE PD 028 Parameter Symbol Parameter Description Test Conditions CIN Input Capacitance COUT Output Capacitance PL 032 TS 032 Typ Max Typ Max Typ Max Unit VIN = 0 V 6 10 8 12 10 12 pF VOUT = 0 V 8 10 8 12 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25C, f = 1 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) Parameter Symbols JEDEC Standard tAVQV tACC tELQV tCE tGLQV tOE tEHQZ tGHQZ tDF (Note 2) tAXQX tOH Am27X256 Parameter Description Test Conditions Address to Output Delay CE = OE = VIL Chip Enable to Output Delay OE = VIL Output Enable to Output Delay CE = VIL -55 -70 -90 -120 -150 -200 -255 Unit Min Max - 55 - 70 - 90 - 120 - 150 - 200 - 250 ns Min Max - 55 - 70 - 90 - 120 - 150 - 200 - 250 ns Min Max - 35 - 40 - 40 - 50 - 50 - 50 - 50 ns Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float Min Max 0 25 0 25 0 25 0 30 0 30 0 30 0 30 ns Output Hold from Addresses, CE, or OE, whichever occurred first Min Max 0 - 0 - 0 - 0 - 0 - 0 - 0 - ns Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27X256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied. 4. For the -55 and -70: Output Load: 1 TTL gate and CL = 30 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0 V to 3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs For all other versions: Output Load: 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V for inputs and outputs 4-34 Am27X256 AMD SWITCHING TEST CIRCUIT 2.7 k Device Under Test +5.0 V CL Diodes = IN3064 or Equivalent 6.2 k 12082E-8 CL = 100 pF including jig capacitance (30 pF for -55 and -70) SWITCHING TEST WAVEFORM 2.4 V 2.0 V 0.8 V Test Points 2.0 V 0.8 V 0.45 V 3V 1.5 V Test Points 1.5 V 0V Input Output Input Output 12082E-9 AC Testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise and fall times are 20 ns. AC Testing: Inputs are driven at 3.0 V for a logic "1" and 0 V for a logic "0". Input pulse rise and fall times are 20 ns for -55 and -70. Am27X256 4-35 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State KS000010 SWITCHING WAVEFORMS 2.4 Addresses 0.45 2.0 0.8 2.0 0.8 Addresses Valid CE tCE OE Output High Z tACC (Note 1) tOE tOH Valid Output tDF (Note 2) High Z 12082E-10 Notes: 1. OE may be delayed up to tACC-tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first. 4-36 Am27X256