FN7045 Rev 3.00 Page 1 of 16
May 4, 2007
FN7045
Rev 3.00
May 4, 2007
EL2125
Ultra-Low Noise, Low Power, Wideband Amplifier
DATASHEET
The EL2125 is an ultra-low noise, wideband amplifier that
runs on half the supply current of competitive parts. It is
intended for use in systems such as ultrasound imaging
where a very small signal needs to be amplified by a large
amount without adding significant noise. Its low power
dissipation enables it to be packaged in the tiny SOT-23
package, which further helps systems where many input
channels create both space and power dissipation problems.
The EL2125 is stable for gains of 10 and greater and uses
traditional voltage feedback. This allows the use of reactive
elements in the feedback loop, a common requirement for
many filter topologies. It operates from ±2.5V to ±15V
supplies and is available in the 5 Ld SOT-23 and 8 Ld SOIC
packages.
The EL2125 is fabricated using Elantec’s proprietary
complementary bipolar process, and is specified for
operation from -45°C to +85°C.
Features
• Voltage noise of only 0.83nV/Hz
• Current noise of only 2.4pA/Hz
• 200µV offset voltage
• 175MHz -3dB BW for AV = 10
• Low supply current - 10mA
• SOT-23 package available
• ±2.5V to ±15V operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ultrasound input amplifiers
• Wideband instrumentation
• Communication equipment
• AGC and PLL active filters
• Wideband sensors
Pinouts
EL2125
(5 LD SOT-23)
TOP VIEW
EL2125
(8 LD SOIC)
TOP VIEW
Ordering Information
PART NUMBER
PART
MARKING
TAPE &
REEL PACKAGE
PKG.
DWG. #
EL2125CW-T7 F 7”
(3k pcs)
5 Ld SOT-23 MDP0038
EL2125CW-T7A F 7”
(250 pcs)
5 Ld SOT-23 MDP0038
EL2125CS 2125CS - 8 Ld SOIC MDP0027
EL2125CS-T7 2125CS 7” 8 Ld SOIC MDP0027
EL2125CS-T13 2125CS 13” 8 Ld SOIC MDP0027
EL2125CSZ
(See Note)
2125CSZ - 8 Ld SOIC
(Pb-free)
MDP0027
EL2125CSZ-T7
(See Note)
2125CSZ 7” 8 Ld SOIC
(Pb-free)
MDP0027
EL2125CSZ-T13
(See Note)
2125CSZ 13” 8 Ld SOIC
(Pb-free)
MDP0027
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
2
3
5
4
-+
OUT
VS-
IN+
VS+
IN-
1
2
3
4
8
7
6
5
OUT
VS-
IN+
VS+IN- -
+
NC
NC
NC
EL2125
FN7045 Rev 3.00 Page 2 of 16
May 4, 2007
Absolute Maximum Ratings (TA = +25°C) Thermal Information
VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Any Input . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V
Ambient Operating Temperature . . . . . . . . . . . . . . . .-45°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Maximum Die Junction Temperature . . . . . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulse d tests, therefore: TJ = TC = TA
Electrical Specifications VS = ±5V, TA = +25°C, RF = 180, RG = 20 RL = 500 unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
VOS Input Offset Voltage (SO8) 0.2 2 mV
Input Offset Voltage (SOT23-5) 3mV
TCVOS Offset Voltage Temperature Coefficient 1.8 µV/°C
IBInput Bias Current -30 -22 µA
IOS Input Bias Current Offset 0.4 2 µA
TCIB Input Bias Current Temperature
Coefficient
0.09 µA/°C
CIN Input Capacitance 2.2 pF
AVOL Open Loop Gain 80 87 dB
PSRR Power Supply Rejection Ratio
(Note 1)
80 97 dB
CMRR Common Mode Rejection Ratio at CMIR 80 106 dB
CMIR Common Mode Input Range -4.6 3.8 V
VOUTH Output Voltage Swing High No load, RF = 1k3.5 3.65 V
VOUTL Output Voltage Swing Low No load, RF = 1k-3.87 -3.7 V
VOUTH2 Output Voltage Swing High RL = 10033.3 V
VOUTL2 Output Voltage Swing Low RL = 100-3.5 -3 V
IOUT Output Short Circuit Current (Note 2) 80 100 mA
ISSupply Current 10.1 11 mA
AC PERFORMANCE - RG = 20, CL = 5pF
BW -3dB Bandwidth 175 MHz
BW ±0.1dB ±0.1dB Bandwidth 34 MHz
BW ±1dB ±1dB Bandwidth 150 MHz
Peaking Peaking 0.4 dB
SR Slew Rate VOUT = 2VP-P, measured at 20% to 80% 150 185 V/µs
OS Overshoot, 4VP-P Output Square Wave Positive 0.6 %
Negative 2.7 %
tSSettling Time to 0.1% of ±1V Pulse 42 ns
EL2125
FN7045 Rev 3.00 Page 3 of 16
May 4, 2007
VNVoltage Noise Spectral Density 10kHz 0.83 nV/Hz
INCurrent Noise Spectral Density 10kHz 2.4 pA/Hz
HD2 2nd Harmonic Distortion (Note 3) -74 dBc
HD3 3rd Harmonic Distortion -91 dBc
NOTES:
1. Measured by moving the supplies from ±4V to ±6V
2. Pulse test only
3. Frequency = 1MHz, VOUT = 2VP-P, into 500 and 5pF load
Electrical Specifications VS = ±5V, TA = +25°C, RF = 180, RG = 20 RL = 500 unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Electrical Specifications VS = ±15V, TA = +25°C, RF = 180, RG = 20, RL = 500 unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
VOS Input Offset Voltage (SO8) 0.6 3 mV
Input Offset Voltage (SOT23-5) 3mV
TCVOS Offset Voltage Temperature Coefficient 4.9 µV/°C
IBInput Bias Current -30 -24 µA
IOS Input Bias Current Offset 0.4 2 µA
TCIB Input Bias Current Temperature
Coefficient
0.08 µA/°C
CIN Input Capacitance 2.2 pF
AVOL Open Loop Gain 80 87 dB
PSRR Power Supply Rejection Ratio
(Note 4)
80 97 dB
CMRR Common Mode Rejection Ratio at CMIR 75 105 dB
CMIR Common Mode Input Range -14.6 13.8 V
VOUTH Output Voltage Swing High No load, RF = 1k13.35 13.5 V
VOUTL Output Voltage Swing Low No load, RF = 1k-13.6 -13 V
VOUTH2 Output Voltage Swing High RL = 10011 11.6 V
VOUTL2 Output Voltage Swing Low RL = 100-10.4 -9.8 V
IOUT Output Short Circuit Current (Note 5) 120 250 mA
ISSupply Current 10.8 12 mA
AC PERFORMANCE - RG = 20, CL = 5pF
BW -3dB Bandwidth 220 MHz
BW ±0.1dB ±0.1dB Bandwidth 23 MHz
BW ±1dB ±1dB Bandwidth 63 MHz
Peaking Peaking 2.5 dB
SR Slew Rate VOUT = 2VP-P, measured at 20% to 80% 180 225 V/µs
OS Overshoot, 4VP-P Output Square Wave 0.6 %
tSSettling Time to 0.1% of ±1V Pulse 38 ns
EL2125
FN7045 Rev 3.00 Page 4 of 16
May 4, 2007
VNVoltage Noise Spectral Density 10kHz 0.95 nV/Hz
INCurrent Noise Spectral Density 10kHz 2.1 pA/Hz
HD2 2nd Harmonic Distortion (Note 6) -73 dBc
HD3 3rd Harmonic Distortion -96 dBc
NOTES:
4. Measured by moving the supplies from ±13.5V to ±16.5V
5. Pulse test only
6. Frequency = 1MHz, VOUT = 2VP-P, into 500 and 5pF load
Electrical Specifications VS = ±15V, TA = +25°C, RF = 180, RG = 20, RL = 500 unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FIGURE 3. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
FIGURE 4. INVERTING FREQUENCY RESPONSE FOR
VARIOUS RF
5
-5
1M 10M 100M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
0
VS = ±5V
AV = 10
RL = 500
CL = 5pF
200M
RF = 1kRF = 499
RF = 180
RF = 100
5
0
-5
1M 10M 100M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS = ±15V
AV = 10
RL = 500
CL = 5pF
300M
RF = 1k
RF = 180
RF = 700
RF = 100
RF = 499
6
2
-2
-6
-10
-14
1M 10M 100M 300M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS = ±5V
AV = -10
RL = 560
CL = 5pF
RF = 1k
RF = 350
RF = 200
RF = 97.6
RF = 499
6
2
-2
-6
-10
-14
1M 10M 100M 300M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS = ±15V
AV = -10
RL = 500
CL = 5pF
RF = 1k
RF = 350
RF = 200
RF = 499
RF = 97.6
EL2125
FN7045 Rev 3.00 Page 5 of 16
May 4, 2007
FIGURE 5. NON-INVERTING FREQUENCY RESPONSE vs GAIN FIGURE 6. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS GAIN
FIGURE 7. INVERTING FREQUENCY RESPONSE vs GAIN FIGURE 8. INVERTING FREQUENCY RESPONSE vs GAIN
FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
FIGURE 10. INVERTING FREQUENCY RESPONSE FOR
VARIOUS OUTPUT SIGNAL LEVELS
Typical Performance Curves (Continued)
-5
0
5
1M 10M 100M 200M
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS = ±5V
RL = 500
CL = 5pF
RG = 20
AV = 50 AV = 20
AV = 10
-5
0
5
NORMALIZED GAIN (dB)
VS = ±15V
RL = 500
CL = 5pF
RF = 700
1M 10M 100M 200M
FREQUENCY (Hz)
AV = 50
AV = 20
AV = 10
6
NORMALIZED GAIN (dB)
2
-2
-6
-10
1M 10M 100M 300M
FREQUENCY (Hz)
-14
AV = -10
AV = -50
VS = ±5V
RL = 500
CL = 5pF
RG = 35
2
AV = -20
-14
0
6
NORMALIZED GAIN (dB)
1M 10M 100M 300M
FREQUENCY (Hz)
AV = -50
AV = -20
AV = -10
VS = ±15V
RL = 500
CL = 5pF
RG = 50
-5
5
NORMALIZED GAIN (dB)
0
1M 10M 100M 200M
FREQUENCY (Hz)
VS = ±5V
AV = 10
RF = 180
RL = 500
CL = 5pF
2VPP
4VPP
30mVPP
500mVPP
1VPP
-14
6
NORMALIZED GAIN (dB)
0
1M 10M 100M 300M
FREQUENCY (Hz)
VS = ±5V
AV = -10
RF = 350
RL = 500
CL = 5pF
2.5VPP
500mVPP
3.3VPP
250mVPP
3mVPP
1VPP
EL2125
FN7045 Rev 3.00 Page 6 of 16
May 4, 2007
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 12. NON-INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 13. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 14. INVERTING FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 15. OPEN LOOP GAIN AND PHASE FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
5
NORMALIZED GAIN (dB)
3
1
-1
-3
-5
1M 10M 100M 200M
FREQUENCY (Hz)
VS = ±5V
AV = 10
RF = 180
RL = 500
CL = 28.5pF
CL = 16pF
CL = 5pF
CL = 1pF
0
5
NORMALIZED GAIN (dB)
-5
1M 10M 100M 200M
FREQUENCY (Hz)
VS = ±5V
AV = 10
RF = 700
RL = 500
CL = 17pF
CL = 11pF
CL = 1.2pF
CL = 5pF
6
NORMALIZED GAIN (dB)
0
1M 10M 100M 300M
FREQUENCY (Hz)
-14
VS = ±5V
AV = 10
RF = 350
RL = 500
CL = 29.4pF
CL = 16.4pF
CL = 5.1pF
CL = 1.2pF
CL = 11.4pF
6
NORMALIZED GAIN (dB)
2
-2
-6
-10
-14
1M 10M 100M 300M
FREQUENCY (Hz)
VS = ±15V
AV = 10
RF = 500
RL = 500
CL = 29.4pF
CL = 16.4pF
CL = 11.4pF
CL = 5.1pF
CL = 1.2pF
OPEN LOOP GAIN (dB)
0
40
20
10K 10M
60
80
100
100K 100M
FREQUENCY (Hz)
1M
PHASE (°)
-250
-50
-150
50
150
250
400M
GAIN
PHASE
VS = ±5V
0
0
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT (mA)
4.8
12
2.4
31215
9.6
7.2
69
EL2125
FN7045 Rev 3.00 Page 7 of 16
May 4, 2007
FIGURE 17. 3dB BANDWIDTH vs SUPPLY VOLTAGE FIGURE 18. PEAKING vs SUPPLY VOLTAGE
FIGURE 19. SMALL SIGNAL STEP RESPONSE FIGURE 20. SMALL SIGNAL STEP RESPONSE
FIGURE 21. LARGE SIGNAL STEP RESPONSE FIGURE 22. LARGE SIGNAL STEP RESPONSE
Typical Performance Curves (Continued)
250
200
150
100
50
0
246810121416
VS (±V)
BANDWIDTH (MHz)
AV = 10
AV = -10
AV = 50 AV = -50AV = 20AV = -20
3
2.5
2
1.5
1
0.5
0
2 4 6 8 10 12 14 16
VS (±V)
PEAKING (dB)
AV = 10
AV = -10
AV = 50
AV = -50
AV = 20
AV = -20
10ns/DIV
20mV/DIV
VINx2
VO
VS = ±5V
RL = 500
RF = 180
AV = 10
CL = 5pF
10ns/DIV
20mV/DIV
VINx2
VO
VS = ±15V
RL = 500
RF = 180
AV = 10
CL = 5pF
TIME (20ns/DIV)
OUTPUT VOLTAGE (0.5V/DIV)
VS = ±5V
RL = 500
RF = 180
AV = 10
CL = 5pF
TIME (20ns/DIV)
OUTPUT VOLTAGE (0.5V/DIV)
VS = ±15V
RL = 500
RF = 180
AV = 10
CL = 5pF
EL2125
FN7045 Rev 3.00 Page 8 of 16
May 4, 2007
FIGURE 23. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
FIGURE 24. 1MHz HARMONIC DISTORTION vs OUTPUT
SWING
FIGURE 25. TOTAL HARMONIC DISTORTION vs FREQUENCY FIGURE 26. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 27. SETTLING TIME vs ACCURACY FIGURE 28. GROUP DELAY
Typical Performance Curves (Continued)
-40
-50
-60
-70
-90
-100
-110
067
VOUT (VPP)
DISTORTION (dBc)
45231
-80
VS = ±5V
RF = 180
AV = 10
RL = 500
2ND HD
3RD HD
-30
-40
-60
-80
-90
-100
-110
05 25
VOUT (VPP)
DISTORTION (dBc)
VS = ±15V
RF = 180
AV = 10
RL = 500
10 15 20
-50
-70
2ND HD
3RD HD
-30
-60
-80
-90
1K 10K 100M
FREQUENCY (Hz)
THD (dBc)
VS = ±5V
VO = 2VPP
AV = 10
RF = 180
RL = 500
100K 1M 10M
-40
-50
-70
100
10
1
0.1
10 100 1K 10K 100K
FREQUENCY (Hz)
VOLTAGE NOISE (nV/Hz),
CURRENT NOISE (pA/Hz)
IN, VS = ±5V
IN, VS = ±15V
VN, VS = ±5V
VN, VS = ±15V
60
50
40
30
20
10
0
0.1 1 10
ACCURACY (%)
SETTLING TIME (ns)
VS = ±15V
VO = 5VPP
VS = ±5V
VO = 5VPP
VS = ±15V
VO = 2VPP
VS = ±5V
VO = 2VPP
-6
14
1 400
FREQUENCY (MHz)
GROUP DELAY (ns)
2
10
6
-2
10 100
AV = 20
AV = 10
VS = ±15V
EL2125
FN7045 Rev 3.00 Page 9 of 16
May 4, 2007
FIGURE 29. CMRR FIGURE 30. PSRR
FIGURE 31. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
FIGURE 32. BANDWIDTH vs TEMPERATURE
FIGURE 33. SLEW RATE vs SWING FIGURE 34. SUPPLY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
-110
-10
10 100M
FREQUENCY (Hz)
CMRR (dB)
-70
-30
-50
-99
100 10M
1k 10k 100k 1M
PSRR (dB)
10
50
30
10k 10M
70
90
110
100k 100M
FREQUENCY (Hz)
1M
PSRR-
PSRR+
600M
ROUT ()
0.001
0.1
0.01
10K
1
10
100
FREQUENCY (Hz)
100M
100K 1M 10M
200
160
40
0
-40 160
TEMPERATURE (°C)
-3dB BANDWIDTH (MHz)
120
80
800 40 120
3.5
3
2.5
1.5
2
1
0.5
0
PEAKING (dB)
BANDWIDTH
PEAKING
SLEW RATE (V/µs)
100
200
150
0
250
300
350
VOUT SWING (VPP)
2051015
5VSR-
15VSR+
15VSR-
5VSR+
13
12
11
9
10
-50 0 100 15050
DIE TEMPERATURE (°C)
IS (mA)
VS = ±5V
VS = ±15V
EL2125
FN7045 Rev 3.00 Page 10 of 16
May 4, 2007
FIGURE 35. OFFSET VOLTAGE vs TEMPERATURE FIGURE 36. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 37. CMRR vs TEMPERATURE FIGURE 38. PSRR vs TEMPERATURE
FIGURE 39. SLEW RATE vs TEMPERATURE FIGURE 40. POSITIVE OUTPUT SWING vs TEMPERATURE
Typical Performance Curves (Continued)
0
-1
-2
-3
-50 0 100 15050
DIE TEMPERATURE (°C)
VS = ±5V
VS = ±15V
VOS (mV)
-50 0 100 15050
DIE TEMPERATURE (°C)
IB+ (µA)
-10
-15
-20
-25
-30
120
100
80
60
-50 0 100 15050
DIE TEMPERATURE (°C)
CMRR (dB)
VS = ±5V
VS = ±15V
110
100
90
80
-50 0 100 15050
DIE TEMPERATURE (°C)
PSRR (dB)
VS = ±5V
VS = ±15V
240
220
200
180
160
-50 0 100 15050
DIE TEMPERATURE (°C)
SR (V/µs)
VS = ±5V
VS = ±15V
VO = 2VPP
3.9
3.7
3.6
3.5
3.8
-50
DIE TEMPERATURE (°C)
VOUTH (V)
0 100 15050
VS = ±5V
EL2125
FN7045 Rev 3.00 Page 11 of 16
May 4, 2007
FIGURE 41. POSITIVE OUTPUT SWING vs TEMPERATURE FIGURE 42. NEGATIVE OUTPUT SWING vs TEMPERATURE
FIGURE 43. NEGATIVE OUTPUT SWING vs TEMPERATURE FIGURE 44. LOADED NEGATIVE OUTPUT SWING vs
TEMPERATURE
FIGURE 45. NEGATIVE OUTPUT SWING vs TEMPERATURE FIGURE 46. LOADED POSITIVE OUTPUT SWING vs
TEMPEARTURE
Typical Performance Curves (Continued)
13.6
13.5
13.4
-50
DIE TEMPERATURE (°C)
0 100 15050
VOUTH (V)
VS = ±15V
-9.75
-9.8
-9.85
-9.9
-9.95
-50
DIE TEMPERATURE (°C)
VOUTL (V)
0 10050
VS = ±5V
150
-13.4
-13.5
-13.6
-13.7
-50
DIE TEMPERATURE (°C)
VOUTL (V)
0 100 15050
VS = ±15V
-3.42
-3.44
-3.46
-3.48
-3.5
-3.52
-50
DIE TEMPERATURE (°C)
VOUTL2 (V)
0 100 15050
VS = ±5V
-9.6
-9.8
-10
-10.2
-10.4
-10.6
-10.8
-50
DIE TEMPERATURE (°C)
VOUTL2 (V)
010015050
VS = ±15V
3.35
3.3
3.25
-50
DIE TEMPERATURE (°C)
VOUTH2 (V)
010015050
VS = ±5V
EL2125
FN7045 Rev 3.00 Page 12 of 16
May 4, 2007
FIGURE 47. LOADED POSITIVE OUTPUT SWING vs
TEMPERATURE
FIGURE 48. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 49. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
12
11.8
11.6
11.4
11.2
11
-50
DIE TEMPERATURE (°C)
VOUTH2 (V)
0 100 15050
VS = ±15V
1.2
0.6
0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
25 125 15075
1
0.4
0.8
0.2
10050 85
488mW
781mW
SO8
JA=160°C/W
SOT23-5
JA=256°C/W
1.8
0.8
0
1.6
0.4
1.2
0.2
0.6
1.4
1
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
25 125 15075 10050 85
543mW
1.136W
SO8
JA=110°C/W
SOT23-5
JA=230°C/W
EL2125
FN7045 Rev 3.00 Page 13 of 16
May 4, 2007
Applications Information
Product Descr iption
The EL2125 is an ultra-low noise, wideband monolithic
operational amplifier built on Elantec's proprietary high
speed complementary bipolar process. It features
0.83nV/Hz input voltage noise, 200µV offset voltage, and
73dB THD. It is intended for use in systems such as
ultrasound imaging where very small signals are needed to
be amplified. The EL2125 also has excellent DC
specifications: 200µV VOS, 22µA IB, 0.4µA IOS, and 106dB
CMRR. These specifications allow the EL2125 to be used in
DC-sensitive applications such as difference amplifiers.
Gain-Bandwidth Product
The EL2125 has a gain-bandwidth product of 800MHz at
±5V. For gains greater than 20, its closed-loop -3dB
bandwidth is approximately equal to the gain-bandwidth
product divided by the small signal gain of the circuit. For
gains less than 20, higher-order poles in the amplifier's
transfer function contribute to even higher closed-loop
bandwidths. For example, the EL2125 has a -3dB bandwidth
of 175MHz at a gain of 10 and decreases to 40MHz at gain
of 20. It is important to note that the extra bandwidth at lower
gain does not come at the expenses of stability. Even though
the EL2125 is designed for gain > 10 with external
compensation, the device can also operate at lower gain
settings. The RC network shown in Figure 50 reduces the
feedback gain at high frequency and thus maintains the
amplifier stability. R values must be less than RF divided by
9 and 1 divided by 2RC must be less than 400MHz.
FIGURE 50.
Choice of Feedback Resistor, RF
The feedback resistor forms a pole with the input
capacitance. As this pole becomes larger, phase margin is
reduced. This increases ringing in the time domain and
peaking in the frequency domain. Therefore, RF has some
maximum value which should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few pF range in parallel with RF can help to
reduce this ringing and peaking at the expense of reducing
the bandwidth. Frequency response curves for various RF
values are shown the in typical performance curves section
of this data sheet.
Pin Descriptions
5 LD SOT-23 8 LD SO PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT
16VOUTOutput
CIRCUIT 1
2 4 VS- Supply
3 3 VINA+ Input
CIRCUIT 2
4 2 VINA- Input Reference Circuit 2
5 7 VS+ Supply
VOUT
VS+
VIN-VIN+
VS+
VS-
-
+
RF
R
C
VIN
VOUT
EL2125
FN7045 Rev 3.00 Page 14 of 16
May 4, 2007
Noise Calculations
The primary application for the EL2125 is to amplify very
small signals. To maintain the proper signal-to-noise ratio, it
is essential to minimize noise contribution from the amplifier.
Figure 51 below shows all the noise sources for all the
components around the amplifier.
FIGURE 51.
•V
N is the amplifier input voltage noise
•I
N+ is the amplifier positive input current noise
•I
N- is the amplifier negative input current noise
•V
RX is the thermal noise associated with each resistor:
where:
• k is Boltzmann's constant = 1.380658 x 10-23
• T is temperature in degrees Kelvin (273+ °C)
The total noise due to the amplifier seen at the output of the
amplifier can be calculated by using the equation below
(Figure 52).
As the equation shows, to keep noise at a minimum, small
resistor values should be used. At higher amplifier gain
configuration where R2 is reduced, the noise due to IN-, R2,
and R1 decreases and the noise caused by IN+, VN, and R3
starts to dominate. Because noise is summed in a root-mean-
squares method, noise sources smaller than 25% of the largest
noise source can be ignored. This can greatly simplify the
formula and make noise calculation much easier to calculate.
Output Drive Capability
The EL2125 is designed to drive low impedance load. It can
easily drive 6VP-P signal into a 100 load. This high output
drive capability makes the EL2125 an ideal choice for RF, IF,
and video applications. Furthermore, the EL2125 is current-
limited at the output, allowing it to withstand momentary short to
ground. However, the power dissipation with output-shorted
cannot exceed the power dissipation capability of the package.
Driving Cables and Capacitive Loads
Although the EL2125 is designed to drive low impedance
load, capacitive loads will decrease the amplifier's phase
margin. As shown the in the performance curves, capacitive
load can result in peaking, overshoot and possible
oscillation. For optimum AC performance, capacitive loads
should be reduced as much as possible or isolated with a
series resistor between 5 to 20. When driving coaxial
cables, double termination is always recommended for
reflection-free performance. When properly terminated, the
capacitance of the coaxial cable will not add to the capacitive
load seen by the amplifier.
Power Supply Bypassing And Printed Circuit
Board Layout
As with any high frequency devices, good printed circuit
board layout is essential for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be kept as short as possible. The power supply pins
must be closely bypassed to reduce the risk of oscillation.
The combination of a 4.7µF tantalum capacitor in parallel
with 0.1µF ceramic capacitor has been proven to work well
when placed at each supply pin. For single supply operation,
where pin 4 (VS-) is connected to the ground plane, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor across pins 7 (VS+) and pin 4 (VS-) will suffice.
For good AC performance, parasitic capacitance should be
kept to a minimum. Ground plane construction again should
be used. Small chip resistors are recommended to minimize
series inductance. Use of sockets should be avoided since
they add parasitic inductance and capacitance which will
result in additional peaking and overshoot.
Supply Voltage Range and Single Supply
Operation
The EL2125 has been designed to operate with supply
voltage range of ±2.5V to ±15V. With a single supply, the
EL2125 will operate from +5V to +30V. Pins 4 and 7 are the
power supply pins. The positive power supply is connected
to pin 7. When used in single supply mode, pin 4 is
connected to ground. When used in dual supply mode, the
negative power supply is connected to pin 4.
As the power supply voltage decreases from +30V to +5V, it
becomes necessary to pay special attention to the input
voltage range. The EL2125 has an input voltage range of
0.4V from the negative supply to 1.2V from the positive
supply. So, for example, on a single +5V supply, the EL2125
has an input voltage range which spans from 0.4V to 3.8V.
The output range of the EL2125 is also quite large, on a +5V
supply, it swings from 0.4V to 3.6V.
-
+VON
VIN
IN+
IN-
R2
R3
R1
VN
VR3
VR2
VR1
VRX 4kTRx=
VON BW=VN21R1
R2
-------+
2
IN-2R1
2IN+2R3
21R1
R2
-------+
2
+4KTR
14KTR
2
R1
R2
-------
2
+ 4KTR
31R1
R2
-------+
2
++ +
FIGURE 52.
EL2125
FN7045 Rev 3.00 Page 15 of 16
May 4, 2007
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X
4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7045 Rev 3.00 Page 16 of 16
May 4, 2007
EL2125
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2003-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
SOT-23 Package Family
e1
N
A
D
E
4
321
E1
0.15 DC
2X 0.20 C
2X
e
B0.20 MDC A-B
b
NX
6
2 3
5
SEATING
PLANE
0.10 C
NX
1 3
C
D
0.15 A-BC
2X
A2
A1
H
c
(L1)
L
0.25
0° +3°
-0°
GAUGE
PLANE
A
MDP0038
SOT-23 PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCESOT23-5 SOT23-6
A 1.45 1.45 MAX
A1 0.10 0.10 ±0.05
A2 1.14 1.14 ±0.15
b 0.40 0.40 ±0.05
c 0.14 0.14 ±0.06
D 2.90 2.90 Basic
E 2.80 2.80 Basic
E1 1.60 1.60 Basic
e 0.95 0.95 Basic
e1 1.90 1.90 Basic
L 0.45 0.45 ±0.10
L1 0.60 0.60 Reference
N 5 6 Reference
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
