SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 * * * * * * * * * SN54ABT16373 . . . WD PACKAGE SN74ABT16373 . . . DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (- 32-mA IOH, 64-mA IOL) Packaged in Plastic 300-mil Shrink Small-Outline Packages and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE description The 4ABT16373 is a 16-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components The output enable (OE) does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16373 is available in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT16373 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ABT16373 is characterized for operation from - 40C to 85C. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated. Copyright 1992, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 1 SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 48 24 25 47 logic diagram (positive logic) 1OE 1EN C3 1LE C1 C4 3D 1D1 2 1 3 44 5 43 6 41 8 40 9 38 11 37 12 35 33 48 2EN 46 36 1 4D 13 2 14 16 32 17 30 19 29 20 27 22 26 23 47 1Q1 1Q1 1Q2 1Q3 1Q4 To Seven Other Channels 1Q5 1Q6 1Q7 2OE 1Q8 2LE 2Q1 24 25 2Q2 C1 2Q3 2D1 36 1D 2Q4 2Q5 2Q6 2Q7 To Seven Other Channels 2Q8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 2 1D * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 13 2Q1 SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions (see Note 2) SN54ABT16373 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC - 24 Low-level output current 48 t / v Input transition rise or fall rate High-level input voltage SN74ABT16373 MIN 2 2 0.8 Input voltage 0 Outputs enabled TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low. 10 - 55 125 - 40 V V 0.8 0 UNIT V VCC - 32 mA V 64 mA 10 ns / V 85 C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 3 SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IOZH IOZL Ioff ICEX IO ICC TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = -18 mA IOH = - 3 mA VCC = 5 V, VCC = 4.5 V, IOH = - 3 mA IOH = - 24 mA VCC = 4.5 V, VCC = 4.5 V, IOH = - 32 mA IOL = 48 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 64 mA VI = VCC or GND VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V VCC = 0, VCC = 5.5 V, VI or VO 4.5 V VO = 5.5 V Outputs high VCC = 5.5 V, VO = 2.5 V TA = 25C TYP MAX SN54ABT16373 MIN -1.2 VCC = 5.5 5 5 V, V IO = 0, 0 VI = VCC or GND MIN MAX SN74ABT16373 MIN -1.2 -1.2 2.5 2.5 2.5 3 3 3 2 2 2 0.55 0.55 1 1 1 A 50 50 A - 50 - 50 - 50 A 100 A 100 50 -100 -180 50 - 50 -180 - 50 50 A -180 mA 2 2 Outputs low 85 85 85 2 2 2 15 1.5 15 1.5 15 1.5 Outputs disabled Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V V 50 2 VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND V V Outputs high ICC UNIT 2 0.55 0.55 - 50 MAX 3.5 mA mA pF Co 9.5 All typical values are at VCC = 5 V. On products compliant to MIL-STD-883, Class B, this parameter does not apply. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25C MIN MAX SN54ABT16373 MIN MAX SN74ABT16373 MIN UNIT MAX tw tsu Pulse duration, LE high 3.3 3.3 3.3 ns Setup time, data before LE 1.5 1.5 1.5 ns th Hold time, data after LE 1 1 1 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q PARAMETER VCC = 5 V, TA = 25C SN54ABT16373 SN74ABT16373 MIN TYP MAX MIN MAX MIN MAX 1.9 4.1 5.3 1.9 6.5 1.9 6.3 2.3 4.3 5.4 2.3 6.5 2.3 6.2 2.1 4.5 5.7 2.1 7 2.1 6.7 2.6 4.5 5.6 2.6 6.3 2.6 6.1 1.5 3.9 5 1.5 6.4 1.5 6.1 1.8 3.8 4.9 1.8 5.8 1.8 5.6 2.4 6.5 8.8 2.4 10.8 2.4 10.3 2.3 5.3 7.6 2.3 8.7 2.3 8.1 UNIT ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 5 SN54ABT16373, SN74ABT16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992 PARAMETER MEASUREMENT INFORMATION 7V S1 500 From Output Under Test Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 1.5 V 3V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 0V tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 7 V (see Note C) tPLH tPHL 1.5 V 1.5 V tPZL VOH Output 3V Output Control 1.5 V tPLH 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input (see Note B) th Output Waveform 2 S1 at Open (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 * * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. 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