SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
Copyright 1992, Texas Instruments Incorporated
1
•Members of the Texas Instruments
Widebus
Family
•State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
•ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
•Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
•Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
•Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
•Flow-Through Architecture Optimizes
PCB Layout
•High-Drive Outputs (–32-mA IOH,
64-mA IOL)
•Packaged in Plastic 300-mil Shrink
Small-Outline Packages and 380-mil
Fine-Pitch Ceramic Flat Packages Using
25-mil Center-to-Center Spacings
description
The 4ABT16373 is a 16-bit transparent D-type
latch with 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low , the Q outputs are latched at the levels set up at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components
The output enable (OE) does not affect internal operations of the latch. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT16373 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16373 is characterized for operation from –40°C to 85°C.
SN54ABT16373 ...WD PACKAGE
SN74ABT16373 ... DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
2
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
HXX Z
logic symbol†logic diagram (positive logic)
1OE
2OE
48
47
1OE 1
1LE
1D1
To Seven Other Channels
21Q1
C1
1D
25
36
2OE 24
2LE
2D1 13 2Q1
C1
1D
To Seven Other Channels
1EN
1
C3
48
1LE
3D
47
1D1 46
1D2 44
1D3 43
1D4
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1
41
1D5 40
1D6 38
1D7 37
1D8
1Q5
8
1Q6
9
1Q7
11
1Q8
12
4D
36
2D1 35
2D2 33
2D3 32
2D4
2Q1
13
2Q2
14
2Q3
16
2Q4
17
30
2D5 29
2D6 27
2D7 26
2D8
2Q5
19
2Q6
20
2Q7
22
2Q8
23
2
2EN
24
C4
25
2LE
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16373 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16373 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) 0.85 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
SN54ABT16373 SN74ABT16373
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 2: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
4
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT16373 SN74ABT16373
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
V
VCC = 4.5 V, IOH = – 3 mA 2.5 2.5 2.5
V
VOH
VCC = 5 V, IOH = –
ā
3 mA 3 3 3
V
V
OH VCC = 4.5 V, IOH = –24 mA 2 2
V
VCC = 4.5 V, IOH = – 32 mA 2‡2
VOL
VCC = 4.5 V, IOL = 48 mA 0.55 0.55
V
V
OL VCC = 4.5 V, IOL = 64 mA 0.55‡0.55
V
IIVCC = 5.5 V, VI = VCC or GND ±1±1±1µA
IOZH VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
IOZL VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
V55VI0
Outputs high 2 2 2
ICC VCC = 5.5 V, IO = 0,
VI=V
CC or GND
Outputs low 85 85 85 mA
V
I =
V
CC
or
GND
Outputs disabled 2 2 2
∆ICC
VCC = 5.5 V, One input at 3.4 V,
15
15
15
mA
∆I
CC
VCC 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
1
.
5
1
.
5
1
.
5
m
A
CiVI = 2.5 V or 0.5 V 3.5 pF
CoVO = 2.5 V or 0.5 V 9.5 pF
†All typical values are at VCC = 5 V.
‡On products compliant to MIL-STD-883, Class B, this parameter does not apply.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°CSN54ABT16373 SN74ABT16373 UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE high 3.3 3.3 3.3 ns
tsu Setup time, data before LE↓1.5 1.5 1.5 ns
thHold time, data after LE↓1 1 1 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CSN54ABT16373 SN74ABT16373 UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
D
Q
1.9 4.1 5.3 1.9 6.5 1.9 6.3
ns
tPHL
D
Q
2.3 4.3 5.4 2.3 6.5 2.3 6.2 ns
tPLH
LE
Q
2.1 4.5 5.7 2.1 7 2.1 6.7
ns
tPHL
LE
Q
2.6 4.5 5.6 2.6 6.3 2.6 6.1 ns
tPZH
OE
Q
1.5 3.9 5 1.5 6.4 1.5 6.1
ns
tPZL
O
E
Q
1.8 3.8 4.9 1.8 5.8 1.8 5.6 ns
tPHZ
OE
Q
2.4 6.5 8.8 2.4 10.8 2.4 10.3
ns
tPLZ
OE
Q
2.3 5.3 7.6 2.3 8.7 2.3 8.1 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT16373, SN74ABT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS469 - FEBRUARY 1991 - REVISED OCTOBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
6
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
tw
Input
(see Note A)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
(see Note B)
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note C)
Output
W aveform 2
S1 at Open
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
[
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1996, Texas Instruments Incorporated