STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
0.1 mF
CLRL
IN1:2.8 5.5-V
IN2:2.8 5.5-V
RILIM
SwitchStatus
R1
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
AUTOSWITCHING POWER MUX
Check for Samples: TPS2114A,TPS2115A
1FEATURES APPLICATIONS
2• Two-Input, One-Output Power Multiplexer with • PCs
Low rDS(on) Switches: • PDAs
– 120 mΩTyp (TPS2114A) • Digital Cameras
– 84 mΩTyp (TPS2115A) • Modems
• Reverse and Cross-Conduction Blocking • Cell Phones
• Wide Operating Voltage Range: 2.8 V to 5.5 V • Digital Radios
• Low Standby Current: 0.5-μA Typ • MP3 Players
• Low Operating Current: 55-μA Typ
• Adjustable Current Limit DESCRIPTION
The TPS211xA family of power multiplexers enables
• Controlled Output Voltage Transition Times seamless transition between two power supplies
Limit Inrush Current and Minimize Output (such as a battery and a wall adapter), each
Voltage Hold-Up Capacitance operating at 2.8 V to 5.5 V and delivering up to 2 A,
• CMOS- and TTL-Compatible Control Inputs depending on package. The TPS211xA family
• Manual and Auto-Switching Operating Modes includes extensive protection circuitry, including user-
programmable current limiting, thermal protection,
• Thermal Shutdown inrush current control, seamless supply transition,
• Available in TSSOP-8 and 3-mm × 3-mm SON-8 cross-conduction blocking, and reverse-conduction
Packages blocking. These features greatly simplify designing
power multiplexer applications.
TYPICAL APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION(1)
TAPACKAGE IOUT ORDERING NUMBER MARKING
0.75 TPS2114APW 2114A
TSSOP-8 (PW)
–40°C to 85°C 1.25 TPS2115APW 2115A
SON-8 (DRB) 2 TPS2115ADRB CGF
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over recommended junction temperature range (unless otherwise noted). VALUE
MIN MAX UNIT
IN1, IN2, D0, D1, ILIM(2) –0.3 6 V
Voltage VO(OUT), VO(STAT)(2) –0.3 6 V
Output sink, IO(STAT) 5 mA
Continuous output, IO(TPS2114APW) 0.9 A
Current Continuous output, IO(TPS2115APW) 1.5 A
Continuous output, IO(TPS2115ADRB), 2.5 A
TJ≤105°C
Power dissipation Continuous total See Power Dissipation Ratings table
Temperature Operating virtual junction, TJ–40 125 °C
Human body model, HBM 2 kV
ESD ratings Charge device model, CDM 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
AVAILABLE OPTIONS
FEATURE TPS2114A TPS2115A
Current limit adjustment range 0.31 A to 0.75 A 0.63 A to 2 A
Manual Yes Yes
Switching modes Automatic Yes Yes
Switch status output Yes Yes
TSSOP-8
Package TSSOP-8 SON-8
2Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
PACKAGE DISSIPATION RATINGS
DERATING FACTOR TA≤25°C POWER TA= 70°C POWER TA= 85°C POWER
PACKAGE ABOVE TA= 25°C RATING RATING RATING
TSSOP-8 (PW) 3.9 mW/°C 387 mW 213 mW 155 mW
SON-8 (DRB) 25.0 mW/°C 2.50 W 1.38 W 1.0 W
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VI(IN2) ≥2.8 V 1.5 5.5 V
Input voltage at IN1, VI(IN1) VI(IN2) < 2.8 V 2.8 5.5 V
VI(IN1) ≥2.8 V 1.5 5.5 V
Input voltage at IN2, VI(IN2) VI(IN1) < 2.8 V 2.8 5.5 V
Input voltage, VI(DO), VI(D1) 0 5.5 V
TPS2114APW 0.31 0.75 A
Nominal current limit adjustment range, TPS2115APW 0.63 1.25 A
IO(OUT)(1) TPS2115ADRB, TJ≤105°C 0.63 2 A
Operating virtual junction temperature, TJ–40 125 °C
(1) Minimum recommended current is based on accuracy considerations.
ELECTRICAL CHARACTERISTICS: POWER SWITCH
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A TPS2115A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
TJ= 25°C, IL= 500 mA, VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110 mΩ
TJ= 25°C, IL= 500 mA, VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 mΩ
TJ= 25°C, IL= 500 mA, VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110 mΩ
Drain-source on-state
rDS(on)(1) resistance (INx−OUT) TJ= 125°C, IL= 500 mA, VI(IN1) = VI(IN2) = 5.0 V 220 150 mΩ
TJ= 125°C, IL= 500 mA, VI(IN1) = VI(IN2) = 3.3 V 220 150 mΩ
TJ= 125°C, IL= 500 mA, VI(IN1) = VI(IN2) = 2.8 V 220 150 mΩ
(1) The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
Copyright © 2004–2012, Texas Instruments Incorporated 3
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: GENERAL
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS (D0 AND D1)
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.7 V
D0 or D1 = high, sink current 1 µA
Input current at D0 or D1 D0 or D1 = low, source current 0.5 1.4 5 μA
SUPPLY AND LEAKAGE CURRENTS
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, 55 90 μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, 1 12 μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
Supply current from IN1
(operating) D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, 75 μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, 1μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 5.5 V, 1μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
D1 = high, D0 = low (IN1 active), VI(IN1) = 3.3 V, 75 μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
Supply current from IN2
(operating) D0 = D1 = low (IN2 active), VI(IN1) = 5.5 V, 1 12 μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
D0 = D1 = low (IN2 active), VI(IN1) = 3.3 V, 55 90 μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = high (inactive), VI(IN1) = 5.5 V, 0.5 2 μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
Quiescent current from IN1
(STANDBY) D0 = D1 = high (inactive), VI(IN1) = 3.3 V, 1μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
D0 = D1 = high (inactive), VI(IN1) = 5.5 V, 1μA
VI(IN2) = 3.3 V, IO(OUT) = 0 A
Quiescent current from IN2
(STANDBY) D0 = D1 = high (inactive), VI(IN1) = 3.3 V, 0.5 2 μA
VI(IN2) = 5.5 V, IO(OUT) = 0 A
Forward leakage current from IN1 D0 = D1 = high (inactive), VI(IN1) = 5.5 V, IN2 open, 0.1 5 μA
(measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ= 25°C
Forward leakage current from IN2 D0 = D1= high (inactive), VI(IN2) = 5.5 V, IN1 open, VO(OUT) 0.1 5 μA
(measured from OUT to GND) = 0 V (shorted), TJ= 25°C
Reverse leakage current to INx D0 = D1 = high (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, 0.3 5 μA
(measured from INx to GND) TJ= 25°C
CURRENT LIMIT CIRCUIT
RILIM = 400 Ω0.51 0.63 0.80 A
Current limit accuracy, TPS2114A RILIM = 700 Ω0.30 0.36 0.50 A
RILIM = 400 Ω0.95 1.25 1.56 A
Current limit accuracy, TPS2115A RILIM = 700 Ω0.47 0.71 0.99 A
Time for short-circuit output current to settle within 10% of
tdCurrent limit settling time 1 ms
its steady state value.
Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 0 μA
UVLO
Falling edge 1.15 1.25 V
IN1 and IN2 UVLO Rising edge 1.30 1.35 V
IN1 and IN2 UVLO hysteresis 30 57 65 mV
Falling edge 2.4 2.53 V
Internal VDD UVLO (the higher of
IN1 and IN2) Rising edge 2.58 2.8 V
Internal VDD UVLO hysteresis 30 50 75 mV
UVLO deglitch for IN1, IN2 Falling edge 110 μs
4Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REVERSE CONDUCTION BLOCKING
D0 = D1 = high, VI(INx) = 3.3 V
Minimum input-to-output voltage Connect OUT to a 5-V supply through a series 1-kΩ
ΔVO(I_block) 80 100 120 mV
difference to block switching resistor. Let D0 = low. Slowly decrease the supply voltage
until OUT connects to IN1.
THERMAL SHUTDOWN
Thermal shutdown threshold TPS211xA is in current limit 135 °C
Recovery from thermal shutdown TPS211xA is in current limit 125 °C
Hysteresis 10 °C
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator 0.1 0.2 V
Deglitch of IN2−IN1 comparator 10 20 50 μs
(both ↑↓)
STAT OUTPUT
Leakage current VO(STAT) = 5.5 V 0.01 1 μA
Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 V
Deglitch time (falling edge only) 150 μs
SWITCHING CHARACTERISTICS
Over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2114A TPS2115A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
POWER SWITCH
Output rise time from VI(IN1) = VI(IN2) = 5 V, TJ= 25°C, CL= 1 μF, IL= 500 mA
tr0.5 1.0 1.5 1 1.8 3 ms
an enable (see Figure 1a)
Output fall time from a VI(IN1) = VI(IN2) = 5 V, TJ= 25°C, CL= 1 μF, IL= 500 mA
tf0.35 0.5 0.7 0.5 1 2 ms
disable (see Figure 1a)
IN1 to IN2 transition, VI(IN1) = 3.3 V, VI(IN2) = 5 V,
TJ= 125°C, CL= 10 μF, IL= 500 mA 40 60 40 60 μs
Measure transition time as 10−90% rise time or from
3.4 V to 4.8 V on VO(OUT) (see Figure 1b).
ttTransition time IN2 to IN1 transition, VI(IN1) = 5 V, VI(IN2) = 3.3 V,
TJ= 125°C, CL= 10 μF, IL= 500 mA 40 60 40 60 μs
Measure transition time as 10−90% rise time or from
3.4 V to 4.8 V on VO(OUT) (see Figure 1b).
VI(IN1) = VI(IN2) = 5 V, measured from enable to 10% of
Turn-on propagation
tPLH1 VO(OUT), TJ= 25°C, CL= 10 μF, IL= 500 mA 0.5 1 ms
delay from enable (see Figure 1a)
VI(IN1) = VI(IN2) = 5 V, measured from disable to 90% of
Turn-off propagation
tPHL1 VO(OUT), TJ= 25°C, CL= 10 μF, IL= 500 mA 3 5 ms
delay from a disable (see Figure 1a)
Logic 1 to Logic 0 transition on D1, VI(IN1) = 1.5 V,
Switch-over rising VI(IN2) = 5 V, VI(D0) = 0 V, measured from D1 to 10% of
tPLH2 40 100 40 100 μs
propagation delay VO(OUT), TJ= 25°C, CL= 10 μF, IL= 500 mA
(see Figure 1c)
Logic 0 to Logic 1 transition on D1, VI(IN1) = 1.5V,
Switch-over falling VI(IN2) = 5V, VI(D0) = 0 V, measured from D1 to 90% of
tPHL2 2 3 10 2 5 10 ms
propagation delay VO(OUT), TJ= 25°C, CL= 10 μF, IL= 500 mA
(see Figure 1c)
Copyright © 2004–2012, Texas Instruments Incorporated 5
IN1
OUT
IN2
GND
8
7
6
5
STAT
D0
D1
ILIM
1
2
3
4
GND
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
Table 1. Truth Table
D1 D0 VI(IN2) > VI(IN1) STAT OUT(1)
0 0 X(2) Hi-Z IN2
0 1 No 0 IN1
0 1 Yes Hi-Z IN2
1 0 X 0 IN1
1 1 X 0 Hi-Z
(1) The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal VDD UVLO.
(2) X = Don’t care.
PIN CONFIGURATIONS
PW PACKAGE DRB PACKAGE
TSSOP-8 3mm × 3mm SON-8
(TOP VIEW) (TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
D0 2 I functionality of D0 and D1.
TTL- and CMOS-compatible input pins. Each pin has a 1-μA pull-up. Table 1 illustrates the
D1 3 I functionality of D0 and D1.
GND 5 I Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
IN1 8 I the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
IN2 6 I above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
A resistor RILIM from ILIM to GND sets the current limit ILto 250/RILIM and 500/RILIM for the
ILIM 4 I TPS2114A and TPS2115A, respectively.
OUT 7 O Power switch output
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1
STAT 1 O switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0).
PAD — I Tie to GND. Connect to internal planes for improved heatsinking with multiple vias.
6Copyright © 2004–2012, Texas Instruments Incorporated
Q2isON
1STAT
Control
Logic
D1
D0
UVLO(IN1)
UVLO(IN2)
UVLO(VDD)
Q2isON Q1isON
_
+
_
++
0.6 V
EN2 EN1
Cross-Conduction
Detector
_
+
Q2
Q1
Charge
Pump
0.5 V
TPS2114A:k=0.2%
TPS2115A:k=0.1%
k* IO(OUT)
_
+
VO(OUT) > VI(INx) +
100mV
_
+
IO(OUT)
Vf=0 V
EN1
IN2
IN1
7
4
OUT
ILIM
Internal VDD
Vf=0 V
VDD
ULVO
Thermal
Sense
1mA
IN2
ULVO
1mA
IN1
ULVO
8
6
2
3
5
IN1
IN2
D0
D1
GND
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2004–2012, Texas Instruments Incorporated 7
0 V 10%
90%
SwitchEnabled
SwitchOff SwitchOff
90%
10%
3.3 V
5 V
Switch#1Enabled Switch#2Enabled
4.8 V
3.4 V
DO D-1
1.5 V 1.85 V
4.65 V
Switch#1Enabled Switch#1EnabledSwitch#2Enabled
5 V
trtf
tPLH1 tPHL1
VO(OUT)
tt
VO(OUT)
VO(OUT)
DO D-1
tPLH2 tPHL2
(a)
(b)
(c)
DO D-1
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Propagation Delays and Transition Timing Waveforms
8Copyright © 2004–2012, Texas Instruments Incorporated
VI(DO)
VI(D1)
VO(OUT)
t Time- - 1ms/div
2V/Div
2V/Div
2V/Div
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
0.1 mF
50 W
5 V
3.3 V
400 W
f=28Hz
78%DutyCycle
Output Switchover Response Test Circuit
OUTPUT SWITCHOVER RESPONSE
NC
1
mF
t-Time -2ms/div
VI(DO)
VI(D1)
VO(OUT)
2V/Div
2V/Div
2V/Div
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
0.1 mF
50 W
5 V
3.3 V
400 W
f=28Hz
78%DutyCycle
1
mF
OUTPUT TURN-ON RESPONSE
Output Turn-On Response Test Circuit
NC
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS
space
Figure 2.
Figure 3.
Copyright © 2004–2012, Texas Instruments Incorporated 9
t-Time -40 ms/div
VI(DO)
VI(D1)
VO(OUT)
2V/Div
2V/Div
2V/Div
Output Switchover Voltage Droop Test Circuit
OUTPUT SWITCHOVER VOLTAGE DROOP
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
0.1 mF
50 W
400 W
f=580Hz
90%DutyCycle
5 V
NC
CL
CL=1 mF
CL=0 mF
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
Figure 4.
10 Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space
Figure 5.
Copyright © 2004–2012, Texas Instruments Incorporated 11
VI(IN1)
VO(OUT)
2V/Div
2V/Div
Auto Switchover Voltage Droop Test Circuit
t-Time 250- ms/div
AUTO SWITCHOVER VOLTAGE DROOP
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115A 0.1 mF
0.1 Fm
50 W
5V
1kW
400W
3.3V 10 mF
VOUT
f=220Hz
20%DutyCycle
STAT
75% lessoutputvoltage
droopcomparedtoTPS2115
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
Figure 6.
12 Copyright © 2004–2012, Texas Instruments Incorporated
0
50
100
150
200
250
300
0 20 40 60 80 100
VI=5 V
VI=3.3 V
InrushCurrent mA-
CLLoadCapacitance- -µF
INRUSH CURRENT
vs
LOAD CAPACITANCE
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW
0.1 mF
0.1 mF
VI
400 W
0.1 mF 47 mF10 mF
50 W
To Oscilloscope
1mF100 mF
f=28Hz
90%DutyCycle
Output Capacitor Inrush Current Test Circuit
II-
NC
NC
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space
Figure 7.
Copyright © 2004–2012, Texas Instruments Incorporated 13
-50 0 50 100 150
TJ-JunctionTemperature - °C
60
80
100
120
140
160
180
TPS2114A
TPS2115A
- -SwitchOn-Resistance mW
rDS(on)
2 3 6
VI(INx) -SupplyVoltage -V
80
85
90
95
100
105
110
115
120
TPS2114A
TPS2115A
- -SwitchOn-Resistance mW
rDS(on)
4 5
40
42
44
46
48
50
52
54
56
58
60
2 3 6
VI(IN1) SupplyV-oltage V-
I(IN1) - mIN1SupplyCurrent -A
IN1SwitchisON
VI(IN2) =0 V
IO(OUT) =0 A
I
4 5
0.82
0.84
0.86
0.88
0.90
0.92
0.94
0.96
2 6
I(IN1) Am
VI(IN1) - -IN1SupplyVoltage V
DeviceDisabled
VI(IN2) =0 V
IO(OUT) =0 A
I-IN1SupplyCurrent-
3 4 5
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
space
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE
vs vs
JUNCTION TEMPERATURE SUPPLY VOLTAGE
Figure 8. Figure 9.
IN1 SUPPLY CURRENT IN1 SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11.
14 Copyright © 2004–2012, Texas Instruments Incorporated
0
10
20
30
40
50
60
70
80
-50 0 50 100 150
II(IN1)
II(IN2)
TJ-JunctionTemperature C- °
IN1SwitchisON
VI(IN1) =5.5 V
VI(IN2) =3.3 V
IO(OUT) =0 A
I(INx) SupplyCurrent -- mA
I
0
0.2
0.4
0.6
0.8
1
1.2
-50 0 50 100 150
II(IN1) =5.5 V
II(IN2) = 3.3 V
TJ-JunctionTemperature C- °
I(INx) - - mSupplyCurrent A
VI(IN2) =3.3 V
IO(OUT) =0 A
I
VI(IN1) =5.5 V
DeviceDisabled
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
space SUPPLY CURRENT SUPPLY CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 12. Figure 13.
Copyright © 2004–2012, Texas Instruments Incorporated 15
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
C2
0.1 mF
CLRL
IN1:2.8 5.5-V
IN2:2.8 5.5-V
RILIM
NC
SwitchStatus
R1
STAT
D0
D1
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2115APW 0.1 mF
0.1 mF
CLRL
IN1:2.8 5.5-V
IN2:2.8 5.5-V
RILIM
SwitchStatus
R1
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS2114A/5A will select the higher of the two supplies. This usually
means that the TPS2114A/5A will swap to IN2.
Figure 14. Auto-Selecting for a Dual Power Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
Figure 15. Manually Switching Power Sources
16 Copyright © 2004–2012, Texas Instruments Incorporated
TPS2114A
TPS2115A
www.ti.com
SBVS044F –MARCH 2004–REVISED MAY 2012
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-
input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the
output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2114A and
TPS2115A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2114A/5A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Table 1). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch
the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS2114A/5A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
Copyright © 2004–2012, Texas Instruments Incorporated 17
TPS2114A
TPS2115A
SBVS044F –MARCH 2004–REVISED MAY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2011) to Revision F Page
• Changed description of power supplies in Description section ............................................................................................ 1
• Added IOUT column to Device Information table .................................................................................................................... 2
• Changed conditions of Absolute Maximum Ratings table .................................................................................................... 2
• Added PW to end of device name in first two continuous output rows in Current parameter of Absolute Maximum
Ratings table ......................................................................................................................................................................... 2
• Added last continuous output row to Current parameter in Absolute Maximum Ratings table ............................................ 2
• Deleted storage temperature row from Absolute Maximum Ratings table ........................................................................... 2
• Changed Current limit adjustment range parameter, TPS2115A specification in Available Options table .......................... 2
• Changed Nominal current limit adjustment range parameter in Recommended Operating Conditions table ...................... 3
• Added footnote 1 to Recommended Operating Conditions table ......................................................................................... 3
Changes from Revision D (July 2006) to Revision E Page
• Updated document to current format .................................................................................................................................... 1
• Changed title, footnote, and CGF marking in Device Information table ............................................................................... 2
• Deleted footnote 1 (not tested in production) from Electrical Characteristics: General table ............................................... 4
• Deleted footnote 1 (not tested in production) from Switching Characteristics table ............................................................. 5
• Added PAD row to Terminal Functions table ........................................................................................................................ 6
18 Copyright © 2004–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 28-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2114APW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2114APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2114APWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2114APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2115ADRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2115ADRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2115ADRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2115ADRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2115APW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2115APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2115APWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2115APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Apr-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2115A :
•Automotive: TPS2115A-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2114APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2115ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2115ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2115APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2114APWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2115ADRBR SON DRB 8 3000 367.0 367.0 35.0
TPS2115ADRBT SON DRB 8 250 210.0 185.0 35.0
TPS2115APWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated