LPC4357FET256,551"" - NXP SEMICONDUCTORS

1. General description

The LPC4357/53 are ARM Cortex-M4 based microcontrollers for embedded applications

which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 1 36 kB of on-chip

SRAM, 16 kB of EEPROM memory, advanced configurable peripherals such as the State

Configurable Timer (SCT) and the Serial Gene ral Purpose I/O (SGPIO) interface, two

High-speed USB controllers, Ethernet, LCD, an external me mo ry controller, and multiple

digital a nd a nalog pe rip her als. The L PC4 35 7/ 53 o per ate at CPU fr equ encies of up to 204

MHz.

The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements

such as low power consumption, enhanced debug features, and a high level of support

block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a

Harvard arch itec tu re with separate local instruction and data buses as well as a third bus

for peripherals, and includ es an internal pr efetch unit th at support s speculative branching.

The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD

instructions. A hardware floating-point processor is integrated in the core.

The ARM Cortex-M0 coprocessor is an energ y-efficient and easy-to-use 32-bit core which

is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,

designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz

performance with a simple instruction set and reduced code size.

2. Features and benefits

Cortex-M4 Proc e sso r core

ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.

ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.

ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

Hardware floating-point unit.

Non-maskable Interrupt (NM I) input.

JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoint s, and four wa tch

points.

Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

System tick timer.

Cortex-M0 Proc e sso r core

ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4

application processor.

Running at frequencies of up to 204 MHz.

JTAG, Serial Wire Debug, and built-in NVIC.

LPC4357/53

32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC

Rev. 1 — 4 June 2012 Objective data sheet

Objective data sheet Rev. 1 — 4 June 2012 2 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

On-chip memory

Up to 1 MB on-chip dual bank flash memory with flash accelerator.

16 kB on-chip EEPROM data memory.

136 kB SRAM for code and data use.

Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

64 kB ROM containing boot code and on-chip software drivers.

128 bit general-purpose One-Time Programmable (OTP) memory.

Configurable digital peripherals

Serial GPIO (SGPIO) interface.

State Configurable Timer (SCT) subsystem on AHB.

Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCT, and ADC0/1.

Serial interfaces

Quad SPI Flash Interface (SPIFI) with four lanes and up to 60 MB per second.

10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY.

One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

USB interface electrical test software included in ROM USB stack.

One 550 UART with DMA support and full modem interface.

Three 550 USARTs with DMA and synchronous mode support and a smart card

interface conforming to ISO7816 specification. One USART with IrDA interface.

Two C_CAN 2.0B controllers with one channel each.

Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

One SPI controller.

One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1Mbit/s.

One standard I2C-bus interface with monitor mode and with standard I/O pins.

Two I2S interfaces, each with DMA support and with one input and one output.

Digital peripherals

External Memory Con tro lle r (EM C) su pp or tin g ex te rn al SRAM , ROM , NO R flash ,

and SDRAM devices.

LCD controller with DMA support and a programmable display resolution of up to

1024 H  768 V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4 /8 bpp Color Look-Up Table (CLUT) and 16 /24-bit direct pixel

mapping.

Secure Digital Input Output (SD/MMC) card interface.

Eight-channel Genera l-Purpose DMA (GPDMA) controller can a ccess all memories

on the AHB and all DMA-capable AHB slaves.

Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors.

Objective data sheet Rev. 1 — 4 June 2012 3 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

Up to eight GPIO pins can be selected from all GPIO pins as edge and level

sensitive interrupt sources.

Two GPIO group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of GPIO pins.

Four general-purpose timer/counters with capture and match capabilities.

One motor control Pulse Width Modulator (PWM) for three-phase motor control.

One Quadrature Encoder Interface (QEI).

Repetitive Interrupt timer (RI timer).

Windowed watchdog timer (WWDT).

Ultra-low power Real-Time Clock (RTC) on separate po wer d oma in with 25 6 bytes

of battery powered backup registers.

Alarm timer; can be battery powered.

Analog peripherals

One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

Two 10-bit ADCs with DMA support and a dat a conversion rate of 40 0 kSamples/s.

Up to eight input channels per ADC.

Decryption:

Hardware-based AES decryption programmable through an on-chip API.

Two 128-bit secure OTP memories for AES key storage and customer use.

Random Number Generator (RNG) accessible through AES API.

Unique ID for each device.

Clock generation unit

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and

voltage.

Ultra-low power Real-Time Clock (RTC) crystal oscillator.

Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency cryst al. The second PLL is dedicated to the Hig h-speed USB, the

third PLL can be used as audio PLL.

Clock output.

Power

Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for th e

core supply and the RTC power domain.

RTC power domain can be powered separately by a 3 V battery supply.

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

Brownout detect with four separate thresholds for interrupt and forced reset.

Power-On Reset (POR).

Available as LQFP208, LBGA256, or TFBGA180 packages.

Objective data sheet Rev. 1 — 4 June 2012 4 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

3. Applications

Motor control Embedded audio applications

Power management Industrial auto m at ion

White goods e-metering

RFID readers

Objective data sheet Rev. 1 — 4 June 2012 5 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4357FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4357FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2

LPC4353FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4353FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

Table 2. Ordering options

Type number Flash Flash

bank A Flash

bank B Total

SRAM LCD Ethernet USB0

(Host,

Device,

OTG)

USB1

(Host,

Device)/

ULPI

interface

ADC

channels GPIO

LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 164

LPC4357FET180 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 118

LPC4357FBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 142

LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 164

LPC4353FET180 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 118

LPC4353FBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 142

Objective data sheet Rev. 1 — 4 June 2012 6 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

5. Block diagram

Fig 1. LPC4357/53 Block diagram

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

I-code bus

D-code bus

system bus

GPDMA LCD SD/

MMC

ETHERNET

10/100

MAC

IEEE 1588

HIGH-SPEED

USB0

HOST/

DEVICE/OTG

HIGH-SPEED

USB1

HOST/DEVICE

EMC

HIGH-SPEED PHY

SPIFI

AES

HS GPIO

SPI

SGPIO

SCT

I2C0

I2S0

I2S1

C_CAN1

MOTOR

CONTROL

PWM

TIMER3

TIMER2

USART2

USART3

SSP1

RI TIMER

QEI

GIMA

BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE

AHB MULTILAYER MATRIX

LPC4357/53

10-bit ADC0

10-bit ADC1

C_CAN0

I2C1

10-bit DAC

BRIDGE

RGU

CCU2

CGU

CCU1

ALARM TIMER

CONFIGURATION

REGISTERS

OTP MEMORY

EVENT ROUTER

POWER MODE CONTROL

12 MHz IRC

RTC POWER DOMAIN

BACKUP REGISTERS

RTC OSC

RTC

002aah076

slaves

masters

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

= connected to GPDMA

GPIO

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

SCU

32 kB AHB SRAM

16 kB +

16 kB AHB SRAM

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

512/256 kB FLASH A

512/256 kB FLASH B

16 kB EEPROM

Objective data sheet Rev. 1 — 4 June 2012 7 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

6. Pinning information

6.1 Pinning

6.2 Pin description

On the LPC4357/53, digit al pin s are grouped into 1 6 port s, named P0 to P9 and PA to PF,

with up to 20 pins used per port. Each digital pin can support up to eight differ ent digital

functions, including General Purpose I/O (GPIO), selectable through the System

Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port

assigned to it.

Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA 180 package

002aah077

LPC4357/53FET256

Transparent top view

2 4 6 8 10 12

1357911

ball A1

index area

002aah078

LPC4357/53FET180

Transparent top view

2 4 6 8 10 12

1357911

ball A1

index area

Fig 4. Pin confi gura t io n LQ FP2 0 8 pac kag e

LPC4357/53FBD208

156

104

208

157

105

002aah079

Objective data sheet Rev. 1 — 4 June 2012 8 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Table 3. Pin description

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Multiplexed digital pins

P0_0 L3 K3 47 [2] N;

PU I/O GPIO0[0] — General purpose digital input/output pin.

I/O SSP1_MISO — Master In Slave Out for SSP1.

IENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

I/O SGPIO0 — General purpose digital input/output pin.

-R — Function reserved.

I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

I/O I2S1_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

P0_1 M2 K2 50 [2] N;

PU I/O GPIO0[1] — General purpose digital input/output pin.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SGPIO1 — General purpose digital input/output pin.

-R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

P1_0 P2 L1 54 [2] N;

PU I/O GPIO0[4] — General purpose digital input/output pin.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

I/O EMC_A5 — External memory address line 5.

-R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

I/O SGPIO7 — General purpose digital input/output pin.

I/O EMC_D12 — External memory data line 12.

P1_1 R2 N1 58 [2] N;

PU I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see

Table 5).

OCTOUT_7 — SCT output 7. Matc h ou tp ut 3 of timer 1.

I/O EMC_A6 — External memory address line 6.

I/O SGPIO8 — General purpose digital input/output pin.

-R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

I/O EMC_D13 — External memory data line 13.

Objective data sheet Rev. 1 — 4 June 2012 9 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P1_2 R3 N2 60 [2] N;

PU I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see

Table 5).

OCTOUT_6 — SCT output 6. Matc h ou tp ut 2 of timer 1.

I/O EMC_A7 — External memory address line 7.

I/O SGPIO9 — General purpose digital input/output pin.

-R — Function reserved.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

I/O EMC_D14 — External memory data line 14.

P1_3 P5 M2 61 [2] N;

PU I/O GPIO0[10] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.

I/O SGPIO10 — General purpose digital input/output pin.

OEMC_OE — LOW active Output Enable signal.

OUSB0_IND1 — USB0 port indicator LED control

output 1.

I/O SSP1_MISO — Master In Slave Out for SSP1.

-R — Function reserved.

OSD_RST — SD/MMC reset signal for MMC4.4 card.

P1_4 T3 P2 64 [2] N;

PU I/O GPIO0[11] — General purpose digital input/output pin.

OCTOUT_9 — SCT output 9. Matc h ou tp ut 3 of timer 3.

I/O SGPIO11 — General purpose digital input/output pin.

OEMC_BLS0 — LOW active Byte Lane select signal 0.

OUSB0_IND0 — USB0 port indicator LED control output 0.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

I/O EMC_D15 — External memory data line 15.

OSD_VOLT1 — SD/MMC bus voltage select output 1.

P1_5 R5 N3 65 [2] N;

PU I/O GPIO1[8] — General purpose digital input/output pin.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

-R — Function reserved.

OEMC_CS0 — LOW active Chip Select 0 signal.

IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external

circuitry required to detect over-current condition).

I/O SSP1_SSEL — Slave Select for SSP1.

I/O SGPIO15 — General purpose digital input/output pin.

OSD_POW — SD/MMC power monitor output.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 10 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P1_6 T4 P3 67 [2] N;

PU I/O GPIO1[9] — General purpose digital input/output pin.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

-R — Function reserved.

OEMC_WE — LOW active Write Enable signal.

-R — Function reserved.

OEMC_BLS0 — LOW active Byte Lane select signal 0.

I/O SGPIO14 — General purpose digital input/output pin.

I/O SD_CMD — SD/MMC command signal.

P1_7 T5 N4 69 [2] N;

PU I/O GPIO1[0] — General purpose digital input/output pin.

IU1_DSR — Data Set Ready input for UART1.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O EMC_D0 — External memory data line 0.

OUSB0_PPWR — VBUS drive signal (towards external charge pump

or power management unit); indicates that VBUS must be driven

(active HIGH).

Add a pull-down resistor to disable the power switch at reset. This

signal has opposite polarity compared to the USB_PPW R used on

other NXP LPC parts.

-R — Function reserved.

P1_8 R7 M5 71 [2] N;

PU I/O GPIO1[1] — General purpose digital input/output pin.

OU1_DTR — Data Terminal Ready output for UART1.

OCTOUT_12 — SCT output 12. Match output 3 of

timer 3.

I/O EMC_D1 — External memory data line 1.

-R — Function reserved.

OSD_VOLT0 — SD/MMC bus voltage select output 0.

P1_9 T7 N5 73 [2] N;

PU I/O GPIO1[2] — General purpose digital input/output pin.

OU1_RTS — Request to Send output for UART1.

OCTOUT_11 — SCT output 11. Match output 3 of timer 2.

I/O EMC_D2 — External memory data line 2.

-R — Function reserved.

I/O SD_DAT0 — SD/MMC data bus line 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 11 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P1_10 R8 N6 75 [2] N;

PU I/O GPIO1[3] — General purpose digital input/output pin.

IU1_RI — Ring Indicato r in p ut for U ART1.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O EMC_D3 — External memory data line 3.

-R — Function reserved.

I/O SD_DAT1 — SD/MMC data bus line 1.

P1_11 T9 P8 77 [2] N;

PU I/O GPIO1[4] — General purpose digital input/output pin.

IU1_CTS — Clear to Send input for UART1.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O EMC_D4 — External memory data line 4.

-R — Function reserved.

I/O SD_DAT2 — SD/MMC data bus line 2.

P1_12 R9 P7 78 [2] N;

PU I/O GPIO1[5] — General purpose digital input/output pin.

IU1_DCD — Data Carrier Detect input for UART1.

-R — Function reserved.

I/O EMC_D5 — External memory data line 5.

IT0_CAP1 — Capture input 1 of timer 0.

-R — Function reserved.

I/O SGPIO8 — General purpose digital input/output pin.

I/O SD_DAT3 — SD/MMC data bus line 3.

P1_13 R10 D6 83 [2] N;

PU I/O GPIO1[6] — General purpose digital input/output pin.

OU1_TXD — Transmitter output for UART1.

-R — Function reserved.

I/O EMC_D6 — External memory data line 6.

IT0_CAP0 — Capture input 0 of timer 0.

-R — Function reserved.

I/O SGPIO9 — General purpose digital input/output pin.

ISD_CD — SD/MMC card detect input.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 12 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P1_14 R11 K7 85 [2] N;

PU I/O GPIO1[7] — General purpose digital input/output pin.

IU1_RXD — Receiver input for UART1.

-R — Function reserved.

I/O EMC_D7 — External memory data line 7.

OT0_MAT2 — Match output 2 of timer 0.

-R — Function reserved.

I/O SGPIO10 — General purpose digital input/output pin.

-R — Function reserved.

P1_15 T12 P11 87 [2] N;

PU I/O GPIO0[2] — General purpose digital input/output pin.

OU2_TXD — Transmitter output for USART2.

I/O SGPIO2 — General purpose digital input/output pin.

IENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

OT0_MAT1 — Match output 1 of timer 0.

-R — Function reserved.

I/O EMC_D8 — External memory data line 8.

-R — Function reserved.

P1_16 M7 L5 90 [2] N;

PU I/O GPIO0[3] — General purpose digital input/output pin.

IU2_RXD — Receiver input for USART2.

I/O SGPIO3 — General purpose digital input/output pin.

IENET_CRS — Ethernet Carrier Sense (MII interface).

OT0_MAT0 — Match output 0 of timer 0.

-R — Function reserved.

I/O EMC_D9 — External memory data line 9.

IENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface).

P1_17 M8 L6 93 [3] N;

PU I/O GPIO0[12] — General purpose digital input/output pin.

I/O U2_UCLK — Serial clock input/output for USART2 in synchronous

mode.

-R — Function reserved.

I/O ENET_MDIO — Ethernet MIIM data input and output.

IT0_CAP3 — Capture input 3 of timer 0.

OCAN1_TD — CAN1 transmitter output.

I/O SGPIO11 — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 13 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P1_18 N12 N10 95 [2] N;

PU I/O GPIO0[13] — General purpose digital input/output pin.

I/O U2_DIR — RS-485/EIA-485 output enable/direction control for

USART2.

-R — Function reserved.

OENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

OT0_MAT3 — Match output 3 of timer 0.

ICAN1_RD — CAN1 receiver input.

I/O SGPIO12 — General purpose digital input/output pin.

I/O EMC_D10 — External memory data line 10.

P1_19 M11 N9 96 [2] N;

PU IENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII

interface) or Ethernet Reference Clock (RMII interface).

I/O SSP1_SCK — Serial clock for SSP1.

-R — Function reserved.

OCLKOUT — Clock output pin.

-R — Function reserved.

OI2S0_RX_MCLK — I2S receive master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

P1_20 M10 J10 100 [2] N;

PU I/O GPIO0[15] — General purpose digital input/output pin.

I/O SSP1_SSEL — Slave Select for SSP1.

-R — Function reserved.

OENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

IT0_CAP2 — Capture input 2 of timer 0.

-R — Function reserved.

I/O SGPIO13 — General purpose digital input/output pin.

I/O EMC_D11 — External memory data line 11.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 14 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P2_0 T16 N14 108 [2] N;

PU I/O SGPIO4 — General purpose digital input/output pin.

OU0_TXD — Transmitter output for USART0. See Table 4 for ISP

mode.

I/O EMC_A13 — External memory address line 13.

OUSB0_PPWR — VBUS drive signal (towards external charge pump

or power management unit); indicates that VBUS must be driven

(active HIGH).

Add a pull-down resistor to disable the power switch at reset. This

signal has opposite polarity compared to the USB_PPW R used on

other NXP LPC parts.

I/O GPIO5[0] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP0 — Capture input 0 of timer 3.

OENET_MDC — Ethernet MIIM clock.

P2_1 N15 M13 116 [2] N;

PU I/O SGPIO5 — General purpose digital input/output pin.

IU0_RXD — Receiver input for USART0. See Table 4 for ISP mode.

I/O EMC_A12 — External memory address line 12.

IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external

circuitry required to detect over-current condition).

I/O GPIO5[1] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP1 — Capture input 1 of timer 3.

-R — Function reserved.

P2_2 M15 L13 121 [2] N;

PU I/O SGPIO6 — General purpose digital input/output pin.

I/O U0_UCLK — Serial clock input/output for USART0 in synchronous

mode.

I/O EMC_A11 — External memory address line 11.

OUSB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[2] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

IT3_CAP2 — Capture input 2 of timer 3.

OEMC_CS1 — LOW active Chip Select 1 signal.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 15 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P2_3 J12 G11 127 [3] N;

PU I/O SGPIO12 — General purpose digital input/output pin.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

OU3_TXD — Transmitter output for USART3. See Table 4 for ISP

mode.

ICTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of

timer 2.

I/O GPIO5[3] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT0 — Match output 0 of timer 3.

OUSB0_PPWR — VBUS drive signal (towards external charge pump

or power management unit); indicates that VBUS must be driven

(active HIGH).

Add a pull-down resistor to disable the power switch at reset. This

signal has opposite polarity compared to the USB_PPW R used on

other NXP LPC parts.

P2_4 K11 L9 128 [3] N;

PU I/O SGPIO13 — General purpose digital input/output pin.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

IU3_RXD — Receiver input for USART3. See Table 4 for ISP mode.

ICTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

I/O GPIO5[4] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT1 — Match output 1 of timer 3.

IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external

circuitry required to detect over-current condition).

P2_5 K14 J12 131 [3] N;

PU I/O SGPIO14 — General purpose digital input/output pin.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

IUSB1_VBUS — Monitors the presence of USB1 bus power.

Note: This signal must be HIGH for USB reset to occur.

IADCTRIG1 — ADC trigger input 1.

I/O GPIO5[5] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT2 — Match output 2 of timer 3.

OUSB0_IND0 — USB0 port indicator LED control output 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 16 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P2_6 K16 J14 137 [2] N;

PU I/O SGPIO7 — General purpose digital input/output pin.

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

I/O EMC_A10 — External memory address line 10.

OUSB0_IND0 — USB0 port indicator LED control

output 0.

I/O GPIO5[6] — General purpose digital input/output pin.

ICTIN_7 — SCT input 7.

IT3_CAP3 — Capture input 3 of timer 3.

OEMC_BLS1 — LOW active Byte Lane select signal 1.

P2_7 H14 G12 138 [2] N;

PU I/O GPIO0[7] — General purpose digital input/output pin. If this pin is

pulled LOW at reset, the part enters ISP mode or boots from an

external source (see Table 4 and Table 5).

OCTOUT_1 — SCT output 1. Matc h ou tp ut 3 of timer 3.

I/O U3_UCLK — Serial clock input/output for USART3 in synchronous

mode.

I/O EMC_A9 — External memory address line 9.

-R — Function reserved.

OT3_MAT3 — Match output 3 of timer 3.

-R — Function reserved.

P2_8 J16 H14 140 [2] N;

PU I/O SGPIO15 — General purpose digital input/output pin. Boot pin (see

Table 5).

OCTOUT_0 — SCT output 0. Matc h ou tp ut 0 of timer 0.

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

I/O EMC_A8 — External memory address line 8.

I/O GPIO5[7] — General purpose digital input/output pin.

-R — Function reserved.

P2_9 H16 G14 144 [2] N;

PU I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see

Table 5).

OCTOUT_3 — SCT output 3. Matc h ou tp ut 3 of timer 0.

I/O U3_BAUD — Baud pin for USART3.

I/O EMC_A0 — External memory address line 0.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 17 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P2_10 G16 F14 146 [2] N;

PU I/O GPIO0[14] — General purpose digital input/output pin.

OCTOUT_2 — SCT output 2. Matc h ou tp ut 2 of timer 0.

OU2_TXD — Transmitter output for USART2.

I/O EMC_A1 — External memory address line 1.

-R — Function reserved.

P2_11 F16 E13 148 [2] N;

PU I/O GPIO1[11] — General purpose digital input/output pin.

OCTOUT_5 — SCT output 5. Matc h ou tp ut 3 of timer 3.

IU2_RXD — Receiver input for USART2.

I/O EMC_A2 — External memory address line 2.

-R — Function reserved.

P2_12 E15 D13 153 [2] N;

PU I/O GPIO1[12] — General purpose digital input/output pin.

OCTOUT_4 — SCT output 4. Matc h ou tp ut 3 of timer 3.

-R — Function reserved.

I/O EMC_A3 — External memory address line 3.

-R — Function reserved.

I/O U2_UCLK — Serial clock input/output for USART2 in synchronous

mode.

P2_13 C16 E14 156 [2] N;

PU I/O GPIO1[13] — General purpose digital input/output pin.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

-R — Function reserved.

I/O EMC_A4 — External memory address line 4.

-R — Function reserved.

I/O U2_DIR — RS-485/EIA-485 output enable/direction control for

USART2.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 18 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P3_0 F13 D12 161 [2] N;

PU I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

OI2S0_RX_MCLK — I2S receive master clock.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O SSP0_SCK — Serial clock for SSP0.

-R — Function reserved.

P3_1 G11 D10 163 [2] N;

PU I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

ICAN0_RD — CAN receiver input.

OUSB1_IND1 — USB1 Port indicator LED control output 1.

I/O GPIO5[8] — General purpose digital input/output pin.

-R — Function reserved.

OLCD_VD15 — LCD data.

-R — Function reserved.

P3_2 F11 D9 166 [2] OL;

PU I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

OCAN0_TD — CAN transmitter output.

OUSB1_IND0 — USB1 Port indicator LED control output 0.

I/O GPIO5[9] — General purpose digital input/output pin.

-R — Function reserved.

OLCD_VD14 — LCD data.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 19 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P3_3 B14 B13 169 [4] N;

PU -R — Function reserved.

I/O SPI_SCK — Serial clock for SPI.

I/O SSP0_SCK — Serial clock for SSP0.

OSPIFI_SCK — Serial clock for SPIFI.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

P3_4 A15 C14 171 [2] N;

PU I/O GPIO1[14] — General purpose digital input/output pin.

-R — Function reserved.

I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.

OU1_TXD — Transmitter output for UART 1.

I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

OLCD_VD13 — LCD data.

P3_5 C12 C11 173 [2] N;

PU I/O GPIO1[15] — General purpose digital input/output pin.

-R — Function reserved.

I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.

IU1_RXD — Receiver input for UART 1.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

I/O I2S1_RX_WS — Receive Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

OLCD_VD12 — LCD data.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 20 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P3_6 B13 B12 174 [2] N;

PU I/O GPIO0[6] — General purpose digital input/output pin.

I/O SPI_MISO — Master In Slave Out for SPI.

I/O SSP0_SSEL — Slave Select for SSP0.

I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.

-R — Function reserved.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

P3_7 C11 C10 176 [2] N;

PU -R — Function reserved.

I/O SPI_MOSI — Master Out Slave In for SPI.

I/O SSP0_MISO — Master In Slave Out for SSP0.

I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

I/O GPIO5[10] — General purpose digital input/output pin.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

P3_8 C10 C9 179 [2] N;

PU -R — Function reserved.

ISPI_SSEL — Slave Select for SPI. Note that this pin in an input pin

only. The SPI in master mode cannot drive the CS input on the slave.

Any GPIO pin can be used for SPI chip select in master mode.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

I/O SPIFI_CS — SPIFI serial flash chip select.

I/O GPIO5[11] — General purpose digital input/output pin.

I/O SSP0_SSEL — Slave Select for SSP0.

-R — Function reserved.

P4_0 D5 D4 1 [2] N;

PU I/O GPIO2[0] — General purpose digital input/output pin.

OMCOA0 — Motor control PWM channel 0, output A.

INMI — External interrupt input to NMI.

-R — Function reserved.

OLCD_VD13 — LCD data.

I/O U3_UCLK — Serial clock input/output for USART3 in synchronous

mode.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 21 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P4_1 A1 D3 3 [5] N;

PU I/O GPIO2[1] — General purpose digital input/output pin.

OCTOUT_1 — SCT output 1. Matc h ou tp ut 3 of timer 3.

OLCD_VD0 — LCD data.

-R — Function reserved.

OLCD_VD19 — LCD data.

OU3_TXD — Transmitter output for USART3.

IENET_COL — Ethernet Collision detect (MII interface).

AI ADC0_1 — ADC0, input channel 1. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

P4_2 D3 A2 12 [2] N;

PU I/O GPIO2[2] — General purpose digital input/output pin.

OCTOUT_0 — SCT output 0. Matc h ou tp ut 0 of timer 0.

OLCD_VD3 — LCD data.

-R — Function reserved.

OLCD_VD12 — LCD data.

IU3_RXD — Receiver input for USART3.

I/O SGPIO8 — General purpose digital input/output pin.

P4_3 C2 B2 10 [5] N;

PU I/O GPIO2[3] — General purpose digital input/output pin.

OCTOUT_3 — SCT output 3. Matc h ou tp ut 3 of timer 0.

OLCD_VD2 — LCD data.

-R — Function reserved.

OLCD_VD21 — LCD data.

I/O U3_BAUD — Baud pin for USART3.

I/O SGPIO9 — General purpose digital input/output pin.

AI ADC0_0 — ADC0, input channel 0. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 22 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P4_4 B1 A1 14 [5] N;

PU I/O GPIO2[4] — General purpose digital input/output pin.

OCTOUT_2 — SCT output 2. Matc h ou tp ut 2 of timer 0.

OLCD_VD1 — LCD data.

-R — Function reserved.

OLCD_VD20 — LCD data.

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

I/O SGPIO10 — General purpose digital input/output pin.

ODAC — DAC output. Configure the pin as GPIO input and use the

analog function select register in the SCU to select the DAC.

P4_5 D2 C2 15 [2] N;

PU I/O GPIO2[5] — General purpose digital input/output pin.

OCTOUT_5 — SCT output 5. Matc h ou tp ut 3 of timer 3.

OLCD_FP — Frame pulse (STN). Vertical synchronization pulse

(TFT).

-R — Function reserved.

I/O SGPIO11 — General purpose digital input/output pin.

P4_6 C1 B1 17 [2] N;

PU I/O GPIO2[6] — General purpose digital input/output pin.

OCTOUT_4 — SCT output 4. Matc h ou tp ut 3 of timer 3.

OLCD_ENAB/LCDM — STN AC bias drive or TFT data enable inp ut.

-R — Function reserved.

I/O SGPIO12 — General purpose digital input/output pin.

P4_7 H4 F4 21 [2] O;

PU OLCD_DCLK — LCD panel clock.

IGP_CLKIN — General purpose clock input to the CGU.

-R — Function reserved.

I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 23 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P4_8 E2 D2 23 [2] N;

PU -R — Function reserved.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

OLCD_VD9 — LCD data.

-R — Function reserved.

I/O GPIO5[12] — General purpose digital input/output pin.

OLCD_VD22 — LCD data.

OCAN1_TD — CAN1 transmitter output.

I/O SGPIO13 — General purpose digital input/output pin.

P4_9 L2 J2 48 [2] N;

PU -R — Function reserved.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OLCD_VD11 — LCD data.

-R — Function reserved.

I/O GPIO5[13] — General purpose digital input/output pin.

OLCD_VD15 — LCD data.

ICAN1_RD — CAN1 receiver input.

I/O SGPIO14 — General purpose digital input/output pin.

P4_10 M3 L3 51 [2] N;

PU -R — Function reserved.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

OLCD_VD10 — LCD data.

-R — Function reserved.

I/O GPIO5[14] — General purpose digital input/output pin.

OLCD_VD14 — LCD data.

-R — Function reserved.

I/O SGPIO15 — General purpose digital input/output pin.

P5_0 N3 L2 53 [2] N;

PU I/O GPIO2[9] — General purpose digital input/output pin.

OMCOB2 — Motor control PWM channel 2, output B.

I/O EMC_D12 — External memory data line 12.

-R — Function reserved.

IU1_DSR — Data Set Ready input for UART 1.

IT1_CAP0 — Capture input 0 of timer 1.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 24 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P5_1 P3 M1 55 [2] N;

PU I/O GPIO2[10] — General purpose digital input/output pin.

IMCI2 — Motor control PWM channel 2, input.

I/O EMC_D13 — External memory data line 13.

-R — Function reserved.

OU1_DTR — Data Terminal Ready outpu t for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

IT1_CAP1 — Capture input 1 of timer 1.

-R — Function reserved.

P5_2 R4 M3 63 [2] N;

PU I/O GPIO2[11] — General purpose digital input/output pin.

IMCI1 — Motor control PWM channel 1, input.

I/O EMC_D14 — External memory data line 14.

-R — Function reserved.

OU1_RTS — Request to Send output for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

IT1_CAP2 — Capture input 2 of timer 1.

-R — Function reserved.

P5_3 T8 P6 76 [2] N;

PU I/O GPIO2[12] — General purpose digital input/output pin.

IMCI0 — Motor control PWM channel 0, input.

I/O EMC_D15 — External memory data line 15.

-R — Function reserved.

IU1_RI — Ring Indicator input for UART 1.

IT1_CAP3 — Capture input 3 of timer 1.

-R — Function reserved.

P5_4 P9 N7 80 [2] N;

PU I/O GPIO2[13] — General purpose digital input/output pin.

OMCOB0 — Motor control PWM channel 0, output B.

I/O EMC_D8 — External memory data line 8.

-R — Function reserved.

IU1_CTS — Clear to Send input for UART 1.

OT1_MAT0 — Match output 0 of timer 1.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 25 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P5_5 P10 N8 81 [2] N;

PU I/O GPIO2[14] — General purpose digital input/output pin.

OMCOA1 — Motor control PWM channel 1, output A.

I/O EMC_D9 — External memory data line 9.

-R — Function reserved.

IU1_DCD — Data Carrier Detect input for UART 1.

OT1_MAT1 — Match output 1 of timer 1.

-R — Function reserved.

P5_6 T13 M11 89 [2] N;

PU I/O GPIO2[15] — General purpose digital input/output pin.

OMCOB1 — Motor control PWM channel 1, output B.

I/O EMC_D10 — External memory data line 10.

-R — Function reserved.

OU1_TXD — Transmitter output for UART 1.

OT1_MAT2 — Match output 2 of timer 1.

-R — Function reserved.

P5_7 R12 N11 91 [2] N;

PU I/O GPIO2[7] — General purpose digital input/output pin.

OMCOA2 — Motor control PWM channel 2, output A.

I/O EMC_D11 — External memory data line 11.

-R — Function reserved.

IU1_RXD — Receiver input for UART 1.

OT1_MAT3 — Match output 3 of timer 1.

-R — Function reserved.

P6_0 M12 M10 105 [2] N;

PU -R — Function reserved.

OI2S0_RX_MCLK — I2S receive master clock.

-R — Function reserved.

I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 26 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P6_1 R15 P14 107 [2] N;

PU I/O GPIO3[0] — General purpose digital input/output pin.

OEMC_DYCS1 — SDRAM chip select 1.

I/O U0_UCLK — Serial clock input/output for USART0 in synchronous

mode.

I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

-R — Function reserved.

IT2_CAP0 — Capture input 2 of timer 2.

-R — Function reserved.

P6_2 L13 K11 111 [2] N;

PU I/O GPIO3[1] — General purpose digital input/output pin.

OEMC_CKEOUT1 — SDRAM clock enable 1.

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

-R — Function reserved.

IT2_CAP1 — Capture input 1 of timer 2.

-R — Function reserved.

P6_3 P15 N13 113 [2] N;

PU I/O GPIO3[2] — General purpose digital input/output pin.

OUSB0_PPWR — VBUS drive signal (towards external charge pump

or power management unit); indicates th at the VBUS signal must be

driven (active HIGH).

Add a pull-down resistor to disable the power switch at reset. This

signal has opposite polarity compared to the USB_PPW R used on

other NXP LPC parts.

I/O SGPIO4 — General purpose digital input/output pin.

OEMC_CS1 — LOW active Chip Select 1 signal.

-R — Function reserved.

IT2_CAP2 — Capture input 2 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 27 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P6_4 R16 M14 114 [2] N;

PU I/O GPIO3[3] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OU0_TXD — Transmitter output for USART0.

OEMC_CAS — LOW active SDRAM Column Address Strobe.

-R — Function reserved.

P6_5 P16 L14 117 [2] N;

PU I/O GPIO3[4] — General purpose digital input/output pin.

OCTOUT_6 — SCT output 6. Matc h ou tp ut 2 of timer 1.

IU0_RXD — Receiver input for USART0.

OEMC_RAS — LOW active SD RAM Row Address Strobe.

-R — Function reserved.

P6_6 L14 K12 119 [2] N;

PU I/O GPIO0[5] — General purpose digital input/output pin.

OEMC_BLS1 — LOW active Byte Lane select signal 1.

I/O SGPIO5 — General purpose digital input/output pin.

IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external

circuitry required to detect over-current condition).

-R — Function reserved.

IT2_CAP3 — Capture input 3 of timer 2.

-R — Function reserved.

P6_7 J13 H11 123 [2] N;

PU -R — Function reserved.

I/O EMC_A15 — External memory address line 15.

I/O SGPIO6 — General purpose digital input/output pin.

OUSB0_IND1 — USB0 port indicator LED control output 1.

I/O GPIO5[15] — General purpose digital input/output pin.

OT2_MAT0 — Match output 0 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 28 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P6_8 H13 F12 125 [2] N;

PU -R — Function reserved.

I/O EMC_A14 — External memory address line 14.

I/O SGPIO7 — General purpose digital input/output pin.

OUSB0_IND0 — USB0 port indicator LED control output 0.

I/O GPIO5[16] — General purpose digital input/output pin.

OT2_MAT1 — Match output 1 of timer 2.

-R — Function reserved.

P6_9 J15 H13 139 [2] N;

PU I/O GPIO3[5] — General purpose digital input/output pin.

-R — Function reserved.

OEMC_DYCS0 — SDRAM chip select 0.

-R — Function reserved.

OT2_MAT2 — Match output 2 of timer 2.

-R — Function reserved.

P6_10 H15 G13 142 [2] N;

PU I/O GPIO3[6] — General purpose digital input/output pin.

OMCABORT — Motor control PWM, LOW-active fast abort.

-R — Function reserved.

OEMC_DQMOUT1 — Data mask 1 used with SDRAM and static

devices.

-R — Function reserved.

P6_11 H12 F11 143 [2] N;

PU I/O GPIO3[7] — General purpose digital input/output pin.

-R — Function reserved.

OEMC_CKEOUT0 — SDRAM clock enable 0.

-R — Function reserved.

OT2_MAT3 — Match output 3 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 29 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P6_12 G15 F13 145 [2] N;

PU I/O GPIO2[8] — General purpose digital input/output pin.

OCTOUT_7 — SCT output 7. Matc h ou tp ut 3 of timer 1.

-R — Function reserved.

OEMC_DQMOUT0 — Data mask 0 used with SDRAM and static

devices.

-R — Function reserved.

P7_0 B16 B14 158 [2] N;

PU I/O GPIO3[8] — General purpose digital input/output pin.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

-R — Function reserved.

OLCD_LE — Line end signal.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

P7_1 C14 C13 162 [2] N;

PU I/O GPIO3[9] — General purpose digital input/output pin.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

OLCD_VD19 — LCD data.

OLCD_VD7 — LCD data.

-R — Function reserved.

OU2_TXD — Transmitter output for USART2.

I/O SGPIO5 — General purpose digital input/output pin.

P7_2 A16 A14 165 [2] N;

PU I/O GPIO3[10] — General purpose digital input/output pin.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

OLCD_VD18 — LCD data.

OLCD_VD6 — LCD data.

-R — Function reserved.

IU2_RXD — Receiver input for USART2.

I/O SGPIO6 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 30 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P7_3 C13 C12 167 [2] N;

PU I/O GPIO3[11] — General purpose digital input/output pin.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

-R — Function reserved.

OLCD_VD17 — LCD data.

OLCD_VD5 — LCD data.

-R — Function reserved.

P7_4 C8 C6 189 [5] N;

PU I/O GPIO3[12] — General purpose digital input/output pin.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

-R — Function reserved.

OLCD_VD16 — LCD data.

OLCD_VD4 — LCD data.

OTRACEDATA[0] — Trace data, bit 0.

-R — Function reserved.

AI ADC0_4 — ADC0, input channel 4. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

P7_5 A7 C7 191 [5] N;

PU I/O GPIO3[13] — General purpose digital input/output pin.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

-R — Function reserved.

OLCD_VD8 — LCD data.

OLCD_VD23 — LCD data.

OTRACEDATA[1] — Trace data, bit 1.

-R — Function reserved.

AI ADC0_3 — ADC0, input channel 3. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

P7_6 C7 F5 194 [2] N;

PU I/O GPIO3[14] — General purpose digital input/output pin.

OCTOUT_11 — SCT output 1. Match output 3 of time r 2.

-R — Function reserved.

OLCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

-R — Function reserved.

OTRACEDATA[2] — Trace data, bit 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 31 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P7_7 B6 D5 201 [5] N;

PU I/O GPIO3[15] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.

-R — Function reserved.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

OTRACEDATA[3] — Trace data, bit 3.

OENET_MDC — Ethernet MIIM clock.

I/O SGPIO7 — General purpose digital input/output pin.

AI ADC1_6 — ADC1, input channel 6. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

P8_0 E5 E4 2 [3] N;

PU I/O GPIO4[0] — General purpose digital input/output pin.

IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent

condition; this signal monitors over-current on the USB bus (external

circuitry required to detect over-current condition).

-R — Function reserved.

IMCI2 — Motor control PWM channel 2, input.

I/O SGPIO8 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT0 — Match output 0 of timer 0.

P8_1 H5 G4 34 [3] N;

PU I/O GPIO4[1] — General purpose digital input/output pin.

OUSB0_IND1 — USB0 port indicator LED control output 1.

-R — Function reserved.

IMCI1 — Motor control PWM channel 1, input.

I/O SGPIO9 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT1 — Match output 1 of timer 0.

P8_2 K4 J4 36 [3] N;

PU I/O GPIO4[2] — General purpose digital input/output pin.

OUSB0_IND0 — USB0 port indicator LED control output 0.

-R — Function reserved.

IMCI0 — Motor control PWM channel 0, input.

I/O SGPIO10 — General purpose digital input/output pin.

-R — Function reserved.

OT0_MAT2 — Match output 2 of timer 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 32 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P8_3 J3 H3 37 [2] N;

PU I/O GPIO4[3] — General purpose digital input/output pin.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-R — Function reserved.

OLCD_VD12 — LCD data.

OLCD_VD19 — LCD data.

-R — Function reserved.

OT0_MAT3 — Match output 3 of timer 0.

P8_4 J2 H2 39 [2] N;

PU I/O GPIO4[4] — General purpose digital input/output pin.

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-R — Function reserved.

OLCD_VD7 — LCD data.

OLCD_VD16 — LCD data.

-R — Function reserved.

IT0_CAP0 — Capture input 0 of timer 0.

P8_5 J1 H1 40 [2] N;

PU I/O GPIO4[5] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-R — Function reserved.

OLCD_VD6 — LCD data.

OLCD_VD8 — LCD data.

-R — Function reserved.

IT0_CAP1 — Capture input 1 of timer 0.

P8_6 K3 J3 43 [2] N;

PU I/O GPIO4[6] — General purpose digital input/output pin.

IUSB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal

from the PHY.

-R — Function reserved.

OLCD_VD5 — LCD data.

OLCD_LP — Line synchronization pulse (STN). Horizontal

synchronization pulse (TFT).

-R — Function reserved.

IT0_CAP2 — Capture input 2 of timer 0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 33 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P8_7 K1 J1 45 [2] N;

PU I/O GPIO4[7] — General purpose digital input/output pin.

OUSB1_ULPI_STP — ULPI link STP signal. Asserted to end or

interrupt transfers to the PHY.

-R — Function reserved.

OLCD_VD4 — LCD data.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

IT0_CAP3 — Capture input 3 of timer 0.

P8_8 L1 K1 49 [2] N;

PU -R — Function reserved.

IUSB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated

by the PHY.

-R — Function reserved.

OCGU_OUT0 — CGU spare clock output 0.

OI2S1_TX_MCLK — I2S1 transmit master clock.

P9_0 T1 P1 59 [2] N;

PU I/O GPIO4[12] — General purpose digital input/output pin.

OMCABORT — Motor control PWM, LOW-active fast abort.

-R — Function reserved.

IENET_CRS — Ethernet Carrier Sense (MII interface).

I/O SGPIO0 — General purpose digital input/output pin.

I/O SSP0_SSEL — Slave Select for SSP0.

P9_1 N6 P4 66 [2] N;

PU I/O GPIO4[13] — General purpose digital input/output pin.

OMCOA2 — Motor control PWM channel 2, output A.

-R — Function reserved.

I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

IENET_RX_ER — Ethernet receive error (MII interface).

I/O SGPIO1 — General purpose digital input/output pin.

I/O SSP0_MISO — Master In Slave Out for SSP0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 34 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P9_2 N8 M6 70 [2] N;

PU I/O GPIO4[14] — General purpose digital input/output pin.

OMCOB2 — Motor control PWM channel 2, output B.

-R — Function reserved.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

IENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O SGPIO2 — General purpose digital input/output pin.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

P9_3 M6 P5 79 [2] N;

PU I/O GPIO4[15] — General purpose digital input/output pin.

OMCOA0 — Motor control PWM channel 0, output A.

OUSB1_IND1 — USB1 Port indicator LED control output 1.

-R — Function reserved.

IENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O SGPIO9 — General purpose digital input/output pin.

OU3_TXD — Transmitter output for USART3.

P9_4 N10 M8 92 [2] N;

PU -R — Function reserved.

OMCOB0 — Motor control PWM channel 0, output B.

OUSB1_IND0 — USB1 Port indicator LED control output 0.

-R — Function reserved.

I/O GPIO5[17] — General purpose digital input/output pin.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O SGPIO4 — General purpose digital input/output pin.

IU3_RXD — Receiver input for USART3.

P9_5 M9 L7 98 [2] N;

PU -R — Function reserved.

OMCOA1 — Motor control PWM channel 1, output A.

OUSB1_PPWR — VBUS drive signal (towards external charge pump

or power management unit); indicates that VBUS must be driven

(active high).

Add a pull-down resistor to disable the power switch at reset. This

signal has opposite polarity compared to the USB_PPW R used on

other NXP LPC parts.

-R — Function reserved.

I/O GPIO5[18] — General purpose digital input/output pin.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O SGPIO3 — General purpose digital input/output pin.

OU0_TXD — Transmitter output for USART0.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 35 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

P9_6 L11 M9 103 [2] N;

PU I/O GPIO4[11] — General purpose digital input/output pin.

OMCOB1 — Motor control PWM channel 1, output B.

IUSB1_PWR_FAULT — USB1 Port power fault signal indicating

over-current condition; this signal monitors over-current on the USB1

bus (external circuitry required to detect over-current condition).

-R — Function reserved.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SGPIO8 — General purpose digital input/output pin.

IU0_RXD — Receiver input for USART0.

PA_0 L12 L10 126 [2] N;

PU -R — Function reserved.

-R — Function reserved.

OI2S1_RX_MCLK — I2S1 receive master clock.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

PA_1 J14 H12 134 [3] N;

PU I/O GPIO4[8] — General purpose digital input/output pin.

IQEI_IDX — Quadrature Encoder Interface INDEX input.

-R — Function reserved.

OU2_TXD — Transmitter output for USART2.

-R — Function reserved.

PA_2 K15 J13 136 [3] N;

PU I/O GPIO4[9] — General purpose digital input/output pin.

IQEI_PHB — Quadrature Encoder Interface PHB input.

-R — Function reserved.

IU2_RXD — Receiver input for USART2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 36 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PA_3 H11 E10 147 [3] N;

PU I/O GPIO4[10] — General purpose digital input/output pin.

IQEI_PHA — Quadrature Encoder Interface PHA input.

-R — Function reserved.

PA_4 G13 E12 151 [2] N;

PU -R — Function reserved.

OCTOUT_9 — SCT output 9. Matc h ou tp ut 3 of timer 3.

-R — Function reserved.

I/O EMC_A23 — External memory address line 23.

I/O GPIO5[19] — General purpose digital input/output pin.

-R — Function reserved.

PB_0 B15 D14 164 [2] N;

PU -R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

OLCD_VD23 — LCD data.

-R — Function reserved.

I/O GPIO5[20] — General purpose digital input/output pin.

-R — Function reserved.

PB_1 A14 A13 175 [2] N;

PU -R — Function reserved.

IUSB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line

direction.

OLCD_VD22 — LCD data.

-R — Function reserved.

I/O GPIO5[21] — General purpose digital input/output pin.

OCTOUT_6 — SCT output 6. Matc h ou tp ut 2 of timer 1.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 37 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PB_2 B12 B11 177 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

OLCD_VD21 — LCD data.

-R — Function reserved.

I/O GPIO5[22] — General purpose digital input/output pin.

OCTOUT_7 — SCT output 7. Matc h ou tp ut 3 of timer 1.

-R — Function reserved.

PB_3 A13 A12 178 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

OLCD_VD20 — LCD data.

-R — Function reserved.

I/O GPIO5[23] — General purpose digital input/output pin.

OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.

-R — Function reserved.

PB_4 B11 B10 180 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

OLCD_VD15 — LCD data.

-R — Function reserved.

I/O GPIO5[24] — General purpose digital input/output pin.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

-R — Function reserved.

PB_5 A12 A11 181 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

OLCD_VD14 — LCD data.

-R — Function reserved.

I/O GPIO5[25] — General purpose digital input/output pin.

ICTIN_7 — SCT input 7.

OLCD_PWR — LCD panel power enable.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 38 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PB_6 A6 C5 - [5] N;

PU -R — Function reserved.

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

OLCD_VD13 — LCD data.

-R — Function reserved.

I/O GPIO5[26] — General purpose digital input/output pin.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

OLCD_VD19 — LCD data.

-R — Function reserved.

AI ADC0_6 — ADC0, input channel 6. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PC_0 D4 - 7 [5] N;

PU -R — Function reserved.

IUSB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated

by the PHY.

-R — Function reserved.

I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).

OLCD_DCLK — LCD panel clock.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

AI ADC1_1 — ADC1, input channel 1. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PC_1 E4 - 9 [2] N;

PU I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.

-R — Function reserved.

IU1_RI — Ring Indicator input for UART 1.

OENET_MDC — Ethernet MIIM clock.

I/O GPIO6[0] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP0 — Capture input 0 of timer 3.

OSD_VOLT0 — SD/MMC bus voltage select output 0.

PC_2 F6 - 13 [2] N;

PU I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.

-R — Function reserved.

IU1_CTS — Clear to Send input for UART 1.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

I/O GPIO6[1] — General purpose digital input/output pin.

-R — Function reserved.

OSD_RST — SD/MMC reset signal for MMC4.4 card.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 39 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PC_3 F5 - 11 [5] N;

PU I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.

-R — Function reserved.

OU1_RTS — Request to Send output for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O GPIO6[2] — General purpose digital input/output pin.

-R — Function reserved.

OSD_VOLT1 — SD/MMC bus voltage select output 1.

AI ADC1_0 — ADC1, input channel 0. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PC_4 F4 - 16 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.

-R — Function reserved.

ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

I/O GPIO6[3] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP1 — Capture input 1 of timer 3.

I/O SD_DAT0 — SD/MMC data bus line 0.

PC_5 G4 - 20 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.

-R — Function reserved.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O GPIO6[4] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP2 — Capture input 2 of timer 3.

I/O SD_DAT1 — SD/MMC data bus line 1.

PC_6 H6 - 22 [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.

-R — Function reserved.

IENET_RXD2 — Ethernet receive data 2 (MII interface).

I/O GPIO6[5] — General purpose digital input/output pin.

-R — Function reserved.

IT3_CAP3 — Capture input 3 of timer 3.

I/O SD_DAT2 — SD/MMC data bus line 2.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 40 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PC_7 G5 - - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.

-R — Function reserved.

IENET_RXD3 — Ethernet receive data 3 (MII interface).

I/O GPIO6[6] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT0 — Match output 0 of timer 3.

I/O SD_DAT3 — SD/MMC data bus line 3.

PC_8 N4 - - [2] N;

PU -R — Function reserved.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

-R — Function reserved.

IENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface).

I/O GPIO6[7] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT1 — Match output 1 of timer 3.

ISD_CD — SD/MMC card detect input.

PC_9 K2 - - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal

from the PHY.

-R — Function reserved.

IENET_RX_ER — Ethernet receive error (MII interface).

I/O GPIO6[8] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT2 — Match output 2 of timer 3.

OSD_POW — SD/MMC power monitor output.

PC_10 M5 - - [2] N;

PU -R — Function reserved.

OUSB1_ULPI_STP — ULPI link STP signal. Asserted to end or

interrupt transfers to the PHY.

IU1_DSR — Data Set Ready input for UART 1.

-R — Function reserved.

I/O GPIO6[9] — General purpose digital input/output pin.

-R — Function reserved.

OT3_MAT3 — Match output 3 of timer 3.

I/O SD_CMD — SD/MMC command signal.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 41 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PC_11 L5 - - [2] N;

PU -R — Function reserved.

IUSB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI data

line direction.

IU1_DCD — Data Carrier Detect input for UART 1.

-R — Function reserved.

I/O GPIO6[10] — General purpose digital input/output pin.

-R — Function reserved.

I/O SD_DAT4 — SD/MMC data bus line 4.

PC_12 L6 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OU1_DTR — Data Terminal Ready outpu t for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

-R — Function reserved.

I/O GPIO6[11] — General purpose digital input/output pin.

I/O SGPIO11 — General purpose digital input/output pin.

I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

I/O SD_DAT5 — SD/MMC data bus line 5.

PC_13 M1 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OU1_TXD — Transmitter output for UART 1.

-R — Function reserved.

I/O GPIO6[12] — General purpose digital input/output pin.

I/O SGPIO12 — General purpose digital input/output pin.

I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

I/O SD_DAT6 — SD/MMC data bus line 6.

PC_14 N1 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

IU1_RXD — Receiver input for UART 1.

-R — Function reserved.

I/O GPIO6[13] — General purpose digital input/output pin.

I/O SGPIO13 — General purpose digital input/output pin.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O SD_DAT7 — SD/MMC data bus line 7.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 42 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PD_0 N2 - - [2] N;

PU -R — Function reserved.

OCTOUT_15 — SCT output 15. Match output 3 of timer 3.

OEMC_DQMOUT2 — Data mask 2 used with SDRAM and static

devices.

-R — Function reserved.

I/O GPIO6[14] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

PD_1 P1 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CKEOUT2 — SDRAM clock enable 2.

-R — Function reserved.

I/O GPIO6[15] — General purpose digital input/output pin.

OSD_POW — SD/MMC power monitor output.

-R — Function reserved.

I/O SGPIO5 — General purpose digital input/output pin.

PD_2 R1 - - [2] N;

PU -R — Function reserved.

OCTOUT_7 — SCT output 7. Matc h ou tp ut 3 of timer 1.

I/O EMC_D16 — External memory data line 16.

-R — Function reserved.

I/O GPIO6[16] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO6 — General purpose digital input/output pin.

PD_3 P4 - - [2] N;

PU -R — Function reserved.

OCTOUT_6 — SCT output 7. Matc h ou tp ut 2 of timer 1.

I/O EMC_D17 — External memory data line 17.

-R — Function reserved.

I/O GPIO6[17] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO7 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 43 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PD_4 T2 - - [2] N;

PU -R — Function reserved.

OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.

I/O EMC_D18 — External memory data line 18.

-R — Function reserved.

I/O GPIO6[18] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO8 — General purpose digital input/output pin.

PD_5 P6 - - [2] N;

PU -R — Function reserved.

OCTOUT_9 — SCT output 9. Matc h ou tp ut 3 of timer 3.

I/O EMC_D19 — External memory data line 19.

-R — Function reserved.

I/O GPIO6[19] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO9 — General purpose digital input/output pin.

PD_6 R6 - 68 [2] N;

PU -R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

I/O EMC_D20 — External memory data line 20.

-R — Function reserved.

I/O GPIO6[20] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO10 — General purpose digital input/output pin.

PD_7 T6 - 72 [2] N;

PU -R — Function reserved.

ICTIN_5 — SCT input 5. Capture input 2 of timer 2.

I/O EMC_D21 — External memory data line 21.

-R — Function reserved.

I/O GPIO6[21] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO11 — General purpose digital input/output pin.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 44 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PD_8 P8 - 74 [2] N;

PU -R — Function reserved.

ICTIN_6 — SCT input 6. Capture input 1 of timer 3.

I/O EMC_D22 — External memory data line 22.

-R — Function reserved.

I/O GPIO6[22] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO12 — General purpose digital input/output pin.

PD_9 T11 - 84 [2] N;

PU -R — Function reserved.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

I/O EMC_D23 — External memory data line 23.

-R — Function reserved.

I/O GPIO6[23] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO13 — General purpose digital input/output pin.

PD_10 P11 - 86 [2] N;

PU -R — Function reserved.

ICTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of

timer 2.

OEMC_BLS3 — LOW active Byte Lane select signal 3.

-R — Function reserved.

I/O GPIO6[24] — General purpose digital input/output pin.

-R — Function reserved.

PD_11 N9 M7 88 [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CS3 — LOW active Chip Select 3 signal.

-R — Function reserved.

I/O GPIO6[25] — General purpose digital input/output pin.

I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 45 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PD_12 N11 P9 94 [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_CS2 — LOW active Chip Select 2 signal.

-R — Function reserved.

I/O GPIO6[26] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_10 — SCT output 10. Match output 3 of timer 3.

-R — Function reserved.

PD_13 T14 - 97 [2] N;

PU -R — Function reserved.

ICTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.

OEMC_BLS2 — LOW active Byte Lane select signal 2.

-R — Function reserved.

I/O GPIO6[27] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_13 — SCT output 13. Match output 3 of timer 3.

-R — Function reserved.

PD_14 R13 L11 99 [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_DYCS2 — SDRAM chip select 2.

-R — Function reserved.

I/O GPIO6[28] — General purpose digital input/output pin.

-R — Function reserved.

OCTOUT_11 — SCT output 11. Match output 3 of timer 2.

-R — Function reserved.

PD_15 T15 P13 101 [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A17 — External memory address line 17.

-R — Function reserved.

I/O GPIO6[29] — General purpose digital input/output pin.

ISD_WP — SD/MMC card write protect input.

OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 46 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PD_16 R14 P12 104 [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A16 — External memory address line 16.

-R — Function reserved.

I/O GPIO6[30] — General purpose digital input/output pin.

OSD_VOLT2 — SD/MMC bus voltage select output 2.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

-R — Function reserved.

PE_0 P14 N12 106 [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A18 — External memory address line 18.

I/O GPIO7[0] — General purpose digital input/output pin.

OCAN1_TD — CAN1 transmitter output.

-R — Function reserved.

PE_1 N14 M12 112 [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O EMC_A19 — External memory address line 19.

I/O GPIO7[1] — General purpose digital input/output pin.

ICAN1_RD — CAN1 receiver input.

-R — Function reserved.

PE_2 M14 L12 115 [2] N;

PU IADCTRIG0 — ADC trigger input 0.

ICAN0_RD — CAN receiver input.

-R — Function reserved.

I/O EMC_A20 — External memory address line 20.

I/O GPIO7[2] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 47 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PE_3 K12 K10 118 [2] N;

PU -R — Function reserved.

OCAN0_TD — CAN transmitter output.

IADCTRIG1 — ADC trigger input 1.

I/O EMC_A21 — External memory address line 21.

I/O GPIO7[3] — General purpose digital input/output pin.

-R — Function reserved.

PE_4 K13 J11 120 [2] N;

PU -R — Function reserved.

INMI — External interrupt input to NMI.

-R — Function reserved.

I/O EMC_A22 — External memory address line 22.

I/O GPIO7[4] — General purpose digital input/output pin.

-R — Function reserved.

PE_5 N16 - 122 [2] N;

PU -R — Function reserved.

OCTOUT_3 — SCT output 3. Matc h ou tp ut 3 of timer 0.

OU1_RTS — Request to Send output for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

I/O EMC_D24 — External memory data line 24.

I/O GPIO7[5] — General purpose digital input/output pin.

-R — Function reserved.

PE_6 M16 - 124 [2] N;

PU -R — Function reserved.

OCTOUT_2 — SCT output 2. Matc h ou tp ut 2 of timer 0.

IU1_RI — Ring Indicator input for UART 1.

I/O EMC_D25 — External memory data line 25.

I/O GPIO7[6] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 48 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PE_7 F15 - 149 [2] N;

PU -R — Function reserved.

OCTOUT_5 — SCT output 5. Matc h ou tp ut 3 of timer 3.

IU1_CTS — Clear to Send input for UART1.

I/O EMC_D26 — External memory data line 26.

I/O GPIO7[7] — General purpose digital input/output pin.

-R — Function reserved.

PE_8 F14 - 150 [2] N;

PU -R — Function reserved.

OCTOUT_4 — SCT output 4. Matc h ou tp ut 3 of timer 3.

IU1_DSR — Data Set Ready input for UART 1.

I/O EMC_D27 — External memory data line 27.

I/O GPIO7[8] — General purpose digital input/output pin.

-R — Function reserved.

PE_9 E16 - 152 [2] N;

PU -R — Function reserved.

ICTIN_4 — SCT input 4. Capture input 2 of timer 1.

IU1_DCD — Data Carrier Detect input for UART 1.

I/O EMC_D28 — External memory data line 28.

I/O GPIO7[9] — General purpose digital input/output pin.

-R — Function reserved.

PE_10 E14 - 154 [2] N;

PU -R — Function reserved.

ICTIN_3 — SCT input 3. Capture input 1 of timer 1.

OU1_DTR — Data Terminal Ready outpu t for UART 1. Can also be

configured to be an RS-485/EIA-485 output enable signal for UART

I/O EMC_D29 — External memory data line 29.

I/O GPIO7[10] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 49 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PE_11 D16 - - [2] N;

PU -R — Function reserved.

OCTOUT_12 — SCT output 12. Match output 3 of timer 3.

OU1_TXD — Transmitter output for UART 1.

I/O EMC_D30 — External memory data line 30.

I/O GPIO7[11] — General purpose digital input/output pin.

-R — Function reserved.

PE_12 D15 - - [2] N;

PU -R — Function reserved.

OCTOUT_11 — SCT output 11. Match output 3 of

timer 2.

IU1_RXD — Receiver input for UART 1.

I/O EMC_D31 — External memory data line 31.

I/O GPIO7[12] — General purpose digital input/output pin.

-R — Function reserved.

PE_13 G14 - - [2] N;

PU -R — Function reserved.

OCTOUT_14 — SCT output 14. Match output 2 of timer 3.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

OEMC_DQMOUT3 — Data mask 3 used with SDRAM and static

devices.

I/O GPIO7[13] — General purpose digital input/output pin.

-R — Function reserved.

PE_14 C15 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

OEMC_DYCS3 — SDRAM chip select 3.

I/O GPIO7[14] — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 50 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PE_15 E13 - - [2] N;

PU -R — Function reserved.

OCTOUT_0 — SCT output 0. Matc h ou tp ut 0 of timer 0.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

OEMC_CKEOUT3 — SDRAM clock enable 3.

I/O GPIO7[15] — General purpose digital input/output pin.

-R — Function reserved.

PF_0 D12 - 159 [2] O;

PU I/O SSP0_SCK — Serial clock for SSP0.

IGP_CLKIN — General purpose clock input to the CGU.

-R — Function reserved.

OI2S1_TX_MCLK — I2S1 transmit master clock.

PF_1 E11 - - [2] N;

PU -R — Function reserved.

-R — Function reserved.

I/O SSP0_SSEL — Slave Select for SSP0.

-R — Function reserved.

I/O GPIO7[16] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO0 — General purpose digital input/output pin.

-R — Function reserved.

PF_2 D11 - 168 [2] N;

PU -R — Function reserved.

OU3_TXD — Transmitter output for USART3.

I/O SSP0_MISO — Master In Slave Out for SSP0.

-R — Function reserved.

I/O GPIO7[17] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO1 — General purpose digital input/output pin.

-R — Function reserved.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 51 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PF_3 E10 - 170 [2] N;

PU -R — Function reserved.

IU3_RXD — Receiver input for USART3.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

-R — Function reserved.

I/O GPIO7[18] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO2 — General purpose digital input/output pin.

-R — Function reserved.

PF_4 D10 L8 172 [2] O;

PU I/O SSP1_SCK — Serial clock for SSP1.

IGP_CLKIN — General purpose clock input to the CGU.

OTRACECLK — Trace clock.

-R — Function reserved.

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

PF_5 E9 - 190 [5] N;

PU -R — Function reserved.

I/O U3_UCLK — Serial clock input/output for USART3 in synchronous

mode.

I/O SSP1_SSEL — Slave Select for SSP1.

OTRACEDATA[0] — Trace data, bit 0.

I/O GPIO7[19] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO4 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC1_4 — ADC1, input channel 4. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 52 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PF_6 E7 - 192 [5] N;

PU -R — Function reserved.

I/O U3_DIR — RS-485/EIA-485 output enable/direction control for

USART3.

I/O SSP1_MISO — Master In Slave Out for SSP1.

OTRACEDATA[1] — Trace data, bit 1.

I/O GPIO7[20] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO5 — General purpose digital input/output pin.

I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter

and read by the receiver . Corresponds to the signal SD in the I2S-bus

specification.

AI ADC1_3 — ADC1, input channel 3. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PF_7 B7 - 193 [5] N;

PU -R — Function reserved.

I/O U3_BAUD — Baud pin for USART3.

I/O SSP1_MOSI — Master Out Slave in for SSP1.

OTRACEDATA[2] — Trace data, bit 2.

I/O GPIO7[21] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO6 — General purpose digital input/output pin.

I/O I2S1_TX_WS — T ransmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

AI/

OADC1_7 — ADC1, input channel 7 or band gap output. Configure the

pin as GPIO input and use the ADC function select register in the

SCU to select the ADC.

PF_8 E6 - - [5] N;

PU -R — Function reserved.

I/O U0_UCLK — Serial clock input/output for USART0 in synchronous

mode.

ICTIN_2 — SCT input 2. Capture input 2 of timer 0.

OTRACEDATA[3] — Trace data, bit 3.

I/O GPIO7[22] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO7 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC0_2 — ADC0, input channel 2. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 53 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

PF_9 D6 - 203 [5] N;

PU -R — Function reserved.

I/O U0_DIR — RS-485/EIA-485 output enable/direction control for

USART0.

OCTOUT_1 — SCT output 1. Matc h ou tp ut 3 of timer 3.

-R — Function reserved.

I/O GPIO7[23] — General purpose digital input/output pin.

-R — Function reserved.

I/O SGPIO3 — General purpose digital input/output pin.

-R — Function reserved.

AI ADC1_2 — ADC1, input channel 2. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PF_10 A3 - 205 [5] N;

PU -R — Function reserved.

OU0_TXD — Transmitter output for USART0.

-R — Function reserved.

I/O GPIO7[24] — General purpose digital input/output pin.

-R — Function reserved.

ISD_WP — SD/MMC card write protect input.

-R — Function reserved.

AI ADC0_5 — ADC0, input channel 5. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

PF_11 A2 - 207 [5] N;

PU -R — Function reserved.

IU0_RXD — Receiver input for USART0.

-R — Function reserved.

I/O GPIO7[25] — General purpose digital input/output pin.

-R — Function reserved.

OSD_VOLT2 — SD/MMC bus voltage select output 2.

-R — Function reserved.

AI ADC1_5 — ADC1, input channel 5. Configure the pin as GPIO input

and use the ADC function select register in the SCU to select the

ADC.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 54 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Clock pins

CLK0 N5 M4 62 [4] O;

PU OEMC_CLK0 — SDRAM clock 0.

OCLKOUT — Clock output pin.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

OEMC_CLK01 — SDRAM clock 0 and clock 1 combined .

I/O SSP1_SCK — Serial clock for SSP1.

IENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII

interface) or Ethernet Reference Clock (RMII interface).

CLK1 T10 - - [4] O;

PU OEMC_CLK1 — SDRAM clock 1.

OCLKOUT — Clock output pin.

-R — Function reserved.

OCGU_OUT0 — CGU spare clock output 0.

-R — Function reserved.

OI2S1_TX_MCLK — I2S1 transmit master clock.

CLK2 D14 P10 141 [4] O;

PU OEMC_CLK3 — SDRAM clock 3.

OCLKOUT — Clock output pin.

-R — Function reserved.

I/O SD_CLK — SD/MMC card clock.

OEMC_CLK23 — SDRAM clock 2 and clock 3 combined .

OI2S0_TX_MCLK — I2S transmit master clock.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

CLK3 P12 - - [4] O;

PU OEMC_CLK2 — SDRAM clock 2.

OCLKOUT — Clock output pin.

-R — Function reserved.

OCGU_OUT1 — CGU spare clock output 1.

-R — Function reserved.

I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the I2S-bus

specification.

Debug pins

DBGEN L4 K4 41 [2] I I JTAG interface control signal. Also used for boundary scan.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 55 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

TCK/SWDCLK J5 G5 38 [2] I; F I Test Clock for JTAG interface (default) or Serial Wire (SW) clock.

TRST M4 L4 42 [2] I; PU I Test Reset for JTAG interface.

TMS/SWDIO K6 K5 44 [2] I; PU I Test Mode Select for JTAG interface (default) or SW debug data

input/output.

TDO/SWO K5 J5 46 [2] O O Test Data Out for JTAG interface (default) or SW trace output.

TDI J4 H4 35 [2] I; PU I Test Data In for JTAG interface.

USB0 pins

USB0_DP F2 E2 26 [6] - I/O USB0 bidirectional D+ line.

USB0_DM G2 F2 28 [6] - I/O USB0 bidirectional D line.

USB0_VBUS F1 E1 29 [6]

[7] - I/O VBUS pin (power on USB cable). This pin includes an internal

pull-down resistor of 64 k (typical)  16 k.

USB0_ID H2 G2 30 [8] - I Indicate s to the transceiver whether connected as an A-device

(USB0_ID LOW) or B-device (U SB0_ID HIGH). For OT G this pin has

an internal pull-up resistor.

USB0_RREF H1 G1 32 [8] - 12.0 k (accuracy 1 %) on-board resistor to ground for curren t

reference.

USB1 pins

USB1_DP F12 D11 129 [9] - I/O USB1 bidirectional D+ line.

USB1_DM G12 E11 130 [9] - I/O USB1 bidirectional D line.

I2C-bus pins

I2C0_SCL L15 K13 132 [10] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus compliance).

I2C0_SDA L16 K14 133 [10] I; F I/O I2C data input/output. Open-drain output (for I2C-bus compliance).

Reset and wake-up pins

RESET D9 B7 185 [11] I; IA I External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at ad dress 0.

WAKEUP0 A9 A9 187 [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a duration of

at least 45 ns wakes up the part.

Input 0 of the ev ent monitor.

WAKEUP1 A10 C8 - [11] I; IA I External wake-up inp ut; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a duration of

at least 45 ns wakes up the part.

Input 1 of the ev ent monitor.

WAKEUP2 C9 E5 - [11] I; IA I External wake-up inp ut; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a duration of

at least 45 ns wakes up the part.

Input 2 of the ev ent monitor.

WAKEUP3 D8 - - [11] I; IA I External wake-up input; can raise an interrupt and can cause

wake-up from any of the low power modes. A pulse with a duration of

at least 45 ns wakes up the part.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 56 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

ADC pins

ADC0_0/

ADC1_0/DAC E3 B6 8 [8] I; IA I ADC input channel 0. Shared between 10-bit ADC0/1 and DAC.

ADC0_1/

ADC1_1 C3 C4 4 [8] I; IA I ADC input channel 1. Shared between 10-bit ADC0/1.

ADC0_2/

ADC1_2 A4 B3 206 [8] I; IA I ADC input channel 2. Shared between 10-bit ADC0/1.

ADC0_3/

ADC1_3 B5 B4 200 [8] I; IA I ADC input channel 3. Shared between 10-bit ADC0/1.

ADC0_4/

ADC1_4 C6 A5 199 [8] I; IA I ADC input channel 4. Shared between 10-bit ADC0/1.

ADC0_5/

ADC1_5 B3 C3 208 [8] I; IA I A DC input channel 5. Shared between 10-bit ADC0/1.

ADC0_6/

ADC1_6 A5 A4 204 [8] I; IA I ADC input channel 6. Shared between 10-bit ADC0/1.

ADC0_7/

ADC1_7 C5 B5 197 [8] I; IA I ADC input channel 7. Shared between 10-bit ADC0/1.

RTC

RTC_ALARM A11 A10 186 [11] - O RTC controlled output.

RTCX1 A8 A8 182 [8] - I Input to the RTC 32 kHz ultra-low power oscillator circuit.

RTCX2 B8 A7 183 [8] - O Output from the RTC 32 kHz ultra-low power oscillator circuit.

SAMPLE B9 B8 - [11] O O Event monitor sample output.

Crystal oscillator pins

XTAL1 D1 C1 18 [8] - I Input to the oscillator circuit and internal clock generator circuits.

XTAL2 E1 D1 19 [8] - O Output from the oscillator amplifier.

Power and ground pins

USB0_VDDA

3V3_DRIVER F3 E3 24 - - Separate analog 3.3 V power supply for driver.

USB0

_VDDA3V3 G3 F3 25 - - USB 3.3 V separate power supply voltage.

USB0_VSSA

_TERM H3 G3 27 - - Dedicated analog ground for clean reference for terminati on

resistors.

USB0_VSSA

_REF G1 F1 31 - - Dedicated clean analog ground for generation of reference currents

and voltages.

VDDA B4 A6 198 - - Analog power supply and ADC reference voltage.

VBAT B10 B9 184 - - RTC power supply: 3.3 V on this pin supplies power to the RTC.

VDDREG F10,

F9,

L8,

D8,

E8 135,

188,

195,

82,

- Main regulator power supply. Tie the VDDREG and VDDIO pins to a

common power supply to ensure the same ramp-up time for both

supply voltages.

VPP E8 - - [12] - - OTP programming voltage.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 57 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in

the SFS register to enable the input buffer; I = input, OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA

= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset

without boot code operation.

[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength.

[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels, and hysteresis; high dr ive strength.

[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed

digital I/O functions with TTL levels and hysteresis.

[5] 5 V tolerant pad providing digit al I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;

if VDDIO not present, do not exceed 3.6 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital

section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP

VDDIO D7,

E12,

F7,

F8,

G10,

H10,

J6,

J7,

K7,

L9,

L10,

N7,

N13

H5,

H10,

52,

57,

102,

110,

155,

160,

202

[12] - - I/O power supply. Ti e the VDDR EG and VDDIO pins to a common

power supply to ensure the same ramp-up time for both supply

voltages.

VSS G9,

H7,

J10,

J11,

F10,

G10,

D7,

E6,

E7,

E9,

K6,

-[13] - - Ground.

VSSIO C4,

D13,

G6,

G7,

G8,

H8,

H9,

J8,

J9,

K9,

K10,

M13,

P7,

P13

-5,

56,

109,

157

[13] - - Ground.

VSSA B2 A3 196 - - Analog ground.

Table 3. Pin description …continued

Pin name

LBGA256

TFBGA180

LQFP208

Reset state

[1]

Type

Description

Objective data sheet Rev. 1 — 4 June 2012 58 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[6] 5 V tolerant transparent analog pad.

[7] For maximum load CL = 6.5 F and maximum resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS

= 0.2 V when it is no longer driven.

[8] Transparent analog pad. Not 5 V tolerant.

[9] Pad provides USB functions; 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with

the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[12] On the LQFP208 and TFBGA180 packages, VPP is internally connected to VDDIO.

[13] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane.

Objective data sheet Rev. 1 — 4 June 2012 59 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus,

and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and

data accesses from different slave ports.

The LPC4357/53 u se a multi-la ye r AHB matr ix to conn ect the ARM Cortex-M4 buses and

other bus mast er s to pe riphe r als in a fle xible ma nn e r that op tim i ze s perfo rm a nc e by

allowing peripherals that are on different slaves ports of the matrix to be accessed

simultaneously by different bus masters.

An ARM Cortex-M0 co-processor is included in the LPC4357/53, capable of off-loading

the main ARM Cortex-M4 application processor . Most peripheral interrupts are connected

to both processors. The processors communicate with each other via an interprocessor

communication protocol.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture

with separate local instruction and dat a buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supp or ts single -cy cle dig ital signal processing and SIMD instructions. A

hardware floating-point processor is integrated in the core. The processor includes a

NVIC with up to 53 interrupts.

7.3 ARM Cortex-M0 co-processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Co rtex-M0 co -proce ssor uses a

3-stage pipeline von Neumann architecture and a small but powerful instruction set

providing high-end processing hardware. The co-processor incorporates a NVIC with 32

interrupts.

7.4 Interprocessor communication

The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on

using shared SRAM as mailbox and one processor raising an interrupt on the other

processor's NVIC, for example after it has delivered a new message in the mailbox. The

receiving processor can reply by raising an interrupt on the sending processor's NVIC to

acknowledge the message.

Objective data sheet Rev. 1 — 4 June 2012 60 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

7.5 AHB multilayer matrix

7.6 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral p art of the Cortex-M4. The tight co upling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most

peripheral interrupts are shared between the Cortex-M 0 and Cortex-M4 NVICs.

7.6.1 Features

•Controls system exceptions and peripheral interrupts.

Fig 5. AHB multilaye r matrix master and slave connections

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

DMA ETHERNET USB1USB0 LCD SD/

MMC

EXTERNAL

MEMORY

CONTROLLER

APB, RTC

DOMAIN

PERIPHERALS

HIGH-SPEED PHY

System

bus

I-

code

bus

D-

code

bus

masters

AHB MULTILAYER MATRIX

= master-slave connection

AHB PERIPHERALS

INTERFACES

002aah080

32 kB AHB SRAM

16 kB AHB SRAM

slaves

64 kB ROM

32 kB LOCAL SRAM

40 kB LOCAL SRAM

256/512 kB FLASH A

256/512 kB FLASH B

16 kB EEPROM

Objective data sheet Rev. 1 — 4 June 2012 61 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

•The Cortex-M4 NVIC supports up to 53 vectored interrupts.

•Eight programmable interrupt priority levels with hardware priority level masking.

•Relocatable vector table.

•Non-Maskable Interrupt (NMI).

•Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.7 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.8 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event

router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,

Deep-sleep, Power-down, and Deep power-down modes. Individual events can be

configured as edge or level sensitive and can be enabled or disabled in the event router.

The event router can be battery powered.

The following events if enabled in the event router can create a wake-up signal from

sleep, deep-sleep, power-down, and deep powe r-down modes and/or create an interrupt:

•External pins WAKEUP0/1/2/3 and RESET

•Alarm timer, RTC (32 kHz oscillator running)

The following events if enabled in the event router can create a wa ke-up signal from sleep

mode only and/or create an interrupt:

•WWDT, BOD interrupts

•C_CAN0/1 and QEI interrupts

•Ethernet, USB0, USB1 signals

•Selected outputs of combined timers (SCT and timer0/1/3)

Remark: Any interrupt can wake up the ARM Cortex-M4 fro m sleep mode if enabled in

the NVIC.

7.9 Global Input Multiplexer Array (GIMA)

The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,

event router, or the ADCs.

7.9.1 Features

•Single selection of a source.

•Signal inversion.

Objective data sheet Rev. 1 — 4 June 2012 62 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

•Can capture a pulse if the input event source is faster than the target clock.

•Synchronization of input event and target clock.

•Single-cycle pulse generation for target.

7.10 On-chip static RAM

The LPC4357/53 support up to136 kB SRAM with separate bus master access for higher

throughput and individual power control for low power operation.

7.11 On-chip flash memory

The LPC4 35 7/53 co ntain up to 1 MB o f dua l-b an k flash pr og ram me mor y. With dual-bank

flash memory, the user code can write or erase one flash bank while reading the other

flash bank without interruption. A two-port flash accelerator maximizes the flash

performance.

In-System Programming (ISP) and In-Application Programming (IAP) routines for

programming the flash memory are provided in the Boot ROM.

7.12 EEPROM

The LPC4357/53 contain up to 16 kB of on-chip byte-erasable and byte-programmable

EEPROM memory.

The EEPROM memory is divided into 128 pages. The user can access pages 1 through

127. Page 128 is protected.

7.13 Boot ROM

The internal ROM memory is used to store the bo ot code of the LPC4357/53. After a

reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

•The ROM memory size is 64 kB.

•Supports booting from external st atic memory such as NOR flash, SPI flash, quad SPI

flash, USB0, and USB1.

•Includes API for OTP programming.

•Includes a flexible USB device stack that supports Human Interfac e Device (HID),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

AES capable parts also support:

•CMAC authentication on the boot image.

•Secure booting from an encrypted image. In development mode booting from a plain

text image is possible. Development mode is terminated by programming the AES

key.

•API for AES programming.

Objective data sheet Rev. 1 — 4 June 2012 63 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Several boot modes are available if P2_ 7 is LOW on reset depe nding on the values of the

OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bit s are

all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2,

and P1_1.

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

Table 4. Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC

bit 3 BOOT_SRC

bit 2 BOOT_SRC

bit 1 BOOT_SRC

bit 0 Description

Pin state 0 0 0 0 Boot source is defined by the re set state of P1_1,

P1_2, P2_8 pins , an d P2 _9 . Se e Table 5.

USART0 0 0 0 1 Enter ISP mode using USART0 pins P2_0 and

P2_1.

SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI

interface using pins P3_3 to P3_8.

EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

USB0011 0Boot from USB0.

USB1011 1Boot from USB1.

SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0

interface on P3_3 (fu nction SSP0_SCK), P3_6

(function SSP0_MISO), P3_7 (function

SSP0_MOSI), and P3_8 (function SSP0_SSEL)[1].

USART3 1 0 0 1 Enter ISP mode using USART3 pins P2_3 and

P2_4.

Table 5. Boot mode when OPT BOOT_SRC bits are zero

Boot mode Pins Description

P2_9 P2_8 P1_2 P1_1

USART0 LOW LOW LOW LOW Enter ISP mode using USART0 pins P2_0 and

P2_1.

SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI

interface on P3_3 to P3_8[1].

EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

USB0 LOW HIGH LOW HIGH Boot from USB0

Objective data sheet Rev. 1 — 4 June 2012 64 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.

7.14 Memory mapping

The memory map shown in Figure 6 and Figure 7 is glo bal to both the Cortex-M4 and the

Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between

both processors. Each processor uses its own ARM private bus memory map for the

NVIC and other system functions.

USB1 LOW HIGH HIGH LOW Boot from USB1.

SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0

interface on P3_3 (function SSP0_SCK), P3_6

(function SSP0_MISO), P3_7 (function

SSP0_MOSI), and P3_8 (function SSP0_SSEL)[1].

USART3 HIGH LOW LOW LOW Enter ISP mode using USART3 pins P2_3 and

P2_4.

Table 5. Boot mode when OPT BOOT_SRC bits are zero

Boot mode Pins Description

P2_9 P2_8 P1_2 P1_1

Objective data sheet Rev. 1 — 4 June 2012 65 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 6. LPC4357/53 Memory mapping (overview)

reserved

peripheral bit band alias region

reserved

high-speed GPIO

reserved

0x0000 0000

0 GB

1 GB

4 GB

0x2200 0000

0x2400 0000

0x2800 0000

0x1000 0000

0x3000 0000

0x4000 0000

0x4001 2000

0x4004 0000

0x4005 0000

0x4010 0000

0x4400 0000

0x6000 0000

AHB peripherals

APB peripherals #0

APB peripherals #1

reserved

RTC domain peripherals

0x4006 0000

0x4008 0000

0x4009 0000

0x400A 0000

0x400B 0000

0x400C 0000

0x400D 0000

0x400E 0000

0x400F 0000

0x400F 1000

0x400F 2000

0x400F 4000

0x400F 8000

clocking/reset peripherals

APB peripherals #2

APB peripherals #3

0x2004 0000

4 x 16 kB AHB SRAM

0x2004 4000

16 kB EEPROM

SGPIO

SPI

0x4010 1000

0x4010 2000

0x4200 0000

reserved

local SRAM/

external static memory banks

0x2000 0000

0x2001 0000

128 MB dynamic external memory DYCS0

256 MB dynamic external memory DYCS1

256 MB dynamic external memory DYCS2

256 MB dynamic external memory DYCS3 0x7000 0000

0x8000 0000

0x8800 0000

0xE000 0000

256 MB shadow area

LPC4357/53

reserved

32 MB AHB SRAM bit banding

reserved

0xE010 0000

0xFFFF FFFF

reserved

128 MB SPIFI data

ARM private bus

reserved

002aah081

reserved

0x1000 0000

0x1000 8000

0x1008 0000

0x1008 A000

0x1040 0000

0x1041 0000

0x1C00 0000

0x1D00 0000

32 kB local SRAM

32 kB + 8 kB local SRAM

reserved

64 kB ROM

0x1E00 0000

0x1F00 0000

0x2000 0000

16 MB static external memory CS3

16 MB static external memory CS2

16 MB static external memory CS1

16 MB static external memory CS0

0x1400 0000

0x1800 0000

0x1A00 0000 256 kB flash A (LPC4357/53)

0x1A04 0000 256 kB flash A (LPC4357)

0x1A08 0000

0x1B00 0000 256 kB flash B (LPC4357/53)

0x1B04 0000 256 kB flash B (LPC4357)

0x1B08 0000

64 MB SPIFI data

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Objective data sheet Rev. 1 — 4 June 2012 66 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 7. LPC4357/53 Memory mapping (peripherals)

reserved

peripheral bit band alias region

high-speed GPIO

reserved

0x4000 0000

0x0000 0000

0x1000 0000

0x4002 0000

0x4004 0000

0x4005 0000

0x4010 0000

0x4400 0000

0x6000 0000

0xFFFF FFFF

AHB peripherals

APB0 peripherals

APB1 peripherals

reserved

RTC domain peripherals

0x4006 0000

0x4008 0000

0x4009 0000

0x400A 0000

0x400B 0000

0x400C 0000

0x400D 0000

0x400E 0000

0x400F 0000

0x400F 1000

0x400F 2000

0x400F 4000

0x400F 8000

clocking/reset peripherals

APB2 peripherals

APB3 peripherals

SGPIO

SPI

0x4010 1000

0x4010 2000

0x4200 0000

reserved

external memories and

ARM private bus

APB2

peripherals

0x400C 1000

0x400C 2000

0x400C 3000

0x400C 4000

0x400C 6000

0x400C 8000

0x400C 7000

0x400C 5000

0x400C 0000 RI timer

USART2

USART3

timer2

timer3

SSP1

QEI

APB1

peripherals

0x400A 1000

0x400A 2000

0x400A 3000

0x400A 4000

0x400A 5000

0x400B 0000

0x400A 0000 motor control PWM

I2C0

I2S0

I2S1

C_CAN1

reserved

AHB

peripherals

0x4000 1000

0x4000 0000

SCT

0x4000 2000

0x4000 3000

0x4000 4000

0x4000 6000

0x4000 8000

0x4001 0000

0x4001 2000

0x4002 0000

0x4000 9000

0x4000 7000

0x4000 5000

DMA

SD/MMC

EMC

USB1

LCD

USB0

reserved

SPIFI

ethernet

reserved

0x4008 1000

0x4008 0000 WWDT

0x4008 2000

0x4008 3000

0x4008 4000

0x4008 6000

0x4008 A000

0x4008 7000

0x4008 8000

0x4008 9000

0x4008 5000

UART1 w/ modem

SSP0

timer0

timer1

SCU

GPIO interrupts

GPIO GROUP0 interrupt

GPIO GROUP1 interrupt

USART0

RTC domain

peripherals

0x4004 1000

0x4004 0000

alarm timer

0x4004 2000

0x4004 3000

0x4004 4000

0x4004 6000

0x4004 7000

0x4005 0000

0x4004 5000

power mode control

CREG

event router

OTP controller

reserved

RTC/event monitor

backup registers

clocking

reset control

peripherals

0x4005 1000

0x4005 0000

CGU

0x4005 2000

0x4005 3000

0x4005 4000

0x4006 0000

CCU2

RGU

CCU1

LPC4357/53

002aah082

reserved

APB3

peripherals

0x400E 1000

0x400E 2000

0x400E 3000

0x400E 4000

0x400F 0000

0x400E 5000

0x400E 0000 I2C1

DAC

C_CAN0

ADC0

ADC1

reserved

GIMA

APB0

peripherals

256 MB memory shadow area

SRAM, flash, EEPROM memories

external memory banks

0x4000 C000

0x4000 D000

reserved

flash A controller

flash B controller

0x4000 E000

0x4000 F000

EEPROM controller

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7.15 Security features

7.15.1 AES decryption

The hardware AES decryption can decode data using the AES algorithm using a 128-bit

key.

Remark: Once an AES key is programme d, no future factory testing can be performed on

this device.

7.15.1.1 Features

•Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI),

EMC, or the USB0/1 interfaces.

•Secure storage of keys.

•Support for CMAC hash calculation to authenticate encrypted data.

•Data is processed in little endian mode. This means that the first byte read from flash

is integrated into the AES codeword as least significant byte. The 16th byte read from

flash is the most significant byte of the first AES codeword.

•AES engine performance of 1 byte/clock cycle.

•DMA transfers supp or te d th ro ug h the GPD M A.

7.15.2 One-Time Programmable (OTP) memory

The OTP provides 128 bit o f memory for genera l purpose use and two 128- bit non-volatile

memories to store AES keys or other custom data.

7.16 General Purpose I/O (GPIO)

The LPC4357/53 provide eight GPIO ports with up to 31 GPIO pins each.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any nu mber of outp uts simultan eou sly. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on

reset. The input buffer must be turned on in the system control block SFS register before

the GPIO input can be read.

7.16.1 Features

•Accelerated GPIO functions:

–GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

–Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

–All GPIO registers are byte and half-word addressable.

–Entire port value can be written in one instruction.

•Bit-level set and clear r egisters allow a single instruction set or clear of any num ber of

bits in one port.

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32-bit ARM Cortex-M4/M0 microcontroller

•Direction control of individual bits.

•Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request (GPIO interrupts).

•Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO

group0 and group1 interrupts).

7.17 Configurable digital peripherals

7.17.1 State Configurable Timer (SCT) subsystem

The SCT allows a wide variety of timing, countin g, ou tp u t mo du lat ion , an d inp u t captu re

operations. The inputs and outputs of the SCT are shared with the capture and match

inputs/outputs of the 32-bit gen er al purp ose counter/tim er s.

The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the

two-counter case, in addition to the counter value the following operational element s are

independent for each half:

•State variable

•Limit, halt, stop, and start conditions

•Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT, but the

last three can use match conditions from either counter:

•Clock selection

•Inputs

•Events

•Outputs

•Interrupts

7.17.1.1 Features

•Two 16-bit counters or one 32-bit counter.

•Counters clocked by bus clock or selected input.

•Counters can be configured as up-counters or up-down counters.

•State variable allows sequencing across multiple counter cycles.

•Event combines input or output condition and/or counter match in a specified sta te.

•Events control outputs and interrupts.

•Selected events can limit, halt, start, or stop a counter.

•Supports:

–up to 8 inputs

–16 outputs

–16 match/capture registers

–16 events

–32 states

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32-bit ARM Cortex-M4/M0 microcontroller

7.17.2 Serial GPIO (SGPIO)

The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate

serial stream processing.

7.17.2.1 Features

•Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to

serial data conversion.

•16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value

from a pin or an output value to a pin with every cycle of a shift clock.

•Each slice is double-buffered.

•Interrupt is generated on a full FIFO, shift clock, or pattern match.

•Slices can be concatenated to increase buffer size.

•Each slice has a 32-bit pattern match filter.

7.18 AHB peripherals

7.18.1 General Purpose DMA (GPDMA)

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral- to -p erip he ra l, an d m em o ry- to -me mo ry transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.18.1.1 Features

•Eight DMA channels. Each channel can support a unidirectional transfer.

•16 DMA request lines.

•Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

•Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

periphera l-to -p e riphe ra l tra ns fe rs ar e su pp or te d.

•Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority.

•AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

•Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

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32-bit ARM Cortex-M4/M0 microcontroller

•Internal four-word FIFO per channel.

•Supports 8, 16, and 32-bit wid e tra n sactions.

•Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

•An interrupt to the pr ocessor ca n be gene rate d on a DMA comp letion or when a DMA

error has occurred.

•Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.18.2 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost seria l flash memories to be conn ected to the ARM

Cortex-M4 processor with little perfo rm a nc e pe na lty com pared to parallel flash de vic es

with higher pin count.

After a few commands configure the interface at startup, the enti re flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasing and

programming.

Many serial flash d evices use a half-duplex command-dr iven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.18.2.1 Features

•Interfaces to serial flash memory in the main memory map.

•Supports classic and 4-bit bidir ec tio na l seria l proto co l s.

•Half-duplex protocol compatible with various vendors and devices.

•Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 60 MB per

second.

•Supports DMA access.

7.18.3 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

•Secure Digital memory (SD version 3.0)

•Secure Digital I/O (SDIO version 2.0)

•Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)

•MultiMedia Cards (MMC version 4.4)

7.18.4 External Memory Controller (EMC)

The LPC4357/53 EMC is a Memory Controller peripheral offering support for

asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it

can be used as an interface with off-chip memory-mapped devices and peripherals.

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32-bit ARM Cortex-M4/M0 microcontroller

7.18.4.1 Features

•Dynamic memory interface support including single data rate SDRAM.

•Asynchronous static memory device support including RAM, ROM, and NOR flash,

with or without asynchronous page mode.

•Low transaction latency.

•Read and write buffers to reduce latency and to improve performance.

•8/16/32 data and 24 address lines wide static memory support.

•16 bit and 32 bit wide chip select SDRAM memory support.

•Static memory features include:

–Asynchronous page mode read

–Programmable Wait States

–Bus turnaround delay

–Output enable and write enable delays

–Extended wait

•Four chip selects for synchronous memory and four chip select s for static memory

devices.

•Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to

SDRAMs.

•Dynamic memory self-refresh mode controlled by software.

•Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. Those are typically 512 MB, 256 MB, and

128 MB parts, with 4, 8, 16, or 32 data bits per device.

•Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.18.5 High-speed USB Host/Device/OTG interface (USB0)

The USB OTG module allows the LPC4357/53 to connect directly to a USB Host such as

a PC (in device mode) or to a USB Device in host mode.

7.18.5.1 Features

•Contains UTMI+ compliant high-speed transceiver (PHY).

•Complies with Universal Serial Bus specification 2.0.

•Complies with USB On-The-Go supplement.

•Complies with Enhanced Host Controller Interface Specification.

•Supports auto USB 2.0 mode disc overy.

•Supports all high-speed USB-co mp lia nt per iph er a ls.

•Supports all full-speed USB-compliant peripherals.

•Supports software Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for OTG perip h er als .

•Supports inter ru pts.

•Supports Start Of Frame (SOF) frame length adjust.

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32-bit ARM Cortex-M4/M0 microcontroller

•This module has its own, integrated DMA engine.

•USB interface electrical test software included in ROM USB stack.

7.18.6 High-speed USB Host/Device interface with ULPI (USB1)

The USB1 interface can operate as a full-speed USB Host/Device interface or can

connect to an ext er nal ULPI PHY for Hi gh -s pe ed op erat ion .

7.18.6.1 Features

•Complies with Universal Serial Bus specification 2.0.

•Complies with Enhanced Host Controller Interface Specification.

•Supports auto USB 2.0 mode disc overy.

•Supports all high-speed USB- co mp lia nt per iph er a ls if conn ec te d to exte rn al UL PI

PHY.

•Supports all full-speed USB-compliant peripherals.

•Supports inter ru pts.

•Supports Start Of Frame (SOF) frame length adjust.

•This module has its own, integrated DMA engine.

•USB interface electrical test software included in ROM USB stack.

7.18.7 LCD controller

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be oper ated. The disp lay resolu tion is se lect able a nd can be up to 1024 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other sys te m fu nc tion s. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

7.18.7.1 Features

•AHB master interface to access frame buffer.

•Setup and control via a separate AHB slave interface.

•Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

•Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

•Supports single and dual-panel color STN displays.

•Supports Thin Film Transistor (TFT) color displays.

•Programmable display resolution including, but not limited to: 320 200, 320 240,

640 200, 640 240, 640 480, 800 600, and 1024 768.

•Hardware cursor support for single-panel displays.

•15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

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•1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

•1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

•16 bpp true-color non-palettized for color STN and TFT.

•24 bpp true-color non-palettized for color TFT.

•Programmable timing for different display panels.

•256 entry, 16-b it palette RAM, arr a ng ed as a 12 8 32-bit RAM.

•Frame, line, and pix el cloc k s ign als .

•AC bias signal for STN, data enable signal for TFT panels.

•Supports little and big-endian, and Windows CE data formats.

•LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.18.8 Ethernet

7.18.8.1 Features

•10/100 Mbit/s

•DMA support

•Power management remote wake-up frame and magic packet detection

•Supports both full-duple x an d half- du ple x op er a tion

–Supports CSMA/CD Protocol for half-duplex operation.

–Supports IEEE 802.3x flow control for full-duplex operation.

–Optional forwarding of received pause control frames to the user applica tio n in

full-duplex operation.

–Back-pressure support for half-duplex operation.

–Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-duplex operation.

•Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.19 Digital serial peripherals

7.19.1 UART1

The LPC4357/53 co ntain one UAR T with standard transmit an d receive data lines, UAR T1

also provides a full modem control handshake interface and support for RS-485/9-bit

mode allowing both software address detection and automatic address detection using

9-bit mode.

UART1 includ es a fractional baud r ate generator. S tanda rd baud rates such as 115200 Bd

can be achieved with an y cry s tal frequen cy ab ov e 2 MH z.

7.19.1.1 Features

•Maximum UART data bit rate of 8 MBit/s.

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

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•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

•Equipped with standard modem interface signals. This module also provides full

support for hardware flow control.

•Support for RS-4 85 /9 -b it/EIA-485 mode (UART1).

•DMA support.

7.19.2 USART0/2/3

The LPC4357/53 contain three USARTs. In addition to standard transmit and receive data

lines, the USARTs support a synchro nous mode.

The USARTs include a fractional ba ud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.19.2.1 Features

•Maximum UART data bit rate of 8 MBit/s.

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

•Support for RS-4 85 /9-bit/EIA-485 mode.

•USART3 includes an IrDA mode to support infrared communication.

•All USARTs have DMA support.

•Support for synchronous mode at a data bit rate of up to 8 Mbit/s.

•Smart card mode conforming to ISO7816 specification

7.19.3 SPI serial I/O controller

The LPC4357/53 contain one SPI controller. SPI is a full duplex serial interface designed

to handle multiple masters and slaves connected to a given bus. Only a single master and

a single slave can communicate on the interface during a given data transfer. During a

data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave

always sends 8 bits to 16 bits of data to the master.

7.19.3.1 Features

•Maximum SPI data bit rate <tbd>

•Compliant with SPI specification

•Synchronous, serial, full duplex communication

•Combined SPI master and slave

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•Maximum data bit rate of one eighth of the input clock rate

•8 bits to 16 bits per transfer

7.19.4 SSP serial I/O controller

Remark: The LPC4357/53 contain two SSP controllers.

The SSP controller ca n operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with

multiple masters and slaves on the bus. Only a single master and a single slave can

communicate on the bus during a given data transfer. The SSP supports full duplex

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.19.4.1 Features

•Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

•DMA transfers supp or te d by GPDM A

7.19.5 I2C-bus interface

Remark: The LPC4357/53 each contain two I2C-bus interfaces.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and

can be controlled by more than one bus master connected to it.

7.19.5.1 Features

•I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

•I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with differ ent bit rates to communicate via

one serial bus.

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•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

•All I2C-bus controllers support multiple address recognition and a bus monitor mode.

7.19.6 I2S interface

Remark: The LPC4357/53 each contain two I2S-bus interfaces.

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S-bus connection has one master, which is

always the master, and one slave. The I 2S-bus interface provide s a separate transmit and

receive channel, each of which can operate as either a master or a slave.

7.19.6.1 Features

•The I2S interfaces has separate input/o ut pu t ch an ne ls, each of which ca n op er a te in

master or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

•Mono and stereo audio data supported.

•The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,

96, 192) kHz.

•Support for an aud io ma st er clock.

•Configurable word select period in master mode (separately for I2S-bus input and

output).

•Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

•Generates interrupt requests when buffer levels cross a programmable boundary.

•Two DMA requests controlled by programmable buffer levels. The DMA requests are

connected to the GPDMA block.

•Controls include reset, stop and mute options sep arately for I2S-bus input and I2S-bus

output.

7.19.7 C_CAN

Remark: The LPC4357/53 each contain two C_CAN controllers.

Controller Area Network (CAN) is the definition of a high performance communication

protocol for seri al data communication. The C_ CAN controller is desig ned to provide a full

implement ation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a high level of reliability.

7.19.7.1 Features

•Conforms to protocol version 2.0 parts A and B.

•Supports bit rate of up to 1 Mbit/s.

•Supports 32 Message Objects.

•Each Message Object has its own identifier mask.

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•Provides programmable FIFO mode (concatenation of Message Objects).

•Provides maskable interrupts.

•Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

•Provides programmable loop-back mode for self-test operation.

7.20 Counter/timers and motor control

7.20.1 General purpose 32-bit timers/external event counters

The LPC4357/53 include four 32-bit timer/counters. The timer/counter is designed to

count cycles of the system derived clock or an externally-supplied clock. It can optionally

generate interrupts, generate timed DMA requests, or perform other actions at specified

timer values, based on four match registers. Each timer/counter also includes two capture

inputs to trap the timer value when an input signal transitions, optionally generating an

interrupt.

7.20.1.1 Features

•A 32-bit timer/counter with a programmable 32-bit prescaler.

•Counter or timer op er a tion .

•Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event can also generate an interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

•Up to two match registers can be used to generate timed DMA requests.

7.20.2 Motor control PWM

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback inputs ar e provided to automatically sense rotor position and use

that information to ramp speed up or down. An abort input causes the PWM to release all

motor drive outputs immediately . At the same time, the motor control PWM is highly

configurable for other generalized timing, counting, capture, and compare applications.

7.20.3 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user code can track the position, direction of rotation,

and velocity. In addition, a third channel, or index signal, can b e used to re set the position

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counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.20.3.1 Features

•Tracks encoder position.

•Increments/decrements depending on direction.

•Programmable for 2 or 4 position counting.

•Velocity capture using built-in timer.

•Velocity compare function with “less than” interrupt.

•Uses 32-bit regis ter s for po sitio n an d ve loc ity.

•Three position co mpare registers with interrup ts.

•Index counter for revolution counting.

•Index compare registe r w ith int er ru p ts.

•Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

•Digital filter with programmable delays for encoder input signals.

•Can accept decoded signal inputs (clk and direction).

7.20.4 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 32-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare function can be masked such that they do not contribute to the match

detection. The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.20.4.1 Features

•32-bit counter. Counter can be free-running or be reset by a generated interrupt.

•32-bit compare value.

•32-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This mechanism allows for combinations not possible

with a simple compare.

7.20.5 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.20.5.1 Features

•Internally resets chip if not periodically reloaded during the programmable time-out

period.

•Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

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•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK) uses the IRC as the clock source.

7.21 Analog peripherals

7.21.1 Analog-to-Digital Converter (ADC0/1)

7.21.1.1 Features

•10-bit successive approximation analog to digital converter.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measuremen t ra ng e 0 to VDDA .

•Sampling frequency up to 400 kSamples/s.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer

outputs 8 or 15, or the PWM output MCOA2.

•Individual result registers for each A/D channel to reduce interrupt overhead.

•DMA support.

7.21.2 Digital-to-Analog Converter (DAC)

7.21.2.1 Features

•10-bit resolution

•Monotonic by design (resistor string architecture)

•Controllable conversion speed

•Low power consum ption

7.22 Peripherals in the RTC power domain

7.22.1 RTC

The Real Time Clock (RTC) is a set of counters for measur ing time when system power is

on, and optionally when it is off. It uses little power when the CPU does not access its

registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the

RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own

power supply pin, VBAT.

Objective data sheet Rev. 1 — 4 June 2012 80 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

7.22.1.1 Features

•Measures the passage of time to maintain a calendar and clock. Provides seconds,

minutes, hours, day of month, month, year, day of week, and day of year.

•Ultra-low power design to support battery powered systems. Less than <tbd> required

for battery operation. Uses power from the CPU power supply when it is present.

•Dedicated battery power supply pin.

•RTC power supply is isolated from the rest of the chip.

•Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.

•Periodic interrup t s can be gene rated from in crement s of any fie ld of th e time registe rs.

•Alarm interrupt can be generated for a specific date/time.

7.22.1.2 Event monitor/recorder

The event monitor/recorder allows recording and creating a time stamp of ev ents related

to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the

event monitor/recorder stores records of such events. The event recorder can be

The event monitor/recorder can monitor the integrity of the device and record any

tampering events.

Features

•Supports three digital event inputs in the VBAT po we r do m ain.

•An event is defined as a level change at the digital event inputs.

•For each event channel, two timestamps mark the first and the last occurrence of an

event. Each channe l also has a dedicated counter tr acking the total n umber of events.

Timestamp values are taken from the RTC.

•Runs in VBAT power domain, independent of system power supply. The

event/reco rd er /m o nito r can ther ef or e op er a te in Deep pow er -down mode.

•Low power consum ption.

•Interrupt available if system is running.

•A qualified event can be used as a wake-up trigger.

•State of event interrupts accessible by software through GPIO.

7.22.2 Alarm timer

The alarm timer is a 1 6-bit timer and count s down at 1 kHz from a prese t value gener ating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt if enabled.

The alarm timer is part of the RTC power domain and can be battery powered.

7.23 System control

7.23.1 Configuration registers (CREG)

The following settings are controlled in the configuration register block:

Objective data sheet Rev. 1 — 4 June 2012 81 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

•BOD trip settings

•Oscillator output

•DMA-to-peripheral muxing

•Ethernet mode

•Memory mapping

•Timer/USART inputs

•Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.

7.23.2 System Control Unit (SCU)

The system control unit determ ines the functio n and el ectrical mo de of the digit a l pins. By

default function 0 is selected for all pins with pull-up enabled. For pins that support a

digital and analog function, the ADC function select registers in the SCU enable the

analog function.

A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are

located on separate pads and are not controlled through the SCU.

In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that

select the pin interrupts are located in the SCU.

7.23.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be

unrelated in freq ue nc y an d ph as e an d can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins. The base clock that generate s the

CPU clock is referred to as CCLK.

Multiple branch cloc ks ar e de rived from each base clock. The branch cloc ks offer flexible

control for power-management purposes. All branch clocks are outputs of one of two

Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase.

7.23.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 %

accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC4357/53 use the IRC as the clock source. The

boot loader then configures the PLL1 to provide a 96 MHz clock for the core and

PLL0USB or PLL0AUDIO as needed if an external boot source is selected.

7.23.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

Objective data sheet Rev. 1 — 4 June 2012 82 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

7.23.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This

PLL accepts an input clock frequency derived from an external oscillator or internal IRC.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the

desired output frequency. The output frequency can be set as a multiple of the sa mpling

frequency fs to 32fs, 64fs, 128  fs, 256 fs, 384  fs, 512  fs and the sampling

frequency fs can range from 16 kHz to 192 kH z (16, 22.05, 32, 44.1, 48, 96,192) kHz.

Many other frequencies are possible as well using the integrated fractional divider.

7.23.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz. This range is possible through an

additional divider in the loop to keep the CCO within its frequency range while the PLL is

providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,

or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset. After reset, software can enable the PLL. The program must

configure and ac tivate the PL L, wa it fo r th e PLL to lo ck, and the n con nect to the PLL as a

clock source. The PLL settling time is 100 s.

7.23.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals on the LPC4357/53.

7.23.9 Power control

The LPC435 7/53 feature severa l independent power domains to control p ower to the core

and the peripherals (see Figure 8). The RTC and its associated peripherals (the alarm

timer, the CREG block, the OTP controller, the back-up registers, and the event router)

are located in the RTC power-domain. The main regulator or a battery supply can power

the RTC. A power selector switch ensures that the RTC block is always powered on.

Objective data sheet Rev. 1 — 4 June 2012 83 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

The LPC4357/53 support four reduced power modes: Sleep, Deep-sleep, Power-down,

and Deep power-down.

The LPC4357/53 can wake up from Deep-sleep, Power-down, and Deep power-down

modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in

the RTC power domain.

7.23.10 Code security (Code Read Protection - CRP)

CRP enables dif ferent levels of securi ty so that access to the on-chip flash and use of the

JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by CRP.

Fig 8. Power domai ns

REAL-TIME CLOCK

BACKUP REGISTERS

RESET/WAKE-UP

CONTROL

REGULATOR

32 kHz

OSCILLATOR

ALWAYS-ON/RTC POWER DOMAIN

MAIN POWER DOMAIN

RTCX1

VBAT

VDDREG

RTCX2

VDDIO

VSS

to memories,

peripherals,

oscillators,

PLLs

to cores

to I/O pads

ADC

DAC

OTP

ADC POWER DOMAIN

OTP POWER DOMAIN

USB0 POWER DOMAIN

VDDA

VSSA

VPP

USB0

USB0_VDDA3V_DRIVER

USB0_VDDA3V3

LPC43xx

ULTRA LOW-POWER

REGULATOR

POWER

SELECTOR

ALARM

RESET

WAKEUP0/1/2/3

to RTC

domain

peripherals

002aag378

to RTC I/O

pads (Vps)

Objective data sheet Rev. 1 — 4 June 2012 84 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

There are three levels of the Code Read Protection:

•In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are

allowed (excluding flash sector 0) using a limited set of the ISP commands. This level

is useful when CRP is required and flash field updates are needed. CRP1 do es

prevent the user code from erasing all sectors.

•In level CRP2, access to the chip via the JTAG is disabled. Only a full flash erase and

update using a reduced set of the ISP commands is allowed.

•In level CRP3, any access to the chip via the JTAG pins or the ISP is disabled. This

mode also disabl es the ISP ov er rid e us ing P2_7 pin. If necessary, the application

code must provide a flash update mechanism using the IAP calls or using the

reinvoke ISP command to enable flash update via USART0.

7.24 Serial Wire Debug/JTAG

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four

watch points.

The ARM Cortex-M0 coprocessor supports JTAG boundary scan and serial wire debug.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Objective data sheet Rev. 1 — 4 June 2012 85 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(REG)(3V3) regulator supply voltage

(3.3 V) on pin VDDREG 2.2 3.6 V

VDD(IO) input/output supply

voltage on pin VDDIO 2.2 3.6 V

VDDA(3V3) analog supply voltage

(3.3 V) on pin VDDA 2.2 3.6 V

VBAT battery supply voltage on pin VBAT 2.2 3.6 V

Vprog(pf) polyfuse programming

voltage on pin VPP 2.7 3.6 V

VIinput voltage when VDD(IO)  2.2 V

5 V tolerant digital I/O pins

[2] 0.5 5.5 V

ADC/DAC pins and digital I/O

pins configured for an analog

function

0.5 VDDA(3V3) V

USB0 pins USB0_DP;

USB0_DM;USB0_VBUS 05.2V

USB0 pins USB0_ID;

USB0_RREF 03.6V

USB1 pins USB1_DP and

USB1_DM 05.2V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up curre n t (0.5VDD(IO)) < VI < (1.5VDD(IO));

Tj < 125 C- 100 mA

Tstg storage temperature [4] 65 +150 C

Ptot(pack) total power dissipation

(per package) based on package heat transfer,

not device power consumption -1.5W

VESD electrostatic discharge

voltage human body model; all pins [5] 2000 +2000 V

Objective data sheet Rev. 1 — 4 June 2012 86 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of

the I/O pins is of ten small and ma ny times can be n egligible. However it can be significant

in some applications.

TjTamb PDRth j a–

+=

Table 7. Thermal characteristics

VDD = 2.2 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified;

Symbol Parameter Conditions Min Typ Max Unit

Tj(max) maximum junction

temperature --125 C

Objective data sheet Rev. 1 — 4 June 2012 87 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

10. Static characteristics

Table 8. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Supply pins

VDD(IO) input/output supply

voltage 2.2 - 3.6 V

VDD(REG)(3V3) regulator supply voltage

(3.3 V) [2] 2.2 - 3.6 V

VDDA(3V3) analog supply voltage

(3.3 V) on pin VDDA 2.2 - 3.6 V

VBAT battery supply voltage 2.2 - 3.6 V

Vprog(pf) polyfuse programming

voltage on pin VPP for OTP [3] 2.7 - 3.6 V

Iprog(pf) polyfuse programming

current on pin VPP; OTP

programming time  1.6

--30mA

IDD(REG)(3V3) regulator supply current

(3.3 V) Regulator supply <tbd>

mode; code

while(1){}

executed from flash; all

peripherals disabled

CCLK = 12 MHz; PLL1

disabled [4][5] -<tbd> - mA

CCLK = 12 MHz; PLL1

enabled [4][6] -<tbd> - mA

CCLK = 120 MHz [4][6] -<tbd>-mA

CCLK = 204 MHz [4][6] -<tbd>-mA

IDD(REG)(3V3) regulator supply current

(3.3 V) Regulator supply <tbd>

mode; after WFE/WFI

instruction executed from

RAM; all peripherals

disabled

sleep mode [4][5] -<tbd>-mA

deep-sleep mode [4] -<tbd>-A

power-down mode [4] -<tbd>-A

deep power-down mode [4] -<tbd>-A

IBAT battery supply current deep-sleep mode [4][7] -<tbd> A

power-down mode [4][7] -<tbd>-A

deep power-down mode [4][7] -<tbd>-A

IDD(IO) I/O supply current deep sleep mode - <tbd> - A

power-down mode - <tbd> - A

deep power-down mode - <tbd> - A

IDD(ADC) ADC supply current deep sleep mode [9] -0.4-A

power-down mode [9] -0.4-A

deep power-down mode [9] -0.007-A

Objective data sheet Rev. 1 — 4 June 2012 88 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

RESET pin

VIH HIGH-level input

voltage [8] 0.8  (Vps 

0.35) -5.5V

VIL LOW-level input voltage [8] 0.5 - 0.3  (Vps 

0.1) V

Vhys hysteresis voltage [8] 0.05  (Vps

 0.35) --V

Standard I/O pins - normal drive strength

CIinput capacitance - - 2 pF

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled -3-nA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

-3- nA

VI=5 V - <tbd> - nA

IOZ OFF-state output

current VO=0V to V

DD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

-3-nA

VIinput voltage pin configured to provide

a digital function;

VDD(IO)  2.2 V

0- 5.5V

VDD(IO) = 0 V 0 - 3.6 V

VOoutput voltage o utput active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7 

VDD(IO)

-5.5V

VIL LOW-level input voltage 0.5 - 0.3 

VDD(IO)

Vhys hysteresis voltage 0.1 

VDD(IO) --V

VOH HIGH-level output

voltage IOH =6 mA VDD(IO) 

0.4 --V

VOL LOW-level output

voltage IOL =6 mA --0.4V

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 6--mA

IOL LOW-level output

current VOL =0.4V 6--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10] --86.5mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10] --76.5mA

Ipd pull-down current VI=5 V [12]

[13]

[14]

-93-A

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 4 June 2012 89 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Ipu pull-up current V I=0V [12]

[13]

[14]

-62 - A

VDD(IO) <V

I5V - 10 - A

Rsseries resistance on I/O pins with analog

function; analog function

enabled

200 

I/O pins - high drive strength

CIinput capacitance - - 2 pF

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled -3-nA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

-3- nA

VI=5 V - <tbd> - nA

IOZ OFF-state output

current VO=0V to V

DD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

-3-nA

VIinput voltage pin configured to provide

a digital function;

VDD(IO)  2.2 V 0 - 5.5 V

VDD(IO) = 0 V 0 - 3.6 V

VOoutput voltage o utput active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7 

VDD(IO)

-5.5V

VIL LOW-level input voltage 0.5 - 0.3 

VDD(IO)

Vhys hysteresis voltage 0.1 

VDD(IO)

--V

Ipd pull-down current VI=V

DD(IO) [12]

[13]

[14]

-62-A

Ipu pull-up current V I=0V [12]

[13]

[14]

-62 - A

VDD(IO) <V

I5V - 10 - A

I/O pins - high drive strength: standard drive mode

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 4--mA

IOL LOW-level output

current VOL =0.4V 4--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10]

[13] --32mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10]

[13] --32mA

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 4 June 2012 90 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

I/O pins - high drive strength: medium drive mode

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 8--mA

IOL LOW-level output

current VOL =0.4V 8--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10]

[13] --65mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10]

[13] --63mA

I/O pins - high drive strength: high drive mode

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 14--mA

IOL LOW-level output

current VOL =0.4V 14--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10]

[13] --113mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10]

[13] --110mA

I/O pins - high drive strength: ultra-high drive mode

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 20--mA

IOL LOW-level output

current VOL =0.4V 20--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10]

[13] --165mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10]

[13] --156mA

I/O pins - high-speed

CIinput capacitance - - 2 pF

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled -3-nA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

-3- nA

VI=5 V - <tbd> - nA

IOZ OFF-state output

current VO=0V to V

DD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

-3-nA

VIinput voltage pin configured to provide

a digital function;

VDD(IO)  2.2 V 0 - 5.5 V

VDD(IO) = 0 V 0 - 3.6 V

VOoutput voltage o utput active 0 - VDD(IO) V

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 4 June 2012 91 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

VIH HIGH-level input

voltage 0.7 

VDD(IO)

-5.5V

VIL LOW-level input voltage 0.5 - 0.3 

VDD(IO)

Vhys hysteresis voltage 0.1 

VDD(IO) --V

VOH HIGH-level output

voltage IOH =8 mA VDD(IO) 

0.4 --V

VOL LOW-level output

voltage IOL =8 mA --0.4V

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V 8--mA

IOL LOW-level output

current VOL =0.4V 8--mA

IOHS HIGH-level short-circuit

output current drive HIGH; connected to

ground [10] --86mA

IOLS LOW-level short-circuit

output current drive LOW; connected to

VDD(IO)

[10] --76mA

Ipd pull-down current VI=V

DD(IO) [12]

[13]

[14]

-62-A

Ipu pull-up current V I=0V [12]

[13]

[14]

-62 - A

VDD(IO) <V

I5V - 0 - A

Open-drain I2C0-bus pins

VIH HIGH-level input

voltage 0.7 

VDD(IO)

--V

VIL LOW-level input voltage 0.5 0.14 0.3 

VDD(IO)

Vhys hysteresis voltage 0.1 

VDD(IO)

--V

VOL LOW-level output

voltage IOLS =3 mA --0.4V

ILI input leakage current VI=V

DD(IO) [11] -4.5-A

VI=5V --10A

Oscillator pins

Vi(XTAL1) input voltage on pin

XTAL1 0.5 - 1.2 V

Vo(XTAL2) output voltage on pin

XTAL2 0.5 - 1.2 V

Cio input/output

capacitance [15] --0.8pF

USB0 pins[16]

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 4 June 2012 92 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] For flash read operations, 2.2 V  VDD(REG)(3V3)  3.6 V; for flash erase/program operations 2.7 V  VDD(REG)(3V3)  3.6 V.

[3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure

the same ramp-up time for both supply voltages.

[4] VDD(REG)(3V3) = VDD(IO)=V

DDA(3V3) = 3.3 V; Tamb =25C for all power consumption measurements.

[5] PLL1 disabled. Normal power mode.

[6] PLL1 enabled. Normal power mode.

[7] On pin VBAT; Tamb =25C. VDD(REG)(3V3) not present.

[8] Vps corresponds to the output of the power switch (see Figure 8) which is determined by the greater of VBAT and VDD(Reg)(3V3).

[9] VDDA(3V3) = 3.3 V; Tamb =25C.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] To VSS.

[12] The values specified are simulated and absolute values.

VIinput voltage on pins USB0_DP;

USB0_DM; USB0_VBUS

VDD(IO)  2.2 V 0 - 5.5 V

VDD(IO) = 0 V 0 - 3.6 V

Rpd pull-down resistance on pin USB0_VBUS 48 64 80 k

VIC common-mode input

voltage high-speed mode 50 200 500 mV

full-speed/low-speed

mode 800 - 2500 mV

chirp mode 50 - 600 mV

Vi(dif) differential input voltage 100 400 11 00 mV

USB1 pins (USB1_DP/USB1_DM)[16]

IOZ OFF-state output

current 0V<V

I<3.3V [16] --10 A

VBUS bus supply voltage [17] --5.25V

VDI differential input

sensitivity voltage (D+) (D)0.2--V

VCM differential common

mode voltage range includes VDI range 0.8 - 2.5 V

Vth(rs)se single-ended recei v er

switching threshold

voltage

0.8 - 2.0 V

VOL LOW-level output

voltage for

low-/full-speed

RL of 1.5 k to 3.6 V - - 0.18 V

VOH HIGH-level output

voltage (driven) for

low-/full-speed

RL of 15 k to GND 2.8 - 3.5 V

Ctrans transceiver capacitance pin to GND - - 20 pF

ZDRV driver output

impedance for driver

which is not high-speed

capable

with 33  series resistor;

steady state drive [18] 36 - 44.1 

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Objective data sheet Rev. 1 — 4 June 2012 93 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[13] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.

[14] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO).

[15] The parameter value specified is a simulated value excluding bond capacitance.

[16] For USB operation 3.0 V  VDD((IO)  3.6 V. Guaranteed by design.

[17] VDD(IO) present.

[18] Includes external resistors of 33 1 % on D+ and D.

10.1 Power consumption

Conditions: Tamb = 25 C; normal mode entered executing code while (1){} from ROM; internal

pull-up resistors disabled; system PLL enabled; IRC enabled, BOD enabled; all peripherals

disabled; all peripheral clocks disabled.

Fig 9. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active

mode

X (X)

X XXXX

001aac984

(X)

<tbd>

Objective data sheet Rev. 1 — 4 June 2012 94 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VDD(REG)(3V3) = 3.0 V, normal mode entered executing code while (1){} from ROM;

internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD enabled; all peripherals

disabled; all peripheral clocks disabled.

Fig 10. Ty pical sup ply current versus temperature in active mode

Conditions: VDD(REG)(3V3) = 3.0 V; internal pull-up resistors disabled; system PLL enabled; IRC

enabled, BOD enabled; all peripherals disabled; all peripheral clocks disabled.

Fig 11. Typical supply current versus temperature in sleep mode

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

Objective data sheet Rev. 1 — 4 June 2012 95 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VBAT = 0 V; VDD(IO) = 0 V.

Fig 12. Ty pical sup ply current versus temperature in Deep-sleep mode

Conditions: VBAT = 0 V; VDD(IO) = 0 V.

Fig 13. Ty pical sup ply current versus temperature in Power-down mode

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

Objective data sheet Rev. 1 — 4 June 2012 96 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VBAT = 0 V; VDD(IO) = 0 V.

Fig 14. Typical supply current versus temperature in Deep power-down mode

X (X)

X XXXX

001aac984

(X)

<tbd>

Objective data sheet Rev. 1 — 4 June 2012 97 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

10.2 BOD static characteristics

[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bit s in the control register CREGE0, see

the LPC43xx user manual.

Table 9. BOD static characteristics[1]

Tamb =25



C; simulated values for nominal pro ce ssing.

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 2.25 - V

de-assertion - <tbd> - V

interrupt level 1

assertion - 2.35 - V

de-assertion - <tbd> - V

interrupt level 2

assertion - 2.95 - V

de-assertion - <tbd> - V

interrupt level 3

assertion - 3.05 - V

de-assertion - <tbd> - V

reset level 0

assertion - 1.9 - V

de-assertion - <tbd> - V

reset level 1

assertion - 2.0 - V

de-assertion - <tbd> - V

reset level 2

assertion - 2.1 - V

de-assertion - <tbd> - V

reset level 3

assertion - 2.2 - V

de-assertion - <tbd> - V

Objective data sheet Rev. 1 — 4 June 2012 98 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

10.3 Electrical pin characteristics

Conditions: VDD(REG)(3V3) =V

DD(IO) =3.3V.

Fig 15. Normal-drive pins; typi ca l LO W le ve l outpu t curre nt IOL versus LOW level output

voltage VOL

Conditions: VDD(REG)(3V3) =V

DD(IO) =3.3V.

Fig 16. Normal-drive pins; typical HIGH level output volt age VOL versus HGH level output

current IOH

002aah030

0 0.1 0.2 0.3 0.4 0.5 0.6

VOL (V)

IOL

(mA)

-40 °C

25 °C

85 °C

IOH (mA)

0362412

002aah039

2.8

2.4

3.2

3.6

VOH

(V)

2.0

T = 85 °C

25 °C

-40 °C

Objective data sheet Rev. 1 — 4 June 2012 99 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; normal-drive;

EHD = 0x0. Conditions: VDD(REG)(3V3) =V

DD(IO) =3.3V;

medium-drive; EHD = 0x1.

Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; high-drive;

EHD = 0x2. Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; ultra

high-drive; EHD = 0x3.

Fig 17. High-drive pin s; typi ca l LOW level outpu t cu rre nt IOL versus LOW level output voltage VOL

002aah040

0 0.1 0.2 0.3 0.4 0.5 0.6

VOL (V)

IOL

(mA)

-40 °C

25 °C

85 °C

002aah041

0 0.1 0.2 0.3 0.4 0.5 0.6

VOL (V)

IOL

(mA)

-40 °C

25 °C

85 °C

002aah043

0 0.1 0.2 0.3 0.4 0.5 0.6

VOL (V)

IOL

(mA)

-40 °C

25 °C

85 °C

002aah044

0 0.1 0.2 0.3 0.4 0.5 0.6

VOL (V)

IOL

(mA)

-40 °C

25 °C

85 °C

Objective data sheet Rev. 1 — 4 June 2012 100 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; normal-drive;

EHD = 0x0. Conditions: VDD(REG)(3V3) =V

DD(IO) =3.3V;

medium-drive; EHD = 0x1.

Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; high-drive;

EHD = 0x2. Conditions: VDD(REG)(3V3) =V

DD(IO) = 3.3 V; ultra

high-drive; EHD = 0x3.

Fig 18. High-drive pins; typical HIGH level output voltage VOH versus HGH level output current IOH

002aah047

(mA)

024168

2.0

3.2

2.8

2.4

3.6

(V)

-40 °C

25 °C

85 °C

002aah048

(mA)

0483216

2.0

3.2

2.8

2.4

3.6

(V)

-40 °C

25 °C

85 °C

002aah049

(mA)

09664

2.0

3.2

2.8

2.4

3.6

(V)

-40 °C

25 °C

85 °C

002aah050

(mA)

0 12080

2.0

3.2

2.8

2.4

3.6

(V)

-40 °C

25 °C

85 °C

Objective data sheet Rev. 1 — 4 June 2012 101 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Conditions: VDD(IO)) = 3.3 V. Simulated values. Values at T = 25 C are typical values. Values at

T=40 C correspond to minimum values.

Fig 19. Typical pu ll-up current Ipu versus input voltage VI

Conditions: VDD(IO)) = 3.3 V. Simulated values. Values at T = 25 C are typical values. Values at

T=40 C correspond to maximum values.

Fig 20. Typical pu ll-do wn current Ipd versus input voltage VI

VI (V)

0 54231

002aag625

-40

-20

-60

+20

Ipu

(μA)

-80

T = 25 °C

-40 °C

VI (V)

0 54231

002aag626

120

Ipd

(μA)

T =25 °C

-40 °C

Objective data sheet Rev. 1 — 4 June 2012 102 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11. Dynamic characteristics

11.1 Flash/EEPROM memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash

in blocks of 512 bytes.

[1] See the LPC43xx user manual how to program the wait states for the different read (RPHASEx) and

erase/program phases (PHASEx)

Table 10. Flash characteristics

Tamb =





C to +85



C, unless otherwise specified. VDD(REG)(3V3) = 2,2 V to 3.6 V for read

operations; VDD(REG)(3V3) = 2.7 V to 3.6 V for erase/program operations.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance sector erase/program [1] 10000 - - cycles

page erase/program; page

in large sector 1000 - -

page erase/program; page

in small sector 10000 - -

tret retention time powered 10 - - years

unpowered 10 - - years

ter erase time page, sector, or multiple

consecutive sectors -50-ms

tprog programming

time [2] -1-ms

Table 11. EEPROM characteristics

Tamb =





Cto+85



C; VDD(REG)(3V3) = 2.7 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency 800 1500 1600 kHz

Nendu endurance 100 000 <tbd> - cycles

tret retention time - 20 - years

taaccess time read - 120 - ns

erase/program; fclk

= 1500 kHz -1.99-ms

erase/program; fclk

= 1600 kHz -1.87-ms

twait wait time read; RPHASE1 [1] 35 - - ns

read; RPHASE2 [1] 70 - - ns

write; PHASE1 [1] 20 - - ns

write; PHASE2 [1] 40 - - ns

write; PHASE3 [1] 10 - - ns

Objective data sheet Rev. 1 — 4 June 2012 103 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.2 Wake-up times

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] Tcy(clk) = 1/CCLK with CCLK = CPU clock frequency.

11.3 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.4 Cryst al oscillator

Table 12. Dynamic characteristic: Wake-up from Deep-sleep, Power-d own, and Deep

power-down modes

Tamb =





C to +85



Symbol Parameter Conditions Min Typ[1] Max Unit

twake wake-up time from Sleep mode [2] <tbd> 5  Tcy(clk) -ns

from Deep-sleep and

Power-down mode 12 51 - s

from Deep power-down mode <tbd> <tbd> - ns

after reset <tbd> <tbd> - ns

Table 13. Dynamic characteristic: external clock

Tamb =





C to +85



C; VDD(IO) over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 2 5 MHz

Tcy(clk) clock cycle time 40 - 1 000 ns

tCHCX clock HIGH time Tcy(clk) <tbd> - - ns

tCLCX clock LOW time Tcy(clk) <tbd> - - ns

tCLCH clock rise time - - <tbd> ns

tCHCL clock fall time - - <tbd> ns

Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Table 14. Dynamic characteristic: oscillator

Tamb =





C to +85



C; VDD(IO) over specified ranges; 2.2 V



VDD(REG)(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

Low-frequency mode (1 MHz - 20 MHz)[5]

Objective data sheet Rev. 1 — 4 June 2012 104 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] Indicates RMS period jitter.

[4] PLL-induced jitter is not included.

[5] Select HF = 0 in the XTAL_OSC_CTRL register.

[6] Select HF = 1 in the XTAL_OSC_CTRL register.

11.5 IRC oscillator

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

tjit(per) period jitter time 5 MHz crystal [3][4] - 13.2 - ps

10 MHz crystal - 6.6 - ps

15 MHz crystal - 4.8 - ps

High-frequency mode (20 MHz - 25 MHz)[6]

tjit(per) period jitter time 20 MHz crystal [3][4] -4.3- ps

25 MHz crystal - 3.7 - ps

Table 14. Dynamic characteristic: oscillator …continued

Tamb =





C to +85



C; VDD(IO) over specified ranges; 2.2 V



VDD(REG)(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

Table 15. Dynamic characteristic: IRC oscillator

Tamb =





C to +85



C; 2.2 V



VDD(REG)(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator

frequency - 11.88 12.00 12.12 MHz

Conditions: Frequency values are typical values.

Fig 22. Internal RC osc illator frequency versus temperature

<tbd>

X (X)

XXXXXX

001aab173

(X)

Objective data sheet Rev. 1 — 4 June 2012 105 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.6 RTC oscillator

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.7 I2C-bus

[1] Parameters are valid over operating temperature range unle ss otherwise specified. See the I2C-bus specification UM10204 for details.

[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

Table 16. Dynamic characteristic: RTC oscillator

Tamb =





C to +85



C; 2.2 V



VDD(REG)(3V3)



3.6 V or 2.2 V



VBAT



3.6 V[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fi(RTC) R TC input frequency - - 32.768 - kHz

IDD(RTC) RTC supply current 280 800 nA

Table 17. Dynamic characteristic: I 2C-bus pins

Tamb =





C to +85



C; 2.2 V



VDD(REG)(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [3][4][5][6] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [2][3][7] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up time

[8][9] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Objective data sheet Rev. 1 — 4 June 2012 106 of 141

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32-bit ARM Cortex-M4/M0 microcontroller

[7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

11.8 I2S-bus interface

Fig 23. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Table 18. Dynamic characteristics: I2S-bus interface pins

Tamb =25



C; 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V ; CL = 20 pF. Conditions and data

refer to I2S0 and I2S1 pins. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

common to input and output

trrise time - 4 - ns

tffall time - 4 - ns

tWH pulse width HIGH on pins I2Sx_TX_SCK

and I2Sx_RX_SCK <tbd> - - -

tWL pulse width LOW on pins I2Sx_TX_SCK

and I2Sx_RX_SCK - - <tbd> ns

output

tv(Q) data output valid time on pin I2Sx_TX_SDA [1] -4.4-ns

on pin I2Sx_TX_WS - 4.3 - ns

input

tsu(D) data input set-up time on pin I2Sx_RX_SDA [1] -0-ns

on pin I2Sx_RX_WS 0.20 ns

th(D) data input hold time on pin I2Sx_RX_SDA [1] -3.7-ns

on pin I2Sx_RX_WS - 3.9 - ns

Objective data sheet Rev. 1 — 4 June 2012 107 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Clock to the I2S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I2S-bus interface

PCLK = BASE_APB1_CLK / 12. I2S clock cycle time Tcy(clk) = 79.2 ns, corresponds to the SCK signal in the

I2S-bus specification.

11.9 USART interface

Fig 24. I2S-bus timing (transmit)

Fig 25. I2S-bus timing (receive)

002aag497

I2Sx_TX_SCK

I2Sx_TX_SDA

I2Sx_TX_WS

Tcy(clk) tftr

tWH tWL

tv(Q)

002aag498

Tcy(clk) tftr

tWH

tsu(D) th(D)

tsu(D) tsu(D)

tWL

I2Sx_RX_SCK

I2Sx_RX_SDA

I2Sx_RX_WS

Table 19. Dynamic characteristics: USART interface

Tamb =25



C; 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V; CL = 20 pF. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

Tcy(clk) clock cycle time on pins Ux_UCLK - 0.1 - s

output

tv(Q) data output valid time on pin Ux_TXD - 6.5 - ns

Objective data sheet Rev. 1 — 4 June 2012 108 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.10 SSP interface

[1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2] Tcy(clk) = 12  Tcy(PCLK).

Table 20. Dynamic characteristics: SSP pins in SPI mode

Tamb =25



C; 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

Tcy(clk) clock cycle time full-duplex mode [1] -40-ns

when only

transmitting -20-ns

SSP master

tDS data set-up time in SPI mode - 8.8 - ns

tDH data hold time in SPI mode - 5.0 - ns

tv(Q) data output valid time in SPI mode - 3.9 - ns

th(Q) data output hold time in SPI mode - 0.4 - ns

SSP slave

Tcy(PCLK) PCLK cycle time 10 ns

Tcy(clk) clock cycle time [2] 120 - - ns

tDS data set-up time in SPI mode - 10.5 - ns

tDH data hold time in SPI mode - 1 - ns

tv(Q) data output valid time in SPI mode - 4.0 - ns

th(Q) data output hold time in SPI mode 0.2 - ns

Objective data sheet Rev. 1 — 4 June 2012 109 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 26. SSP master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID DATA V ALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

D ATA V ALID DATA V ALID

th(Q)

D ATA V ALID D ATA V ALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

Objective data sheet Rev. 1 — 4 June 2012 110 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 27. SSP slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

clk(H)

clk(L)

v(Q)

D ATA V ALID DATA V ALID

h(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

v(Q)

D ATA V ALID DATA V ALID

h(Q)

D ATA V ALID D ATA V ALID

CPHA = 1

CPHA = 0

002aae830

Objective data sheet Rev. 1 — 4 June 2012 111 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.11 External memory interface

Table 21. Dynamic characteristics: Static external memory interface

CL= 22 pF for EMC_Dn CL= 20 pF for all others; Tamb =





C to 85



C; 2.2 V



VDD(REG)(3V3)



3.6 V ;

2.7 V



VDD(IO)



3.6 V; values guaranteed by design.

Symbol Parameter[1] Conditions Min Typ Max Unit

Read cycle parameters

tCSLAV CS LOW to address valid

time 3.1 - 1.6 ns

tCSLOEL CS LOW to OE LOW time [2] 0.6 + Tcy(clk) 

WAITOEN - 1.3 + Tcy(clk) 

WAITOEN ns

tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns

tOELOEH OE LOW to OE HIGH time [2] 0.6 +

(WAITRD 

WAITOEN + 1) 

Tcy(clk)

-0.4 +

(WAITRD 

WAIT OEN + 1) 

Tcy(clk)

tam memory access time - - 16 +

(WAITRD 

WAITOEN +1) 

Tcy(clk)

th(D) data input hold time 16 - - ns

tCSHBLSH CS HIGH to BLS HIGH time PB = 1 0.4 - 1.9 ns

tCSHOEH CS HIGH to OE HIGH time 0.4 - 1.4 ns

tOEHANV OE HIGH to address invalid PB = 1 2.0 - 2.6 ns

tCSHEOR CS HIGH to end of read

time [3] 2.0 - 0 ns

tCSLSOR CS LOW to start of read

time [4] 0- 1.8ns

Write cycle parameters

tCSLAV CS LOW to address valid

time 3.1 - 1.6 ns

tCSLDV CS LOW to data valid time 3.1 - 1.5 ns

tCSLWEL CS LOW to WE LOW time PB = 1 1.5 - 0.2 ns

tCSLBLSL CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns

tWELWEH WE LOW to WE HIGH time PB = 1 [2] 0.6 +

(WAITWR 

WAITWEN + 1) 

Tcy(clk)

-0.4 +

(WAITWR 

WAITWEN + 1) 

Tcy(clk)

tWEHDNV WE HIGH to data invalid

time PB = 1 [2] 0.9 + Tcy(clk) - 2.3 + Tcy(clk) ns

tWEHEOW WE HIGH to end of write

time PB = 1 [2]

[5] 0.4 + Tcy(clk) -0.3 + Tcy(clk) ns

tCSLBLSL CS LOW to BLS LOW PB = 0 0.7 - 1.8 ns

tBLSLBLSH BLS LOW to BLS HIGH time PB = 0 [2] 0.9 +

(WAITWR 

WAITWEN + 1) 

Tcy(clk)

-0.1 +

(WAITWR 

WAITWEN + 1) 

Tcy(clk)

tBLSHEOW BLS HIGH to end of write

time PB = 0 [2]

[5] 1.9 + Tcy(clk) -0.5 + Tcy(clk) ns

Objective data sheet Rev. 1 — 4 June 2012 112 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges.

[2] Tcy(clk) = 1/CCLK (see LPC43xx User manual).

[3] End Of Read (EOR): longest of tCSHOEH, tOEHANV, tCSHBLSH.

[4] Start Of Read (SOR): longest of tCSLAV, tCSLOEL, tCSLBLSL.

[5] End Of Write (EOW): earliest of address not valid or EMC_BLSn HIGH.

tBLSHDNV BLS HIGH to data invalid

time PB = 0 [2] 2.5 + Tcy(clk) - 1.4 + Tcy(clk) ns

tCSHEOW CS HIGH to end of write

time [5] 2.0 - 0 ns

tBLSHDNV BLS HIGH to data invalid

time PB = 1 2.5 - 1.4 ns

tWEHANV WE HIGH to address invalid

time PB = 1 0.9 + Tcy(clk) - 2.4 + Tcy(clk) ns

Table 21. Dynamic characteristics: Static external memory interface …continued

CL= 22 pF for EMC_Dn CL= 20 pF for all others; Tamb =





C to 85



C; 2.2 V



VDD(REG)(3V3)



3.6 V ;

2.7 V



VDD(IO)



3.6 V; values guaranteed by design.

Symbol Parameter[1] Conditions Min Typ Max Unit

Fig 28. External static memory read/write access (PB = 0)

tCSLDV

tCSLBLSL

tCSHEOW

tBLSHEOW

tCSLAV

EOR

SOR EOW

EMC_An

EMC_CSn

EMC_OE

EMC_BLSn

EMC_WE

EMC_Dn

002aag699

tCSHOEH

tOEHANV

tCSHEOR

tam

tCSLSOR

tOELOEH

tCSLOEL

tCSLAV

th(D)

tBLSLBLSH

tBLSHDNV

Objective data sheet Rev. 1 — 4 June 2012 113 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 29. External static memory read/write access (PB = 1)

EMC_An

tCSLAV

tCSLBLSL

EMC_CSn

EMC_OE

EMC_BLSn

EMC_WE

tCSLSOR

tCSLDV

tam

th(D)

EOR

SOR EOW

EMC_Dn

tCSLWEL tWELWEH tWEHEOW

002aag700

tCSLBLSL

tCSLAV

tCSLOEL

tOELOEH

tCSHOEH

tOEHANV

tCSHBLSH

tCSHEOR

tCSHEOW

tWEHDNV

tBLSHDNV

Objective data sheet Rev. 1 — 4 June 2012 114 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual).

The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =

CLK2_DELAY = CLK3_DELAY.

Table 22. Dynamic characteristics: Dynamic extern al memory interface

Simulated data over temperature and process range; CL= 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,

EMC_An; CL= 9 pF for EMC_Dn; CL= 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb =





C to 85



2.2 V



VDD(REG)(3V3)



3.6 V; VDD(IO) =3.3 V



10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY

= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.

Symbol Parameter Min Typ Max Unit

Tcy(clk) clock cycle time 8.4 - - ns

Common to read and write cycles

td(DYCSV) DYCS delay time - 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns

th(DYCS) DYCS hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) -ns

td(RASV) row address strobe valid delay time - 3.1 + 0.5  Tcy(clk) 4.9 + 0.5  Tcy(clk) ns

th(RAS) row address strobe hold time 0.5 + 0.5  Tcy(clk) 1.1 + 0.5  Tcy(clk) -ns

td(CASV) column address strobe valid delay time - 2.9 + 0.5  Tcy(clk) 4.6 + 0.5  Tcy(clk) ns

th(CAS) column address strobe hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) -ns

td(WEV) WE valid delay time - 3.2 + 0.5  Tcy(clk) 5.9 + 0.5  Tcy(clk) ns

th(WE) WE hold time 1.3 + 0.5  Tcy(clk) 1.4 + 0.5  Tcy(clk) -ns

td(DQMOUTV) DQMOUT valid delay time - 3.1 + 0.5  Tcy(clk) 5.0 + 0.5  Tcy(clk) ns

th(DQMOUT) DQMOUT hold time 0.2 + 0.5  Tcy(clk) 0.8 + 0.5  Tcy(clk) -ns

td(AV) address vali d delay time - 3.8 + 0.5  Tcy(clk) 6.3 + 0.5  Tcy(clk) ns

th(A) address hold time 0.3 + 0.5  Tcy(clk) 0.9 + 0.5  Tcy(clk) -ns

td(CKEOUTV) CKEOUT valid delay time - 3.1 + 0.5  Tcy(clk) 5.1 + 0.5  Tcy(clk) ns

th(CKEOUT) CKEOUT hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) -ns

Read cycle parameters

tsu(D) data input set-up time 1.5 0.5 - ns

th(D) data input hold time - 0.8 2.2 ns

Write cycle parameters

td(QV) data output valid delay time - 3.8 + 0.5  Tcy(clk) 6.2 + 0.5  Tcy(clk) ns

th(Q) data output hold time 0.5  Tcy(clk) 0.7 + 0.5  Tcy(clk) -ns

Table 23. Dynamic characteristics: Dynamic exte rnal memory interface; EMC_CLK[3:0]

delay values

Tamb =





C to 85



C; VDD(IO) =3.3 V



10 %; 2.2 V



VDD(REG)(3V3)



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

tddelay time delay value

CLKn_DELAY = 0

[1]

0.0 0.0 0.0 ns

CLKn_DELAY = 1 [1] 0.4 0.5 0.8 ns

CLKn_DELAY = 2 [1] 0.7 1.0 1.7 ns

CLKn_DELAY = 3 [1] 1.1 1.6 2.5 ns

CLKn_DELAY = 4 [1] 1.4 2.0 3.3 ns

CLKn_DELAY = 5 [1] 1.7 2.6 4.1 ns

CLKn_DELAY = 6 [1] 2.1 3.1 4.9 ns

CLKn_DELAY = 7 [1] 2.5 3.6 5.8 ns

Objective data sheet Rev. 1 — 4 June 2012 115 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 23 .

Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK

Fig 30. SDRAM timing

002aag703

cy(clk)

EMC_CLKn

delay = 0

EMC_CLKn

delay > 0

EMC_DYCSn,

EMC_RAS,

EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

h(Q)

h(D)

su(D)

h(D)

su(D)

EMC_D[31:0]

write

EMC_D[31:0]

read; delay = 0

EMC_D[31:0]

read; delay > 0

h(x)

d(xV)

d(QV)

h(x)

d(xV)

EMC_CLKn delay t

; programmable CLKn_DELAY

Objective data sheet Rev. 1 — 4 June 2012 116 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.12 USB interface

[1] Characterized but not implemented as production test. Guaranteed by design.

Table 24. Dynamic characteristics: USB0 and USB1 pins (full-speed)

CL = 50 pF; Rpu = 1.5 k



on D+ to VDD(IO), unless otherwise specified; 3.0 V



VDD(IO)



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time 10 % to 90 % 8.5 - 13.8 ns

tffall time 10 % to 90 % 7.7 - 13.7 ns

tFRFM differential rise and fall time

matching tr/t

f--109%

VCRS output signal crossover voltage 1.3 - 2.0 V

tFEOPT source SE0 interval of EOP see Figure 31 160 - 175 ns

tFDEOP source jitter for differential transition

to SE0 transition see Figure 31 2-+5ns

tJR1 receiver jitter to next transition 18.5 - +18.5 ns

tJR2 receiver jitter for paired transitions 10 % to 90 % 9-+9ns

tEOPR1 EOP width at receiver must reject as

EOP; see

Figure 31

[1] 40 --ns

tEOPR2 EOP width at receiver must accept as

EOP; see

Figure 31

[1] 82 --ns

Fig 31. Differential da ta-to-EOP transition skew and EOP width

002aab561

TPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × TPERIOD + tFDEOP

Objective data sheet Rev. 1 — 4 June 2012 117 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] Characterized but not implemented as production test.

[2] Total average power consumption.

[3] The driver is active only 20 % of the time.

Table 25. Static characteristics: USB0 PHY pins[1]

Symbol Parameter Conditions Min Typ Max Unit

High-speed mode

Pcons power consumption [2] -68-mW

IDDA(3V3) analog suppl y current (3.3 V) on pin USB0_VDDA3V3_ DRIVER;

total supply current

[3]

-18-mA

during transmit - 31 - mA

during receive - 14 - mA

with driver tri-stated - 14 - mA

IDDD digital supply current - 7 - mA

Full-speed/low-speed mode

Pcons power consumption [2] -15-mW

IDDA(3V3) analog suppl y current (3.3 V) on pin USB0_VDDA3V3_ DRIVER;

total supply current - 3.5 - mA

during transmit - 5 - mA

during receive - 3 - mA

with driver tri-stated - 3 - mA

IDDD digital supply current - 3 - mA

Suspend mode

IDDA(3V3) analog suppl y current (3.3 V) - 24 - A

with driver tri-stated - 24 - A

with OTG functionality enabled - 3 - mA

IDDD digital supply current - 30 - A

VBUS detector outputs

Vth threshold voltage for VBUS valid 4.4 - - V

for session end 0.2 - 0.8 V

for A valid 0.8 - 2 V

for B valid 2 - 4 V

Vhys hysteresis voltage for session end - 150 10 mV

A valid - 200 10 mV

B valid - 200 10 mV

Objective data sheet Rev. 1 — 4 June 2012 118 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.13 Ethernet

[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2] T iming values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

Table 26. Dynamic characteristics: Ethernet

Tamb =





C to 85



C, 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V. Values guaranteed by

design.

Symbol Parameter Conditions Min Max Unit

RMII mode

fclk clock frequency for ENET_RX_CLK [1] -50MHz

clk clock duty cycle [1] 50 50 %

tsu set-up time for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2] 4- ns

thhold time for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2] 2- ns

MII mode

fclk clock frequency for ENET_TX_CLK [1] - 25 MHz

clk clock duty cycle [1] 50 50 %

tsu set-up time for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER [1][2] 4- ns

thhold time for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER [1][2] 2- ns

fclk clock frequency for ENET_RX_CLK [1] - 25 MHz

clk clock duty cycle [1] 50 50 %

tsu set-up time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2] 4- ns

thhold time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2] 2- ns

Fig 32. Ethernet timing

002aag210

tsu

ENET_RX_CLK

ENET_TX_CLK

ENET_RXD[n]

ENET_RX_DV

ENET_RX_ER

ENET_TXD[n]

ENET_TX_EN

ENET_TX_ER

Objective data sheet Rev. 1 — 4 June 2012 119 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

11.14 SD/MMC

11.15 LCD

Table 27. Dynamic characteristics: SD/MMC

Tamb = 25



C, 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V, CL = 20 pF. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency on pin SD_CLK; data transfer

mode - 40 <tbd> MHz

on pin SD_CLK; identification

mode <tbd> MHz

tsu(D) data input set-up

time on pins SD_CMD, SD_DATn

as inputs <tbd

>9.9 - ns

th(D) data input hold time on pins SD_CMD, SD_DATn

as inputs <tbd

>0.3 - ns

td(QV) data output val i d

delay time on pins SD_CMD, SD_DATn

as outputs - 6.9 <tbd> ns

th(Q) data output ho l d

time on pins SD_CMD, SD_DATn

as outputs <tbd

>0.3 - ns

Fig 33. SD/MMC timing

002aag204

SD_CLK

SD_DATn (O)

SD_DATn (I)

td(QV)

th(D)

tsu(D)

Tcy(clk)

th(Q)

SD_CMD (O)

SD_CMD (I)

Table 28. Dynamic characteristics: LCD

Tamb =25



C; 2.2 V



VDD(REG)(3V3)



3.6 V; 2.7 V



VDD(IO)



3.6 V; CL = 20 pF. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency on pin LCD_DCLK - 50 <tbd> MHz

tsu(D) data input set-up

time <tbd> - ns

th(D) data input hold time <tbd> <tbd> - ns

td(QV) data output valid

delay time - 14.1 <tbd> ns

th(Q) data output hold time <tbd> <tbd> - ns

Objective data sheet Rev. 1 — 4 June 2012 120 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

12. ADC/DAC electrical characteristics

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 34.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 34.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 34.

[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 34.

[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 34.

[7] Tamb = 25 C.

[8] Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs  Cia).

Table 29. ADC characteristics

VDDA(3V3) over specified ranges; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDDA(3V3) V

Cia analog input capacitance - - 2 pF

EDdifferential linearity error 2.7 V  VDDA(3V3)  3.6 V [1][2] -0.8 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 1.0 - LSB

EL(adj) integral non-linearity 2.7 V  VDDA(3V3)  3.6 V [3] -0.8 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 1.5 - LSB

EOoffset error 2.7 V  VDDA(3V3)  3.6 V [4] -0.15 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 0.15 - LSB

EGgain error 2.7 V  VDDA(3V3)  3.6 V [5] -0.3 - %

2.2 V  VDDA(3V3) < 2.7 V - 0.35 - %

ETabsolute error 2.7 V  VDDA(3V3)  3.6 V [6] -3- LSB

2.2 V  VDDA(3V3) < 2.7 V - 4- LSB

Rvsi voltage source interface

resistance see Figure 35 -- 1/(7 

fclk(ADC) 

Cia)

k

Riinput resistance [7][8] -- 1.2 M

fclk(ADC) ADC clock frequency - - 4.5 MHz

fssampling frequency 10-bit resolution; 11 clock

cycles - - 400 kSamples/s

2-bit resolution; 3 clock

cycles 1.5 MSamples/s

Objective data sheet Rev. 1 — 4 June 2012 121 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 34. 10-bit ADC ch a ra c t er i stics

002aaf959

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDDA(3V3) − VSSA

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Objective data sheet Rev. 1 — 4 June 2012 122 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

[1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual).

[2] Settling time is calculated within 1/2 LSB of the final value.

Rs < 1/((7  fclk(ADC)  Cia)  2 k

Fig 35. ADC interface to pins

LPC43xx

ADC0_n/ADC1_n

Cia = 2 pF

Rvsi

VSS

VEXT

002aah084

ADC

COMPARATOR

2 kΩ (analog pin)

2.2 kΩ (multiplexed pin)

Table 30. DAC characteristics

VDDA(3V3) over specified ranges; Tamb =





C to +85



C; unless otherwise specified

Symbol Parameter Conditions Min Typ Max Unit

EDdifferential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] -0.8 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 1.0 - LSB

EL(adj) integral non-linearity code = 0 to 975

2.7 V  VDDA(3V3)  3.6 V

[1] -1.0 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 1.5 - LSB

EOoffset error 2.7 V  VDDA(3V3)  3.6 V [1] -0.8 - LSB

2.2 V  VDDA(3V3) < 2.7 V - 1.0 - LSB

EGgain error 2.7 V  VDDA(3V3)  3.6 V [1] -0.3 - %

2.2 V  VDDA(3V3) < 2.7 V - 1.0 - %

CLload capacitance - - 200 pF

RLload resistance 1 - - k

tssettling time [1] 0.4 s

Objective data sheet Rev. 1 — 4 June 2012 123 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

13. Application information

13.1 LCD panel signal usage

Table 31. LCD panel connections for STN single panel mode

External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel

LPC43xx pin

used LCD function LPC43xx pin

used LCD function

LCD_VD[23:8] - - - - - -

LCD_VD7 - - P8_4 UD[7] P8_4 UD[7]

LCD_VD6 - - P8_5 UD[6] P8_5 UD[6]

LCD_VD5 - - P8_6 UD[5] P8_6 UD[5]

LCD_VD4 - - P8_7 UD[4] P8_7 UD[4]

LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3]

LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2]

LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1]

LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0]

LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP

LCD_ENAB/

LCDM P4_6 LCDENAB/

LCDM

LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP

LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK

LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE

LCD_PWR P7_7 CDPWR P7_7 LCDPWR P7_7 LCDPWR

GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN

Table 32. LCD panel connections for STN dual panel mode

External pin 4-bit mono STN du al panel 8-bit mono STN dual panel Color STN dual panel

LPC43xx pin

used LCD function LPC43xx pin

used LCD function

LCD_VD[23:16] - - - - - -

LCD_VD15 - - PB_4 LD[7] PB_4 LD[7]

LCD_VD14 - - PB_5 LD[6] PB_5 LD[6]

LCD_VD13 - - PB_6 LD[5] PB_6 LD[5]

LCD_VD12 - - P8_3 LD[4] P8_3 LD[4]

LCD_VD11 P4_9 LD[3] P4_9 LD[3] P4_9 LD[3]

LCD_VD10 P4_10 LD[2] P4_10 LD[2] P4_10 LD[2]

LCD_VD9 P4_8 LD[1] P4_8 LD[1] P4_8 LD[1]

LCD_VD8 P7_5 LD[0] P7_5 LD[0] P7_5 LD[0]

LCD_VD7 - - UD[7] P8_4 UD[7]

LCD_VD6 - - P8_5 UD[6] P8_5 UD[6]

LCD_VD5 - - P8_6 UD[5] P8_6 UD[5]

LCD_VD4 - - P8_7 UD[4] P8_7 UD[4]

LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3]

Objective data sheet Rev. 1 — 4 June 2012 124 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2]

LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1]

LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0]

LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP

LCD_ENAB/

LCDM P4_6 LCDENAB/

LCDM

LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP

LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK

LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE

LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR

GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN

Table 32. LCD panel connections for STN dual panel mode

External pin 4-bit mono STN du al panel 8-bit mono STN dual panel Color STN dual panel

LPC43xx pin

used LCD function LPC43xx pin

used LCD function

Table 33. LCD panel connections for TFT panels

External

pin TFT 12 bit (4:4:4

mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC43xx

pin used LCD

function LPC43xx

pin used LCD

function LPC43xx pin

used LCD

function LPC43xx

pin used LCD

function

LCD_VD23 PB_0 BLUE3 PB_0 BLUE4 PB_0 BLUE4 BLUE7

LCD_VD22 PB_1 BLUE2 PB_1 BLUE3 PB_1 BLUE3 BLUE6

LCD_VD21 PB_2 BLUE1 PB_2 BLUE2 PB_2 BLUE2 BLUE5

LCD_VD20 PB_3 BLUE0 PB_3 BLUE1 PB_3 BLUE1 BLUE4

LCD_VD19 - - P7_1 BLUE0 P7_1 BLUE0 BLUE3

LCD_VD18 - - - - P7_2 intensity BLUE2

LCD_VD17 - - - - - - P7_3 BLUE1

LCD_VD16 - - - - - - P7_4 BLUE0

LCD_VD15 PB_4 GREEN3 PB_4 GREEN5 PB_4 GREEN4 PB_4 GREEN7

LCD_VD14 PB_5 GREEN2 PB_5 GREEN4 PB_5 GREEN3 PB_5 GREEN6

LCD_VD13 PB_6 GREEN1 PB_6 GREEN3 PB_6 GREEN2 PB_6 GREEN5

LCD_VD12 P8_3 GREEN0 P8_3 GREEN2 P8_3 GREEN1 P8_3 GREEN4

LCD_VD11 - - P4_9 GREEN1 P4_9 GREEN0 P4_9 GREEN3

LCD_VD10 - - P4_10 GREEN0 P4_10 intensity P4_10 GREEN2

LCD_VD9 - - - - - - P4_8 GREEN1

LCD_VD8 - - - - - - P7_5 GREEN0

LCD_VD7 P8_4 RED3 P8_4 RED4 P8_4 RED4 P8_4 RED7

LCD_VD6 P8_5 RED2 P8_5 RED3 P8_5 RED3 P8_5 RED6

LCD_VD5 P8_6 RED1 P8_6 RED2 P8_6 RED2 P8_6 RED5

LCD_VD4 P8_7 RED0 P8_7 RED1 P8_7 RED1 P8_7 RED4

LCD_VD3 - - P4_2 RED0 P4_2 RED0 P4_2 RED3

LCD_VD2 - - - - P4_3 intensity P4_3 RED2

LCD_VD1 - - - - - - P4_4 RED1

Objective data sheet Rev. 1 — 4 June 2012 125 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

13.2 Crystal oscillator

The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see

LPC43xx user manual).

The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.

The oscillator can operate in one of two modes: slave mode and oscillation mode.

•In slave mode, couple the input clock signal with a capacitor of 100 pF (CC in

Figure 36), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this

configuration can be left unconnected.

•External components and models used in oscillation mode are shown in Figure 37,

and in Table 34 and Table 35. Since the feedback resistance is integrated on chip,

only a crystal and the capacitances CX1 and CX2 need to be connected externally in

case of fundamental mode oscillation (L, CL and RS repres en t the f un d am e ntal

frequency). Capacitance CP in Figure 37 repr esent s the pa rallel p ackage cap acit ance

and must not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the

crystal manufacturer.

LCD_VD0 - - - - - - P4_1 RED0

LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP

LCD_ENAB

/LCDM P4_6 LCDENAB/

LCDM P4_6 LCDENAB/

LCDM

LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP

LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK

LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE

LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR

GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN

Table 33. LCD panel connections for TFT panels

External

pin TFT 12 bit (4:4:4

mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit

LPC43xx

pin used LCD

function LPC43xx

pin used LCD

function LPC43xx pin

used LCD

function LPC43xx

pin used LCD

function

Table 34. Recommended values for CX1/X2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency Maximum crystal series

resistance RS

External load capacitors

CX1, CX2

2 MHz < 200 33 pF, 33 pF

< 200 39 pF, 39 pF

< 200 56 pF, 56 pF

4 MHz < 200 18 pF, 18 pF

< 200 39 pF, 39 pF

< 200 56 pF, 56 pF

8 MHz < 200 18 pF, 18 pF

< 200 39 pF, 39 pF

Objective data sheet Rev. 1 — 4 June 2012 126 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

12 MHz < 160 18 pF, 18 pF

< 160 39 pF, 39 pF

16 MHz < 120 18 pF, 18 pF

< 80 33 pF, 33 pF

20 MHz < 100 18 pF, 18 pF

< 80 33 pF, 33 pF

Table 35. Recommended values for CX1/X2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency Maximum crystal series

resistance RS

External load capacitors CX1,

CX2

15 MHz < 80 18 pF, 18 pF

20 MHz < 80 39 pF, 39 pF

< 100 47 pF, 47 pF

Fig 36. Slave mode operation of the on-chip oscillator

Fig 37. Oscillator modes with extern al crystal model used for CX1/CX2 evaluation

Table 34. Recommended values for CX1/X2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency Maximum crystal series

resistance RS

External load capacitors

CX1, CX2

LPC43xx

XTAL1

100 pF

002aag379

002aag380

LPC43xx

XTAL1 XTAL2

CX2

CX1

XTAL

=CLCP

Objective data sheet Rev. 1 — 4 June 2012 127 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

13.3 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 an d

CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and

CRTCX2 ar e C RTCX1/2 = 20 (typical)  4 pF.

An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended

amplitude of the clock signal is V i(RMS) = 100 mV to 200 mV with a coupling capacitance of

5 pF to 10 pF.

13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

Connect the crystal on the PCB as close as possible to the oscillator input and output pins

of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone

crystal usag e have a common ground plane . Also connect the exter nal components to the

ground plain. To keep the noise coupled in via the PCB as small as possible, make loops

and parasitics as small as possible. Choose smaller values of CX1 and CX2 if parasitics

increase in the PCB layout.

Ensure that no high-speed or high-drive signals are near the RTCX1/2 signals.

13.5 Standard I/O pi n configuration

Figure 39 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver enabled/disabled

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Digital input: Input buffer enabled/disabled

•Analog input

The default configuration for standard I/O pins is input buffer disabled and pull-up

enabled. The weak MOS devices provide a drive capability equivalent to pull-up and

pull-down resistors.

Fig 38. RTC 32 kHz oscillator circuit

002aah083

LPC43xx

RTCX1 RTCX2

CRTCX2

CRTCX1

XTAL

Objective data sheet Rev. 1 — 4 June 2012 128 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

13.5.1 Reset pin configuration

Fig 39. Standard I/O pin configuration with analog input

slew rate bit EHS

pull-up enable bit EPUN

pull-down enable bit EPD

glitch

filter

analog I/O

ESD

VDDIO

VSSIO

input buffer enable bit EZI

filter select bit ZIF

data input to core

data output from core

enable output driver

002aah028

Fig 40. Reset pin configuration

reset

002aag702

DD(IO)

Rpu

ESD

20 ns RC

GLITCH FILTER PIN

Objective data sheet Rev. 1 — 4 June 2012 129 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

14. Package outline

Fig 41. Package outline LBGA256 package

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC

MO-192

JEITA

- - - - - -

SOT740-2

05-06-16

05-08-04

UNIT A

max

mm 1.55 0.45

0.35 1.1

0.9 0.55

0.45 17.2

16.8 17.2

16.8

DIMENSIONS (mm are the original dimensions)

LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm

A2b D E e

0.25

0.1

0.12

0.35

1/2 e

AA2

detail X

ball A1

index area

y1C

2 4 6 8 10 12 14 16

1 3 5 7 9 11 13 15

ball A1

index area

∅ vM

∅ wM

05 10 mm

scale

Objective data sheet Rev. 1 — 4 June 2012 130 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 42. Package outline of the TFBGA180 package

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT570-3

08-07-09

10-04-15

UNIT

mm max

nom

min

1.20

1.06

0.95

0.40

0.35

0.30

0.50

0.45

0.40

12.1

12.0

11.9

12.1

12.0

11.9 0.8 10.4 0.15 0.12

DIMENSIONS (mm are the original dimensions)

TFBGA180: thin fine-pitch ball grid array package; 180 balls

0 5 10 mm

scale

A1A2

0.80

0.71

0.65

b D E e e1

10.4

e2v w

0.05

y y1

0.1

ball A1

index area

2468101214

135791113

1/2 e

1/2 e AC B

∅ vMC∅ wM

ball A1

index area

detail X

AA2

Objective data sheet Rev. 1 — 4 June 2012 131 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 43. Package outline of the LQFP208 p ackage

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 28.1

27.9 0.5 30.15

29.85 1.43

1.08 7

0.080.121 0.08

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT459-1 136E30 MS-026 00-02-06

03-02-20

D(1)

28.1

27.9

30.15

29.85

1.43

1.08

pin 1 index

EA1

detail X L

(A )

HA2

vMB

vMA

208

157

156 105

104

0 5 10 mm

scale

LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

max.

1.6

Objective data sheet Rev. 1 — 4 June 2012 132 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

15. Soldering

Fig 44. Reflow soldering of the LBGA256 package

DIMENSIONS in mm

PSLSPSRHxHy

SOT740-2

solder land plus solder paste

occupied area

Footprint information for reflow soldering of LBGA256 package

solder land

solder paste deposit

solder resist

Generic footprint pattern

Refer to the package outline drawing for actual layout

detail X

see detail X

sot740-2_fr

1.00 0.450 0.450 0.600 17.500 17.500

Objective data sheet Rev. 1 — 4 June 2012 133 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 45. Reflow soldering of the TFBGA180 package

DIMENSIONS in mm

PSLSPSRHxHy

SOT570-3

solder land plus solder paste

occupied area

Footprint information for reflow soldering of TFBGA180 package

solder land

solder paste deposit

solder resist

Generic footprint pattern

Refer to the package outline drawing for actual layout

detail X

see detail X

sot570-3_fr

0.80 0.400 0.400 0.550 12.575 12.575

Objective data sheet Rev. 1 — 4 June 2012 134 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Fig 46. Reflow soldering of the LQFP208 package

SOT459-1

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP208 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C

sot459-1_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

31.300 31.300 28.300 28.3000.500 0.560 0.2801.500 0.400 28.500 28.500 31.550 31.550

Objective data sheet Rev. 1 — 4 June 2012 135 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

16. Abbreviations

Table 36. Abbreviations

Acronym Description

ADC Analog-to-Di gital Converter

AES Advanced Encryption Standard

AHB Advanced High-performan ce Bus

APB Advanced Peripheral Bus

API Application Programming Interface

BOD BrownOut Detection

CAN Controller Area Network

CMAC Cipher-based Message Authentication Code

CSMA/CD Carrier Sense Multiple Access with Collision Detection

DAC Digital-to-Analog Converte r

DC-DC Direct Current-to-Direct Current

DMA Direct Memory Access

GPIO General Purpose Input/Output

IRC Internal RC

IrDA Infrared Data Association

JTAG Joint Test Action Group

LCD Liquid Crystal Display

LSB Least Significant Bit

MAC Med ia Access Control

MCU MicroController Unit

MIIM Media Independent Interface Management

n.c. not connected

OHCI Open Host Controller Interface

OTG On-The-Go

PHY Physical Layer

PLL Phase-Locked Loop

PMC Power Mode Control

PWM Pulse Width Modulator

RIT Repetitive Interrupt Timer

RMII Reduced Media Independent Interface

SDRAM Synchronou s Dynamic Random Access Memory

SIMD Single Instruction Multiple Data

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

TCP/IP Transmission Control Protocol/Internet Protocol

TTL Tra nsi stor-Transi sto r Lo g i c

UART Universal Asynchronous Receiver/Transmitter

ULPI UTMI+ Low Pin Interface

Objective data sheet Rev. 1 — 4 June 2012 136 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

USART Universal Synchro nous Asynchronous Receiver/Transmitter

USB Universal Serial Bus

UTMI USB2.0 Transceiver Macrocell Interface

Table 36. Abbreviations …continued

Acronym Description

Objective data sheet Rev. 1 — 4 June 2012 137 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

17. Revision history

Table 37. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC4357_53 v.1 20120604 Objective data sheet - -

Objective data sheet Rev. 1 — 4 June 2012 138 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descri bed in this d ocument may have change d since this document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environme ntal

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminar y specification.

Product [short] dat a sheet Production This document contains the product specification.

Objective data sheet Rev. 1 — 4 June 2012 139 of 141

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Objective data sheet Rev. 1 — 4 June 2012 140 of 141

continued >>

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 5

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . 59

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 59

7.2 ARM Cortex-M4 processor. . . . . . . . . . . . . . . 59

7.3 ARM Cortex-M0 co-processor . . . . . . . . . . . . 59

7.4 Interprocessor communication . . . . . . . . . . . . 59

7.5 AHB multilayer matrix. . . . . . . . . . . . . . . . . . . 60

7.6 Nested Vectored Interrupt Controller (NVIC) . 60

7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 61

7.7 System Tick timer (SysTick) . . . . . . . . . . . . . . 61

7.8 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.9 Global Input Multiplexer Array (GIMA) . . . . . . 61

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 62

7.11 On-chip flash memory . . . . . . . . . . . . . . . . . . 62

7.12 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.13 Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.14 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 64

7.15 Security features. . . . . . . . . . . . . . . . . . . . . . . 67

7.15.1 AES decryption. . . . . . . . . . . . . . . . . . . . . . . . 67

7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.15.2 One-Time Programmable (OTP) memory . . . 67

7.16 General Purpose I/O (GPIO) . . . . . . . . . . . . . 67

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.17 Configurable digital peripherals . . . . . . . . . . . 68

7.17.1 State Configurable Timer (SCT) subsystem. . 68

7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.17.2 Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 69

7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.18 AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 69

7.18.1 General Purpose DMA (GPDMA). . . . . . . . . . 69

7.18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.18.2 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 70

7.18.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.18.3 SD/MMC card interface . . . . . . . . . . . . . . . . . 70

7.18.4 External Memory Controller (EMC). . . . . . . . . 70

7.18.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.18.5 High-speed USB Host/Device/OT G interface

(USB0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.18.6 High-speed USB Host/Device interface with

ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.18.7 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 72

7.18.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.18.8 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.18.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.19 Digital serial peripherals. . . . . . . . . . . . . . . . . 73

7.19.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.19.2 USART0/2/3. . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.19.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.19.3 SPI serial I/O controller . . . . . . . . . . . . . . . . . 74

7.19.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.19.4 SSP serial I/O controller. . . . . . . . . . . . . . . . . 75

7.19.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.19.5 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 75

7.19.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.19.6 I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.19.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.19.7 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.19.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.20 Counter/timers and motor control . . . . . . . . . 77

7.20.1 General purpose 32-bit timers/external event

counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.20.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.20.2 Motor control PWM . . . . . . . . . . . . . . . . . . . . 77

7.20.3 Quadrature Encoder Interface (QEI) . . . . . . . 77

7.20.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.20.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 78

7.20.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.20.5 Windowed WatchDog Timer (WWDT) . . . . . . 78

7.20.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.21 Analog peripherals. . . . . . . . . . . . . . . . . . . . . 79

7.21.1 Analog-to-Digital Converter (ADC0/1) . . . . . . 79

7.21.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.21.2 Digital-to-Analog Converter (DAC). . . . . . . . . 79

7.21.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.22 Peripherals in the RTC power domain. . . . . . 79

7.22.1 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.22.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.22.1.2 Event monitor/recorder . . . . . . . . . . . . . . . . . 80

7.22.2 Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.23 System control. . . . . . . . . . . . . . . . . . . . . . . . 80

7.23.1 Configuration registers (CREG). . . . . . . . . . . 80

NXP Semiconductors LPC4357/53

32-bit ARM Cortex-M4/M0 microcontroller

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 June 2012

Document identifier : LP C 435 7_ 53

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

7.23.2 System Control Unit (SCU). . . . . . . . . . . . . . . 81

7.23.3 Clock Generation Unit (CGU). . . . . . . . . . . . . 81

7.23.4 Internal RC oscillator (IRC). . . . . . . . . . . . . . . 81

7.23.5 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 81

7.23.6 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 82

7.23.7 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.23.8 Reset Generation Unit (RGU). . . . . . . . . . . . . 82

7.23.9 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.23.10 Code security (Code Read Protection - CRP) 83

7.24 Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 84

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 85

9 Thermal characteristics . . . . . . . . . . . . . . . . . 86

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 87

10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 93

10.2 BOD static characteristics. . . . . . . . . . . . . . . . 97

10.3 Electrical pin characteristics. . . . . . . . . . . . . . 98

11 Dynamic characteristics . . . . . . . . . . . . . . . . 102

11.1 Flash/EEPROM memory . . . . . . . . . . . . . . . 102

11.2 Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 103

11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . 103

11.4 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 103

11.5 IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 104

11.6 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . 105

11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.8 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . 106

11.9 USART interface. . . . . . . . . . . . . . . . . . . . . . 107

11.10 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 108

11.11 External memory interface . . . . . . . . . . . . . . 111

11.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . 11 6

11.13 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

11.14 SD/MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

11.15 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12 ADC/DAC electrical characteristics . . . . . . . 120

13 Application information. . . . . . . . . . . . . . . . . 123

13.1 LCD panel signal usage . . . . . . . . . . . . . . . . 123

13.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 125

13.3 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . 127

13.4 XTAL and RTCX Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . 127

13.5 Standard I/O pin configuration . . . . . . . . . . . 127

13.5.1 Rese t pin configuration. . . . . . . . . . . . . . . . . 128

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 129

15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 135

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . 137

18 Legal information. . . . . . . . . . . . . . . . . . . . . . 138

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 138

18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 138

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 138

18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 139

19 Contact information . . . . . . . . . . . . . . . . . . . 139

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140