1. General description
The LPC4357/53 are ARM Cortex-M4 based microcontrollers for embedded applications
which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 1 36 kB of on-chip
SRAM, 16 kB of EEPROM memory, advanced configurable peripherals such as the State
Configurable Timer (SCT) and the Serial Gene ral Purpose I/O (SGPIO) interface, two
High-speed USB controllers, Ethernet, LCD, an external me mo ry controller, and multiple
digital a nd a nalog pe rip her als. The L PC4 35 7/ 53 o per ate at CPU fr equ encies of up to 204
MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard arch itec tu re with separate local instruction and data buses as well as a third bus
for peripherals, and includ es an internal pr efetch unit th at support s speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energ y-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
performance with a simple instruction set and reduced code size.
2. Features and benefits
Cortex-M4 Proc e sso r core
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NM I) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoint s, and four wa tch
points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 Proc e sso r core
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
application processor.
Running at frequencies of up to 204 MHz.
JTAG, Serial Wire Debug, and built-in NVIC.
LPC4357/53
32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC
Rev. 1 — 4 June 2012 Objective data sheet
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Objective data sheet Rev. 1 — 4 June 2012 2 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
136 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64 kB ROM containing boot code and on-chip software drivers.
128 bit general-purpose One-Time Programmable (OTP) memory.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with four lanes and up to 60 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
Two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One SPI controller.
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1Mbit/s.
One standard I2C-bus interface with monitor mode and with standard I/O pins.
Two I2S interfaces, each with DMA support and with one input and one output.
Digital peripherals
External Memory Con tro lle r (EM C) su pp or tin g ex te rn al SRAM , ROM , NO R flash ,
and SDRAM devices.
LCD controller with DMA support and a programmable display resolution of up to
1024 H 768 V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4 /8 bpp Color Look-Up Table (CLUT) and 16 /24-bit direct pixel
mapping.
Secure Digital Input Output (SD/MMC) card interface.
Eight-channel Genera l-Purpose DMA (GPDMA) controller can a ccess all memories
on the AHB and all DMA-capable AHB slaves.
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
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Objective data sheet Rev. 1 — 4 June 2012 3 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
Four general-purpose timer/counters with capture and match capabilities.
One motor control Pulse Width Modulator (PWM) for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer (WWDT).
Ultra-low power Real-Time Clock (RTC) on separate po wer d oma in with 25 6 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
Analog peripherals
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
Two 10-bit ADCs with DMA support and a dat a conversion rate of 40 0 kSamples/s.
Up to eight input channels per ADC.
Decryption:
Hardware-based AES decryption programmable through an on-chip API.
Two 128-bit secure OTP memories for AES key storage and customer use.
Random Number Generator (RNG) accessible through AES API.
Unique ID for each device.
Clock generation unit
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and
voltage.
Ultra-low power Real-Time Clock (RTC) crystal oscillator.
Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency cryst al. The second PLL is dedicated to the Hig h-speed USB, the
third PLL can be used as audio PLL.
Clock output.
Power
Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for th e
core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available as LQFP208, LBGA256, or TFBGA180 packages.
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 4 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
3. Applications
Motor control Embedded audio applications
Power management Industrial auto m at ion
White goods e-metering
RFID readers
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Objective data sheet Rev. 1 — 4 June 2012 5 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
4.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4357FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4357FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4353FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4353FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
Table 2. Ordering options
Type number Flash Flash
bank A Flash
bank B Total
SRAM LCD Ethernet USB0
(Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels GPIO
LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 164
LPC4357FET180 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 118
LPC4357FBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 142
LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 164
LPC4353FET180 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 118
LPC4353FBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 142
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Objective data sheet Rev. 1 — 4 June 2012 6 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
Fig 1. LPC4357/53 Block diagram
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
I-code bus
D-code bus
system bus
GPDMA LCD SD/
MMC
ETHERNET
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0
HOST/
DEVICE/OTG
HIGH-SPEED
USB1
HOST/DEVICE
EMC
HIGH-SPEED PHY
SPIFI
AES
HS GPIO
SPI
SGPIO
SCT
I2C0
I2S0
I2S1
C_CAN1
MOTOR
CONTROL
PWM
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
AHB MULTILAYER MATRIX
LPC4357/53
10-bit ADC0
10-bit ADC1
C_CAN0
I2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
002aah076
slaves
slaves
masters
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU
32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
512/256 kB FLASH A
512/256 kB FLASH B
16 kB EEPROM
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Objective data sheet Rev. 1 — 4 June 2012 7 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
6. Pinning information
6.1 Pinning
6.2 Pin description
On the LPC4357/53, digit al pin s are grouped into 1 6 port s, named P0 to P9 and PA to PF,
with up to 20 pins used per port. Each digital pin can support up to eight differ ent digital
functions, including General Purpose I/O (GPIO), selectable through the System
Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port
assigned to it.
Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA 180 package
002aah077
LPC4357/53FET256
Transparent top view
T
R
P
N
M
L
J
G
K
H
F
E
D
C
B
A
2 4 6 8 10 12
13
14
15
16
1357911
ball A1
index area
002aah078
LPC4357/53FET180
Transparent top view
N
L
P
M
K
J
H
G
F
D
B
E
C
A
2 4 6 8 10 12
13
14
1357911
ball A1
index area
Fig 4. Pin confi gura t io n LQ FP2 0 8 pac kag e
LPC4357/53FBD208
156
53
104
208
157
105
1
52
002aah079
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Objective data sheet Rev. 1 — 4 June 2012 8 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
Table 3. Pin description
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
Multiplexed digital pins
P0_0 L3 K3 47 [2] N;
PU I/O GPIO0[0] — General purpose digital input/output pin.
I/O SSP1_MISO — Master In Slave Out for SSP1.
IENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
I/O SGPIO0 — General purpose digital input/output pin.
-R — Function reserved.
-R — Function reserved.
I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
I/O I2S1_TX_WS — T ransmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
P0_1 M2 K2 50 [2] N;
PU I/O GPIO0[1] — General purpose digital input/output pin.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
IENET_COL — Ethernet Collision detect (MII interface).
I/O SGPIO1 — General purpose digital input/output pin.
-R — Function reserved.
-R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII interface).
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter
and read by the receiver . Corresponds to the signal SD in the I2S-bus
specification.
P1_0 P2 L1 54 [2] N;
PU I/O GPIO0[4] — General purpose digital input/output pin.
ICTIN_3 — SCT input 3. Capture input 1 of timer 1.
I/O EMC_A5 — External memory address line 5.
-R — Function reserved.
-R — Function reserved.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SGPIO7 — General purpose digital input/output pin.
I/O EMC_D12 — External memory data line 12.
P1_1 R2 N1 58 [2] N;
PU I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see
Table 5).
OCTOUT_7 — SCT output 7. Matc h ou tp ut 3 of timer 1.
I/O EMC_A6 — External memory address line 6.
I/O SGPIO8 — General purpose digital input/output pin.
-R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
-R — Function reserved.
I/O EMC_D13 — External memory data line 13.
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Objective data sheet Rev. 1 — 4 June 2012 9 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P1_2 R3 N2 60 [2] N;
PU I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see
Table 5).
OCTOUT_6 — SCT output 6. Matc h ou tp ut 2 of timer 1.
I/O EMC_A7 — External memory address line 7.
I/O SGPIO9 — General purpose digital input/output pin.
-R — Function reserved.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
-R — Function reserved.
I/O EMC_D14 — External memory data line 14.
P1_3 P5 M2 61 [2] N;
PU I/O GPIO0[10] — General purpose digital input/output pin.
OCTOUT_8 — SCT output 8. Matc h ou tp ut 0 of timer 2.
I/O SGPIO10 — General purpose digital input/output pin.
OEMC_OE — LOW active Output Enable signal.
OUSB0_IND1 — USB0 port indicator LED control
output 1.
I/O SSP1_MISO — Master In Slave Out for SSP1.
-R — Function reserved.
OSD_RST — SD/MMC reset signal for MMC4.4 card.
P1_4 T3 P2 64 [2] N;
PU I/O GPIO0[11] — General purpose digital input/output pin.
OCTOUT_9 — SCT output 9. Matc h ou tp ut 3 of timer 3.
I/O SGPIO11 — General purpose digital input/output pin.
OEMC_BLS0 — LOW active Byte Lane select signal 0.
OUSB0_IND0 — USB0 port indicator LED control output 0.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
I/O EMC_D15 — External memory data line 15.
OSD_VOLT1 — SD/MMC bus voltage select output 1.
P1_5 R5 N3 65 [2] N;
PU I/O GPIO1[8] — General purpose digital input/output pin.
OCTOUT_10 — SCT output 10. Match output 3 of timer 3.
-R — Function reserved.
OEMC_CS0 — LOW active Chip Select 0 signal.
IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external
circuitry required to detect over-current condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
OSD_POW — SD/MMC power monitor output.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
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NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P1_6 T4 P3 67 [2] N;
PU I/O GPIO1[9] — General purpose digital input/output pin.
ICTIN_5 — SCT input 5. Capture input 2 of timer 2.
-R — Function reserved.
OEMC_WE — LOW active Write Enable signal.
-R — Function reserved.
OEMC_BLS0 — LOW active Byte Lane select signal 0.
I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
P1_7 T5 N4 69 [2] N;
PU I/O GPIO1[0] — General purpose digital input/output pin.
IU1_DSR — Data Set Ready input for UART1.
OCTOUT_13 — SCT output 13. Match output 3 of timer 3.
I/O EMC_D0 — External memory data line 0.
OUSB0_PPWR — VBUS drive signal (towards external charge pump
or power management unit); indicates that VBUS must be driven
(active HIGH).
Add a pull-down resistor to disable the power switch at reset. This
signal has opposite polarity compared to the USB_PPW R used on
other NXP LPC parts.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
P1_8 R7 M5 71 [2] N;
PU I/O GPIO1[1] — General purpose digital input/output pin.
OU1_DTR — Data Terminal Ready output for UART1.
OCTOUT_12 — SCT output 12. Match output 3 of
timer 3.
I/O EMC_D1 — External memory data line 1.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
OSD_VOLT0 — SD/MMC bus voltage select output 0.
P1_9 T7 N5 73 [2] N;
PU I/O GPIO1[2] — General purpose digital input/output pin.
OU1_RTS — Request to Send output for UART1.
OCTOUT_11 — SCT output 11. Match output 3 of timer 2.
I/O EMC_D2 — External memory data line 2.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O SD_DAT0 — SD/MMC data bus line 0.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
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NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P1_10 R8 N6 75 [2] N;
PU I/O GPIO1[3] — General purpose digital input/output pin.
IU1_RI — Ring Indicato r in p ut for U ART1.
OCTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O EMC_D3 — External memory data line 3.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O SD_DAT1 — SD/MMC data bus line 1.
P1_11 T9 P8 77 [2] N;
PU I/O GPIO1[4] — General purpose digital input/output pin.
IU1_CTS — Clear to Send input for UART1.
OCTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O EMC_D4 — External memory data line 4.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O SD_DAT2 — SD/MMC data bus line 2.
P1_12 R9 P7 78 [2] N;
PU I/O GPIO1[5] — General purpose digital input/output pin.
IU1_DCD — Data Carrier Detect input for UART1.
-R — Function reserved.
I/O EMC_D5 — External memory data line 5.
IT0_CAP1 — Capture input 1 of timer 0.
-R — Function reserved.
I/O SGPIO8 — General purpose digital input/output pin.
I/O SD_DAT3 — SD/MMC data bus line 3.
P1_13 R10 D6 83 [2] N;
PU I/O GPIO1[6] — General purpose digital input/output pin.
OU1_TXD — Transmitter output for UART1.
-R — Function reserved.
I/O EMC_D6 — External memory data line 6.
IT0_CAP0 — Capture input 0 of timer 0.
-R — Function reserved.
I/O SGPIO9 — General purpose digital input/output pin.
ISD_CD — SD/MMC card detect input.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
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NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P1_14 R11 K7 85 [2] N;
PU I/O GPIO1[7] — General purpose digital input/output pin.
IU1_RXD — Receiver input for UART1.
-R — Function reserved.
I/O EMC_D7 — External memory data line 7.
OT0_MAT2 — Match output 2 of timer 0.
-R — Function reserved.
I/O SGPIO10 — General purpose digital input/output pin.
-R — Function reserved.
P1_15 T12 P11 87 [2] N;
PU I/O GPIO0[2] — General purpose digital input/output pin.
OU2_TXD — Transmitter output for USART2.
I/O SGPIO2 — General purpose digital input/output pin.
IENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
OT0_MAT1 — Match output 1 of timer 0.
-R — Function reserved.
I/O EMC_D8 — External memory data line 8.
-R — Function reserved.
P1_16 M7 L5 90 [2] N;
PU I/O GPIO0[3] — General purpose digital input/output pin.
IU2_RXD — Receiver input for USART2.
I/O SGPIO3 — General purpose digital input/output pin.
IENET_CRS — Ethernet Carrier Sense (MII interface).
OT0_MAT0 — Match output 0 of timer 0.
-R — Function reserved.
I/O EMC_D9 — External memory data line 9.
IENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface).
P1_17 M8 L6 93 [3] N;
PU I/O GPIO0[12] — General purpose digital input/output pin.
I/O U2_UCLK — Serial clock input/output for USART2 in synchronous
mode.
-R — Function reserved.
I/O ENET_MDIO — Ethernet MIIM data input and output.
IT0_CAP3 — Capture input 3 of timer 0.
OCAN1_TD — CAN1 transmitter output.
I/O SGPIO11 — General purpose digital input/output pin.
-R — Function reserved.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 13 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P1_18 N12 N10 95 [2] N;
PU I/O GPIO0[13] — General purpose digital input/output pin.
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.
-R — Function reserved.
OENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
OT0_MAT3 — Match output 3 of timer 0.
ICAN1_RD — CAN1 receiver input.
I/O SGPIO12 — General purpose digital input/output pin.
I/O EMC_D10 — External memory data line 10.
P1_19 M11 N9 96 [2] N;
PU IENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII
interface) or Ethernet Reference Clock (RMII interface).
I/O SSP1_SCK — Serial clock for SSP1.
-R — Function reserved.
-R — Function reserved.
OCLKOUT — Clock output pin.
-R — Function reserved.
OI2S0_RX_MCLK — I2S receive master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
P1_20 M10 J10 100 [2] N;
PU I/O GPIO0[15] — General purpose digital input/output pin.
I/O SSP1_SSEL — Slave Select for SSP1.
-R — Function reserved.
OENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
IT0_CAP2 — Capture input 2 of timer 0.
-R — Function reserved.
I/O SGPIO13 — General purpose digital input/output pin.
I/O EMC_D11 — External memory data line 11.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 14 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P2_0 T16 N14 108 [2] N;
PU I/O SGPIO4 — General purpose digital input/output pin.
OU0_TXD — Transmitter output for USART0. See Table 4 for ISP
mode.
I/O EMC_A13 — External memory address line 13.
OUSB0_PPWR — VBUS drive signal (towards external charge pump
or power management unit); indicates that VBUS must be driven
(active HIGH).
Add a pull-down resistor to disable the power switch at reset. This
signal has opposite polarity compared to the USB_PPW R used on
other NXP LPC parts.
I/O GPIO5[0] — General purpose digital input/output pin.
-R — Function reserved.
IT3_CAP0 — Capture input 0 of timer 3.
OENET_MDC — Ethernet MIIM clock.
P2_1 N15 M13 116 [2] N;
PU I/O SGPIO5 — General purpose digital input/output pin.
IU0_RXD — Receiver input for USART0. See Table 4 for ISP mode.
I/O EMC_A12 — External memory address line 12.
IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external
circuitry required to detect over-current condition).
I/O GPIO5[1] — General purpose digital input/output pin.
-R — Function reserved.
IT3_CAP1 — Capture input 1 of timer 3.
-R — Function reserved.
P2_2 M15 L13 121 [2] N;
PU I/O SGPIO6 — General purpose digital input/output pin.
I/O U0_UCLK — Serial clock input/output for USART0 in synchronous
mode.
I/O EMC_A11 — External memory address line 11.
OUSB0_IND1 — USB0 port indicator LED control output 1.
I/O GPIO5[2] — General purpose digital input/output pin.
ICTIN_6 — SCT input 6. Capture input 1 of timer 3.
IT3_CAP2 — Capture input 2 of timer 3.
OEMC_CS1 — LOW active Chip Select 1 signal.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 15 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P2_3 J12 G11 127 [3] N;
PU I/O SGPIO12 — General purpose digital input/output pin.
I/O I2C1_SDA — I2C1 data input/output (this pin does not use a
specialized I2C pad).
OU3_TXD — Transmitter output for USART3. See Table 4 for ISP
mode.
ICTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of
timer 2.
I/O GPIO5[3] — General purpose digital input/output pin.
-R — Function reserved.
OT3_MAT0 — Match output 0 of timer 3.
OUSB0_PPWR — VBUS drive signal (towards external charge pump
or power management unit); indicates that VBUS must be driven
(active HIGH).
Add a pull-down resistor to disable the power switch at reset. This
signal has opposite polarity compared to the USB_PPW R used on
other NXP LPC parts.
P2_4 K11 L9 128 [3] N;
PU I/O SGPIO13 — General purpose digital input/output pin.
I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a
specialized I2C pad).
IU3_RXD — Receiver input for USART3. See Table 4 for ISP mode.
ICTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
I/O GPIO5[4] — General purpose digital input/output pin.
-R — Function reserved.
OT3_MAT1 — Match output 1 of timer 3.
IUSB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external
circuitry required to detect over-current condition).
P2_5 K14 J12 131 [3] N;
PU I/O SGPIO14 — General purpose digital input/output pin.
ICTIN_2 — SCT input 2. Capture input 2 of timer 0.
IUSB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.
IADCTRIG1 — ADC trigger input 1.
I/O GPIO5[5] — General purpose digital input/output pin.
-R — Function reserved.
OT3_MAT2 — Match output 2 of timer 3.
OUSB0_IND0 — USB0 port indicator LED control output 0.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 16 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P2_6 K16 J14 137 [2] N;
PU I/O SGPIO7 — General purpose digital input/output pin.
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.
I/O EMC_A10 — External memory address line 10.
OUSB0_IND0 — USB0 port indicator LED control
output 0.
I/O GPIO5[6] — General purpose digital input/output pin.
ICTIN_7 — SCT input 7.
IT3_CAP3 — Capture input 3 of timer 3.
OEMC_BLS1 — LOW active Byte Lane select signal 1.
P2_7 H14 G12 138 [2] N;
PU I/O GPIO0[7] — General purpose digital input/output pin. If this pin is
pulled LOW at reset, the part enters ISP mode or boots from an
external source (see Table 4 and Table 5).
OCTOUT_1 — SCT output 1. Matc h ou tp ut 3 of timer 3.
I/O U3_UCLK — Serial clock input/output for USART3 in synchronous
mode.
I/O EMC_A9 — External memory address line 9.
-R — Function reserved.
-R — Function reserved.
OT3_MAT3 — Match output 3 of timer 3.
-R — Function reserved.
P2_8 J16 H14 140 [2] N;
PU I/O SGPIO15 — General purpose digital input/output pin. Boot pin (see
Table 5).
OCTOUT_0 — SCT output 0. Matc h ou tp ut 0 of timer 0.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.
I/O EMC_A8 — External memory address line 8.
I/O GPIO5[7] — General purpose digital input/output pin.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
P2_9 H16 G14 144 [2] N;
PU I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see
Table 5).
OCTOUT_3 — SCT output 3. Matc h ou tp ut 3 of timer 0.
I/O U3_BAUD — Baud pin for USART3.
I/O EMC_A0 — External memory address line 0.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 17 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P2_10 G16 F14 146 [2] N;
PU I/O GPIO0[14] — General purpose digital input/output pin.
OCTOUT_2 — SCT output 2. Matc h ou tp ut 2 of timer 0.
OU2_TXD — Transmitter output for USART2.
I/O EMC_A1 — External memory address line 1.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
P2_11 F16 E13 148 [2] N;
PU I/O GPIO1[11] — General purpose digital input/output pin.
OCTOUT_5 — SCT output 5. Matc h ou tp ut 3 of timer 3.
IU2_RXD — Receiver input for USART2.
I/O EMC_A2 — External memory address line 2.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
P2_12 E15 D13 153 [2] N;
PU I/O GPIO1[12] — General purpose digital input/output pin.
OCTOUT_4 — SCT output 4. Matc h ou tp ut 3 of timer 3.
-R — Function reserved.
I/O EMC_A3 — External memory address line 3.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O U2_UCLK — Serial clock input/output for USART2 in synchronous
mode.
P2_13 C16 E14 156 [2] N;
PU I/O GPIO1[13] — General purpose digital input/output pin.
ICTIN_4 — SCT input 4. Capture input 2 of timer 1.
-R — Function reserved.
I/O EMC_A4 — External memory address line 4.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 18 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P3_0 F13 D12 161 [2] N;
PU I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
OI2S0_RX_MCLK — I2S receive master clock.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
OI2S0_TX_MCLK — I2S transmit master clock.
I/O SSP0_SCK — Serial clock for SSP0.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
P3_1 G11 D10 163 [2] N;
PU I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
ICAN0_RD — CAN receiver input.
OUSB1_IND1 — USB1 Port indicator LED control output 1.
I/O GPIO5[8] — General purpose digital input/output pin.
-R — Function reserved.
OLCD_VD15 — LCD data.
-R — Function reserved.
P3_2 F11 D9 166 [2] OL;
PU I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter
and read by the receiver . Corresponds to the signal SD in the I2S-bus
specification.
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter
and read by the receiver . Corresponds to the signal SD in the I2S-bus
specification.
OCAN0_TD — CAN transmitter output.
OUSB1_IND0 — USB1 Port indicator LED control output 0.
I/O GPIO5[9] — General purpose digital input/output pin.
-R — Function reserved.
OLCD_VD14 — LCD data.
-R — Function reserved.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 19 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P3_3 B14 B13 169 [4] N;
PU -R — Function reserved.
I/O SPI_SCK — Serial clock for SPI.
I/O SSP0_SCK — Serial clock for SSP0.
OSPIFI_SCK — Serial clock for SPIFI.
OCGU_OUT1 — CGU spare clock output 1.
-R — Function reserved.
OI2S0_TX_MCLK — I2S transmit master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
P3_4 A15 C14 171 [2] N;
PU I/O GPIO1[14] — General purpose digital input/output pin.
-R — Function reserved.
-R — Function reserved.
I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.
OU1_TXD — Transmitter output for UART 1.
I/O I2S0_TX_WS — T ransmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter
and read by the receiver . Corresponds to the signal SD in the I2S-bus
specification.
OLCD_VD13 — LCD data.
P3_5 C12 C11 173 [2] N;
PU I/O GPIO1[15] — General purpose digital input/output pin.
-R — Function reserved.
-R — Function reserved.
I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.
IU1_RXD — Receiver input for UART 1.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter
and read by the receiver . Corresponds to the signal SD in the I2S-bus
specification.
I/O I2S1_RX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification.
OLCD_VD12 — LCD data.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 20 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P3_6 B13 B12 174 [2] N;
PU I/O GPIO0[6] — General purpose digital input/output pin.
I/O SPI_MISO — Master In Slave Out for SPI.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.
-R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
-R — Function reserved.
-R — Function reserved.
P3_7 C11 C10 176 [2] N;
PU -R — Function reserved.
I/O SPI_MOSI — Master Out Slave In for SPI.
I/O SSP0_MISO — Master In Slave Out for SSP0.
I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
I/O GPIO5[10] — General purpose digital input/output pin.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
-R — Function reserved.
-R — Function reserved.
P3_8 C10 C9 179 [2] N;
PU -R — Function reserved.
ISPI_SSEL — Slave Select for SPI. Note that this pin in an input pin
only. The SPI in master mode cannot drive the CS input on the slave.
Any GPIO pin can be used for SPI chip select in master mode.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
I/O SPIFI_CS — SPIFI serial flash chip select.
I/O GPIO5[11] — General purpose digital input/output pin.
I/O SSP0_SSEL — Slave Select for SSP0.
-R — Function reserved.
-R — Function reserved.
P4_0 D5 D4 1 [2] N;
PU I/O GPIO2[0] — General purpose digital input/output pin.
OMCOA0 — Motor control PWM channel 0, output A.
INMI — External interrupt input to NMI.
-R — Function reserved.
-R — Function reserved.
OLCD_VD13 — LCD data.
I/O U3_UCLK — Serial clock input/output for USART3 in synchronous
mode.
-R — Function reserved.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 21 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P4_1 A1 D3 3 [5] N;
PU I/O GPIO2[1] — General purpose digital input/output pin.
OCTOUT_1 — SCT output 1. Matc h ou tp ut 3 of timer 3.
OLCD_VD0 — LCD data.
-R — Function reserved.
-R — Function reserved.
OLCD_VD19 — LCD data.
OU3_TXD — Transmitter output for USART3.
IENET_COL — Ethernet Collision detect (MII interface).
AI ADC0_1 — ADC0, input channel 1. Configure the pin as GPIO input
and use the ADC function select register in the SCU to select the
ADC.
P4_2 D3 A2 12 [2] N;
PU I/O GPIO2[2] — General purpose digital input/output pin.
OCTOUT_0 — SCT output 0. Matc h ou tp ut 0 of timer 0.
OLCD_VD3 — LCD data.
-R — Function reserved.
-R — Function reserved.
OLCD_VD12 — LCD data.
IU3_RXD — Receiver input for USART3.
I/O SGPIO8 — General purpose digital input/output pin.
P4_3 C2 B2 10 [5] N;
PU I/O GPIO2[3] — General purpose digital input/output pin.
OCTOUT_3 — SCT output 3. Matc h ou tp ut 3 of timer 0.
OLCD_VD2 — LCD data.
-R — Function reserved.
-R — Function reserved.
OLCD_VD21 — LCD data.
I/O U3_BAUD — Baud pin for USART3.
I/O SGPIO9 — General purpose digital input/output pin.
AI ADC0_0 — ADC0, input channel 0. Configure the pin as GPIO input
and use the ADC function select register in the SCU to select the
ADC.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 22 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P4_4 B1 A1 14 [5] N;
PU I/O GPIO2[4] — General purpose digital input/output pin.
OCTOUT_2 — SCT output 2. Matc h ou tp ut 2 of timer 0.
OLCD_VD1 — LCD data.
-R — Function reserved.
-R — Function reserved.
OLCD_VD20 — LCD data.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.
I/O SGPIO10 — General purpose digital input/output pin.
ODAC — DAC output. Configure the pin as GPIO input and use the
analog function select register in the SCU to select the DAC.
P4_5 D2 C2 15 [2] N;
PU I/O GPIO2[5] — General purpose digital input/output pin.
OCTOUT_5 — SCT output 5. Matc h ou tp ut 3 of timer 3.
OLCD_FP — Frame pulse (STN). Vertical synchronization pulse
(TFT).
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O SGPIO11 — General purpose digital input/output pin.
P4_6 C1 B1 17 [2] N;
PU I/O GPIO2[6] — General purpose digital input/output pin.
OCTOUT_4 — SCT output 4. Matc h ou tp ut 3 of timer 3.
OLCD_ENAB/LCDM — STN AC bias drive or TFT data enable inp ut.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O SGPIO12 — General purpose digital input/output pin.
P4_7 H4 F4 21 [2] O;
PU OLCD_DCLK — LCD panel clock.
IGP_CLKIN — General purpose clock input to the CGU.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
-R — Function reserved.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I2S-bus
specification.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description
LPC4357_53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Objective data sheet Rev. 1 — 4 June 2012 23 of 141
NXP Semiconductors LPC4357/53
32-bit ARM Cortex-M4/M0 microcontroller
P4_8 E2 D2 23 [2] N;
PU -R — Function reserved.
ICTIN_5 — SCT input 5. Capture input 2 of timer 2.
OLCD_VD9 — LCD data.
-R — Function reserved.
I/O GPIO5[12] — General purpose digital input/output pin.
OLCD_VD22 — LCD data.
OCAN1_TD — CAN1 transmitter output.
I/O SGPIO13 — General purpose digital input/output pin.
P4_9 L2 J2 48 [2] N;
PU -R — Function reserved.
ICTIN_6 — SCT input 6. Capture input 1 of timer 3.
OLCD_VD11 — LCD data.
-R — Function reserved.
I/O GPIO5[13] — General purpose digital input/output pin.
OLCD_VD15 — LCD data.
ICAN1_RD — CAN1 receiver input.
I/O SGPIO14 — General purpose digital input/output pin.
P4_10 M3 L3 51 [2] N;
PU -R — Function reserved.
ICTIN_2 — SCT input 2. Capture input 2 of timer 0.
OLCD_VD10 — LCD data.
-R — Function reserved.
I/O GPIO5[14] — General purpose digital input/output pin.
OLCD_VD14 — LCD data.
-R — Function reserved.
I/O SGPIO15 — General purpose digital input/output pin.
P5_0 N3 L2 53 [2] N;
PU I/O GPIO2[9] — General purpose digital input/output pin.
OMCOB2 — Motor control PWM channel 2, output B.
I/O EMC_D12 — External memory data line 12.
-R — Function reserved.
IU1_DSR — Data Set Ready input for UART 1.
IT1_CAP0 — Capture input 0 of timer 1.
-R — Function reserved.
-R — Function reserved.
Table 3. Pin description …continued
Pin name
LBGA256
TFBGA180
LQFP208
Reset state
[1]
Type
Description