Publication# 12081 Rev. EAmendment/0
Issue Date: May 1995 4-37
Advanced
Micro
Devices
Am27X512
512 Kilobit (65,536 x 8-Bit) CMOS ExpressROM Device
FINAL
DISTINCTIVE CHARACTERISTICS
■As an OTP EPROM alternative:
— Factory optimized programming
— Fully tested and guaranteed
■As a Mask ROM alternative:
— Shorter leadtime
— Lower volume per code
■Fast access time
— 70 ns
■Single +5 V power supply
■Compatible with JEDEC-approved EPROM
pinout
■±10% power supply tolerance
■High noise immunity
■Low power dissipation
— 100 µA maximum CMOS standby current
■Available in Plastic Dual In-Line Package (PDIP),
Plastic Leaded Chip Carrier (PLCC), and Thin
Small Outline Package (TSOP)
■Latch-up protected to 100 mA from –1 V to
VCC +1 V
■Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
GENERAL DESCRIPTION
The Am27X512 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC and
DC operating conditions to your stable code. It is organ-
ized as 65,536 by 8 bits and is available in plastic dual
in-line (PDIP), plastic leaded chip carrier (PLCC), and
thin small outline (TSOP) packages. ExpressROM de-
vices provide a board-ready memory solution for me-
dium to high volume codes with short leadtimes. This
offers manufacturers a cost-effective and flexible alter-
native to OTP EPROMs and mask programmed ROMs.
Access times as fast as 70 ns allow operation with high-
performance microprocessors with reduced WAIT
states. The Am27X512 offers separate Output Enable
(OE) and Chip Enable (CE) controls, thus eliminating
bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 µW in
standby mode.
BLOCK DIAGRAM
Output
Buffers
Y
Gating
Output Enable
Chip Enable
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ7
VCC
VSS
OE
524,288-Bit
Cell Matrix
A0–A15
Address
Inputs
12081E-1
CE
AMD
4-38 Am27X512
PRODUCT SELECTOR GUIDE
Family Part No.
Ordering Part No:
VCC ± 5% -255
VCC ± 10% -70 -90 -120 -150 -200
Max Access Time (ns) 70 90 120 150 200 250
CE (E) Access (ns) 70 90 120 150 200 250
OE (G) Access (ns) 70 40 50 65 75 100
Am27X512
CONNECTION DIAGRAMS
Top View
A15
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A8
A9
A11
NC
OE (G)/VPP
A10
CE (E)
DQ7
DQ6
A7
A12
DU
VCC
A14
A13
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
3
4
5
6
7
8
9
16
15
14
13
12
11
10
17
18
19
20
22
21
23
24
25
26
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
A8
A9
DQ7
DQ6
DQ5
DQ4
A11
1
2
A12
A13
28
27
CE (E)
A10
Note:
1. JEDEC nomenclature is in parentheses.
12081E-2
OE (G)/VPP
12081E-3
A15
PDIP PLCC
A14
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
OE/VPP
A11
A9
A8
A13
NC
A14
VCC
A15
NC
A12
A7
A6
A5
A4
A3
NC
A10
CE/PGM
O7
O6
O5
O4
O3
VSS
O2
O1
O0
NC
A0
A1
A2
12081E-4
Standard Pinout
TSOP*
*Contact local AMD sales office for package availability
AMD
4-39Am27X512
PIN DESIGNATIONS
A0–A15 = Address Inputs
CE (E) = Chip Enable Input
DQ0–DQ7 = Data Inputs/Outputs
DU = No External Connection (Do Not Use)
NC = No Internal Connection
OE (G) = Output Enable Input
VCC =V
CC Supply Voltage
VPP = Program Voltage Input
VSS = Ground
LOGIC SYMBOL
CE (E)
OE (G)
DQ0–DQ7
A0–A15
16 8
12081E-5
AMD
4-40 Am27X512
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is
formed by a combination of:
AM27X512 J
e. CODE DESIGNATION
d. TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
c. PACKAGE TYPE
P = 28-Pin Plastic Dual In-Line Package (PD 028)
J = 32-Pin Rectangular Plastic Leaded
Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TS 032)
b. SPEED OPTION
See Product Selector Guide and
Valid Combinations
a. DEVICE NUMBER/DESCRIPTION
Am27X512
512 Kilobit (65,536 x 8-Bit) CMOS ExpressROM Device
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
C
Assigned by AMD
-70 XXXXX
AM27X512-70
AM27X512-90
AM27X512-120
AM27X512-150
AM27X512-200
AM27X512-255
PC, JC, PI, JI,
EC, EI
AMD
4-41Am27X512
FUNCTIONAL DESCRIPTION
Read Mode
The Am27X512 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable OE
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs tOE after the falling edge of
OE, assuming that CE has been LOW and addresses
have been stable for at least tACC–tOE.
Standby Mode
The Am27X512 has a CMOS standby mode which re-
duces the maximum VCC current to 100 µA. It is placed
in CMOS-standby when CE is at VCC ± 0.3 V. The
Am27X512 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0 mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
■Low memory power dissipation
■Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE/VPP be
made a common connection to all devices in the array
and connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on
ExpressROM device arrays, a 4.7-µF bulk electrolytic
capacitor should be used between VCC and VSS for each
eight devices. The location of the capacitor should be
close to where the power supply is connected to
the array.
MODE SELECT TABLE
CE OE/VPP Outputs
Read VIL VIL DOUT
Output Disable X VIH Hi-Z
Standby (TTL) VIH X Hi-Z
Standby (CMOS) VCC ± 0.3 V X Hi-Z
Mode Pins
Note:
1. X = Either VIH or VIL
AMD
4-42 Am27X512
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products –65°C to +125°C. . . . . . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Voltage with Respect to VSS
All pins except VCC –0.6 V to VCC + 0.6 V. . . . . . .
VCC –0.6 V to +7.0 V. . . . . . . . . . . . . . . . . . . . . . .
Note:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
transitions, the inputs may overshoot V
SS
to –2.0 V for pe-
riods of up to 20 ns. Maximum DC voltage on input and
I/O pins is V
CC
+ 0.5 V which may overshoot to V
CC
+
2.0 V for periods up to 20ns.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)0°C to +70°C. . . . . . .
Industrial (I) Devices
Ambient Temperature (TA) –40°C to +85°C. . . . .
Supply Read Voltages
VCC for Am27X512-255 +4.75 V to +5.25 V. . . . . .
VCC for all other
valid combinations +4.50 V to +5.50 V. . . . . . . . .
Operating ranges define those limits between which the
functionality of the device is guaranteed.
AMD
4-43Am27X512
DC CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 2 and 4)
Parameter Parameter
Symbol Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = – 400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to +VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to +VCC 1.0 µA
ICC1 VCC Active Current CE = VIL, f = 10 MHz, 30 mA
(Note 3) IOUT = 0 mA
ICC2 VCC TTL Standby Current CE = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. Caution: the Am27X512 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. I
CC1
is tested with
OE
/V
PP
= V
IH
to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods less than 20 ns.
12081E-7
Figure 1. Typical Supply Current
vs. Frequency
VCC = 5.5 V, T = 25°C
Figure 2. Typical Supply Current
vs. Temperature
VCC = 5.5 V, f = 10 MHz
12081E-6
–75 –55 –25 0 25 50 75 100 125 150
30
25
20
15
10
12345678910
30
25
20
15
10
Supply Current
in mA
Supply Current
in mA
Frequency in MHz Temperature in °C
AMD
4-44 Am27X512
CAPACITANCE
Parameter Test
Symbol Parameter Description Conditions Typ Max Typ Max Typ Max Unit
CIN Input Capacitance VIN = 0 V 6 10 9 12 10 12 pF
COUT Output Capacitance VOUT = 0 V 8 10 9 12 12 14 pF
PL 032 TS 032 PD 028
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 3, and 4)
Parameter Test
JEDEC Standard Description Conditions -70 -90 -120 -150 -200 -255 Unit
tAVQV tRCC Address to CE = OE =VIL Min – – – – – –
Output Delay Max 70 90 120 150 200 250 ns
tELQV tCE Chip Enable to OE = VIL Min – – – – – –
Output Delay Max 70 90 120 150 200 250 ns
tGLQV tOE Output Enable to CE = VIL Min – – – – – –
Output Delay Max 40 40 50 50 50 50 ns
tEHQZ tDF Min 0 0 0 0 0 0
tGHQZ (Note 2) Max 25 30 30 30 30 30 ns
tAXQX tOH Output Hold from Min 0 0 0 0 0 0
Addresses,CE,orOE, Max – – – – – – ns
whicheveroccurredfirst
Parameter
Symbols Am27X512
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27X512 must not be removed from (or inserted into) a socket or board when V
PP
or V
CC
is applied.
4. Output Load: 1 TTL gate and C
L
= 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V for inputs and outputs
Chip Enable HIGH or
Output Enable HIGH,
whichever comes
first, to Output Float
AMD
4-45Am27X512
SWITCHING TEST CIRCUIT
Device
Under
Test
Diodes = IN3064
or Equivalent
CL
CL = 100 pF including jig capacitance
6.2 kΩ
2.7 kΩ
12081E-8
+5.0 V
SWITCHING TEST WAVEFORM
12081E-9
AC Testing: Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are < 20 ns.
2.4 V
0.45 V
2.0 V
0.8 V
Test Points
2.0 V
0.8 V
Input Output
AMD
4-46 Am27X512
KEY TO SWITCHING WAVEFORMS
KS000010
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
SWITCHING WAVEFORMS
12081E-10
Notes:
1.
OE
may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from
OE
or
CE
, whichever occurs first.
Addresses
CE
OE
Output
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF
(Note 2)
tOH
