MB89PV470-201CF - Fujitsu Limited

FUJITSU MICROELECTRONICS

DATA SHEET

2008.9

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89470 Series

MB89475/P475/PV470

■DESCRIPTION

The MB89470 series has been developed as a general-purpose version of the F2MC*-8L family consisting of

proprietary 8-bit, single-chip micro controllers.

In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-

bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, external interrupt 1 (edge) ,

exter n al int er rupt 2 (level) , 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset.

The MB89470 series is designed suitable for home appliance as well as in a wide range of applications for

consumer product.

* : F2MC is the abbreviation of FU JITSU Flexible Microcontroller.

■ FEATURES

• Package used

QFP package , LQFP package and SH-DIP package for MB89P475, MB89475

MQFP package for MB89 PV470 (Continued)

DS07-12552-2E

MB89470 Series

2DS07-12552-2E

(Continued)

• High-speed operating capability at low voltage

• Minimum execution time : 0.32 µs/12.5 MHz

•F

2MC-8L family CPU core

• Six timers

PWC timer (also usable as an interval timer)

PWM timer

8/16-bit timer/counter × 2

21-bit timebase timer

Watch prescaler

•Buzzer

7 frequency types are selectable by software

• External interrupts

Edge detection (Sel ectable edge) : 4 channels

Low-level interrupt (Wake-up function) : 5 channels

• A/D converter (8 channels)

10-bit successive approximation type

• UART/SIO

Synchronous/asynchronous data transfer capable

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Subclock mode (for dual clock prod uct)

Watch mode (for dual clock pr oduct)

• Watchdog timer reset

• I/O ports : Max 39 channels

Multiplication and division instructions

Instruction set optimized for controllers 16-bit arithmetic ope rations

Bit test and branch instructions

Bit manipulation instructions, etc.

MB89470 Series

DS07-12552-2E 3

■PRODUCT LINEUP

(Continued)

Part number

Parameter MB89475 MB89P475 MB89PV470

Classification Mass production products

(mask ROM produ ct) OTP Piggy-back

ROM size 16 K × 8-bit (internal ROM) 16 K × 8-bit (int ernal PROM,

can be written to by ROM

programmer) 32 K × 8-bit (external ROM)

RAM size 512 × 8 bits 1 K × 8 bits

CPU functions

Number of instru ctions

Instruction bit length

Instructi on length

Data bit length

Minimum execution time

Minimum interrupt processing time

: 136

: 8 bits

: 1 to 3 bytes

: 1, 8, 16 bits

: 0.32 µs/12.5 MHz

: 2.88 µs/12.5 MHz

Ports

Output-only ports (N-channel open drain)

Input-only ports

I/O ports (CMOS)

Total

: 7 pins

: 3 pins (1 pin in product with

dual clock)

: 29 pins

: 39 pins

21-bit Time-b ase

timer Interrupt period (0.82 ms, 3.3 ms, 26.2 ms, 419.4 ms) at 10 MHz

Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz

Watchdog timer Reset period ( 209.7 ms to 419.4 ms) at 10 MHz

Reset period ( 167.8 ms to 335.5 ms) at 12.5 MHz

Watch prescaler 17 bits

Interrupt cycle : 31.25 ms, 0.25 ms, 0. 5 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock

Pulse width count

timer

2 channels

8-bit one-shot timer operation (supports underflow output, operating clock period : 1, 4, 32

tinst*, external)

8-bit reload timer operation (supports square wave output, operating clock period : 1, 4,

32 tinst*, external)

8-bit pulse width measurem ent operatio n (support s continuous mea surement, H width, L

width, rising edge to rising edge, falling edge to falling edge measurement and both edge

measurement)

PWM timer 8-bit reload timer operation (supports square wave output, operating clock period : 1, 4,

32 tinst*, external)

8-bit resolution PWM operation

8/16-bit timer /

counter 1, 2

Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with

its own independent opera ting clock cycle) , or as one 16-bit timer/counter

In Timer 1 or 16-bit timer/counter operation, event cou nter operation (external clock-trig-

gered) and square wave output capable

8/16-bit timer /

counter 3, 4

Can be operated either as a 2-channel 8-bit timer/counter (Timer 3 and Timer 4, each with

its own independent opera ting clock cycle) , or as one 16-bit timer/counter

In Timer 3 or 16-bit timer/counter operation, event cou nter operation (external clock-trig-

gered) and square wave output capable

External interrupt 4 independent ch annels (selectable edge, interrupt vector, request flag)

5 channels (low level interrupt)

MB89470 Series

4DS07-12552-2E

(Continued)

* : tinst is one instruction cycle (execution time) , which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock.

■PACKAGE AND CORRESPONDING PRODUCTS

O : Available

X : Not available

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Bef ore e v aluating using the piggyback product, verify its differ ence s fr om the product th at wil l actu ally be use d.

Take particular care on the following point :

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• For the MB89PV470, add the current consumed by the EPROM mounted in t he piggy-back socket.

• When operating at low speed, the current consumed by the one-time PROM product is greater than that for

the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode.

• For more informat ion, see “■ ELECTRICAL CHARACTERISTICS”.

3. Oscillation stabilization time after power-on reset

• For MB89PV470, there is no powe r-on stabilization time after power-on reset.

• F or MB89P475, there is power-on stabilization time after power-on reset.

• For MB89475, the power-on stabilization time can be select.

• For more information, refer to “■ MASK OPTIONS”.

Part number

Parameter MB89475 MB89P475 MB89PV470

A/D converter 10-bit resolution × 8 channels

A/D conversion function (conversion time : 60 tinst*)

Supports repeate d activation by internal clock.

UART/SIO Synchr on o us/ as yn chr o no us dat a tra n sfe r cap a ble

(Max baud rate : 78.125 Kbps at 10 MHz)

(7 and 8 bits with parity bit ; 8 and 9 bits without parity bit)

Buzzer output 7 frequency types (F CH/212, FCH/211, FCH/210, FCH/29, FCL/25, FCL/24, FCL/23) are selectable by

software.

Standby mode Sleep mode, stop mod e, subclock mode (dual clock pro duct) and watch mode (dual clo ck

product)

Process CMOS

Operating Voltage 2.2 V to 5.5 V 3.5 V to 5.5 V 2.7 V t o 5.5 V

Part number

Package MB89475 MB89P475 MB89PV470

DIP-48P-M01 O O X

FPT-48P-M26 O O X

FPT-48P-M13 O O X

MQP-48C-P01 X X O

MB89470 Series

DS07-12552-2E 5

■PIN ASSIGNMENTS

(Continued)

(TOP VIEW)

(DIP-48P-M01 )

*1 : For pin no. 2, connect this pin to an external 0.1 µF capacitor to ground (for MB89P475 only) .

For MB89PV470 and MB89475, this pin should be left unconnected.

*2 : High current drive type

VSS

C*1

P40/X0A

P41/X1A

P17/TO2

P16/EC2

P15/TO1

P14/EC1

P13/INT13

P12/INT12

P11/INT11

P10/INT10

P07/AN7

P06/AN6

P05/AN5

P04/AN4

P03/AN3

P02/AN2

P01/AN1

P00/AN0

AVSS

AVCC

P54/INT24

P53/INT23

MODE

P42

RST

P20/SCK1

P21/SO1

P22/SI1

P23/PWC

P24/PWM

P25/SI2

VCC

P26/SO2

P27/SCK2

P30/BUZ*2

P31*2

P32*2

P33*2

P34*2

P35*2

P36*2

P50/INT20

P51/INT21

P52/INT22

MB89470 Series

6DS07-12552-2E

(Continued)

(TOP VIEW)

(FPT-48P-M26)

(FPT-48P-M13)

*1 : For pin no. 20, connect this pin to an external 0.1 µF capacitor to gro und (for MB89P475 only) .

For MB89PV470 and MB89475, this pin should be left unconnected .

*2 : High current drive type

P33*2

P32*2

P31*2

P30/BUZ*2

P27/SCK2

P26/SO2

VCC

P25/SI2

P24/PWM

P23/PWC

P22/SI1

P21/SO1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/EC1

P15/TO1

P34*2

P35*2

P36*2

P50/INT20

P51/INT21

P52/INT22

P53/INT23

P54/INT24

AVCC

AVSS

P00/AN0

P01/AN1

P20/SCK1

RST

P42

MODE

VSS

C *1

P40/X0A

P41/X1A

P17/TO2

P16/EC2

MB89470 Series

DS07-12552-2E 7

(Continued)

(TOP VIEW)

(MQP-48C-P01)

*1 : Package uppe r-side pin assignment ( MB89PV470 only)

N.C. : As connected internally, do not use.

*2 : Pin no. 20 should be left unconne cted.

*3 : High current drive type

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

49 Vpp 57 N.C. 65 O4 73 OE

50A1258A266O574N.C.

51 A7 59 A1 67 O6 75 A11

52 A6 60 A0 68 O7 76 A9

53 A5 61 O1 69 O8 77 A8

54 A4 62 O2 70 CE 78 A13

55 A3 63 O3 71 A10 79 A14

56 N.C. 64 Vss 72 N.C. 80 Vcc

P33*3

P32*3

P31*3

P30/BUZ*3

P27/SCK2

P26/SO2

VCC

P25/SI2

P24/PWM

P23/PWC

P22/SI1

P21/SO1

P02/AN2

P03/AN3

P04/AN4

P05/AN5

P06/AN6

P07/AN7

P10/INT10

P11/INT11

P12/INT12

P13/INT13

P14/EC1

P15/TO1

P34*3

P35*3

P36*3

P50/INT20

P51/INT21

P52/INT22

P53/INT23

P54/INT24

AVCC

AVSS

P00/AN0

P01/AN1

P20/SCK1

RST

P42

MODE

VSS

C*2

P40/X0A

P41/X1A

P17/TO2

P16/EC2

MB89470 Series

8DS07-12552-2E

■PIN DESCRIPTION

(Continued)

Pin no. Pin name I/O

circuit Function

LQFP/QFP/

MQFP*2SDIP*1

17 47 X0 AConnection pins for a crystal or other oscillator.

An external clock can be connected to X0. In this case, leave X1

open.

18 48 X1

16 46 MODE B Input pins for setting the memory access mode.

Connect directly to VSS.

14 44 RST C

Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor

and a hysteresis inpu t. The pin outputs an “L” level wh en an internal

reset request is present. Inputting an “L” level initializes internal cir-

cuits.

38 to 31 20 to 13 P00/AN0 to

P07/AN7 DGeneral-purpose I/O port.

The pins are shared with the analog inputs for the A/D convert er.

30 to 27 12 to 9 P10/INT10

P13/INT13 EGeneral-purpose I/O port.

A hysteresis input fo r INT10 to INT13.

The pin is shared with an external interrupt 1 input.

26 8 P14/EC1 E General-purpose I/O port.

A hysteresis input for EC1.

The pin is shared with th e 8/1 6 bi t time r 1 inp ut .

25 7 P15/TO1 F General-purpose I/O port.

The pin is shared with the output of 8/16-bit timer 1.

24 6 P16/EC2 E General-purpose I/O port.

A hysteresis input for EC2.

The pin is shared with th e 8/1 6 bi t time r 2 inp ut .

23 5 P17/TO2 F General-purpose I/O port.

The pin is shared with the output of 8/16-bit timer 2.

13 43 P20/SCK1 E General-purpose I/O port.

A hysteresis input for SCK1.

The pin is shared with the clock I/O of UART/SIO 1.

12 42 P21/SO1 F General-purpose I/O port.

The pin is shared with th e ser i a l data ou tpu t of UART/ S IO 1.

11 41 P22/SI1 E General-purpose I/O port.

A hysteresis input for SI1.

The pin is shared with th e ser ia l da ta input of UART/SIO 1.

10 40 P23/PWC E General-purpose I/O port.

A hysteresis input fo r PWC.

This pin is shared with PWC input.

939P24/PWMF

General-purpose input port.

This pin is shared with PWM output.

8 38 P25/SI2 E General-purpose I/O port.

A hysteresis input for SI2.

The pin is shared with th e ser ia l da ta input of UART/SIO 2.

MB89470 Series

DS07-12552-2E 9

(Continued)

*1 : DIP-48P-M01

*2 : FPT-48P-M26/FPT-48P-M13/MQP-48C-P01

*3 : When MB89475 or MB89PV470 is used, this pin will become a N.C. pin without internal connection.

When MB89P475 is used, connect this pin to an external 0.1 µF capacitor to grou nd.

Pin no. Pin name I/O

circuit Function

LQFP/QFP/

MQFP*2SDIP*1

636P26/SO2F

General-pur pose I/O port.

The pin is shared with the seri al data output of UART/SIO 2.

535P27/SCK2E

General-pur pose I/O port.

A hysteresis input for SCK2.

The pin is shared with the clock I/O of UART/SIO 2.

434P30/BUZG

N-channel open-dr ain output.

The pin is shared with buzzer output.

3 to 1,

48 to 46 33 to

28 P31 to P36 G N-channel open-drain output.

21 3 P40/X0A

H General-purpose input port. (single clock system)

AConnection pins for a crystal or other oscillator. (dual clock system)

An external clock can be connected to X0A. In this case, leave X1A

open.

22 4 P41/X1A

H General-purpose input port. (single clock system)

AConnection pins for a crystal or other oscillator. (dual clock system)

An external clock can be connected to X0A. In this case, leave X1A

open.

15 45 P42 H General-purpose input port.

45 to 41 27 to

P50/INT20

P54/INT24 EGeneral-purpose I/O port.

A hysteresis input for INT20 to INT24.

The pin is shared with an external interrupt 2 input.

20 2 C ⎯Capacitor connection pin *3

737VCC ⎯Power supply pin ( +5 V) .

19 1 VSS ⎯Power supp ly pin (GND) .

40 22 AVCC ⎯A/D converter power supply pin.

39 21 AVSS ⎯A/D converter power supply pin.

Use at the same voltage level as VSS.

MB89470 Series

10 DS07-12552-2E

•External EPROM Socket (MB89PV470 only)

* : MQP-48C-P01

Pin no. Pin

name I/O Function

MQFP*

49 Vpp O “H” level output pin

A12

O Address output pins.

O3 I Data input pins.

64 VSS O Power supply pin (GND) .

I Data input pins.

70 CE O Chip enable pin for the ROM. Outputs “H” in standby mode.

71 A10 O Address output pin.

73 OE O Output enable pin for the ROM. Always outputs “L”.

A11

A13

A14

O Address output pins.

80 VCC O Power supply pin for the EPROM.

N.C. ⎯Internally connected pins. Always leave open.

MB89470 Series

DS07-12552-2E 11

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• Main and sub-clo ck circuits

• Oscillation feedback resistance

is approx. 500 kΩ f or main clock

circuit and 5 MΩ for sub-clock cir-

cuit.

• Hysteresis input

• The pull-down resistor is

approx. 50 kΩ.

(No pull-down resistor in

MB89P475)

• The pull-up resistance (P-chan-

nel) is approx. 50 kΩ.

• Hysteresis input

• CMOS output

•CMOS input

• Selec table pull-up resis tor

Approx. 50 kΩ

• CMOS output

•CMOS input

• Selec table pull-up resis tor

Approx. 50 kΩ

X1 (X1A)

X0 (X0A)

Nch Pch Pch

Nch

Stop mode control signal

Pch

Nch

Pch

Nch

Rpull-up

resistor register

ADIN

Pch

Nch

pull-up

resistor register

resources

port

MB89470 Series

12 DS07-12552-2E

(Continued)

Type Circuit Remarks

• CMOS output

•CMOS input

• Selec table pull-up resis tor

Approx. 50 kΩ

• N-channel open-drain output

• Selec table pull-up resis tor

Approx. 50 kΩ

H•CMOS input

Pch

Nch

pull-up

resistor regsiter

Pch

Nch

pull-up

resistor register

port

MB89470 Series

DS07-12552-2E 13

■HANDLING DEVICES

1. Preventing Latchup

Latchup ma y occur on CMOS I Cs if v oltage higher than VCC or lo wer than VSS is applied t o input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ra tings.

Also, take ca re to preven t the ana log power s upply (AVCC) and analog input from exceeding the digital power

supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Lea ving unu sed input pin s open could cause malfunctions . Th ey should be conn ected to a pull- up or pull-do wn

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter

Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the c ommercial freq uency (50 Hz to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

7. Note to noise in the External Reset Pin (RST)

If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it m ay cause malf unc-

tions. Use causion so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).

MB89470 Series

14 DS07-12552-2E

■PROGRAMMING OTPROM IN MB89P475 WITH SERIAL PROGRAMMER

1. Programming the OTPROM with serial programmer

• All OTP products can be programmed with serial programmer.

2. Programming the OTPROM

• To program the OTPROM using FUJITSU MCU programmer MB91919-001 .

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -281077 0

FAX (65) -2810220

3. Programming Adapter for OTPROM

• To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter

listed below.

Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -2810770

FAX (65) -2810220

4. OTPROM Content Protection

For product with OTPROM content protection feature (MB89P475-102, MB89P475-202) , OTPROM content can

be read using serial programmer if the OTPROM cont ent protection mechanism is not activated.

One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM

content. I f the prot ection code “00H” is wr itten in this address (FFFCH) , the OTPROM content cannot be read

by any serial programmer.

Note : The program written into the OTPROM cannot be verified once the OTPROM protection code is written (“00H”

in FFFCH) . It is advised to write the OTPROM protection code at last.

5. Programming Yield

All bits cannot be progr ammed at Fujit su shipping test to a bl ank ed O TPR OM microcomputer, d ue to its nature .

For this reason, a programming yield of 100% cannot be assured at all times.

Package Compatible so cket adap t er

DIP-48P-M01 MB91919-805+MB91919-800

FPT-48P-M26 MB91919-806+MB91919-800

FPT-48P-M13 MB91919-807+MB91919-800

MB89470 Series

DS07-12552-2E 15

■PROGRAMMING OTPROM IN MB89P475 WITH PROGRAMMER

1. Programming OTPROM with parallel programmer

• Only products without protection feature (i.e. MB89P475-101 and MB89P475-201) can be programmed with

parallel programmer. Product with protection feature (i.e. MB89P475-102 and MB89P475-202) cannot be

programmed with parallel programmer.

2. ROM Writer Adapters and Recommended ROM Writers

• The following shows ROM writer adapters and recommended ROM writers.

Fujitsu Microelectronics Asia Pte Ltd. (Serial programmer)

Inquiries : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -2810770

Writing data to the OTPROM

(1) Set the OTPROM writer for the CU50-OTP (device code : cdB6DC) .

(2) Load the program data to the OTPROM writer.

(3) Write data using the OTPROM writer.

3. Programming Yield

All bits cannot be progr ammed at Fujit su shipping test to a bl ank ed O TPR OM microcomputer, d ue to its nature .

For this reason, a programming yield of 100% cannot be assured at all times.

Package Applicable adapter model Recommended writer

DIP-48P-M01 MB91919-601

MB91919-001FPT-48P-M26 MB91919-602

FPT-48P-M13 MB91919-603

MB89470 Series

16 DS07-12552-2E

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Memory Space

Memory space in each mode is diagrammed below.

3. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

0000H

7FFFH

0000H

RAM

Not available

PROM

32 KB EPROM

32 KB

I/O

0080H

FFFFH

8000H

0880H

Address Normal operating

mode Corresponding a ddresses on

the EPROM programmer

MB89470 Series

DS07-12552-2E 17

■ BLOCK DIAGRAM

*1 : High Current Pins

*2 : Unconnected pin for MB89PV470 and MB89475

*3 : P40, P41 pins for single-clock system and X01A, X1A pins fo r dual-clock system

X0 Oscillator

Clock Controller

Sub-clock

Oscillator

Reset circuit

(Watchdog timer)

21-bit Time-base

timer

External interrupt 2

(Level)

External interrupt 1

(Level)

8/16-bit Timer 1, 2

UART/SIO 1

UART/SIO 2

Buzzer

8-bit PWC

8-bit PWM

8/16-bit Timer 3, 4

Watch Prescaler

Internal data bus

CMOS Input port 4

CMOS I/O port 0 P00/AN0

to P07/AN7

AVCC

AVSS

P10/INT10 to P13/INT13

P14/EC1

P15/TO1

P16/EC2

P20/SCK1

P21/SO1

P22/SI1

P23/PWC

P24/PWM

P25/SI2

P26/SO2

P27/SCK2

P30/BUZ*1

P31*1 to P36*1

P17/TO2

CMOS I/O port 1

CMOS I/O port 2

N-ch open-drain output port 3 6

10-bit

A/D converter

CMOS I/O port 5

1 Kbyte RAM/512 Byte RAM

16 Kbyte ROM

Other pins

MODE, VCC, VSS, C*2

F2MC-8L

CPU

P40/X0A*3

P41/X1A*3

P42

P50/INT20 to

P54/INT24

RST

MB89470 Series

18 DS07-12552-2E

■CPU CORE

1. Memory Space

The microcontroller s of th e MB89 470 seri es offe r a me mor y space of 64 Kbytes fo r sto ring all of I/ O, data, and

program are as. The I/O area is locat ed at the lowest address. The dat a area is prov ided immediately ab ove the

I/O area. Th e data area ca n be divided in to register, stack, and direct areas accor ding to the app lication. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89470 series is structured as illustrated below.

0000H

0080H

0100H

MB89PV470

I/O

RAM

Vacant

External

ROM

(32 K)

0000H

0080H

0100H

0200H

C000HC000H

8000H

FFFFH

I/O

RAM

Vacant

FFFFH

0280H0280H

0200H

0480H

FFC0HFFC0H

0000H

0080H

0100H

MB89P475MB89475

I/O

RAM

Vacant

Vector table (reset, interrupt, vector call instruction)

ROM ROM

FFFFH

0200H

FFC0H

General-

purpose

registers

General-

purpose

registers

General-

purpose

registers

Memory Map

MB89470 Series

DS07-12552-2E 19

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following registers are provided :

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR) . (See the diagram below.)

Program counter (PC) : A 16-bit registe r for indicating instruction storage positions

Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.

When the instruction is an 8-bit data processing instruction, the lower byte is

used.

Index register (IX) : A 16-bit register for index modification

Extra pointer (EP) : A 16-bit pointer for indicating a mem ory ad dr es s

Stack pointer (SP) : A 16-bit register for indicating a stack area

Program status (PS) : A 16-bit register for storing a register pointer, a condition code

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

16 bits

FFFDH

Undefined

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

Initial value

RP CCR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RP VacancyVacancy Vacancy H I IL1, 0 N Z VC

Structure of the Program Status Register

MB89470 Series

20 DS07-12552-2E

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag : Set when a carry or a borrow f rom bit 3 to bit 4 occurs as a result of an arithmet ic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1 IL0 Interrupt level High-low

00 1High

Low = no interrupt

10 2

11 3

N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag : Set if the compleme nt on 2 overflows as a result of an arit hmetic operation. Reset if the overflow doe s

not occur.

C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared other-

wise. Set to the shift-out vallue in the case of a shift instruction.

"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1

RP Lower OP codes

A7 A6 A5 A4 A3 A2 A1 A0

A15Generated addresses A14 A13 A12 A11 A10 A9 A8

Rule for Conversion of Actual Addresses of the General-purpose Register Area

MB89470 Series

DS07-12552-2E 21

The following gene ra l- pu rp o s e re gis te rs ar e pr ov ide d :

General-purpose registers : An 8-bit resister for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 32 banks can be used on the MB89470 series. The bank currently in use is

indicated by the register bank pointer (RP) .

This address = 0100

+ 8 × (RP)

Memory area

32 banks

MB89470 Series

22 DS07-12552-2E

■I/O MAP

(Continued)

Address Register name Register Description Read/Write Initial value

00HPDR0 Port 0 data register R/W XXXXXXXXB

01HDDR0 Port 0 data direction reg ister W* 00000000B

02HPDR1 Port 1 data register R/W XXXXXXXXB

03HDDR1 Port 1 data direction reg ister W* 00000000B

04HPDR2 Port 2 data regi ster R/W 00000000B

05H (Reserved)

06HDDR2 Port 2 data direction register R/W 00000000B

07HSYCC System clock control register R/W -XXMM-00B

08HSTBC Standby control register R/W 0001XXXXB

09HWDTC Watchdog timer control register W* 0---XXXXB

0AHTBTC Timebase timer con trol register R/W 00---000B

0BHWPCR Watch prescaler control register R/W 00--0000B

0CHPDR3 Port 3 data register R/W -1111111B

0DHPDR4 Port 4 data register R -----XXXB

0EHRSFR Reset flag register R XXXX----B

0FHBUZR Buzzer register R/W -----000B

10HPDR5 Port 5 data register R/W ---XXXXXB

11HDDR5 Port 5 data direction register R/W ---00000B

12H, 13H (Reserved)

14HT4CR Timer 4 control register R/W 000000X0B

15HT3CR Timer 3 control register R/W 000000X0B

16HT4DR Timer 4 data register R/W XXXXXXXXB

17HT3DR Timer 3 data register R/W XXXXXXXXB

18HT2CR Timer 2 control register R/W 000000X0B

19HT1CR Timer 1 control register R/W 000000X0B

1AHT2DR Timer 2 data register R/W XXXXXXXXB

1BHT1DR Timer 1 data register R/W XXXXXXXXB

1CH to 1FH (Reserved)

20HADC1 A/D control reg ister 1 R/W -00000X0B

21HADC2 A/D control register 2 R/W -0000001B

22HADDH A/D data register (Upper byte) R ------XXB

23HADDL A/D data register (Lower byte) R XXXXXXXXB

24HADER A/D input enable register R/W 11111111B

25H (Reserved)

26HSMC11 UART/SIO serial mode control register 11 R/W 00000000B

MB89470 Series

DS07-12552-2E 23

(Continued)

* : Bit manipulation instr u ction cannot be used.

Address Register name Register Description Read/Write Initial value

27H SMC12 UART/SIO serial mod e control register 12 R/W 00000000B

28HSSD1 UART/SIO serial status and data register 1 R 00001---B

29HSIDR1/SODR1 UART/SIO serial data register 1 R/W * XXXXXXXXB

2AHSRC1 UART/SIO serial rate control register 1 R/W XXXXXXXXB

2BHSMC21 UART serial mode control register 21 R/W 00000000B

2CHSMC22 UART serial mode control register 22 R/W 00000000B

2DHSSD2 UART ser ia l status an d da ta reg ist er 2 R 00001---B

2EHSIDR2/SODR2 UART serial data register 2 R/W * XXXXXXXXB

2FHSRC2 UART serial rate control register 2 R/W XXXXXXXXB

30HEIC1 External interrupt 1 control register 1 R/W 00000000B

31HEIC2 External interrupt 1 control register 2 R/W 00000000B

32HEIE2 External interrupt 2 enable register R/W ---00000B

33HEIF2 External interrupt 2 flag register R/W -------0B

34HPCR1 PWC control register 1 R/W 0-0--000B

35HPCR2 PWC control register 2 R/W 00000000B

36HPLBR PWC reload buffer register R/W XXXXXXXXB

37H (Reserved)

38HCNTR PWM timer control register R/W 0-00000000B

39HCOMR PWM timer compare register W* XXXXXXXXB

3AH to 6FH (Reserved)

70HPURC0 Port 0 pull up resistor control register R/W 11111111B

71HPURC1 Port 1 pull up resistor control register R/W 11111111B

72HPURC2 Port 2 pull up resistor control register R/W 11111111B

73HPURC3 Port 3 pull up resistor control register R/W -1111111B

74H (Reserved)

75HPURC5 Port 5 pull up resistor control register R/W ---1111B

76H to 7AH (Reserved)

7BHILR1 Interrupt level setting register 1 W* 11111111B

7CHILR2 Interrupt level setting register 2 W* 11111111B

7DHILR3 Interrupt level setting register 3 W* 11111111B

7EHILR4 Interrupt level setting register 4 W* 11111111B

7FH (Reserved)

MB89470 Series

24 DS07-12552-2E

•Read/write access symb o ls

•Initial value symbols

R/W : Readable and writable

R : Read-only

W : Write-only

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is undefined.

- : Unused bit.

M : The initial value of this bit is determined by mask option.

MB89470 Series

DS07-12552-2E 25

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V)

WARNING: Semiconductor devices can be permanently damaged by ap plication of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage VCC

AVCC VSS − 0.3 VSS + 6.0 V AVCC must not exceed V CC

Input voltage VIVSS − 0.3 VCC + 0.3 V

Output voltage VOVSS − 0.3 VCC + 0.3 V

“L” level maximum output cur rent IOL ⎯15 mA

“L” level average output current

IOLAV1 ⎯4mA

Average value (operating current

× operating rat e)

P00 to P07, P10 to P17,

P20 to P27, P50 to P54, RST

IOLAV2 ⎯12 mA Average value (operating current

× operating rat e)

P30 to P36

“L” level total maximum output

current ΣIOL ⎯100 mA

“L” level total average output

current ΣIOLAV ⎯40 mA Average value (operating current

× operating rat e)

“H” level maximum outp ut current IOH ⎯−15 mA

“H” level average output current IOHAV ⎯−2mA

Average value (operating current

× operating rat e)

“H” level total maximum output

current ΣIOH ⎯−50 mA

“H” level total average out put

current ΣIOHAV ⎯−20 mA Average value (operating current

× operating rat e)

Power consumption PD⎯300 mW

Operating temperature TA−40 +85 °C

Storage temperature Tstg −55 +150 °C

MB89470 Series

26 DS07-12552-2E

2. Recommended Operating Conditions (AVSS = VSS = 0.0 V)

* : These v alues depend on the oper ating conditions and the analog assurance range. See “Operating Voltage vs.

Main Clock Operating Frequency” and “5. A/D Converter Electrical Characteristics.”

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage VCC

AVCC

2.2* 5.5 V Operation assurance

range MB89475

3.5* 5.5 V Operation assurance

range MB89P475

2.7* 5.5 V Operation assurance

range MB89PV470

1.5 5.5 V Retains the RAM state in

stop mode

Operating temperature TA−40 +85 °C

MB89470 Series

DS07-12552-2E 27

• Operating Voltage vs. Main Clock Operating Frequency

“Operating Voltage vs. Main Clock Operating Frequency” indicates the operating frequency of the external oscilla-

tor at an instruction cycle of 4/FCH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the oper-

ating speed is switched using a gear.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconducto r device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data shee t. Users consider ing application outside th e listed cond itions are advised t o contact

their representatives beforehand.

5.5

5.0

4.5

4.0

3.5

3.0

2.0

2.7

2.2

1.0

Note : This area is not assured for MB89P475.

This area is not assured for MB89PV470 and MB89P475.

2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0

4.0 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 0.36 0.33

12.5

0.32

;

Operating

Voltage (V)

Analog accuracy

assurance range :

VCC = AVCC = 4.5 V to 5.5 V

Main clock

operating Freq. (MHz)

Min execution

time (inst. cycle) (µs)

;

MB89470 Series

28 DS07-12552-2E

3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

(Continued)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

“H” level

input voltage

VIH

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P42,

P50 to P54

⎯0.7 VCC ⎯VCC + 0.3 V

VIHS

RST, MODE, EC1,

EC2, SC K1, SI1,

SCK2, SI2, PWC,

INT10 to INT13,

INT20 to INT24

⎯0.8 VCC ⎯VCC + 0.3 V

“L” level

input voltage

VIL

P00 to P07,

P10 to P17,

P20 to P27,

P40 to P42,

P50 to P54

⎯VSS − 0.3 ⎯0.3 VCC V

VILS

RST, MODE, EC1,

EC2, SC K1, SI1,

SCK2, SI2, PWC,

INT10 to INT13,

INT20 to INT24

⎯VSS − 0.3 ⎯0.2 VCC V

Open-drain

output pin

application

voltage

VDP30 to P36 ⎯VSS − 0.3 ⎯VCC + 0.3 V

“H” level

output

voltage VOH

P00 to P07,

P10 to P17,

P20 to P27,

P50 to P54

IOH = −2.0 mA 4.0 ⎯⎯V

“L” level

output

voltage

VOL1

P00 to P07,

P10 to P17,

P20 to P27,

P50 to P54, RST

IOL = 4.0 mA ⎯⎯0.4 V

VOL2 P30 to P36 IOL = 12.0 mA ⎯⎯0.4 V

Input leak-

age current ILI

P00 to P07,

P10 to P17,

P20 to P27,

P50 to P54

0.45 V < VI < VCC −5⎯+5µAWithout

pull-up

resistor

Open drain

output

leakage

current

ILOD P30 to P36 0.45 V < VI < VCC −5⎯+5µA

MB89470 Series

DS07-12552-2E 29

(Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

P arameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Pull-down

resistance RDOWN MODE VI = VCC 25 50 100 kΩExcept

MB89P475

Pull-up

resistance RPULL

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P36,

P50 to P54, RST

VI = 0.0 V 25 50 100 kΩ

When pull-up

resistor is

selected (ex-

cept RST)

Power

supply

current

ICC1

VCC

FCH = 12.5 MHz

tinst = 0.32 µs

Main clock

run mode

⎯713mA

ICC2

FCH = 12.5 MHz

tinst = 5.12 µs

Main clock

run mode

⎯13mA

ICCS1

FCH = 12.5 MHz

tinst = 0.32 µs

Main clock

sleep mode

⎯2.5 5 mA

ICCS2

FCH = 12.5 MHz

tinst = 5.12 µs

Main clock

sleep mode

⎯0.7 2 mA

ICCL FCL =

32.768 kHz

Subclock mode

⎯37 85 µAMB89PV470

MB89475

⎯350 785 µA MB89P475

ICCLS

FCL =

32.768 kHz

Subclock sleep

mode

⎯11 30 µA

ICCT

FCL =

32.768 kHz

Watch mode

Main clock

stop mode

⎯1.4 15 µAMB89PV470

MB89475

⎯5.6 21 µA MB89P475

ICCH Ta = +25 °C

Subclock stop

mode 110µA

IAAVcc FCH = 12.5 MHz ⎯2.8 6 mA A/D

converting

IAH Ta = +25 °C⎯15µAA/D stop

Input

capacitance CIN Other than VCC,

VSS, AVCC, AVSS f = 1 MHz ⎯515pF

MB89470 Series

30 DS07-12552-2E

4. AC Characteristics

(1) Reset Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Notes : •tHCYL is the oscillation cycle (1/FC) to input to the X0 pin.

•If the reset pulse applied to the external re set pin (RST) does not meet the specifications, it may cause

malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external

reset pin (RST).

(2) Power-on Reset (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Note : Make sure that power supply rises within the selected oscillation stabilization time.

Rapid changes in power su pply vo ltag e may cause a powe r- on reset . If po we r su pp ly volt age need s t o be

varied in the course of ope ration, a smooth voltage rise is recommended.

Parameter Symbol Condition Value Unit Remarks

Min Max

RST “L” pulse width tZLZH ⎯48 tHCYL ⎯ns

Parameter Symbol Condition Value Unit Remarks

Min Max

Power supply rising time tR⎯⎯50 ms

Power supply cut-off ti me tOFF 1⎯ms Due to repeated operations

0.2 V

ZLZH

RST

0.2 V

3.5 V

0.2 V 0.2 V

tOFF

VCC

MB89470 Series

DS07-12552-2E 31

(3) Clock Timing (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Clock frequency FCH X0, X1 1 ⎯12.5 MHz

FCL X0A, X1A ⎯32.768 ⎯kHz

Clock cycle time tHCYL X0, X1 80 ⎯1000 ns

tLCYL X0A, X1A ⎯30.5 ⎯µs

Input clock pulse width

PWH

PWL X0 20 ⎯⎯ns

External clock

PWHL

PWLL X0A ⎯15.2 ⎯µs

Input clock rising/falling time tCR

tCF X0, X0A ⎯⎯10 ns

0.2 V

0.8 V

0.2 V

HCYL

X0 X1

C1 C2

FCH

When a crystal

ceramic oscillator is used

Open

When an external clock is used

FCH

X0 X1

X0 and X1 Timing and Conditions

Main Clock Conditions

MB89470 Series

32 DS07-12552-2E

(4) Instruction Cycle

Parameter Symbol Value Unit Remarks

Instruction cycle

(minimum execution time) tinst

4/FCH, 8/FCH, 16/FCH, 64/FCH µs (4/FCH) tinst = 0.32 µs when op erating

at FCH = 12.5 MHz

2/FCL µstinst = 61.036 µs when operating at

FCL = 32.768 kHz

X0A X1A

C0C1

Rd Open

When a crystal

ceramic oscillator is used When sub-clock is not used in dual clock product

X0A X1A

FCL Open

When an external clock is used

FCL

X0A X1A

0.8 VCC

tLCYL

0.2 VCC

PWHL PWLL

tCF tCR

X0A

Subclock Timing and Conditions

Subclock Conditions

MB89470 Series

DS07-12552-2E 33

(5) Serial I/O Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

* : For information on tinst, see “ (4) Instruction Cycle.”

Parameter Symbol Pin Condition Value Unit

Min Max

Serial clock cycle time tSCYC SCK1, SCK2

Internal shift

clock mode

2 tinst*⎯µs

SCK ↓ → SO time tSLOV SCK1, SO1, SCK2, SO2 −200 +200 ns

Valid SI → SCK ↑tIVSH SI1, SCK1, SI2, SCK2 1/2 tinst*⎯ns

SCK ↑ → valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 1/2 tinst*⎯ns

Serial clock “H” pulse width tSHSL SCK1, SCK2 External

shift clock

mode

1 tinst*⎯µs

Serial clock “L” pulse width tSLSH 1 tinst*⎯µs

SCK ↓ → SO time tSLOV SCK1, SO1, SCK2, SO2 0 200 n s

Valid SI → SCK ↑tIVSH SI1, SCK1, SI2, SCK2 1/2 tinst*⎯ns

SCK ↑ → valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 1/2 tinst*⎯ns

0.8 V

2.4 V

0.8 VCC

0.2 VCC

0.8 V

tSCYC

tSLOV

tIVSHtSHIX

SCK1, SCK2

SO1, SO2

SI1, SI2

0.8 V

0.8 VCC

0.2 VCC

0.2 VCC0.2 VCC

2.4 V

0.8 VCC 0.8 VCC

0.8 VCC

0.2 VCC

tSLSHtSHSL

tSLOV

tIVSHtSHIX

SCK1, SCK2

SO1, SO2

SI1, SI2

0.8 V

0.8 VCC

0.2 VCC

Internal Clock Operation

External Clock Operation

MB89470 Series

34 DS07-12552-2E

(6) Peripheral Input Timing (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

* : For information on tinst, see “ (4) Instruction Cycle.”

Parameter Symbol Pin Value Unit Remarks

Min Max

Peripheral input “H” pulse width 1 tILIH1 INT10 to INT1 3 ,

INT20 to INT24, EC1,

EC2, PWC

2 tinst*⎯µs

Peripheral input “L” pulse width 1 tIHIL1 2 tinst*⎯µs

0.2 V

0.8 V

IHIL1

0.8 V

INT10 to INT13,

INT20 to INT24,

EC1, EC2,

PWC

0.2 V

ILIH1

MB89470 Series

DS07-12552-2E 35

5. A/D Converter Electrical Characteristics

(1) A/D Converter Electrical Characteristi cs

(AVCC = VCC = 4.5 V to 5.5 V, AV SS = VSS = 0.0 V, TA = −40 °C to +85 °C)

* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics”.

(2) A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 210 = 1024.

• Linearity error (unit : LSB)

The de viation o f the straight line connecting the z ero tr ansition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics.

• Differential linearity error (unit : LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.

• Total error (u nit : LSB)

The difference between theoretical and actual conversion values.

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Resolution

⎯

⎯10 ⎯bit

Total error ⎯⎯±4.0 LSB

Linearity error ⎯⎯±2.5 LSB

Differential linearity error ⎯⎯±1.9 LSB

Zero transition voltage VOT AVSS −

1.5 LSB AVSS +

0.5 LSB AVSS +

2.5 LSB V

Full-scale transition

voltage VFST AVCC −

4.5 LSB AVCC −

2.5 LSB AVCC −

0.5 LSB V

A/D mode conversion time ⎯⎯⎯60 tinst*µs

Analog port input current IAIN AN0 to

AN7

⎯⎯10 µA

Analog input voltage VAIN AVSS ⎯AVCC V

MB89470 Series

36 DS07-12552-2E

(Continued)

FST

1.5 LSB

1 LSB

Analog input

Theoretical I/O characteristics

Digital output

0.5 LSB

3FF

3FE

3FD

004

003

002

001

Analog input

Total error

Digital output

VNT

Actual conversion

value

Actual

conversion

value

Theoretical

value

{1 LSB × N +

VOT}

AVCCAVSS

3FF

3FE

3FD

004

003

002

001

004

003

002

001

Analog input

Zero transition error

Digital output

Actual conversion

value

(Actual measurement)

Actual conversion

value3FF

3FE

3FD

3FC

Analog input

Full-scale transition error

Digital output

FST

(Actual

measurement)

Actual conversion

value

Theoretical value

Actual conversion value

1 LSB = VFST − VOT

1022 (V) Total error = VNT − {1 LSB × N + 0.5 LSB}

1 LSB

MB89470 Series

DS07-12552-2E 37

(Continued)

3FF

3FE

3FD

004

003

002

001

AVSS AVCC

VNT

{1 LSB × N + VOT}

Analog input

Linearity error

Digital output

Actual conversion

value

Actual conversion

value

Theoretical value

VOT (Actual measurement)

VFST

(Actual

measurement)

V (N + 1) T

VNT

N + 1

N − 1

N − 2

AVSS AVCC

Analog input

Differential linearity error

Digital output

Actual conversion

value

Actual conversion

value

Theoretical value

−1

Differential linearity error V (N + 1) T − VNT

1 LSB

Linearity err or VNT − {1 LSB × N + VOT}

1 LSB

= =

MB89470 Series

38 DS07-12552-2E

(3) Notes on Using A/D Converter

• Input impedance of the analog inp ut pins

The A/D con verter used for th e MB89470 series contains a sample & hold circuit as illustrated below to fetch

analog input v oltage into the sample & hold capacitor for 16 instruction cycles after act ivation A/ D conv ersion.

F or this reason, if the output impedance of the e xternal circuit f or the analog input is high, a nalog input voltage

might not stabilize within the analog input sampling per iod. Therefore, it is recommended to keep the output

impedance of the external circuit low.

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Sample & hold circuit MB89475

MB89PV470 MB89P475

R : analog input equivalent re sistance 2.2 kΩ2.6 kΩ

C : analog input equivalent capacitance 45 pF 28 pF

Analog input pin

Sample & hold circuit

If the analog input

impedance is higher

than to 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

Comparator

R C

Analog channel selector

Close for 16 instruction cycles after

activating A/D conversion.

Analog Input Circuit Model

MB89470 Series

DS07-12552-2E 39

■EXAMPLE CHARACTERISTICS

• “L” level output voltag e

• “H” level output voltage

• “H” level input voltage/“L” level input voltage

= 3.0 V

= 3.5 V

= 4.0 V

= 4.5 V

= 5.0 V

= 5.5 V

= 6.0 V

VOL1 − IOL (MB89475)

Ta = + 25 °C

VOL1 (V)

0.8

0.6

0.4

0.2

0.00246810

IOL1

(mA)

0.4

0.3

0.2

0.1

0.00246810121416

= 3.0 V

= 3.5 V

= 4.0 V

= 4.5 V

= 5.0 V

= 5.5 V

= 6.0 V

Ta = + 25 °C

VOL2 − IO2 (MB89475)

VOL2 (V)

IOL2 (mA)

(VCC − VOH ) − IOH (MB89475)

− V

(V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0−2−4−6−8−10

(mA)

VCC = 3.0 V

VCC = 3.5 V VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 6.0 V

VCC = 5.5 V

Ta = + 25 °C

CMOS Input (MB89475)

VIN (V)

VCC (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1234567

Ta = + 25 C

VIN (V)

VCC (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1234567

Ta = + 25 C

VIHS

VILS

CMOS hysteresis Input (MB89475)

VIHS : Threshold when input voltage in hysteresis

characteristics is set to “H” level.

VILS : Threshold when input voltage in hysteresis

characteristics is set to “L” level.

MB89470 Series

40 DS07-12552-2E

• Power supply current (External clock)

(Continued)

CC1

− V

(MB89475)

ICC1 (mA)

VCC (V)

0.0

2.0

4.0

6.0

8.0

10.0

1234567

Ta = + 25 °CFCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

FCH = 4.0 MHz

FCH = 2.0 MHz

FCH = 1.0 MHz

CC2

− V

(MB89475)

ICC1 (mA)

VCC (V)

0.0

0.2

0.4

0.6

0.8

1.0

1234567

Ta = + 25 °CFCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

FCH = 4.0 MHz

FCH = 2.0 MHz

FCH = 1.0 MHz

1.2

1.4

ICC1 (mA)

VCC (V)

0.0

0.5

1.0

1.5

2.0

2.5

1234567

Ta = + 25 °CFCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

FCH = 4.0 MHz

FCH = 2.0 MHz

FCH = 1.0 MHz

3.0

3.5

CCS1

− V

(MB89475)

ICC2 (mA)

VCC (V)

0.0

0.2

0.4

0.6

0.8

1.0

1234567

Ta = + 25 °CFCH = 12.5 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

FCH = 4.0 MHz

FCH = 2.0 MHz

FCH = 1.0 MHz

CCS2

− V

(MB89475)

MB89470 Series

DS07-12552-2E 41

(Continued)

Ta = + 25 °CFCH = 32.768 MHz

ICCL (µA)

1234567

VCC (V)

ICCL − VCC (MB89475)

FCH = 32.768 MHz

Ta = + 25 °C

ICCLS (µA)

ICCLS − VCC (MB89475)

1234567

VCC (V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

1234567

VCC (V)

ICCT (µA)

ICCT − VCC (MB89475)

Ta = + 25 °C

FCH = 32.768 MHz

MB89470 Series

42 DS07-12552-2E

• Pull-up resistance

Ta = + 25 °C

RPULL − VCC (MB89475)

RPULL (kΩ)

120

160

200

240

280

320

1234567

VCC (V)

MB89470 Series

DS07-12552-2E 43

■MASK OPTIONS

■ORDERING IN FORMATION

No. Part number MB89475 MB89P475 MB89PV470

Specifying procedure Specify when

ordering mask Setting not possible Setting not possible

1Selection of clock mode

• Single clock mode

• Dual clock mode Selectable 101/ 102 : Single clock

201/202 : Dual clock 101 : Single clock

201 : Dual clock

Selection of oscillation stabilization

time (OSC)

• The initial value of the oscillation

stabilization time for the main

cloc k can be set by selecting the

v a lues of th e WT M1 an d WT M0

bits on the right.

Selectable

OSC

1 : 214/FCH

2 : 217/FCH

3 : 218/FCH

Fixed to oscillation

stabilization time of

218/FCH

Fixed to oscillation

stabilization time of

218/FCH

Selection of power-on stabilization

time

• Nil

•2

17/FCH

Selectable Fixed to power-on sta-

bilization time of

217/FCH Fixed to nil

Part number Pa ckage Remarks

MB89475PFM

MB89P475-101PFM

MB89P475-102PFM

MB89P475-201PFM

MB89P475-202PFM

48-pin Plastic QFP

(FPT-48P-M13)

101 :

Single clock, without content protection

102 :

Single clock, with content protection

201 :

Dual clock, without content protection

202 :

Dual clock, with content protection

MB89475PMC

MB89P475-101PMC

MB89P475-102PMC

MB89P475-201PMC

MB89P475-202PMC

48-pin Plastic LQFP

(FPT-48P-M26)

MB89475P-SH

MB89P475-101P-SH

MB89P475-102P-SH

MB89P475-201P-SH

MB89P475-202P-SH

48-pin Plastic SH-DIP

(DIP-48P-M01)

MB89PV470-101CF

MB89PV470-201CF 48-pin Ceramic MQFP

(MQP-48C-P01)

MB89470 Series

44 DS07-12552-2E

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

48-pin plastic SH-DIP Lead pitch 1.778mm(70mil)

Row spacing 15.24mm(600mil)

Sealing method Pl astic mold

48-pin plastic SH-DIP

(DIP-48P-M01)

1994-2008 FUJITSU MICROELECTRONICS LIMITED D48002S-3C-4

43.69

+0.20

–0.30

+.008

–.012

1.720

13.80±0.25

(.543±.010)

INDEX-1

5.25(.207)

3.00(.118)

0.45±0.10

(.018±.004)

+.020

–0

.039

–0

+0.50

1.00

1.778±0.18

(.070±.007)

1.778(.070)

MAX

0.25±0.05

(.010±.002)

15.24(.600)

TYP 15°MAX

INDEX-2

40.894(1.610)REF

MAX

MIN

0.51(.020)MIN

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

MB89470 Series

DS07-12552-2E 45

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

48-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 7× 7 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weigh t 0.1 7 g

Code

(Reference) P-LFQFP48-7×7-0.50

48-pin plastic LQFP

(FPT-48P-M26)

2003 FUJITSU LIMITED F48040S-c-2-2

3625

INDEX

9.00±0.20(.354±.008)SQ

0.145±0.055

(.006±.002)

0.08(.003)

"A" 0˚~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Details of "A" part

112

0.08(.003)

(.008±.002)

0.20±0.05

0.50(.020)

LEAD No.

(Mounting height)

.276 –.004

+.016

–0.10

+0.40

7.00

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89470 Series

46 DS07-12552-2E

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/ (Continued)

48-pin plastic QFP Lead pitch 0.80 mm

Package width ×

package length 10 × 10 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 2.35 mm MAX

Code

(Reference) P-QFP44-10×10-0.80

48-pin plastic QFP

(FPT-48P-M13)

2003-2008 FUJITSU MICROELECTRONICS LIMITED F48023S-c-3-5

(.013±.002)

0.32±0.05

0.80(.031)

0.20(.008)

0.10(.004)

(.007±.002)

0.17±0.06

10.00±0.20(.394±.008)SQ

13.10±0.40(.516±.016)SQ

112

2536

INDEX

Details of "A" part

0.80±0.20

(.031±.008)

0.88±0.15

(.035±.006)

0.25(.010)

.008

–.008

+.004

–0.20

+0.10

0.20

(Stand off)

1.95

+0.40

–0.20

+.016

–.008

.077 (Mounting height)

0~8

"A"

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89470 Series

DS07-12552-2E 47

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

48-pin ceramic MQFP Lead pitch 0.8 mm

Lead shape Straight

Motherboard

materialCeramic

Mounted package

materialPlastic

48-pin ceramic MQFP

(MQP-48C-P01)

1994-2008 FUJITSU MICROELECTRONICS LIMITED M48001SC-4-3

14.82±0.35

(.583±.014)

15.00±0.25

(.591±.010)

17.20(.677)TYP

PIN No.1 INDEX

.430

–0

+.005

–0.0

+0.13

10.92

1.02±0.13

(.040±.005)

7.14(.281) 8.71(.343)

TYP

0.30(.012)TYP 4.50(.177)TYP

PAD No.1 INDEX

0.15±0.05

(.006±.002)

8.50(.335)MAX

0.60(.024)TYP1.10

+0.45

–0.25

+.018

–.010

.043

0.40±0.08

(.016±.003)

0.80±0.22

(.0315±.0087)

8.80(.346)REF

1.00(.040)TYP

1.50(.059)TYP

PIN No.1 INDEX

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

MB89470 Series

48 DS07-12552-2E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

Page Section Change Results

⎯⎯

Changed the package code.

FPT-48P-M05 → FPT-48P-M26

15 ■ PROGRAMMING OTPROM IN MB89P475

WITH PROGRAMMER Changed the "2. RO M Writer Adapters and Recom-

mended ROM Writers".

16 ■ PROGRAMMING TO THE EPROM WITH

PIGGYBACK/EVALUATION DEVICE Deleted the “2. Programming Socket Adapter”

■ ORDERING INFORMATION Order informations are changed.

MB89475PFV → MB89475PMC

MB89P475-101PFV → MB89P475-101PMC

MB89P475-102PFV → MB89P475-102PMC

MB89P475-201PFV → MB89P475-201PMC

MB89P475-202PFV → MB89P475-202PMC

45 ■ PACKAGE DIMENSIONS Changed the package figure.

FPT-48P-M05 → FPT-48P-M26

MB89470 Series

DS07-12552-2E 49

MEMO

MB89470 Series

50 DS07-12552-2E

MEMO

MB89470 Series

DS07-12552-2E 51

MEMO

MB89470 Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Ja pan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

F or further inf ormation please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U .S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

FUJITSU MICROELECTR ONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-36 88 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONI CS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The informatio n, such as desc riptions of function and application circuit examples, in this document a re present ed solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of functio n and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual p roper ty right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and househo ld use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe p hysical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redund ancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Business & Media Promotion Dept.