GLT40516-10E 32k x 16 Embedded EDO DRAM FEATURES Logical organization: 32k x 16 bits Physical organization: 256 x 128 x 16 Single 3.3V 0.3V power supply 256 cycle refresh in 4 ms Refresh modes: RAS only, CBR, and Hidden Dual CAS for Byte Write and Byte Read control Separate I/O operation 100 MHz page mode EDO cycle 30 ns row access time Redundancy: 2 WL/256K, 2 CS/1M GENERAL DESCRIPTION The 512Kbit Embedded DRAM (EmDRAM) is an asynchronous design with non-multiplexed row and column addressing scheme. The memory operations are controlled by RAS, CASH/CASL, and WE. Byte access is controlled by CASH (upper byte) and CASL (lower byte). The EmDRAM has been designed to support 200Mbyte data rate with a 30 ns latency when operated in the page mode with extended data output (EDO). this maximum rate can be sustained for one page of 12 bytes. Performance Data Parameter -30 Max. RAS access time, tRAC 30 ns Max. column address access time, tAA 12 ns Max. CAS access time, tCAC 8 ns Min. extended data out page mode cycle time, tPC 10 ns Min. read/write cycle time, tRC 60 ns May 1997 (Rev. 1) 1 GLT40516-10E FUNCTIONAL BLOCK DIAGRAM OE WE UCAS LCAS A[8:0] Column Address Buffers I/O Controller Y[8:0] Column Decoders DQ[7:0] Input Buffer Internal Address Counter Row Address Buffers Refresh Control Clock X[8:0] Sense Amps I/O Selector Output Buffer DQ[15:8] Input Buffer Memory Cells VSS VCC Figure 1. GLT44016 - 256K X 16 Signal Descriptions [1] Symbol Type Description DI[15:0] Input Data in. DO[15:0] Output Data out. XRA[7:0] Input Row address. XCA[7:0] Input Column address. RAS Input Row address strobe (active low). CASH Input Column address strobe, access DI/DO[15:8] (active low) CASL Input Column address strobe, access DI/DO[7:0] (active low) WE Input Write enable (active low). OE Input Output enable (active low). VDD Supply 3.3v voltage supply, 2 pairs double bond minimum VSS Supply Ground (voltage return), 2 pairs double bond minimum 1. On-chip power supply to the EmDRAM should be separated from the Logic portion. 2 G-LINK Technology May 1997 (Rev. 1) I/O Controller Output Buffer Word Drivers Timing Generator Row Decoders RAS GLT40516-10E Function Table Input Pin DQ Pin RAS LCAS UCAS WE OE DQ[7:0] DQ[15:8] H - - - - High-Z High-Z Functional Mode L H H - - High-Z High-Z Refresh L L H H L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High Z Standby - Truth Table Function RAS CAS WE OE Address DQM0 DQM1 DQM2 DQM3 DI[31:0] Standby H Read L H X L H Write (Early) Write DI[7:0] L L L L Write DI[15:8] L Write DI[23:16] L DO[31:0] X X X X X X X High-Z L Row/Col X X X X X Data Out L X Row/Col H H H H Data In High-Z L X Row/Col L H H H Data In High-Z L L X Row/Col H L H H Data In High-Z L L X Row/Col H H L H Data In High-Z Write DI[31:24] L L L X Row/Col H H H L Data In High-Z Read-Write L L HL LH Row/Col H H H H Data In Data Out Page-Mode Read (First Cycle) L HL H L Row/Col X X X X X Data Out HL H L Col X X X X X Data Out Page-Mode Read (Subsequent Cycles) Page-Mode Write (First Cycle) L HL L X Row/Col H H H H Data In High-Z Page-Mode Write (Subsequent Cycle) L HL L X Col H H H H Data In High-Z Page-Mode R-W (First Cycle) L HL HL LH Row/Col H H H H Data In Data Out Page-Mode R-W (Subsequent Cycle) L HL HL LH Col H H H H Data In Data Out HL L X X X X X X X X High-Z L H X X Row X X X X X High-Z CBR Refresh RAS-only Refresh G-LINK Technology May 1997 (Rev. 1) 3 GLT40516-10E ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Symbol Parameter Conditions Value Unit VT Voltage on any pin relative to VSS TA = 25 C -0.5 to +4.6 V IOS Short circuit output current TA = 25 C 50 mA PD Power dissipation TA = 25 C 1 W TOPR Operating temperature - 0 to +70 C TSTG Storage temperature - -55 to +150 C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = 0C to +70C) Symbol Min Typ Max Unit Power supply voltage 3.0 3.3 3.6 V 0 0 0 V VIH Input high voltage 2.4 - VCC +1 V VIL Input low voltage -1.0 - 0.8 V Min Typ VCC Parameter VSS Capacitance (VCC = 3.3V 10%, TA = 25C, f = 1 MHz) Symbol Max Unit Input capacitance (A[8:0]) - 1 pF CIN2 Input capacitance (RAS, LCAS, UCAS, WE, OE) - 1 pF CI/O Input/Output capacitance (DQ[15:0]) - 1 pF Note CIN1 Parameter DC Characteristics (VCC = 3.3V 10%, TA = 0C to +70C) -30 Symbol Parameter Condition Min Max Units 2.4 VCC V IOL = -1.0mA 0 0.4 V 0V VIN VCC -2 -2 A Output Leakage Current DQi Disable 0V VO 3.6V -10 Average Power Supply Current (Operating) RAS, CAS Cycling tRC = Min. ICC2 Power Supply Current (Standby) RAS, CAS=VIH ICC3 Average Power Supply Current (RAS-only Refresh) RAS Cycling CAS = VIH tRC = Min. ICC4 Average Power Supply Current (Fast Page Mode) ICC5 Average Power Supply Current (CAS-Before-RAS Refresh) VOH Output High Voltage IOH = -2 mA VOL Output Low Voltage ILI Input Leakage Current ILO ICC1 1. ICC Max. is specified for ICC for the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4 G-LINK Technology May 1997 (Rev. 1) -10 A 200 mA [1] [2] mA [1] 200 mA [1] [2] RAS = VIL CAS Cycling tHCP = Min. 140 mA [1] [3] RAS Cycling CAS-Before-RAS 200 mA GLT40516-10E AC Characteristics (VCC = 3.3 V 10%, TA = 0 C - 70 C, CL = 1 pF) Min Max Units tRC Symbol Random Read/Write cycle time Description 60 - ns Notes tPC Page Mode Read/Write cycle 10 - ns [1] [2] tOFF Read Data valid from RAS high 0 - ns [3] tDOH Read Data valid from next CAS low 3 - ns [4] tAA Access time from Column Address - 12 ns tRAC Access time from RAS low - 30 ns tCAC Access time from CAS low - 8 ns [2] tCPA Access time from CAS precharge - 14 ns [3] tRAS RAS pulse width 30 - ns tRCD RAS to CAS delay time 15 35 ns tCSH CAS hold time for RAS 30 tCAS CAS pulse width 4 - ns tASR Row Address setup time 3 - ns tRAH Row Address hold time 3 - ns tASC Column Address setup time 3 - ns tCAH Column Address hold time 3 - ns [2] [5] [6] [4] tCP CAS precharge time 4 - ns [7] tDS Write Data setup time 3 - ns [4] tDH Write Data hold time 3 - ns [2] tRP RAS precharge time 20 - ns tCRP CAS to RAS precharge time 15 - ns [3] tRSH CAS low to RAS high hold time 10 - ns [2] tRCS Read command setup time 0 - ns [4] tRCH Read command hold time from CAS high 0 - ns [3] tRRH Read command hold time from RAS high 0 - ns tWCS Write command setup time 5 - ns tWCH Write command hold time 5 - ns tWP WE pulse width 8 - ns tT Transition time (rise and fall) - 1.5 ns tRWL Write command to RAS high 8 - ns tCWL Write command to CAS high 8 - ns 1. 2. 3. 4. 5. 6. 7. [5] Maximum CASH to CASL skew is 1 ns. Last CASx LOW. Last CASx HIGH. First CASx LOW. First CASx HIGH. Last CASx LOW to first CASx HIGH. Last CASx HIGH to first CASx LOW. G-LINK Technology May 1997 (Rev. 1) 5 GLT40516-10E tRC tRAS tRP tAR RAS tCSH tCRP tRCD tRSH tCAS LCAS, UCAS tRAD tASR A[8:0] tRAL tRAH tASC ROW tCAH COLUMN tAA tRCH tRCS tRRH WE tCAC tROH tOEA OE tOFF tRAC DQ tOEZ Hi-Z VALID DATA Don't Care Figure 2. Read Cycle (RAS Output Control) tRC tRAS tRP tAR RAS tCSH tCRP tRCD tRSH tCAS LCAS, UCAS tRAD tASR A[8:0] tRAH tRAL tASC ROW tCAH COLUMN tAA tRCS tRRH WE tCAC tROH tOEA OE tOFF tOEZ tRAC DQ Hi-Z VALID DATA Don't Care Figure 3. Read Cycle (CAS Output Control) 6 G-LINK Technology May 1997 (Rev. 1) GLT40516-10E tRC tRAS tRP tAR RAS tCSH tCRP tRCD tRSH tCAS LCAS, UCAS tRAD tASR A[8:0] tRAL tRAH tASC ROW tCAH COLUMN tWCR tWSC tWCH tWP WE tCWL tRWL OE tDHR tDS DQ tDH VALID DATA Hi-Z Don't Care Figure 4. Early Write (LCAS and UCAS Active) tRC tRAS tRP tAR RAS tCSH tCRP tRCD tRSH tCAS LCAS, UCAS tRAD tASR A[8:0] tRAH tRAL tASC ROW tCAH COLUMN tCWL tRWL tRCS tWP WE tWCR tOEH OE tDS DQ tDH VALID DATA Don't Care Figure 5. Late Write (LCAS and UCAS Active) G-LINK Technology May 1997 (Rev. 1) 7 GLT40516-10E tRMW tRAS tRP tAR RAS tCSH tCRP tRCD tRSH tCAS LCAS, UCAS tRAD tASR A[8:0] tRAH tRAL tASC tCAH ROW COLUMN tAWD tRCS tCWL tRWL tWP tCWD WE tRWD tOEA tDZO tOEH OE tRAC tDZC tOED tOEZ tCAC DQ tDS OUT tDH IN Don't Care Figure 6. Read Modify Write Cycle (LCAS and UCAS Active) tRC tRASP tRP tAR RAS tCSH tCRP tPC tRCD tCAS tRSH tCP tCAS tCP tCAS LCAS, UCAS tRAD tRAH tASR A[8:0] tASC ROW tCAH tASC COLUMN tCAH COLUMN tRAL tCAH tASC COLUMN tRRH tRCS tRCH WE tCAC tOEA tCPA tAA tCPA tAA tREZ tOEZ OE tAA tRAC DQ HZ tCAC tCOH VALID DATA tCAC tCOH VALID DATA VALID DATA Don't Care Figure 7. Fast Page Mode Read Cycle with Extended Data Out 8 G-LINK Technology May 1997 (Rev. 1) GLT40516-10E tRC tRASP tRP tAR RAS tCSH tCRP tRCD tASR tRAD tRAH tASC tCP tCAS tHPC tCAS tCP tRSH tCAH tASC tCAS tCP tCAS tCRP LCAS, UCAS A[8:0] ROW tRAL tCAH tASC COLUMN tCAH COLUMN tASC tCAH COLUMN COLUMN tRRH tRCH tWEP tRCS tRCS tRCH WE tRAC tCHO tOEP tOEA tOCH tOEP tCAC OE tCAC tAA tCPA tCAC tAA tCOH DQ tAA tOEA tOEZ VALID DATA tOEZ tOEA tCAC tWEZ tAA VALID DATA VALID DATA tREZ VALID DATA VALID DATA Don't Care Figure 8. Fast Page Mode Read Hi-Z Operation tRC tRASP tRP tAR RAS tCSH tCRP tPC tRCD tCAS tRSH tCP tCAS tCP tCAS LCAS, UCAS tRAD tRAH tASR A[8:0] tASC ROW tCAH tASC COLUMN tCWL tWCH tWCS tCAH COLUMN tWP WE COLUMN tCWL tWCH tWCS tRAL tCAH tASC tCWL tWCH tWCS tWP tWP OE tDS DQ tDH INPUT DATA tDS tDH INPUT DATA tDS tDH INPUT DATA Don't Care Figure 9. Fast Page Mode Early Write Cycle G-LINK Technology May 1997 (Rev. 1) 9 GLT40516-10E tRC tRASP tRP tAR RAS tCSH tCRP tPRMW tRCD tCAS tCP tCAS tRSH tCAS tCP LCAS, UCAS tRAD tRAH tASR A[8:0] tRAL tASC tCAH ROW tASC tCAH COLUMN tRCS tASC tCAH COLUMN tCWD tCWL tWP tAWD COLUMN tCWD tCWL tWP tAWD tCWD tAWD tCWL tWP WE tOEA tOEZ tOEA tOEZ tOEA tOEZ OE tCAC tDH tDS tAA DQ OUT tCAC tDH tDS tAA IN OUT tCAC tDH tDS tAA IN OUT IN Don't Care Figure 10. Fast Page Mode Read Modify Write Cycle tRC tRP tRAS tRP RAS tRPC LCAS, UCAS tCSR tCHR tRPC INHIBIT FALLING TRANSITION A[8:0] WE OE tOFF DQ HZ Don't Care Figure 11. CAS-before-RAS Refresh Cycle 10 G-LINK Technology May 1997 (Rev. 1) GLT40516-10E tRC tRAS tRP tRAS tAR RAS tCRP tRCD tRSH tCHR LCAS, UCAS tRAD tRAH tASR A[8:0] tRAL tCAH tASC ROW COLUMN tRCS tROH tRRH WE tCAC tOFF tOEA tOEZ OE tAA tRAC DQ HZ VALID DATA Don't Care Figure 12. Hidden Refresh Cycle tRC tRAS tRP RAS tCRP tRPC LCAS, UCAS tASR A[8:0] tRAH ROW WE, OE DQ Hi-Z Don't Care Figure 13. RAS-Only Refresh Cycle G-LINK Technology May 1997 (Rev. 1) 11 GLT40516-10E www.glinktech.com G-LINK Technology 2701 Northwestern Parkway Santa Clara, CA 95051, USA TEL: 408-492-9068 * FAX: 408-492-9067 G-LINK Technology Corporation, Taiwan 2F, No. 12, R&D Road II Science-Based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: 03-578-2833 * FAX: 03-578-5820 (c) 1998 G-LINK Technology All rights reserved. No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of G-LINK Technology. Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given. G-LINK Technology reserves the right to change products or specifications without notice. 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