LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 LMC662 CMOS Dual Operational Amplifier Check for Samples: LMC662 FEATURES DESCRIPTION * * * * * * * * * * * The LMC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It operates from +5V to +15V and features rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain into realistic loads (2 k and 600) are all equal to or better than widely accepted bipolar equivalents. 1 2 Rail-to-Rail Output Swing Specified for 2 k and 600 Loads High Voltage Gain: 126 dB Low Input Offset Voltage: 3 mV Low Offset Voltage Drift: 1.3 V/C Ultra Low Input Bias Current: 2 fA Input Common-Mode Range Includes V- Operating Range from +5V to +15V Supply ISS = 400 A/amplifier; Independent of V+ Low Distortion: 0.01% at 10 kHz Slew Rate: 1.1 V/s This chip is built with TI's advanced Double-Poly Silicon-Gate CMOS process. See the LMC660 datasheet for a Quad CMOS operational amplifier with these same features. APPLICATIONS * * * * * * * * High-Impedance Buffer or Preamplifier Precision Current-to-Voltage Converter Long-Term Integrator Sample-and-Hold Circuit Peak Detector Medical Instrumentation Industrial Controls Automotive Sensors Connection Diagram Figure 1. 8-Pin PDIP, SOIC Typical Application Figure 2. Low-Leakage Sample-and-Hold These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2013, Texas Instruments Incorporated LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Differential Input Voltage Supply Voltage Supply Voltage (V+ - V-) 16V Output Short Circuit to V+ See (4) Output Short Circuit to V- See (5) Lead Temperature (Soldering, 10 sec.) 260C Storage Temp. Range -65C to +150C (V+) +0.3V, (V-) -0.3V Voltage at Input/Output Pins Current at Output Pin 18 mA Current at Input Pin 5 mA Current at Power Supply Pin 35 mA Power Dissipation See (6) Junction Temperature 150C ESD Tolerance (7) 1000V (1) (2) (3) (4) (5) (6) (7) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. A military RETS electrical test specification is available on request. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150C. Output currents in excess of 30 mA over long term may adversely affect reliability. The maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)-TA)/JA. Human body model, 1.5 k in series with 100 pF. Operating Ratings (1) Temperature Range LMC662AI -40C TJ +85C LMC662C 0C TJ +70C Supply Voltage Range 4.75V to 15.5V See (2) Power Dissipation Thermal Resistance (JA) (1) (2) (3) 2 (3) 8-Pin PDIP 101C/W 8-Pin SOIC 165C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. For operating at elevated temperatures the device must be derated based on the thermal resistance JA with PD = (TJ-TA)/JA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Parameter Test Conditions Input Offset Voltage Typ (1) LMC662AI LMC662C Limit (1) Limit (1) 1 Input Offset Voltage Average Drift 3 6 mV 3.3 6.3 max V/C 1.3 Input Bias Current 0.002 pA 4 Input Offset Current 2 max 0.001 pA 2 Input Resistance Common Mode Units 1 >1 0V VCM 12.0V max Tera 83 + 70 63 dB 68 62 min 70 63 dB 68 62 min 74 dB min Rejection Ratio V = 15V Positive Power Supply 5V V+ 15V Rejection Ratio VO = 2.5V Negative Power Supply 0V V- -10V 94 84 83 73 Input Common-Mode V+ = 5V & 15V -0.4 -0.1 -0.1 V Voltage Range For CMRR 50 dB 0 0 max V+ - 2.3 V+ - 2.3 V V - 2.5 V+ - 2.4 min 440 300 V/mV 400 200 min 180 90 V/mV 83 Rejection Ratio V+ - 1.9 + Large Signal RL = 2 k (2) Voltage Gain Sourcing Output Swing 2000 Sinking 500 RL = 600 (2) 1000 120 80 min 220 150 V/mV Sourcing 200 100 min Sinking 100 50 V/mV 60 40 min 4.82 4.78 V 4.79 4.76 min 0.15 0.19 V 0.17 0.21 max 4.41 4.27 V 4.31 4.21 min 0.30 0.50 0.63 V 0.56 0.69 max 14.63 14.50 14.37 V 14.44 14.32 min 0.35 0.44 V 0.40 0.48 max 13.35 12.92 V 13.15 12.76 min 1.16 1.45 V 1.32 1.58 max 250 + V = 5V 4.87 RL = 2 k to V+/2 0.10 V+ = 5V 4.61 RL = 600 to V+/2 V+ = 15V RL = 2 k to V+/2 0.26 V+ = 15V 13.90 + RL = 600 to V /2 0.79 (1) (2) Typical values represent the most likely parametric norm. Limits are specified by testing or correlation. V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 3 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Parameter Output Current Test Conditions Sourcing, VO = 0V LMC662AI LMC662C Limit (1) Limit (1) 16 13 mA 14 11 min 16 13 mA 14 11 min 28 23 mA 25 21 min 39 28 23 mA 24 20 min 0.75 1.3 1.6 mA 1.5 1.8 max Typ (1) 22 V+ = 5V Sinking, VO = 5V Output Current Sourcing, VO = 0V 21 40 V+ = 15V Sinking, VO = 13V See Supply Current (3) Both Amplifiers VO = 1.5V (3) Units Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Parameter Slew Rate Test Conditions See (2) Typ (1) 1.1 LMC662AI LMC662C Limit (1) Limit (1) 0.8 0.8 0.6 0.7 Units V/s min Gain-Bandwidth Product 1.4 MHz Phase Margin 50 Deg 17 dB Gain Margin Amp-to-Amp Isolation See (3) 130 dB Input-Referred Voltage Noise F = 1 kHz 22 nVHz Input-Referred Current Noise F = 1 kHz 0.0002 pAHz Total Harmonic Distortion F = 10 kHz, AV = -10 0.01 % RL = 2 k, VO = 8 VPP V+ = 15V (1) (2) (3) 4 Typical values represent the most likely parametric norm. Limits are specified by testing or correlation. V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred. V+ = 15V and RL = 10 k connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 Typical Performance Characteristics VS = 7.5V, TA = 25C unless otherwise specified Supply Current vs. Supply Voltage Offset Voltage Figure 3. Figure 4. Input Bias Current Output Characteristics Current Sinking Figure 5. Figure 6. Output Characteristics Current Sourcing Input Voltage Noise vs. Frequency Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 5 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 7.5V, TA = 25C unless otherwise specified CMRR vs. Frequency Open-Loop Frequency Response Figure 9. Figure 10. Frequency Response vs. Capacitive Load Non-Inverting Large Signal Pulse Response Figure 11. Figure 12. Stability vs. Capacitive Load Stability vs. Capacitive Load Note: Avoid resistive loads < 500, as they may cause instability. Figure 13. 6 Note: Avoid resistive loads < 500, as they may cause instability. Figure 14. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 APPLICATION HINTS AMPLIFIER TOPOLOGY The topology chosen for the LMC662, shown in Figure 15, is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the integrator. As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain stages with two fed forward. Figure 15. LMC662 Circuit Topology (Each Amplifier) The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, even with a 600 load. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, under heavy load (600) the gain will be reduced as indicated in the Electrical Characteristics. COMPENSATING INPUT CAPACITANCE The high input resistance of the LMC662 op amps allows the use of large feedback and source resistor values without losing gain accuracy due to loading. However, the circuit will be especially sensitive to its layout when these large-value resistors are used. Every amplifier has some capacitance between each input and AC ground, and also some differential capacitance between the inputs. When the feedback network around an amplifier is resistive, this input capacitance (along with any additional capacitance due to circuit board traces, the socket, etc.) and the feedback resistors create a pole in the feedback path. In the following General Operational Amplifier Circuit, Figure 16, the frequency of this pole is (1) where: CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray capacitance from the IC socket (if one is used), circuit board traces, etc., and RP is the parallel combination of RF and RIN. This formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp configurations. When the feedback resistors are smaller than a few k, the frequency of the feedback pole will be quite high, since CS is generally less than 10 pF. If the frequency of the feedback pole is much higher than the "ideal" closed-loop bandwidth (the nominal closed-loop bandwidth in the absence of CS), the pole will have a negligible effect on stability, as it will add only a small amount of phase shift. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 7 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com However, if the feedback pole is less than approximately 6 to 10 times the "ideal" -3 dB frequency, a feedback capacitor, CF, should be connected between the output and the inverting input of the op amp. This condition can also be stated in terms of the amplifier's low-frequency noise gain: To maintain stability, a feedback capacitor will probably be needed if: (2) where: (3) is the amplifier's low-frequency noise gain and GBW is the amplifier's gain bandwidth product. An amplifier's lowfrequency noise gain is represented by the formula: (4) regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback capacitor is more likely to be needed when the noise gain is low and/or the feedback resistor is large. If the above condition is met (indicating a feedback capacitor will probably be needed), and the noise gain is large enough that: (5) the following value of feedback capacitor is recommended: (6) If (7) the feedback capacitor should be: (8) Note that these capacitor values are usually significantly smaller than those given by the older, more conservative formula: (9) CS consists of the amplifier's input capacitance plus any stray capacitance from the circuit board and socket. CF compensates for the pole caused by CS and the feedback resistor. Figure 16. General Operational Amplifier Circuit 8 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may be necessary in any of the above cases to use a somewhat larger feedback capacitor to allow for unexpected stray capacitance, or to tolerate additional phase shifts in the loop, or excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance to be sufficiently stable. For example, a printed circuit board's stray capacitance may be larger or smaller than the breadboard's, so the actual optimum value for CF may be different from the one estimated using the breadboard. In most cases, the value of CF should be checked on the actual circuit, starting with the computed value. CAPACITIVE LOAD TOLERANCE Like many other op amps, the LMC662 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at low gains. As shown in Figure 17, the addition of a small resistor (50 to 100) in series with the op amp's output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation. Figure 17. Rx, Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 18. Typically a pull up resistor conducting 500 A or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 18. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC662, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 9 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC662's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's inputs. See Figure 19. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the LMC662's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's performance. See Figure 20, Figure 21, and Figure 22 for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 23. Figure 19. Example, using the LMC660, of Guard Ring in P.C. Board Layout Figure 20. Guard Ring Connections: Inverting Amplifier Figure 21. Guard Ring Connections: Non-Inverting Amplifier 10 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 Figure 22. Guard Ring Connections: Follower Figure 23. Guard Ring Connections: Howland Current Pump The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Do not insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 24. (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) Figure 24. Air Wiring Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 11 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com BIAS CURRENT TESTING The test method of Figure 25 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then (10) Figure 25. Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of Ib-, the leakage of the capacitor and socket must be taken into account. Switch S2 should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted) (11) where Cx is the stray capacitance at the + input. Typical Single-Supply Applications (V+ = 5.0 VDC) Additional single-supply applications ideas can be found in the LM358 datasheet. The LMC662 is pin-for-pin compatible with the LM358 and offers greater bandwidth and input resistance over the LM358. These features will improve the performance of many existing single-supply applications. Note, however, that the supply voltage range of the LM662 is smaller than that of the LM358. Figure 26. Low-Leakage Sample-and-Hold 12 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 (V+ = 5.0 VDC) Figure 27. Instrumentation Amplifier For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7. Oscillator frequency is determined by R1, R2, C1, and C2: fOSC = 1/2RC where R = R1 = R2 and C = C1 = C2. Figure 28. Sine-Wave Oscillator This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 13 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com (V+ = 5.0 VDC) Figure 29. 1 Hz Square-Wave Oscillator Figure 30. Power Amplifier fO = 10 Hz Q = 2.1 Gain = -8.8 Figure 31. 10 Hz Bandpass Filter 14 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 LMC662 www.ti.com SNOSC51C - APRIL 1998 - REVISED MARCH 2013 (V+ = 5.0 VDC) fc = 10 Hz d = 0.895 Gain = 1 2 dB passband ripple Figure 32. 10 Hz High-Pass Filter Figure 33. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) Gain = -46.8 Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV). Figure 34. High Gain Amplifier with Offset Voltage Reduction Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 15 LMC662 SNOSC51C - APRIL 1998 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C * 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LMC662 PACKAGE OPTION ADDENDUM www.ti.com 19-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMC662AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC66 2AIM LMC662AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC66 2AIM LMC662AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC66 2AIM LMC662AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC66 2AIM LMC662AIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC 662AIN LMC662CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LMC66 2CM LMC662CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LMC66 2CM LMC662CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LMC66 2CM LMC662CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LMC66 2CM LMC662CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LMC 662CN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Mar-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC662AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC662AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC662CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC662CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC662AIMX SOIC D 8 2500 367.0 367.0 35.0 LMC662AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC662CMX SOIC D 8 2500 367.0 367.0 35.0 LMC662CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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