LTC4253BIGN#TRPBF - Linear Technology Corporation

LTC4253B

4253bf

–48V/2.5A Hot Swap Controller

Start-Up Behavior

Typical applicaTion

FeaTures DescripTion

–48V Hot Swap Controller

with Sequencer

The LT C

4253B negative voltage Hot Swap™ controller

allows a board to be safely inserted and removed from a

live backplane. Output current is controlled by three stages

of current-limiting: a timed circuit breaker, active current

limiting and a fast feedforward path that limits peak cur-

rent under worst-case catastrophic fault conditions. The

LTC4253B latches off after a circuit fault.

Adjustable undervoltage and overvoltage detectors dis-

connect the load whenever the input supply exceeds the

desired operating range. The LTC4253B’s supply input is

shunt-regulated, allowing safe operation with very high

supply voltages. A multifunction timer delays initial start-up

and controls the circuit breaker’s response time. The circuit

breaker’s response time can be accelerated by sensing

excessive MOSFET drain voltage, keeping the MOSFET

within its safe operating area (SOA). An adjustable soft-

start circuit controls MOSFET inrush current at start-up.

Three power good outputs are sequenced by an adjustable

timer and two ENABLE inputs to enable external power

modules at start-up or disable them if the circuit breaker

trips. The LTC4253B improves the ruggedness of the

LTC4253 shunt regulator.

applicaTions

n Allows Safe Board Insertion and Removal from a

Live –48V Backplane

n Floating Topology Permits Very High Voltage

Operation

n Adjustable Analog Current Limit with Breaker Timer

Ideal for Tw o Battery Feeds

n Fast Response Time Limits Peak Fault Current

n Three Sequenced Power Good Outputs

n Improved Ruggedness Shunt Regulator

n Adjustable Soft-Start Current Limit

n Adjustable Timer with Drain Voltage Accelerated

Response

n Latchoff After Fault

n Available in a 16-Pin SSOP Package

n –48V Distributed Power Systems

n Negative Power Supply Control

n Central Office Switching

n High Availability Servers

n Disk Arrays

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and Hot

Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners.

5.6k 5.6k 5.6k

†

PWRGD1

VIN

EN2 EN3

VIN

VEE

LTC4253B

LOAD1

PWRGD2

PWRGD3

DRAIN

GATE

SQTIMER

SENSETIMER

LOAD2

LOAD3

2.5k

15k(1/4W)/6

RESET

4253b TA01

10Ω

0.02Ω

IRF530S *DIODES, INC.

†MOC207

††RECOMMENDED FOR HARSH ENVIRONMENTS.

18nF

0.33µF

0.1µF

68nF

10nF

100µF

B3100*

402k

–48V A

–48V B

–48V RTN

B3100*

††

32.4k

1µF

DIN††

DDZ13B*

GATE

10V

SENSE

50mV

VOUT

50V

1ms/DIV 4253b TA01b

LTC4253B

4253bf

pin conFiguraTionabsoluTe MaxiMuM raTings

Current into VIN (100µs Pulse) .............................100mA

Current into DRAIN (100µs Pulse) .........................20mA

VIN, DRAIN Minimum Voltage ................................–0.3V

Input/Output (Except SENSE

and DRAIN) Voltage ................................... –0.3V to 16V

SENSE Voltage ........................................... –0.6V to 16V

Current Out of SENSE (20µs Pulse) .................. –200mA

Maximum Junction Temperature .......................... 125°C

Operating Temperature Range

LTC4253BC .............................................. 0°C to 70°C

LTC4253BI ........................................... –40°C to 85°C

Storage Temperature Range .............. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................... 300°C

(Note 1), All voltages referred to VEE

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

EN2

PWRGD2

PWRGD1

VIN

RESET

SENSE

VEE

PWRGD3

EN3

SQTIMER

TIMER

DRAIN

GATE

TJMAX = 125°C, θJA = 110°C/W

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4253BCGN#PBF LTC4253BCGN#TRPBF 4253B 16-Lead Plastic SSOP 0°C to 70°C

LTC4253BIGN#PBF LTC4253BIGN#TRPBF 4253B 16-Lead Plastic SSOP –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LT C Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4253B

4253bf

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VZVIN – VEE Zener Voltage IIN = 2mA ●11.5 13 14.5 V

RZVIN – VEE Zener Dynamic Impedance IIN = (2mA to 30mA) 5 Ω

IIN VIN Supply Current UV = OV = 4V, VIN = (VZ – 0.3V) ●0.8 2 mA

VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN)●9.2 11.5 V

VLKH VIN Undervoltage Lockout Hysteresis ●0.5 1 1.5 V

VIH TTL Input High Voltage ●2 V

VIL TTL Input Low Voltage ●0.8 V

VHYST TTL Input Buffer Hysteresis 600 mV

IRESET RESET Input Current VEE ≤ VRESET ≤ VIN ●±0.1 ±10 µA

IEN EN2, EN3 Input Current VEN = 4V

VEN = 0V

●

60 120

±0.1

180

±10

µA

VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE)●40 50 60 mV

VACL Analog Current Limit Voltage VACL = (VSENSE – VEE), SS = Open or 2.2V ●80 100 120 mV

VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE)●150 200 300 mV

VSS SS Voltage After End of SS Timing Cycle ●2 2.2 2.4 V

ISS SS Pin Current UV = OV = 4V, VSENSE = VEE,

VSS = 0V (Sourcing)

●12 22 32 µA

UV = OV = 0V, VSENSE = VEE,

VSS = 1V (Sinking)

28 mA

RSS SS Output Impedance 100 kΩ

VOS Analog Current Limit Offset Voltage 10 mV

VACL + VOS

VSS

Ratio (VACL + VOS) to SS Voltage 0.05 V/V

IGATE GATE Pin Output Current UV = OV = 4V, VSENSE = VEE,

VGATE = 0V (Sourcing)

●30 50 70 µA

UV = OV = 4V, VSENSE – VEE = 0.15V,

VGATE = 3V (Sinking)

17 mA

UV = OV = 4V, VSENSE – VEE = 0.3V,

VGATE = 1V (Sinking)

190 mA

VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA ●10 12 VZV

VGATEL Gate Low Threshold Before Gate Ramp Up 0.5 V

VGATEH Gate High Threshold VGATEH = VIN – VGATE, for PWRGD1,

PWRGD2, PWRGD3 Status

2.8 V

VUVHI UV Pin Threshold HIGH UV Low to High ●3.075 3.225 3.375 V

VUVLO UV Pin Threshold LOW UV High to Low ●2.775 2.925 3.075 V

VUVHST UV Pin Hysteresis 230 300 350 mV

VOVHI OV Pin Threshold HIGH OV Low to High ●5.85 6.15 6.45 V

VOVLO OV Pin Threshold LOW OV High to Low ●5.55 5.85 6.15 V

VOVHST OV Pin Hysteresis 230 300 350 mV

ISENSE SENSE Pin Input Current UV = 0V = 4V, VSENSE = 50mV (Sourcing) ●15 30 µA

IINP UV, OV Pin Input Current UV = OV = 4V ●±0.1 ±1 µA

VTMRH TIMER Pin Voltage High Threshold ●3.5 4 4.5 V

LTC4253B

4253bf

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VTMRL TIMER Pin Voltage Low Threshold ●0.8 1 1.2 V

ITMR TIMER Pin Current Timer On (Initial Cycle/Latchoff,

Sourcing), VTMR = 2V

●3 5 7 µA

Timer Off (Initial Cycle, Sinking),

VTMR = 2V

28 mA

Timer On (Circuit Breaker, Sourcing,

IDRN = 0µA), VTMR = 2V

●120 200 280 µA

Timer On (Circuit Breaker, Sourcing,

IDRN = 50µA), VTMR = 2V

600 µA

Timer Off (Circuit Breaker, Sinking),

VTMR = 2V

●3 5 7 µA

∆ITMRACC

∆IDRN

ITMR at IDRN = 50µA – ITMR at IDRN = 0µA

50µA

Timer On (Circuit Breaker with

IDRN = 50µA)

●7 8 9 µA/µA

VSQTMRH SQTIMER Pin Voltage High Threshold ●3.5 4 4.5 V

VSQTMRL SQTIMER Pin Voltage Low Threshold 0.33 V

ISQTMR SQTIMER Pin Current SQTIMER On (Power Good

Sequence, Sourcing), VSQTMR = 2V

●3 5 7 µA

SQTIMER Off (Power Good

Sequence, Sinking), VSQTMR = 2V

28 mA

VDRNL DRAIN Pin Voltage Low Threshold For PWRGD1, PWRGD2, PWRGD3 Status ●2 2.39 3 V

IDRNL DRAIN Leakage Current VDRAIN = 5V

VDRAIN = 4V

±0.1 ±1 µA

µA

VDRNCL DRAIN Pin Clamp Voltage IDRN = 50µA ●6 7 8.5 V

VPGL PWRGD1, PWRGD2, PWRGD3

Output Low Voltage

IPG = 1.6mA

IPG = 5mA

●

0.25 0.4

1.2

IPGH PWRGD1, PWRGD2, PWRGD3

Output High Current

VPG = 0V (Sourcing) ●30 50 70 µA

tSQ SQTIMER Default Ramp Period SQTIMER Pin Floating,

VSQTMR Ramps from 0.5V to 3.5V

250 µs

tSS SS Default Ramp Period SS Pin Floating, VSS Ramps from 0.2V to 2V 250 µs

tPLLUG UV Low to GATE Low ●0.4 5 µs

tPHLOG OV High to GATE Low ●0.4 5 µs

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to VEE unless otherwise

specified.

LTC4253B

4253bf

Typical perForMance characTerisTics

IEN vs VEN

Circuit Breaker Current Limit

Voltage VCB vs Temperature

Analog Current Limit Voltage

VACL vs Temperature

Fast Current Limit Voltage VFCL vs

Temperature IGATE (Source) vs Temperature IGATE (ACL, Sink) vs Temperature

VZ vs Temperature IIN vs VIN IIN vs Temperature

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

(V)

4253b G01

14.5

14.0

13.5

13.0

12.5

12.0

IIN = 2mA

VIN (V)

05 10 15 20

(mA)

4253b G02

1000

100

0.1

TA = 85°C

TA = 125°C

TA = –40°C

TA = 25°C

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

(µA)

4253b G03

1000

950

900

850

800

750

700

650

600

550

500

VIN = VZ – 0.3V

VEN (V)

0 2 4 6 8 10 12 14 16

(µA)

4253b G04

180

160

140

120

100

IIN = 2mA

TA = 25°C

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

VCB (mV)

4253b G05

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

ACL

(mV)

4253b G06

150

140

130

120

110

100

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

FCL

(mV)

4253b G07

300

280

260

240

220

200

180

160

140

120

100

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

GATE

(µA)

4253b G08

UV/OV = 4V

TIMER = 0V

VSENSE = VEE

VGATE = 0V

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

GATE

(mA)

4253b G09

UV/OV = 4V

TIMER = 0V

VSENSE – VEE = 0.15V

VGATE = 3V

LTC4253B

4253bf

Typical perForMance characTerisTics

VGATEH vs Temperature UV Threshold vs Temperature OV Threshold vs Temperature

ISENSE vs (VSENSE – VEE) ISENSE vs Temperature TIMER Threshold vs Temperature

IGATE (FCL, Sink) vs Temperature VGATE vs Temperature VGATEL vs Temperature

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

GATE

(mA)

4253b G10

400

350

300

250

200

150

100

UV/OV = 4V

TIMER = 0V

VSENSE – VEE = 0.3V

VGATE = 1V

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

GATEH

(V)

4253b G13

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

UV/OV = 4V

VGATEH = VIN – VGATE

IIN = 2mA

VSENSE – VEE (V)

–1.5 –1 –0.5 0 0.5 1 1.5

–I

SENSE

(mA)

4253b G16

0.01

0.1

100

1000

UV/OV = 4V

TIMER = 0V

GATE = HIGH

TA = 25°C

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

GATE

(V)

4253b G11

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

UV/OV = 4V

TIMER = 0V

VSENSE = VEE

IIN = 2mA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

UV THRESHOLD (V)

4253b G14

3.375

3.275

3.175

3.075

2.975

2.875

2.775

IIN = 2mA

VUVH

VUVL

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

SENSE

(µA)

4253b G17

–5

–10

–15

–20

–25

–30

UV/OV = 4V

TIMER = 0V

VSENSE – VEE = 50mV

VGATE = HIGH

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

VGATEL (V)

4253b G12

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

UV/OV = 4V

TIMER = 0V

GATE THRESHOLD

BEFORE RAMP UP

TEMPERATURE (°C)

–55 –35

5.0

OV THRESHOLD (V)

5.4

5.6

5.8

65 85 105

6.4

4253b G15

5.2

–15 5 25 45 125

6.0

6.2 VOVH

IIN = 2mA

VOVL

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

TIMER THRESHOLD (V)

4253b G18

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

IIN = 2mA

VTMRH

VTMRL

LTC4253B

4253bf

Typical perForMance characTerisTics

∆ITMRACC/∆IDRN vs Temperature

SQTIMER Threshold

vs Temperature VDRNL vs Temperature

VDRNCL vs Temperature IDRN vs VDRAIN VPGL vs Temperature

ITMR (Initial Cycle, Sourcing)

vs Temperature

ITMR (Circuit Breaker, Sourcing)

vs Temperature ITMR vs IDRN

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

TMR

(µA)

4253b G19

IIN = 2mA

VTMR = 2V

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

∆I

TMRACC

/∆I

DRN

(µA/µA)

4253b G22

9.0

8.8

8.6

8.4

8.2

8.0

7.8

7.6

7.4

7.2

7.0

IIN = 2mA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

DRNCL

(V)

4253b G25

8.0

7.8

7.6

7.4

7.2

7.0

6.8

6.6

6.4

6.2

6.0

IIN = 2mA

IDRN = 50µA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

TMR

(µA)

4253b G20

240

230

220

210

200

190

180

170

160

IIN = 2mA

IDRN = 0µA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

SQTMR

(V)

4253b G23

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

IIN = 2mA

VSQTMRH

VSQTMRL

VDRAIN (V)

02 4 6 8 10 12 14 16

DRN

(mA)

4253b G26

100

0.1

0.01

0.001

0.0001

0.00001

IIN = 2mA

TA = –40°C

TA = 25°C

TA = 85°C

TA = 125°C

IDRN (mA)

0.001 0.01 0.1 1 10

ITMR (mA)

4253b G21

0.1

IIN = 2mA

TA = 25°C

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

VDRNL (V)

4253b G24

2.60

2.55

2.50

2.45

2.40

2.35

2.30

2.25

2.20

IIN = 2mA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

VPGL (V)

4253b G27

3.0

2.5

2.0

1.5

1.0

0.5

IIN = 2mA

IPG = 10mA

IPG = 5mA

IPG = 1.6mA

LTC4253B

4253bf

Typical perForMance characTerisTics

IPGH vs Temperature tSS vs Temperature tSQ vs Temperature

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

PGH

(µA)

4253b G28

IIN = 2mA

VPWRGD = 0V

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

(µs)

4253b G29

300

290

280

270

260

250

240

230

220

210

200

IIN = 2mA

SS PIN FLOATING

VSS RAMPS FROM 0.2V TO 2V

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

tSQ (µs)

4253b G30

500

450

400

350

300

250

200

150

100

IIN = 2mA

VSQTMR RAMPS FROM 0.5V TO 3.5V

EN2 (Pin 1): Power Good Status Output Tw o Enable. This

is a TTL compatible input that is used to control PWRGD2

and PWRGD3 outputs. When EN2 is driven low, both

PWRGD2 and PWRGD3 will go high. When EN2 is driven

high, PWRGD2 will go low provided PWRGD1 has been

active for more than one power good sequence delay

(tSQT) provided by the sequencing timer. EN2 can be used

to control the power good sequence. This pin is internally

pulled low by a 120µA current source.

PWRGD2 (Pin 2): Power Good Status Output Tw o . Power

good sequence starts with PWRGD1 latching active low.

PWRGD2 will latch active low after EN2 goes high and

after one power good sequence delay tSQT provided by

the sequencing timer from the time PWRGD1 goes low,

whichever comes later. PWRGD2 is reset by PWRGD1

going high or EN2 going low. This pin is internally pulled

high by a 50µA current source.

PWRGD1 (Pin 3): Power Good Status Output One. At start-

up, PWRGD1 latches active low and starts the power good

sequence when the DRAIN pin is below 2.39V and GATE

is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN

(UVLO), RESET going high or circuit breaker fault time-out.

This pin is internally pulled high by a 50µA current source.

VIN (Pin 4): Positive Supply Input. Connect this pin to the

positive side of the supply through a dropping resistor. A

shunt regulator clamps VIN at 13V above VEE. An internal

undervoltage lockout (UVLO) circuit holds GATE low until

the VIN pin is greater than VLKO, overriding UV and OV. If

UV is high, OV is low and VIN comes out of UVLO, TIMER

starts an initial timing cycle before initiating GATE ramp

up. If VIN drops below approximately 8.2V, GATE pulls

low immediately.

pin FuncTions

LTC4253B

4253bf

RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-

chronous TTL compatible input. RESET going high will pull

GATE, SS, TIMER, SQTIMER low and the PWRGD outputs

high. The RESET pulse must be wide enough to discharge

any voltage on the TIMER pin below VTMRL. After the reset

of a latched fault, the chip waits for the interlock conditions

before recovering as described in Interlock Conditions in

the Operation section.

SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush

current during start up, thereby effecting control over di/dt.

A 20X attenuated version of the SS pin voltage is presented

to the current limit amplifier. This attenuated voltage limits

the MOSFET’s drain current through the sense resistor

during the soft-start current limiting. At the beginning

of the start-up cycle, the SS capacitor (CSS) is ramped

by a 22µA current source. The GATE pin is held low until

SS exceeds 20 • VOS = 0.2V. SS is internally shunted by

a 100k RSS which limits the SS pin voltage to 2.2V. This

corresponds to an analog current limit SENSE voltage of

100mV. If the SS capacitor is omitted, the SS pin ramps

up in about 250µs. The SS pin is pulled low under any of

the following conditions: UVLO at VIN, UV, OV, during the

initial timing cycle, a circuit breaker fault time-out or the

RESET pin going high.

SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.

Load current is monitored by a sense resistor RS connected

between SENSE and VEE, and controlled in three steps. If

SENSE exceeds VCB (50mV), the circuit breaker compara-

tor activates a (200µA+8•IDRN) TIMER pull-up current.

If SENSE exceeds VACL, the analog current-limit amplifier

pulls GATE down to regulate the MOSFET current at VACL/

RS. In the event of a catastrophic short-circuit, SENSE may

overshoot VACL. If SENSE reaches VFCL (200mV), the fast

current-limit comparator pulls GATE low with a strong

pull-down. To disable the circuit breaker and current limit

functions, connect SENSE to VEE.

VEE (Pin 8): Negative Supply Voltage Input. Connect this

pin to the negative side of the power supply.

GATE (Pin 9): N-channel MOSFET Gate Drive Output. This

pin is pulled high by a 50µA current source. GATE is pulled

low by invalid conditions at VIN (UVLO), UV, OV, during the

initial timing cycle, a circuit breaker fault time-out or the

RESET pin going high. GATE is actively servoed to control

the fault current as measured at SENSE. Compensation

capacitor, CC, at GATE stabilizes this loop. A comparator

monitors GATE to ensure that it is low before allowing an

initial timing cycle, then the GATE ramps up after an over-

voltage event or restart after a current limit fault. During

GATE start-up, a second comparator detects GATE within

2.8V of VIN before PWRGD1 can be set and power good

sequencing starts.

DRAIN (Pin 10): Drain Sense Input. Connecting an exter-

nal resistor, RD between this pin and the MOSFET’s drain

(VOUT) allows voltage sensing below 6.15V and current

feedback to TIMER. A comparator detects if DRAIN is below

2.39V and together with the GATE high comparator, sets

the PWRGD1 flag. If VOUT is above VDRNCL, the DRAIN

pin is clamped at approximately VDRNCL. RD current is

internally multiplied by 8 and added to TIMER’s 200µA

during a circuit breaker fault cycle. This reduces the fault

time and MOSFET heating.

OV (Pin 11): Overvoltage Input. For the LTC4253B, the

threshold at the OV pin is set at 6.15V with 0.3V hysteresis.

If OV > 6.15V, GATE pulls low. When OV returns below

5.85V, GATE start-up begins without an initial timing cycle.

If OV occurs in the middle of an initial timing cycle, the

initial timing cycle is restarted after OV goes away. OV

does not reset the latched fault or PWRGD1 flag. The

internal UVLO at VIN always overrides OV. A 1nF to 10nF

capacitor at OV prevents transients and switching noise

from affecting the OV thresholds and prevents glitches

at the GATE.

pin FuncTions

LTC4253B

4253bf

pin FuncTions

UV (Pin 12): Undervoltage Input. For the LTC4253B, the

threshold at the UV pin is set at 3.225V with 0.3V hyster-

esis. If UV < 2.925V, PWRGD1 pulls high, both GATE and

TIMER pull low. If UV rises above 3.225V, this initiates

an initial timing cycle followed by GATE start-up. The

internal UVLO at VIN always overrides UV. A low at UV

resets an internal fault latch. A 1nF to 10nF capacitor at

UV prevents transients and switching noise from affecting

the UV thresholds and prevents glitches at the GATE pin.

TIMER (Pin 13): Timer Input. Timer is used to generate

an initial timing delay at start-up, and to delay shutdown

in the event of an output overload (circuit breaker fault).

Timer starts an initial timing cycle when the following

conditions are met: RESET is low, UV is high, OV is low,

VIN clears UVLO, TIMER pin is low, GATE pin is lower

than VGATEL, SS < 0.2V, and VSENSE – VEE < VCB. A pull-up

current of 5µA then charges CT, generating a time delay.

If CT charges to VTMRH (4V), the timing cycle terminates.

TIMER quickly pulls low and GATE is activated.

If SENSE exceeds 50mV while GATE is high, a circuit

breaker cycle begins with a 200µA pull-up current charg-

ing CT. If DRAIN is approximately 7V during this cycle,

the timer pull-up has an additional current of 8 • IDRN. If

SENSE drops below 50mV before TIMER reaches 4V, a

5µA pull-down current slowly discharges the CT. In the

event that CT eventually integrates up to the VTMRH (4V)

threshold, the circuit breaker trips, GATE quickly pulls low

and PWRGD1 pulls high. TIMER latches high with a 5µA

pull-up source. This latched fault may be cleared by driv-

ing RESET high until TIMER is pulled low. Other ways of

clearing the fault include pulling the VIN pin momentarily

below (VLKO – VLKH), pulling TIMER low with an external

device or pulling UV below 2.925V.

SQTIMER (Pin 14): Sequencing Timer Input. The sequenc-

ing timer provides a delay tSQT for the power good sequenc-

ing. This delay is adjusted by connecting an appropriate

capacitor to this pin. If the SQTIMER capacitor is omitted,

the SQTIMER pin ramps from 0V to 4V in about 300µs.

EN3 (Pin 15): Power Good Status Output Three Enable.

This is a TTL compatible input that is used to control the

PWRGD3 output. When EN3 is driven low, PWRGD3 will

go high. When EN3 is driven high, PWRGD3 will go low

provided PWRGD2 has been active for for more than one

power good sequence delay (tSQT). EN3 can be used to

control the power good sequence. This pin is internally

pulled low by a 120µA current source.

PWRGD3 (Pin 16): Power Good Status Output Three. Power

good sequence starts with PWRGD1 latching active low.

PWRGD3 will latch active low after EN3 goes high and

after one power good sequence delay tSQT provided by

the sequencing timer from the time PWRGD2 goes low,

whichever comes later. PWRGD3 is reset by PWRGD1

going high or EN3 going low. This pin is internally pulled

high by a 50µA current source.

LTC4253B

4253bf

block DiagraM

VEE

1×

6.15V

1×

8×1×

VIN

VEE

PWRGD3

50µA

6.15V

VEE

120µA

VEE

120µA

VIN

VEE

VIN

VEE

200µA

OV 11

EN3 15

VIN

VEE VEE

22µA

95k

RSS

SS 6

VIN

VEE

50µA

VIN

VEE

PWRGD2

50µA

EN2 1

VEE

PWRGD1

50µA

VEE

RESET

SQTIMER

DELAY

LOGIC

SQTIMER

DELAY

–

TIMER 13

–

0.33V

–

UV 12

2.925V +

–

0.5V

–

2.39V

–

VIN

VEE

5µA

VIN

VEE

5µA

–2.8V

–200mV

–

10mV

VEE

–

–50mV

4253b BD

FCL

–

ACL

VEE

SENSE7

GATE

DRAIN

SQTIMER

LTC4253B

4253bf

operaTion

Hot Circuit Insertion

When circuit boards are inserted into a live backplane,

the supply bypass capacitors can draw huge transient

currents from the power bus as they charge. The flow

of current damages the connector pins and glitches the

power bus, causing other boards in the system to reset.

The LTC4253B is designed to turn on a circuit board sup-

ply in a controlled manner, allowing insertion or removal

without glitches or connector damage.

Initial Start-Up

The LTC4253B resides on a removable circuit board and

control the path between the connector and load or power

conversion circuitry with an external MOSFET switch (see

Figure 1). Both inrush control and short-circuit protection

are provided by the MOSFET.

A detailed schematic is shown in Figure 2. – 48V and

–48RTN receive power through the longest connector pins

and are the first to connect when the board is inserted. The

GATE pin holds the MOSFET off during this time. UV/OV

determines whether or not the MOSFET should be turned

on based upon internal high accuracy thresholds and an

external divider. UV/OV does double duty by also moni-

toring whether or not the connector is seated. The top of

the divider detects –48RTN by way of a short connector

pin that is the last to mate during the insertion sequence.

Figure 2. –48V/2.5A Application with a Wider Operating Range

Figure 1. Basic LTC4253B Hot Swap Topology

LTC4253B

–48RTN

4253b F01

PLUG-IN BOARD

–48V

BACKPLANE

CLOAD

ISOLATED

DC/DC

CONVERTER

MODULE

LOW

VOLTAGE

CIRCUITRY

–

5.6k

PWRGD1

VIN

VEE

LTC4253B

POWER

MODULE 1

PWRGD2

PWRGD3

EN3

EN2

RESET

DRAINSS

GATESQTIMER

SENSETIMER

POWER

MODULE 2

POWER

MODULE 3

RIN

2.5k

15k(1/4W)/6

PUSH

RESET

EN3

4253b F02

EN2

10Ω

RD 1M

0.02Ω

IRF530S VIN

18nF

0.33µF

10nF

–48RTN

(LONG PIN)

–48RTN

(SHORT PIN)

–48V

(LONG PIN)

CSQ

0.1µF

CSS 68nF

R7 POWER

MODULE 1

OUTPUT

POWER

MODULE 2

OUTPUT

VIN R8

100µF

CIN

1µF

DIN††

DDZ13B*

38.3k

432k

47k

4.75k

† † †

†

*DIODES, INC.

†MOC207

††RECOMMENDED FOR HARSH ENVIRONMENTS.

VIN

LTC4253B

4253bf

operaTion

Interlock Conditions

A start-up sequence commences once these “interlock”

conditions are met:

1. The input voltage VIN exceeds VLKO (UVLO).

2. The voltage at UV > VUVHI.

3. The voltage at OV < VOVLO.

4. The input voltage at RESET < 0.8V.

5. The (SENSE – VEE) voltage < 50mV (VCB)

6. The voltage at SS is < 0.2V (20 • VOS)

7. The voltage on the TIMER capacitor (CT)

is < 1V (VTMRL).

8. The voltage at GATE is < 0.5V (VGATEL)

The first four conditions are continuously monitored and

the latter four are checked prior to initial timing or GATE

ramp-up. Upon exiting an OV condition, the TIMER pin

voltage requirement is inhibited. Details are described in

the Applications Information, Timing Waveforms section.

If RESET < 0.8V occurs after the LTC4253B comes out of

UVLO (interlock condition 1) and undervoltage (interlock

condition 2), GATE and SS are released without an initial

TIMER cycle once the other interlock conditions are

met (see Figure 12a). If not, TIMER begins the start-up

sequence by sourcing 5µA into CT. If VIN, UV or OV falls

out of range or RESET asserts, the start-up cycle stops

and TIMER discharges CT to less than 1V, then waits until

the aforementioned conditions are once again met. If CT

successfully charges to 4V, TIMER pulls low and both SS

and GATE pins are released. GATE sources 50µA (IGATE),

charging the MOSFET gate and associated capacitance.

The SS voltage ramp limits VSENSE to control the inrush

current. PWRGD1 pulls active low when GATE is within

2.8V of VIN and DRAIN is lower than VDRNL. This sets off

the power good sequence in which PWRGD2 and then

PWRGD3 is subsequently pulled low after a delay, adjust-

able through the SQTIMER capacitor CSQ or by external

control inputs EN2 and EN3. In this way, external loads

or power modules controlled by the three PWRGD signals

are turned on in a controlled manner without overloading

the power bus.

Tw o modes of operation are possible during the time

the MOSFET is first turned on, depending on the values

of external components, MOSFET characteristics and

nominal design current. One possibility is that the MOS-

FET will turn on gradually so that the inrush into the load

capacitance remains a low value. The output will simply

ramp to –48V and the LTC4253B will fully enhance the

MOSFET. A second possibility is that the load current

exceeds the soft-start current limit threshold of [VSS(t)/

20 – VOS]/RS. In this case the LTC4253B ramps the output

by sourcing soft-start limited current into the load capaci-

tance. If the soft-start voltage is below 1.2V, the circuit

breaker TIMER is held low. Above 1.2V, TIMER ramps up.

It is important to set the timer delay so that, regardless

of which start-up mode is used, the TIMER ramp is less

than one circuit breaker delay time. If this condition is

not met, the LTC4253B may shut down after one circuit

breaker delay time.

Board Removal

When the board is withdrawn from the card cage, the UV/

OV divider is the first to lose connection. This shuts off

the MOSFET and commutates the flow of current in the

connector. When the power pins subsequently separate

there is no arcing.

Current Control

Three levels of protection handle short-circuit and over-

load conditions. Load current is monitored by SENSE and

resistor RS. There are three distinct thresholds at SENSE:

50mV for a timed circuit breaker function; 100mV for an

analog current limit loop; and 200mV for a fast, feedfor-

ward comparator which limits peak current in the event

of a catastrophic short-circuit.

If, due to an output overload, the voltage drop across RS

exceeds 50mV, TIMER sources 200µA into CT. CT eventu-

ally charges to a 4V threshold and the LTC4253B shuts

off. If the overload goes away before CT reaches 4V and

SENSE measures less than 50mV, CT slowly discharges

(5µA). In this way the LTC4253B’s circuit breaker function

responds to low duty cycle overloads, and accounts for the

fast heating and slow cooling characteristic of the MOSFET.

LTC4253B

4253bf

applicaTions inForMaTion

operaTion

Higher overloads are handled by an analog current limit

loop. If the drop across RS reaches VACL, the current

limiting loop servos the MOSFET gate and maintains a

constant output current of VACL/RS. In current limit mode,

VOUT (MOSFET drain-source voltage drop) typically rises

and this increases MOSFET heating. If VOUT > VDRNCL,

connecting an external resistor, RD between VOUT and

DRAIN allows the fault timing cycle to be shortened by

accelerating the charging of the TIMER capacitor. The

TIMER pull-up current is increased by 8 • IDRN. Note that

because SENSE > 50mV, TIMER charges CT during this

time, and the LTC4253B eventually shuts down.

Low impedance failures on the load side of the LTC4253B,

coupled with 48V or more driving potential, can produce

current slew rates well in excess of 50A/µs. Under these

conditions, overshoot is inevitable. A fast SENSE com-

parator with a threshold of 200mV detects overshoot and

pulls GATE low much harder and hence much faster than

the weaker current limit loop. The VACL/RS current limit

loop then takes over and servos the current as previously

described. As before, TIMER runs and shuts down the

LTC4253B when CT reaches 4V.

If CT reaches 4V, the LTC4253B latches off with a 5µA

pull-up current source. The LTC4253B circuit breaker latch

is reset by either pulling the RESET pin active high until

TIMER goes low, pulling UV momentarily low, dropping

the input voltage VIN below the internal UVLO threshold

or pulsing TIMER momentarily low with a switch.

Although short-circuits are the most obvious fault type,

several operating conditions may invoke overcurrent

protection. Noise spikes from the backplane or load, input

steps caused by the connection of a second, higher voltage

supply, transient currents caused by faults on adjacent

circuit boards sharing the same power bus or the inser-

tion of non-hot swappable products could cause higher

than anticipated input current and temporary detection

of an overcurrent condition. The action of TIMER and CT

rejects these events allowing the LTC4253B to “ride out”

temporary overloads and disturbances that could trip a

simple current comparator and, in some cases, blow a fuse.

(Refer to Block Diagram)

its pins, the area in and around the LTC4253B and all as-

sociated components should be free of any other planes

such as chassis ground, return, or secondary-side power

and ground planes.

VIN may be biased with additional current up to 30mA,

to accommodate external loading such as the PWRGD

opto-couplers shown in Figure 2. As an alternative to

running higher current, simply buffer VIN with an emitter

follower. A method that cascodes the PWRGD outputs is

shown in Figure 16.

VIN is rated to handle 30mA within the thermal limits of

the package, and is tested to survive a 100µs, 100mA

SHUNT REGULATOR

A fast responding shunt regulator clamps the VIN pin to

13V (VZ). Power is derived from –48RTN by an external

current limiting resistor, RIN. A 1µF decoupling capacitor,

CIN filters supply transients and contributes a short delay

at start-up.

To meet creepage requirements RIN may be split into two

or more series connected units. This introduces a wider

total spacing than is possible with a single component

while at the same time ballasting the potential across the

gap under each resistor. The LTC4253B is fundamentally

a low voltage device that operates with –48V as its refer-

ence ground. To further protect against arc discharge into

LTC4253B

4253bf

applicaTions inForMaTion

pulse. To protect VIN against damage from higher am-

plitude spikes, clamp VIN to VEE with a 13V Zener diode.

Star connect VEE and all VEE-referred components to the

sense resistor Kelvin terminal as illustrated in Figure 2,

keeping trace lengths between VIN, CIN, DIN and VEE as

short as possible.

INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)

A hysteretic comparator, UVLO, monitors VIN for undervolt-

age. The thresholds are defined by VLKO and its hysteresis

VLKH. When VIN rises above VLKO, the chip is enabled;

below (VLKO – VLKH), it is disabled and GATE is pulled low.

The UVLO function at VIN should not be confused with the

UV and OV pins. These are completely separate functions.

UV/OV COMPARATORS

A UV hysteretic comparator detects undervoltage condi-

tions at the UV pin, with the following thresholds:

UV low-to-high (VUVHI) = 3.225V

UV high-to-low (VUVLO) = 2.925V

An OV hysteretic comparator detects overvoltage condi-

tions at the OV pin, with the following thresholds:

OV low-to-high (VOVHI) = 6.150V

OV high-to-low (VOVLO) = 5.850V

The UV and OV trip point ratio is designed to match the

standard telecom operating range of 43V to 82V when

connected together as in the Typical Application. A resistive

divider is used to scale the supply voltage. Using 402k and

32.4k gives a typical operating range of 43.2V to 82.5V.

The undervoltage shutdown and overvoltage recovery

thresholds are then 39.2V and 78.4V. 1% divider resistors

are recommended to preserve threshold accuracy.

The resistive divider values shown set a standing current

of slightly more than 100µA and define an impedance at

UV/OV of 30kΩ. In most applications, 30kΩ impedance

coupled with 300mV UV hysteresis make the LTC4253B

insensitive to noise. If more noise immunity is desired,

add a 1nF to 10nF filter capacitor from UV/OV to VEE.

The separate UV and OV pins can be used for wider op-

erating range such as 35.6V to 76.3V range as shown in

Figure 2. Other combinations are possible with different

resistors arrangement.

UV/OV OPERATION

A low input to the UV comparator will reset the chip and

pull the GATE and TIMER pins low. A low-to-high UV

transition will initiate an initial timing sequence if the other

interlock conditions are met. A high-to-low transition in the

UV comparator immediately shuts down the LTC4253B,

pulls the MOSFET gate low and resets the three latched

PWRGD signals high.

An overvoltage condition is detected by the OV compara-

tor and pulls GATE low, thereby shutting down the load,

but it will not reset the circuit breaker TIMER and PWRGD

flags. Returning from the overvoltage condition will

restart the GATE pin if all the interlock conditions except

TIMER are met. Only during the initial timing cycle does

OV condition have an effect of resetting TIMER.

DRAIN

Connecting an external resistor, RD, to this dual function

DRAIN pin allows VOUT (MOSFET drain-source voltage

drop) sensing without it being damaged by large volt-

age transients. Below 5V, negligible pin leakage allows

a DRAIN low comparator to detect VOUT less than 2.39V

(VDRNL). This, together with the GATE low comparator,

sets the PWRGD flag.

When VOUT > VDRNCL, the DRAIN pin is clamped at VDRNCL

and the current flowing in RD is given by:

IDRN ≈VOUT

−

VDRNCL

(1)

This current is scaled up 8 times during a circuit breaker

fault before being added to the nominal 200µA. This ac-

celerates the fault TIMER pull-up when the MOSFET’s

drain-source voltage exceeds VDRNCL and effectively

shortens the MOSFET heating duration.

LTC4253B

4253bf

applicaTions inForMaTion

TIMER

The operation of the TIMER pin is somewhat complex as

it handles several key functions. A capacitor CT is used at

TIMER to provide timing for the LTC4253B. Four different

charging and discharging modes are available at TIMER:

1. 5µA slow charge; initial timing delay.

2. (200µA+8•IDRN) fast charge; circuit breaker delay.

3. 5µA slow discharge; circuit breaker “cool-off.”

4. Low impedance switch; resets the TIMER capacitor after

an initial timing delay, in UVLO, in UV and in OV during

initial timing and when RESET is high.

For initial timing delay, the 5µA pull-up is used. The

low impedance switch is turned off and the 5µA current

source is enabled when the interlock conditions are met.

CT charges to 4V in a time period given by:

t=4V •CT

5µA

(2)

When CT reaches VTMRH ( 4V), the low impedance switch

turns on and discharges CT. A GATE start-up cycle begins

and both SS and GATE outputs are released.

CIRCUIT BREAKER TIMER OPERATION

If the SENSE pin detects more than 50mV drop across RS,

the TIMER pin charges CT with (200µA+8•IDRN). If CT

charges to 4V, the GATE pin pulls low and the LTC4253B

latches off. The LTC4253B remains latched off until the

RESET pin is momentarily pulsed high, the UV pin is

momentarily pulsed low, the TIMER pin is momentarily

discharged low by an external switch or VIN dips below

UVLO and is then restored. The circuit breaker timeout

period is given by:

t=4V •CT

200µA+8•IDRN

(3)

If VOUT < 5V, an internal PMOS isolates DRAIN pin leakage

current and this makes IDRN = 0 in Equation (3). If VOUT is

above VDRNCL during the circuit breaker fault period, the

charging of CT is accelerated by 8 • IDRN of Equation (1).

Intermittent overloads may exceed the 50mV threshold at

SENSE but, if their duration is sufficiently short, TIMER

will not reach 4V and the LTC4253B will not shut the

external MOSFET off. To handle this situation, the TIMER

discharges CT slowly with a 5µA pull-down whenever the

SENSE voltage is less than 50mV. Therefore, any intermit-

tent overload with VOUT < 5V and an aggregate duty cycle

of more than 2.5% will eventually trip the circuit breaker

and shut down the LTC4253B. Figure 3 shows the circuit

breaker response time in seconds normalized to 1µF. The

asymmetric charging and discharging of CT is a fair gauge

of MOSFET heating.

The normalized circuit response time is estimated by:

CT(µF) =4

205 +8•IDRN

( )

•D−5







for D>2.5%

(4)

FAULT DUTY CYCLE, D (%)

20 40 60 800

NORMALIZED RESPONSE TIME (s/µF)

0.1

0.01 100

4253b F03

CT(µF)

(205 + 8 • IDRN) • D – 5

IDRN = 0µA

Figure 3. Circuit Breaker Response Time

LTC4253B

4253bf

applicaTions inForMaTion

POWER GOOD SEQUENCING

After the initial TIMER cycle, GATE ramps up to turn on

the external MOSFET which in turn pulls DRAIN low.

When GATE is within 2.8V of VIN and DRAIN is lower than

VDRNL, the power good sequence starts with PWRGD1

pulling active low. This starts off a 5µA pull-up on the

SQTIMER pin which ramps up until it reaches the 4V

threshold then pulls low. When the SQTIMER pin floats,

this delay tSQT is about 300µs. Connecting an external

capacitor CSQ from SQTIMER to VEE modifies the delay to:

tSQT =

4V •C

5µA

(5)

PWRGD2 asserts when EN2 goes high and PWRGD1 has

asserted for more than one tSQT. When PWRGD2 suc-

cessfully pulls low, SQTIMER ramps up on another delay

cycle. PWRGD3 asserts when EN2 and EN3 go high and

PWRGD2 has asserted for more than one tSQT.

All three PWRGD signals are reset in UVLO, in UV condi-

tion, if RESET is high or when CT charges up to 4V. In

addition, PWRGD2 is reset by EN2 going low. PWRGD3 is

reset by EN2 or EN3 going low. An overvoltage condition

has no effect on the PWRGD flags. A 50µA current pulls

each PWRGD pin high when reset. As power modules

signal common are different from PWRGD, optoisolation

is recommended. These three pins can sink an optodiode

current. Figure 16 shows an NPN configuration for the

PWRGD interface. A limiting base resistor should be used

for each NPN and the module enable input should have

protection from negative bias current.

SOFT-START

Soft-start is effective in limiting the inrush current during

GATE start-up. Unduly long soft-start intervals can exceed

the MOSFET’s SOA duration if powering-up into an active

load. When the SS pin floats, an internal current source

ramps SS from 0V to 2.2V in about 300µs. Connecting an

external capacitor, CSS, from SS to ground modifies the

ramp to approximate an RC response of:

VSS(t) ≈VSS 1−e

– t

RSSCSS













(6)

An internal resistor divider (95k/5k) scales VSS(t) down

by 20 times to give the analog current limit threshold:

VACL(t) =VSS(t)

20 – VOS

(7)

This allows the inrush current to be limited to VACL(t)/RS.

The offset voltage, VOS (10mV), ensures CSS is sufficiently

discharged and the ACL amplifier is in current limit mode

before GATE start-up. SS is discharged low during UVLO

at VIN , UV, OV, during the initial timing cycle, a latched

circuit breaker fault or the RESET pin going high.

GATE

GATE is pulled low to VEE under any of the following condi-

tions: in UVLO, when RESET pulls high, in an undervoltage

condition, in an overvoltage condition, during the initial

timing cycle or a latched circuit breaker fault. When GATE

turns on, a 50µA current source charges the MOSFET gate

and any associated external capacitance. VIN limits the

gate drive to no more than 14.5V.

Gate-drain capacitance (CGD) feedthrough at the first

abrupt application of power can cause a gate-source

voltage sufficient to turn on the MOSFET. A unique circuit

pulls GATE low with practically no usable voltage at VIN

and eliminates current spikes at insertion. A large external

gate-source capacitor is thus unnecessary for the purpose

of compensating CGD. Instead, a smaller value (≥10nF)

capacitor CC is adequate. CC also provides compensation

for the analog current limit loop.

GATE has two comparators: the GATE low comparator looks

for <0.5V threshold prior to initial timing; the GATE high

comparator looks for <2.8V relative to VIN and, together

with DRAIN low comparator, sets PWRGD1 output during

GATE start-up.

LTC4253B

4253bf

applicaTions inForMaTion

TIMER commences charging CT (trace 4) while the analog

current limit loop maintains the fault current at 100mV/RS,

which in this case is 5A (trace 2). Note that the backplane

voltage (trace 1) sags under load. Timer pull-up is acceler-

ated by VOUT. When CT reaches 4V, GATE turns off, the

PWRGD signals pull high, the load current drops to zero

and the backplane rings up to over 100V. The transient

associated with the GATE turn-off can be controlled with

a snubber to reduce ringing and a transient voltage sup-

pressor (such as Diodes Inc. SMAT70A) to clip off large

spikes. The choice of RC for the snubber is usually done

experimentally. The value of the snubber capacitor is usu-

ally chosen between 10 to 100 times the MOSFET COSS.

The value of the snubber resistor is typically between 3Ω

to 100Ω.

A low impedance short on one card may influence the

behavior of others sharing the same backplane. The initial

glitch and backplane sag as seen in Figure 4 trace1, can

rob charge from output capacitors on the adjacent card.

When the faulty card shuts down, current flows in to

refresh the capacitors. If LTC4253B is used by the other

cards, they respond by limiting the inrush current to a

value of VACL/RS. If CT is sized correctly, the capacitors

will recharge long before CT times out.

Figure 4. Output Short-Circuit Behavior of LTC4253B

Sense

The SENSE pin is monitored by the circuit breaker (CB)

comparator, the analog current limit (ACL) amplifier, and

the fast current limit (FCL) comparator. Each of these three

measures the potential of SENSE relative to VEE. When

SENSE exceeds 50mV, the CB comparator activates the

200µA TIMER pull-up. At 100mV the ACL amplifier servos

the MOSFET current, and at 200mV the FCL comparator

abruptly pulls GATE low in an attempt to bring the MOSFET

current under control. If any of these conditions persists

long enough for TIMER to charge CT to 4V (see Equation3),

the LTC4253B shuts down and pulls GATE low.

If the SENSE pin encounters a voltage greater than VACL,

the ACL amplifier will servo GATE downwards in an attempt

to control the MOSFET current. Since GATE overdrives the

MOSFET in normal operation, the ACL amplifier needs time

to discharge GATE to the threshold of the MOSFET. For a

mild overload the ACL amplifier can control the MOSFET

current, but in the event of a severe overload the current

may overshoot. At SENSE = 200mV the FCL comparator

takes over, quickly discharging the GATE pin to near VEE

potential. FCL then releases, and the ACL amplifier takes

over. All the while TIMER is running. The effect of FCL is

to add a nonlinear response to the control loop in favor

of reducing MOSFET current.

Owing to inductive effects in the system, FCL typically

overcorrects the current limit loop, and GATE undershoots.

A zero in the loop (resistor RC in series with the gate ca-

pacitor) helps the ACL amplifier to recover.

SHORT-CIRCUIT OPERATION

Circuit behavior arising from a load side low impedance

short is shown in Figure 4. Initially the current overshoots

the analog current limit level of VSENSE=200mV (trace 2)

as the GATE pin works to bring VGS under control (trace3).

The overshoot glitches the backplane in the negative direc-

tion and when the current is reduced to 100mV/RS, the

backplane responds by glitching in the positive direction.

GATE

0.5ms

10V

SENSE

0.5ms

200mV

–48RTN

0.5ms

50V

TIMER

0.5ms

4253b F04

SUPPLY RING OWING

TO CURRENT OVERSHOOT

SUPPLY RING OWING

TO MOSFET TURN-OFF

ONSET OF OUTPUT

SHORT-CIRCUIT

FAST CURRENT

LIMIT

CTIMER RAMP LATCH OFF

TRACE 1

TRACE 2

TRACE 3

TRACE 4

ANALOG

CURRENT LIMIT

LTC4253B

4253bf

MOSFET SELECTION

The external MOSFET switch must have adequate safe

operating area (SOA) to handle short-circuit conditions

until TIMER times out. These considerations take prece-

dence over DC current ratings. A MOSFET with adequate

SOA for a given application can always handle the required

current but the opposite may not be true. Consult the

manufacturer’s MOSFET data sheet for safe operating

area and effective transient thermal impedance curves.

MOSFET selection is a 3-step process by assuming the

absence of soft-start capacitor. First, RS is calculated and

then the time required to charge the load capacitance is

determined. This timing, along with the maximum short-

circuit current and maximum input voltage, defines an

operating point that is checked against the MOSFET’s

SOA curve.

To begin a design, first specify the required load current

and Ioad capacitance, IL and CL. The circuit breaker cur-

rent trip point (VCB/RS) should be set to accommodate

the maximum load current. Note that maximum input

current to a DC/DC converter is expected at VSUPPLY(MIN).

RS is given by:

RS=VCB(MIN)

IL(MAX)

(8)

where VCB(MIN) = 40mV represents the guaranteed mini-

mum circuit breaker threshold.

During the initial charging process, the LTC4253B may

operate the MOSFET in current limit, forcing (VACL) be-

tween 80mV to 120mV across RS. The minimum inrush

current is given by:

IINRUSH(MIN) =VACL(MIN)

(9)

Maximum short-circuit current limit is calculated using

the maximum VSENSE. This gives

ISHORTCIRCUIT(MAX) =VACL(MAX)

(10)

The TIMER capacitor CT must be selected based on the

slowest expected charging rate; otherwise TIMER might

time out before the load capacitor is fully charged. A value

for CT is calculated based on the maximum time it takes

the load capacitor to charge. That time is given by:

tCL(CHARGE) =C•V

I=CL•VSUPPLY(MAX)

IINRUSH(MIN)

(11)

The maximum current flowing in the DRAIN pin is given by:

IDRN(MAX) =VSUPPLY(MAX) −VDRNCL

(12)

Approximating a linear charging rate, IDRN drops from

IDRN(MAX) to zero, the IDRN component in Equation (3)

can be approximated with 0.5 • IDRN(MAX). Rearranging

the equation, TIMER capacitor CT is given by:

CT=tCL(CHARGE) •(200µA+4•IDRN(MAX))

(13)

Returning to Equation (3), the TIMER period is calcu-

lated and used in conjunction with VSUPPLY(MAX) and

ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec-

tive MOSFET.

As a numerical design example for the LTC4253B, consider

a 30W load, which requires 1A input current at 36V. If

VSUPPLY(MAX) = 72V and CL = 100µF, RD = 1MΩ, Equation

(8) gives RS=40mΩ; Equation (13) gives CT = 414nF.

To account for errors in RS, CT, TIMER current (200µA),

TIMER threshold (4V), RD, DRAIN current multiplier and

DRAIN voltage clamp (VDRNCL), the calculated value should

be multiplied by 1.5, giving the nearest standard value of

CT=680nF.

If a short-circuit occurs, a current of up to 120mV/40mΩ = 3 A

will flow in the MOSFET for 6.3ms as dictated by CT = 680nF

in Equation (3). The MOSFET must be selected based on

this criterion. The IRF530S can handle 100V and 3A for

10ms and is safe to use in this application.

applicaTions inForMaTion

LTC4253B

4253bf

Computing the maximum soft-start capacitor value during

soft-start to a load short is complicated by the nonlinear

MOSFET’s SOA characteristics and the RSSCSS response.

An overconservative but simple approach begins with the

maximum circuit breaker current, given by:

ICB(MAX) =VCB(MAX)

(14)

where VCB(MAX) is 60mV.

From the SOA curves of a prospective MOSFET, determine

the time allowed, tSOA(MAX). CSS is given by:

CSS =

SOA(MAX)

0.916 •RSS

(15)

In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX)

for the IRF530S is 40ms. From Equation (15), CSS =

437nF. Actual board evaluation showed that CSS = 100nF

was appropriate. The ratio ( RSS • CSS ) to tCL(CHARGE) is

a good gauge as large ratios may result in the time-out

period expiring prematurely. This gauge is determined

empirically with board level evaluation.

SUMMARY OF DESIGN FLOW

To summarize the design flow, consider the Typical Ap-

plication shown on the front page. It was designed for

80W and CL=100µF.

Calculate maximum load current: 80W/43V = 1.86A.

Calculate RS: from Equation (8) RS = 20mΩ.

Calculate ISHORTCIRCUIT(MAX): from Equation (10)

ISHORTCIRCUIT(MAX) = 6A.

Select a MOSFET that can handle 6A at 82V: IRF530S.

Calculate CT: from Equation (13) CT = 256nF. Select

CT = 330nF, which gives the circuit breaker time-out

period tMAX = 1.65ms.

Consult MOSFET SOA curves: the IRF530S can handle 6A

at 100V for 2.5ms, so it is safe to use in this application.

Calculate CSS: using Equations (14) and (15) select

CSS=68nF.

FREQUENCY COMPENSATION

The LTC4253B typical frequency compensation network

for the analog current limit loop is a series RC (10Ω)

and CC connected from GATE to VEE. Figure 5 depicts

the relationship between the compensation capacitor CC

and the MOSFET’s CISS. The line in Figure 5 is used to

select a starting value for CC based upon the MOSFET’s

CISS specification. Optimized values for CC are shown for

several popular MOSFETs. Differences in the optimized

value of CC versus the starting value are small. Neverthe-

less, compensation values should be verified by board

level short-circuit testing.

As seen in Figure 4, at the onset of a short-circuit event,

the input supply voltage can ring dramatically due to series

inductance. If this voltage avalanches the MOSFET, current

continues to flow through the MOSFET to the output. The

analog current limit loop cannot control this current flow

and therefore the loop undershoots. This effect cannot be

eliminated by frequency compensation. A Zener diode is

required to clamp the input supply voltage and prevent

MOSFET avalanche.

Figure 5. Recommended Compensation Capacitor

CC vs MOSFET CISS for the LTC4253B

MOSFET CISS (pF)

COMPENSATION CAPACITOR C

(nF)

4253b F05

002000 4000 6000 8000

IRF530

IRF540

IRF740

IRF3710

NTY100N10

applicaTions inForMaTion

LTC4253B

4253bf

applicaTions inForMaTion

SENSE RESISTOR CONSIDERATIONS

For proper circuit breaker operation, Kelvin-sense PCB con-

nections between the sense resistor and the LTC4253B’s

VEE and SENSE pins are strongly recommended. The

drawing in Figure 6 illustrates the correct way of making

connections between the LTC4253B and the sense resis-

tor. PCB layout should be balanced and symmetrical to

minimize wiring errors. In addition, the PCB layout for the

sense resistor should include good thermal management

techniques for optimal sense resistor power dissipation.

Figure 6. Making PCB Connections to the Sense Resistor

TIMING WAVEFORMS

System Power-Up

Figure 7 details the timing waveforms for a typical power-

up sequence in the case where a board is already installed

in the backplane and system power is applied abruptly. At

time point 1, the supply ramps up, together with UV/OV,

VOUT and DRAIN. VIN and the PWRGD signals follow at

a slower rate as set by the VIN bypass capacitor. At time

point 2, VIN exceeds VLKO and the internal logic checks for

UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL,

SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When

all conditions are met, initial timing starts and the TIMER

capacitor is charged by a 5µA current source pull-up. At

time point 3, TIMER reaches the VTMRH threshold and

the initial timing cycle terminates. The TIMER capacitor

is quickly discharged. At time point 4, the VTMRL thresh-

old is reached and the conditions of GATE < VGATEL,

SENSE<VCB and SS < 20 • VOS must be satisfied before

the GATE start-up cycle begins. SS ramps up as dictated

by RSS • CSS (as in Equation 6); GATE is held low by the

analog current limit (ACL) amplifier until SS crosses 20 •

VOS. Upon releasing GATE, 50µA sources into the external

MOSFET gate and compensation network. When the GATE

voltage reaches the MOSFET’s threshold, current flows

into the load capacitor at time point 5. At time point 6,

load current reaches SS control level and the analog cur-

rent limit loop activates. Between time points 6 and 8, the

GATE voltage is servoed, the SENSE voltage is regulated

at VACL(t) (Equation 7) and soft-start limits the slew rate

of the load current. If the SENSE voltage (VSENSE – VEE)

reaches the VCB threshold at time point 7, circuit breaker

TIMER activates. The TIMER capacitor, CT, is charged by

a (200µA+8•IDRN) current pull-up. As the load capaci-

tor nears full charge, load current begins to decline. At

time point 8, the load current falls and the SENSE voltage

drops below VACL(t). The analog current limit loop shuts

off and the GATE pin ramps further. At time point 9, the

SENSE voltage drops below VCB, the fault TIMER ends,

followed by a 5µA discharge cycle (cool-off). The duration

between time points 7 and 9 must be shorter than one

circuit breaker delay to avoid fault time-out during GATE

ramp-up. When GATE ramps past the VGATEH threshold at

time pointA, PWRGD1 pulls low. At time point B, GATE

reaches its maximum voltage as determined by VIN. At

time point A, SQTIMER starts its ramp-up to 4V. Having

satisfied the requirement that PWRGD1 is low for more than

one tSQT, PWRGD2 pulls low after EN2 pulls high above

the VIH threshold at time point C. This sets off the second

SQTIMER ramp-up. Having satisfied the requirement that

PWRGD2 is low for more than one tSQT, PWRGD3 pulls

low after EN3 pulls high at time point D.

CURRENT FLOW

FROM LOAD

CURRENT FLOW

TO –48V BACKPLANE

SENSE RESISTOR

TRACK WIDTH W:

0.03" PER AMP

ON 1 OZ COPPER

SENSE

VEE

4253b F06

LTC4253B

4253bf

applicaTions inForMaTion

4253b F07

GATE

START-UP

INITIAL TIMING

VLKO

VGATEL

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

SENSE

VOUT

1 2 3 4 56 7 89

DRAIN

PWRGD1

A B

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

C D

CLEARS V

LKO

, CHECK UV > V

UVHI

, OV < V

OVLO

, RESET < 0.8V, GATE < V

GATEL

, SENSE < V

SS < 20 • VOS AND TIMER < VTMRL

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

VSQTMRH

5µA

VSQTMRH

VIH

VTMRH

VACL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

5µA 5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

Figure 7. System Power-Up Timing (All Waveforms Are Referenced to VEE)

LTC4253B

4253bf

applicaTions inForMaTion

Live Insertion with Short Pin Control of UV/OV

In the example shown in Figure 8, power is delivered

through long connector pins whereas the UV/OV divider

makes contact through a short pin. This ensures the power

connections are firmly established before the LTC4253B

is activated. At time point 1, the power pins make contact

and VIN ramps through VLKO. At time point2, the UV/OV

divider makes contact and its voltage exceeds VUVHI. In

Figure 8. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)

GATE

START-UP

INITIAL TIMING

VUVHI

VLKO

VGATEL

VSQTMRH

VSQTMRL

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

SENSE

UV CLEARS V

UVHI

, CHECK OV < V

OVHI

, RESET < 0.8V, GATE < V

GATEL

SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

VOUT

1 2 3 4 5 6 7 89

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

DRAIN

PWRGD1

A B

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

C D

5µA

VSQTMRH

4253b F08

VSQTMRL

VTMRH

VACL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA 5µA 5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

LTC4253B

4253bf

applicaTions inForMaTion

addition, the internal logic checks for OV < VOVHI, RESET

< 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and

TIMER<VTMRL. When all conditions are met, initial timing

starts and the TIMER capacitor is charged by a 5µA current

source pull-up. At time point 3, TIMER reaches the VTMRH

threshold and the initial timing cycle terminates. The TIMER

capacitor is quickly discharged. At time point4, the VTMRL

threshold is reached and the conditions of GATE<VGATEL,

SENSE<VCB and SS<20 • VOS must be satisfied before

the GATE start-up cycle begins. SS ramps up as dictated

by RSS • CSS; GATE is held low by the analog current

limit amplifier until SS crosses 20 • VOS. Upon releasing

GATE, 50µA sources into the external MOSFET gate and

compensation network. When the GATE voltage reaches

the MOSFET’s threshold, current begins flowing into the

load capacitor at time point 5. At time point 6, load current

reaches SS control level and the analog current limit loop

activates. Between time points 6 and 8, the GATE voltage

is servoed and the SENSE voltage is regulated at VACL(t)

and soft-start limits the slew rate of the load current. If the

SENSE voltage (VSENSE – VEE) reaches the VCB threshold

at time point 7, the circuit breaker TIMER activates. The

TIMER capacitor, CT is charged by a (200µA+8•IDRN)

current pull-up. As the load capacitor nears full charge,

load current begins to decline. At point8, the load cur-

rent falls and the SENSE voltage drops below VACL(t).

The analog current limit loop shuts off and the GATE pin

ramps further. At time point 9, the SENSE voltage drops

below VCB and the fault TIMER ends, followed by a 5µA

discharge current source (cool-off). When GATE ramps

past VGATEH threshold at time point A, PWRGD1 pulls low,

starting off the PWRGD sequence. PWRGD2 pulls low at

time point C when EN2 is high and PWRGD1 is low for

more than one tSQT. PWRGD3 pulls low at time point D

when EN2 and EN3 is high and PWRGD2 is low for more

than one tSQT. At time point B, GATE reaches its maximum

voltage as determined by VIN.

Undervoltage Timing

In Figure 9 when the UV pin drops below VUVLO at time

point 1, the LTC4253B shuts down with TIMER, SS and

GATE pulled low. If current has been flowing, the SENSE

pin voltage decreases to zero as GATE collapses. When

UV recovers and clears VUVHI at time point 2, an initial

time cycle begins followed by a start-up cycle.

VIN Undervoltage Lockout Timing

VIN undervoltage lockout comparator, UVLO has a similar

timing behavior as the UV pin timing except it looks at

VIN < (VLKO–VLKH) to shut down and VIN > VLKO to start.

In an undervoltage lockout condition, both UV and OV

comparators are held off. When VIN exits undervoltage

lockout, the UV and OV comparators are enabled.

Overvoltage Timing

During normal operation, if the OV pin exceeds VOVHI as

shown at time point 1 of Figure 10, the TIMER and PWRGD

status are unaffected; SS and GATE pull down; load discon-

nects. At time point 2, OV recovers and drops below the

VOVLO threshold; GATE start-up begins. If the overvoltage

glitch is long enough to deplete the load capacitor, time

points 4 through 7 may occur.

Circuit Breaker Timing

In Figure 11a, the TIMER capacitor charges at 200µA if

the SENSE pin exceeds VCB but VDRN is less than 5V. If

the SENSE pin returns below VCB before TIMER reaches

the VTMRH threshold, TIMER is discharged by 5µA. In

Figure 11b, when TIMER exceeds VTMRH, GATE pulls

down immediately and the chip shuts down. In Figure11c,

multiple momentary faults cause the TIMER capacitor to

integrate and reach VTMRH followed by GATE pull down and

the chip shuts down. During chip shutdown, the LTC4253B

latches TIMER high with a 5µA pull-up current source.

LTC4253B

4253bf

applicaTions inForMaTion

50µA

VSQTMRL

UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

TIMER

GATE

SENSE

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

1 2 3 4 56 7 89 A B C D

4253b F09

INITIAL TIMING GATE

START-UP

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES

VUVLO

VGATEL

VUVHI

VACL

VSQTMRH

VSQTMRL

VCB

5µA

50µA

VSQTMRH

VDRNCL

VDRNL

VIN – VGATEH

50µA

200µA + 8 • IDRN

VTMRH

VTMRL

5µA

Figure 9. Undervoltage Timing (All Waveforms Are Referenced to VEE)

LTC4253B

4253bf

applicaTions inForMaTion

VACL

VCB

VIN – VGATEH

TIMER

GATE

SENSE

1 2 34 5 6 7 8 9

GATE

START-UP 4253b F10

OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

OV OVERSHOOTS V

OVHI

. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED

VOVHI VOVLO

VTMRH

VGATEL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

5µA

200µA + 8 • IDRN

CB FAULT CB FAULT CB FAULT CB FAULT

1 2 1 2 1 2 3 4

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

4253b F11

CB TIMES-OUTCB TIMES-OUT

VTMRH

VACL

VCB

VACL

VCB

5µA 5µA

VDRNCL

200µA + 8 • IDRN

VTMRH

VACL

VCB

VDRNCL

200µA + 8 • IDRN

VTMRH

Figure 10. Overvoltage Timing (All Waveforms Are Referenced to VEE)

Figure 11. Circuit Breaker Timing Behavior (All Waveforms Are Referenced to VEE)

(11a) Momentary Circuit Breaker Fault (11b) Circuit Breaker Time-Out (11c) Multiple Circuit Breaker Fault

LTC4253B

4253bf

applicaTions inForMaTion

Resetting a Fault Latch

A latched circuit breaker fault of the LTC4253B has the

benefit of a long cooling time. The latched fault can be

reset by pulsing the RESET pin high until the TIMER pin

is pulled below VTMRL(1V) as shown in Figure 12b. After

the RESET pulse, SS and GATE ramp up without an initial

timing cycle provided the interlock conditions are satisfied.

Alternative methods of reset include using an external

switch to pulse the UV pin below VUVLO or the VIN pin

below (VLKO – VLKH). Pulling the TIMER pin below VTMRL

and the SS pin to 0V then simultaneously releasing them

also achieves a reset. An initial timing cycle is generated

for reset by pulsing the UV pin or VIN pin, while no initial

timing cycle is generated for reset by pulsing of the TIMER

and SS pins.

Using Reset as an ON/OFF Switch

The asynchronous RESET pin can be used as an ON/OFF

function to cut off supply to the external power modules or

loads controlled by the LTC4253B. Pulling RESET high will

pull GATE, SS, TIMER and SQTIMER low and the PWRGD

signal high. The supply is fully cut off if the RESET pulse is

maintained wide enough to fully discharge the GATE and

SS pins. As long as RESET is high, GATE, SS, TIMER and

SQTIMER are strapped to VEE and the supply is cut off.

When RESET is released, if the LTC4253B are in UVLO, UV,

OV or VSENSE > VCB, turn-on is delayed until the interlock

conditions are met before recovering as described in the

Operation, Interlock Conditions section. If not, the GATE

pin will ramp up in a soft start cycle without going through

an initial cycle as in Figure 12c.

Analog Current Limit and Fast Current Limit

In Figure 13a, when SENSE exceeds VACL, GATE is regulated

by the analog current limit amplifier loop. When SENSE

drops below VACL, GATE is allowed to pull up. In Figure 13b,

when a severe fault occurs, SENSE exceeds VFCL and GATE

immediately pulls down until the analog current amplifier

establishes control. If the severe fault causes VOUT

to exceed

VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows

into the DRAIN pin and is multiplied by8. This extra cur-

rent is added to the TIMER pull-up current of 200µA. This

accelerated TIMER current of (200µA+8•IDRN) produces

a shorter circuit breaker fault delay. Careful selection of

CT, RD and MOSFET helps prevent SOA damage in a low

impedance fault condition.

Soft-Start

f the SS pin is not connected, this pin defaults to a linear

voltage ramp, from 0V to 2.2V in about 300µs at GATE

start-up, as shown in Figure 14a. If a soft-start capacitor,

CSS, is connected to this SS pin, the soft-start response

is modified from a linear ramp to an RC response (Equa-

tion6), as shown in Figure 14b. This feature allows load

current to slowly ramp-up at GATE start-up. Soft-start

is initiated at time point 3 by a TIMER transition from

VTMRH to VTMRL (time points 1 and 2), by the OV pin fall-

ing below the VOVLO threshold after an OV condition or

by the RESET pin falling < 0.8V after a Reset condition.

When the SS pin is below 0.2V, the analog current limit

amplifier keeps GATE low. Above 0.2V, GATE is released

and 50µA ramps up the compensation network and GATE

capacitance at time point 4. Meanwhile, the SS pin voltage

continues to ramp up. When GATE reaches the MOSFET’s

threshold, the MOSFET begins to conduct. Due to the

MOSFET’s high gm, the MOSFET current quickly reaches

the soft-start control value of VACL(t) (Equation7). At time

point6, the GATE voltage is controlled by the current limit

amplifier. The soft-start control voltage reaches the circuit

breaker voltage, VCB at time point7 and the circuit breaker

TIMER activates. As the load capacitor nears full charge,

load current begins to decline below VACL(t). The current

limit loop shuts off and GATE releases at time point8. At

time point9, SENSE voltage falls below VCB and TIMER

deactivates.

Large values of CSS can cause premature circuit breaker

time-out as VACL(t) may marginally exceed the VCB potential

during the circuit breaker delay. The load capacitor is un-

able to achieve full charge in one GATE start-up cycle. A

more serious side effect of a large CSS value is that SOA

duration may be exceeded during soft-start into a low

impedance load. A soft-start voltage below VCB will not

activate the circuit breaker TIMER.

LTC4253B

4253bf

applicaTions inForMaTion

Figure 12. Reset Functions (All Waveforms Are Referenced to VEE)

(12a) Reset Forcing Start-Up without

Initial TIMER Cycle

(12b) Reset of the LTC4253B’s Latched Fault (12c) Reset as an ON/OFF Switch

RESET PULSE

WIDTH MUST FULLY

DISCHARGE TIMER

1 2 34 5 6 7 8 9

LATCHED TIMER RESET BY

RESET PULLING HIGH

RESET < V

, CHECK UVLO, UV, OV CONDITION, GATE < V

GATEL

SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

UV/OV

VTMRH

VIH

VIL

VACL

VCB

VTMRL

VGATEL

VLKO

VUVHI

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

RESET PULSE

WIDTH MUST FULLY

DISCHARGE GATE AND SS

1 2 34 5 6 7 8 9

4253b F12

RESET < VIL, CHECK UVLO, UV, OV CONDITION, VSENSE < VCB

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

UV/OV

VIH

VIL

VACL

VCB

VTMRL

VGATEL

VLKO

VUVHI

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

1 23 4 5 6 7 8

RESET < V

, CHECK UVLO, UV, OV CONDITION, GATE < V

GATEL

SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

VIN VIN VIN

UV/OV

VIL

VACL

VCB

VTMRL

VGATEL

VLKO

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

VUVHI

LTC4253B

4253bf

applicaTions inForMaTion

Figure 13. Current Limit Behavior (All Waveforms Are Referenced to VEE)

(13a) Analog Current Limit Fault (13b) Fast Current Limit Fault

Figure 14. Soft-Start Timing (All Waveforms Are Referenced to VEE)

(14a) Without External CSS (14b) With External CSS

1 212 34

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

4253b F13

CB TIMES-OUT

VTMRH

VACL

VCB VACL

VFCL

VCB

5µA 200µA + 8 • IDRN

200µA + 8 • IDRN

VDRNCL

VTMRH

12 34 5 6 7 7a 8 9 10 11

END OF INITIAL TIMING CYCLE

12 3 4 5 6 7 8 9 10 11

END OF INITIAL TIMING CYCLE

4253b F14

TIMER

GATE

SENSE

DRAIN

PWRGD1

VTMRH

VACL

VCB

VTMRL

VTMRH

VTMRL

VGS(th) VGS(th)

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN TIMER

GATE

SENSE

DRAIN

PWRGD1

VACL

VCB

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

5µA

50µA

VDRNCL

VDRNL

VIN – VGATEH

200µA + 8 • IDRN

LTC4253B

4253bf

5.6k

BZV85C43

5.6k

PWRGD1

VIN

VEE

LTC4253B

POWER

MODULE 1

PWRGD2

PWRGD3

EN3

EN2

RESET

DRAINSS

GATESQTIMER

SENSETIMER

POWER

MODULE 2

POWER

MODULE 3

RIN

2.5k

15k(1/4W)/6

36.5k

EN3

4253b F15

EN2

10Ω

RD 1M

0.02Ω

IRF530S VIN

18nF

0.33µF

10nF

CSQ

0.1µF

CSS 68nF

R8 POWER

MODULE 1

OUTPUT

POWER

MODULE 2

OUTPUT

VIN R9

0.1µF

100µF

CIN

1µF

402k

32.4k

1% †

†

† † †

RESET

(LONG PIN)

–48V RTN

(SHORT PIN)

–48V RTN

(LONG PIN)

–48V

(LONG PIN)

DIN††

DDZ13B*

*DIODES, INC.

†MOC207

††RECOMMENDED FOR HARSH ENVIRONMENTS.

applicaTions inForMaTion

Power Limit Circuit Breaker

Figure 15 shows the LTC4253B in a power limit circuit

breaking application. The SENSE pin is modulated by board

voltage VSUPPLY. The D1 Zener voltage, VZ, is set to be the

same as the lowest operating voltage, VSUPPLY(MIN)=43V.

If the goal is to have the high supply operating voltage,

VSUPPLY(MAX) = 82V give the same power as available at

VSUPPLY(MIN), then resistors R3 and R4 are selected by:

R3 =VCB

VSUPPLY(MAX)

(16)

If R4 is 22Ω, then R3 is 36.5k. The peak circuit breaker

power limit is:

POWER(MAX)=VSUPPLY(MIN) +VSUPPLY(MAX)

( )

4•VSUPPLY(MIN) •VSUPPLY(MAX)

•POWER AT VSUPPLY(MIN)

=1.108V •POWER AT VSUPPLY(MIN)

(17)

when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX))

= 62.5V

The peak power at the fault current limit occurs at the supply

overvoltage threshold. The fault current limited power is:

POWER(FAULT)=

VSUPPLY

( )

•VACL −(VSUPPLY −VZ)•R4











(18)

Circuit Breaker with Foldback Current Limit

Figure 16 shows the LTC4253B in a foldback current limit

application. When VOUT is shorted to the –48V RTN supply,

current flows through resistors R3 and R4. This results in

a voltage drop across R4 and a corresponding reduction

in voltage drop across the sense resistor, RS, as the ACL

amplifier servos the sense voltage between the SENSE

and VEE pins to about 100mV. The short-circuit current

through RS reduces as the VOUT voltage increases during

an output short-circuit condition. Without foldback current

limiting resistor R4, the current is limited to 5A during

analog current limit. With R4, the short-circuit current is

limited to 1.5A when VOUT is shorted to 82V.

Figure 15. Power Limit Circuit Breaker Application

LTC4253B

4253bf

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

GN16 (SSOP) 0204

1 2 345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ±.004

(0.38 ±0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC4253B

4253bf

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2012

LT 0112 • PRINTED IN USA

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V

LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Auto-retry/Latched Off

LTC1642A Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V

LT4250 –48V Hot Swap Controller Active Current Limiting, Supplies from –20V to –80V

LTC4251B/LTC4251B-1/

LTC4251B-2

–48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V

LTC4252B-1/LTC4252B-2

LTC4252C-1/LTC4252C-2

–48V Hot Swap Controllers in MS8/MS10 Fast Active Current Limiting, Supplies from –15V, Drain

Accelerated Response, 1% Accurate UV/OV Thresholds

Figure 16. –48V/2.5A Application with Foldback Current Limiting and Transistor Enabled Sequencing without Feedback

100k

PWRGD1

VIN EN2 EN3

VIN

VEE

LTC4253B

POWER

MODULE 1

PWRGD2

PWRGD3

RESET

DRAIN

GATESQTIMER

SENSETIMER

POWER

MODULE 2

POWER

MODULE 3

RIN

10k

20k(1/4W)/2

4253b F16

10Ω

38.3k

0.02Ω

IRF530S

VOUT

18nF

33Ω

1µF

10nF

47k

CSQ

0.1µF

CSS 68nF

0.1µF

100µF

CIN

1µF

402k

32.4k

†

RESET

(LONG PIN)

–48V RTN

(SHORT PIN)

–48V RTN

(LONG PIN)

–48V

(LONG PIN)

*DIODES, INC.

†FMMT493

††RECOMMENDED FOR HARSH ENVIRONMENTS.

DIN††

DDZ13B*