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DRV8823-Q1
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
DRV8823-Q1 4-Bridge Serial Interface Motor Driver
1
1 Features
• Qualified for Automotive Applications 3 Description
The DRV8823-Q1 device provides an integrated
• AEC-Q100 Qualified with the Following Results: motor driver solution for printers and other office
– Device Temperature Grade 1: –40°C to 125°C automation equipment applications.
Ambient Operating Temperature Range The motor driver circuit includes four H-bridge drivers.
– Device HBM ESD Classification Level H2 Each of the motor driver blocks employ N-channel
– Device CDM ESD Classification Level C4B power MOSFETs configured as an H-bridge to drive
• PWM Motor Driver with Four H-Bridges the motor windings.
– Drives Two Stepper Motors, One Stepper and A simple serial interface allows control of all functions
Two DC Motors, or Four DC Motors of the motor driver with only a few digital signals. A
low-power sleep function is also provided.
– Up to 1.5-A Current Per Winding
– Low On-Resistance The motor drivers provide PWM current control
capability. The current is programmable, based on an
– Programmable Maximum Winding Current externally supplied reference voltage and an external
– Three-Bit Winding Current Control Allows up to current sense resistor. In addition, eight current levels
Eight Current Levels (set through the serial interface) allow microstepping
– Selectable Slow or Mixed Decay Modes with bipolar stepper motors.
• 8-V to 32-V Operating Supply Voltage Range Internal shutdown functions are provided for
• Internal Charge Pump for Gate Drive overcurrent protection, short-circuit protection,
undervoltage lockout, and overtemperature.
• Built-in 3.3-V Reference
• Serial Digital Control Interface The DRV8823-Q1 is packaged in a 48-pin HTSSOP
package (Eco-friendly: RoHS and no Sb/Br).
• Fully Protected Against Undervoltage,
Overtemperature, and Overcurrent Device Information(1)
• Thermally-Enhanced Surface Mount Package PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8823-Q1 HTSSOP (48) 12.50 mm × 6.10 mm
2 Applications (1) For all available packages, see the orderable addendum at
Automotive the end of the data sheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8823-Q1
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
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Table of Contents
7.4 Device Functional Modes........................................ 12
1 Features.................................................................. 17.5 Programming........................................................... 14
2 Applications ........................................................... 18 Application and Implementation ........................ 16
3 Description............................................................. 18.1 Application Information............................................ 16
4 Revision History..................................................... 28.2 Typical Application ................................................. 16
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 19
6 Specifications......................................................... 510 Layout................................................................... 19
6.1 Absolute Maximum Ratings ..................................... 510.1 Layout Guidelines ................................................. 19
6.2 ESD Ratings ............................................................ 510.2 Layout Example .................................................... 20
6.3 Recommended Operating Conditions....................... 510.3 Thermal Considerations........................................ 20
6.4 Thermal Information.................................................. 511 Device and Documentation Support................. 22
6.5 Electrical Characteristics........................................... 611.1 Documentation Support ........................................ 22
6.6 Timing Requirements................................................ 611.2 Community Resources.......................................... 22
6.7 Dissipation Ratings ................................................... 711.3 Trademarks........................................................... 22
6.8 Typical Characteristics.............................................. 711.4 Electrostatic Discharge Caution............................ 22
7 Detailed Description.............................................. 911.5 Glossary................................................................ 22
7.1 Overview................................................................... 912 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 10 Information ........................................................... 22
7.3 Feature Description................................................. 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2013) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
Changes from Original (June 2012) to Revision A Page
• Updated electrical characteristics table.................................................................................................................................. 6
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
28
27
26
25
24
23
22
21
20
NC
AOUT1
VM
VM
AOUT2
AISEN SCS
NC
RESETn
ABVREF
BISEN
CDVREF
TEST
SLEEPn
V3P3
BOUT2
BOUT1
SCLK
TEST
SDATA
SSTB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VCP
CP2
CP1
VM
DOUT2
DISEN
DOUT1
VM
NC
NC
CISEN
COUT2
TEST
COUT1
TEST
PGND
Solder These
Pins to Copper
Heatsink Area
Solder These
Pins to Copper
Heatsink Area
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5 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP
Top View
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To Logic
ESD
Internal
Pulldown
Hysteresis
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SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
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Pin Functions
PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
POWER AND GROUND
1, 2, Connect all VM pins together to motor supply voltage.
VM – Motor supply voltage (multiple pins)
23, 24 Bypass to GND with several 0.1-μF, 35-V ceramic capacitors.
V3P3 16 – 3.3 V regulator output Bypass to GND with 0.47-μF, 6.3-V ceramic capacitor.
10–15, Connect all PGND pins to GND and solder to copper heatsink
GND – Power ground (multiple pins)
34–39 areas.
CP1 7 IO Charge pump flying capacitor Connect a 0.01-μF capacitor between CP1 and CP2.
CP2 8 IO
VCP 9 IO Charge pump storage capacitor Connect a 0.1-μF, 16 V ceramic capacitor to VM.
MOTOR DRIVERS
ABVREF 17 I Bridge A & B current set reference voltage Sets current trip threshold
AOUT1 5 O Bridge A output 1 Connect to first coil of bipolar stepper motor 1, or DC motor
winding.
AOUT2 3 O Bridge A output 2
ISENA 4 – Bridge A current sense Connect to current sense resistor for bridge A.
BOUT1 48 O Bridge B output 1 Connect to second coil of bipolar stepper motor 1, or DC
motor winding.
BOUT2 46 O Bridge B output 2
ISENB 47 – Bridge B current sense Connect to current sense resistor for bridge B.
CDVREF 18 I Bridge C & D current set reference voltage Sets current trip threshold
COUT1 27 O Bridge C output 1 Connect to first coil of bipolar stepper motor 2, or DC motor
winding.
COUT2 25 O Bridge C output 2
ISENC 26 – Bridge C current sense Connect to current sense resistor for bridge C.
DOUT1 22 O Bridge D output 1 Connect to second coil of bipolar stepper motor 2, or DC
motor winding.
DOUT2 20 O Bridge D output 2
ISEND 22 – Bridge D current sense Connect to current sense resistor for bridge D.
SERIAL INTERFACE
SDATA 31 I Serial data input Data is clocked in on rising edge of SCLK.
SCLK 33 I Serial input clock Logic high enables serial data to be clocked in.
SCS 45 I Serial chip select Logic high latches serial data.
SSTB 30 I Serial data strobe Active low resets serial interface and disables outputs.
RESETn 43 I Reset input Active low input disables outputs and charge pump.
SLEEPn 42 I Sleep input
TEST PINS
19, 28,
TEST I Test inputs Do not connect these pins - used for factory test only.
29, 32
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output, PU = internal pullup
Figure 1. Logic Inputs
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VMPower supply voltage –0.3 34 V
VILogic input voltage(3) –0.5 5.75 V
IO(peak) Peak motor drive output current, t < 1 μs Internally limited
IOMotor drive output current(4) 1.5 A
PDContinuous total power dissipation See Dissipation Ratings
TAOperating ambient temperature –40 125 °C
TJOperating virtual junction temperature –40 150 °C
Tstg Storage temperature –60 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Input pins may be driven in this voltage range regardless of presence or absence of VM.
(4) Power dissipation and thermal limits must be observed.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±2000
Corner pins (1, 2, 23, 24, 48, and
V(ESD) Electrostatic discharge ±750 V
Charged device model (CDM), per 27)
AEC Q100-011 Other pins ±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VMMotor power supply voltage 8 32 V
VREF VREF input voltage 1 4 V
IMOT Continuous motor drive output current(1) 1 1.5 A
(1) Power dissipation and thermal limits must be observed.
6.4 Thermal Information DRV8823-Q1
THERMAL METRIC(1) DCA (HTSSOP) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 31.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.3 °C/W
RθJB Junction-to-board thermal resistance 15 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 14.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VMoperating supply current VM= 24 V, no loads 5 8 mA
VUVLO VMundervoltage lockout voltage VMrising 6.5 8 V
VCP Charge pump voltage Relative to VM12 V
VV3P3 VV3P3 output voltage 3.20 3.30 3.40 V
LOGIC-LEVEL INPUTS (INTERNAL PULLDOWNS)
VIL Input low voltage 0.7 V
VIH Input high voltage 2 V
VHYS Input hysteresis 0.3 0.45 0.6 V
Input current
IIN VIN = 3.3 V 100 μA
(internal pulldown current)
OVERTEMPERATURE PROTECTION
TTSD Thermal shutdown temperature Die temperature 150 °C
MOTOR DRIVERS
VM= 24 V, IO= 0.8 A, TA= 25°C 0.25
Motor number 1 FET on resistance
RDS(ON) VM= 24 V, IO= 0.8 A, TA= 85°C 0.31 0.37 Ω
(each individual FET) VM= 24 V, IO= 0.8 A, TA= 85°C to 125°C .435 .570
VM= 24 V, IO= 0.8 A, TA= 25°C 0.30
Motor number 2 FET on resistance
RDS(ON) VM= 24 V, IO= 0.8 A, TA= 85°C 0.38 0.45 Ω
(each individual FET) VM= 24 V, IO= 0.8 A, TA= 85°C to 125°C .446 .570
IOFF Off-state leakage current ±12 μA
fPWM Motor PWM frequency(1) 42 50 57 kHz
tBLANK ITRIP blanking time(2) 3.75 μs
tFOutput fall time 50 350 ns
tROutput rise time 50 350 ns
IOCP Overcurrent protect level 1.5 3 4.5 A
tOCP Overcurrent protect trip time 2.7 μs
tMD Mixed decay percentage Measured from beginning of PWM cycle 75%
CURRENT CONTROL
IREF xVREF input current xVREF = 3.3 V –3% 3 μA
xVREF = 2.5 V, derived from V3P3; 71% to 100% –5% 5%
current
ΔICHOP Chopping current accuracy xVREF = 2.5 V, derived from V3P3; 20% to 56% current –10% 10%
(1) Factory option 100 kHz.
(2) Factory options for 2.5 μs, 5 μs or 6.25 μs.
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
1 tCYC Clock cycle time 62 ns
2 tCLKH Clock high time 25 ns
3 tCLKL Clock low time 25 ns
4 tSU(SDATA) Setup time, SDATA to SCLK 5 ns
5 tH(DATA) Hold time, SDATA to SCLK 1 ns
6 tSU(SCS) Setup time, SCS to SCLK 5 ns
7 tH(SCS) Hold time, SCS to SCLK 1 ns
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3.80
4.00
4.20
4.40
4.60
4.80
5.00
5.20
-40°C 0°C 25°C 70°C 85°C
Supply Current (mA)
Temperature (ƒC)
8 V
24 V
27 V
C001
C002
SCLK
SDATA
SCS
5
7
4
6
3
2
Data
Invalid
1
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6.7 Dissipation Ratings DERATING FACTOR
BOARD PACKAGE RθJA TA< 25°C TA= 70°C TA= 85°C TA= 125°C
ABOVE TA= 25°C
Low-K(1) 75.7°C/W 13.2 mW/°C 1.65 W 1.06 W 0.86 W 0.332 W
Low-K(2) 32°C/W 31.3 mW/°C 3.91 W 2.50 W 2.03 W 0.778 W
DCA
High-K(3) 30.3°C/W 33 mW/°C 4.13 W 2.48 W 2.15 W 0.83 W
High-K(4) 22.3°C/W 44.8 mW/°C 5.61 W 3.59 W 2.91 W 1.118 W
(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm22-oz copper on back
side.
(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm21-oz copper on back
side and solid 1-oz internal ground plane.
Figure 2. Timing Diagram
6.8 Typical Characteristics
Figure 3. Supply Current over Temperature Figure 4. Supply Current over Supply Voltage
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0.00
100.00
200.00
300.00
400.00
500.00
600.00
-40°C 0°C 25°C 70°C 85°C
Rdson (mŸ)
Temperature (ƒC)
8 V
24 V
27 V
C008
0.00
100.00
200.00
300.00
400.00
500.00
600.00
-40°C 0°C 25°C 70°C 85°C
Rdson (mŸ)
Temperature (ƒC)
8 V
24 V
27 V
C007
0.00
100.00
200.00
300.00
400.00
500.00
600.00
-40°C 0°C 25°C 70°C 85°C
Rdson (mŸ)
Temperature (ƒC)
8 V
24 V
27 V
C010
0.00
100.00
200.00
300.00
400.00
500.00
600.00
-40°C 0°C 25°C 70°C 85°C
Rdson (mŸ)
Temperature (ƒC)
8 V
24 V
27 V
C009
10.00
15.00
20.00
25.00
30.00
35.00
40.00
45.00
-40°C 0°C 25°C 70°C 85°C
Charge Pump Voltage (V)
Temperature (ƒC)
8 V
24 V
27 V
C005
C006
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Typical Characteristics (continued)
Figure 6. Charge Pump Voltage over Supply Voltage
Figure 5. Charge Pump Voltage over Temperature
Figure 7. HS RDS(on) Aout1 over Temperature Figure 8. HS RDS(on) Aout2 over Temperature
Figure 9. LS RDS(on) Aout1 over Temperature Figure 10. LS RDS(on) Aout2 over Temperature
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7 Detailed Description
7.1 Overview
The DRV8823-Q1 is a dual stepper motor driver solution for automotive applications that require independent
control of two different motors. The device integrates four NMOS H-bridges, a microstepping indexer, and
various fault protection features. The DRV8823-Q1 can be powered with a supply voltage between 8 V and 32 V,
and is capable of providing an output current up to 1.5-A full scale. Actual full-scale current will depend on
ambient temperature, supply voltage and PCB ground size.
A serial data interface is included to control all functions of the motor driver. Current regulation through all four H-
bridges is achieved using three register bits per H-bridge. The three register bits are used to scale the current in
each bridge as a percentage of the full-scale current set by VREF input pin and sense resistor. The current
regulation is configurable with two different decay modes; slow decay and mixed decay.
The gate drive to each FET in all four H-Bridges is controlled to prevent any cross-conduction (shoot-through
current) during transitions.
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Charge
Pump and
Gate Drive
Regulator
Thermal
Shutdown
AOUT1
AOUT2
BOUT1
BOUT2
GND
ABVREF
0.1 F
16 V
μ
0.01 μF
35 V
24 V
24 V
24 V
24 V
24 V
VM
CP1
CP2
VCP
AISEN
BISEN
VCP
OCP
VM
Oscillator
COUT1
COUT2
DOUT1
DOUT2
Step
Motor
Step
Motor
VM
CISEN
DISEN
VM
UVLO
RESET
VGD
SDATA
SCLK
SCS
SSTB
RESETn
SLEEPn
Dig.
VCC
V3P3 3.3 V
Regulator
0.47 F
6.3 V
μ
CDVREF
Serial
Interface
and
Logic
PWM H-Bridge
Driver A
PWM H-Bridge
Driver B
PWM H-Bridge
Driver C
PWM H-Bridge
Driver D
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7.2 Functional Block Diagram
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AOUT1
BOUT1
AOUT2
BOUT2
VM
VM
ISENA
ISENB
APHASE
Pre-
drive
Pre-
drive
VCP, VGD
VCP, VGD
VM
VM
+
+
–
–
PWM
PWM
ABVREF
OCP
OCP
OCP
OCP
ABDECAY
BENBL
DAC
DAC
A
A
=
=
5
5
AI[2:0]
BI[2:0]
3
AENBL
BPHASE
AI[2:0]
3
3
From Serial Interface
Step
Motor
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7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8823-Q1 device contains four H-bridge motor drivers with current-control PWM circuitry. A block
diagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor)
is shown in Figure 11. Drivers C and D are the same as A and B (though the RDS(ON) of the output FETs is
different).
Figure 11. Motor Driver Circuit
Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor
supply voltage.
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Feature Description (continued)
7.3.2 Protection Circuits
The DRV8823-Q1 device is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.2.1 Overcurrent Protection (OCP)
All of the drivers in the DRV8823-Q1 device are protected with an overcurrent protection (OCP) circuit.
The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output
FET if the current through it exceeds a preset level. This circuit limits the current to a level that is safe to prevent
damage to the FET.
A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than
a preset period, all drivers in the device are disabled.
The device is re-enabled upon the removal and re-application of power at the VM pins.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device are shut down.
The device remains disabled until the die temperature falls to a safe level. After the temperature falls, the device
may be re-enabled upon the removal and re-application of power at the VM pin.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device is disabled. Operation resumes when VM rises above the UVLO threshold. The indexer logic is reset to its
initial condition in the event of a UVLO.
7.3.2.4 Shoot-Through Current Prevention
The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot-through current)
during transitions.
7.4 Device Functional Modes
7.4.1 Bridge Control
The xENBL bits in the serial interface registers enable current flow in each H-bridge when set to 1.
The xPHASE bits in the serial interface registers control the direction of current flow through each H-bridge.
Table 1 shows the logic.
Table 1. H-Bridge Logic
xPHASE xOUT1 xOUT2
1 H L
0 L H
7.4.2 Current Regulation
The motor driver employs fixed-frequency PWM current regulation (also called current chopping). When a
winding is activated, the current through it rises until it reaches a threshold, then the current is switched off until
the next PWM period.
The PWM frequency is fixed at 50 kHz, but it may also be set to 100 kHz through the factory option.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the VREF pin.
The full-scale (100%) chopping current is calculated as follows:
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CHOP
ISENSE
V
I
5 R
=
´
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(1)
Example:
If a 0.5-Ωsense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current is:
2.5 V/(5 × 0.5 Ω)=1A.
Three serial interface register bits per H-bridge (xI2, xI1 and xI0) are used to scale the current in each bridge as
a percentage of the full-scale current set by the VREF input pin and sense resistance. The function of the bits is
shown in Table 2.
Table 2. H-Bridge Bit Functions
RELATIVE CURRENT
xI2 xI1 xI0 (% FULL-SCALE CHOPPING
CURRENT)
0 0 0 20
0 0 1 38
0 1 0 56
0 1 1 71
1 0 0 83
1 0 1 92
1 1 0 98
1 1 1 100
7.4.3 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current
chopping threshold is reached. This is shown in Figure 12 as case 1. The current flow direction shown indicates
positive current flow in Figure 12.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 12 as case 2.
In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 12 as case 3.
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xOUT1 xOUT2
3
1
2
3
Drive current
Slow decay (brake)
Fast decay (reverse)
VM
1
2
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Figure 12. Decay Mode
The DRV8823-Q1 device supports slow decay and a mixed decay mode. Mixed decay mode begins as fast
decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of
the fixed PWM period.
Slow or mixed decay mode is selected by the state of the xDECAY bits in the serial interface registers. If the
xDECAY bit is 0, slow decay is selected. If the xDECAY bit is 1, mixed decay is selected.
7.4.4 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
7.5 Programming
7.5.1 Serial Data Transmission
Data transfers consist of 16 bits of serial data, shifted into the SDATA pin LSB first.
On serial writes to the DRV8823-Q1 device, additional clock edges following the final data bit continues to shift
data bits into the data register; therefore, the last 16 bits presented are latched and used.
One of two registers is selected by setting bits in an address field in the four upper bits in the serial data
transferred (ADDR in the tables below). One 16-bit register is used to control motor number 1 (bridges A and B),
and a second 16-bit register is used to control motor 2 (bridges C and D).
Data can only be transferred into the serial interface if the SCS input pin is active high.
Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising
edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have
been transferred.
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Product Folder Links: DRV8823-Q1
SCS
SCLK
SDATA
SSTB
D0 D8
D2 D10
D4 D12
D6 D14
D1 D9
D3 D11
D5 D13
D7
See Note 1
See Note 2
D15
DRV8823-Q1
www.ti.com
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
Programming (continued)
Table 3. Motor 1 Command (Bridges A and B)
D15–
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D12
ADDR
Name BDECAY B12 B11 B10 BPHASE BENBL ADECAY A12 A11 A10 APHASE AENBL
(= 0000)
Reset x 0 0 0 0 0 0 0 0 0 0 0 0
Value
Table 4. Motor 2 Command (Bridges C and D)
D15–
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D12
ADDR
Name DDECAY D12 D11 D10 DPHASE DENBL CDECAY C12 C11 C10 CPHASE CENBL
(= 0001)
Reset x 0 0 0 0 0 0 0 0 0 0 0 0
Value
Note 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This allows
8- or 16-bit transfers.
Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data continues to
be shifted into the data register.
Figure 13. Serial Data Timing Diagram
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DRV8823-Q1
DRV8823-Q1
VM
VM
AOUT2
AISEN
AOUT1
NC
CP1
CP2
VCP
PGND
PGND
PGND
PGND
PGND
PGND
V3P3
ABVREF
CDVREF
TEST
DOUT2
DISEN
DOUT1
VM
VM
BOUT1
BISEN
BOUT2
SCS
NC
RESETn
SLEEPn
NC
NC
PGND
PGND
PGND
PGND
PGND
PGND
SCLK
TEST
SDATA
SSTB
TEST
TEST
COUT1
CISEN
COUT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
M
+–
+–
M
+–
+–
0.01µF
0.1µF
0.1µF
.3 Ω
.3 Ω
.3 Ω
.3 Ω
0.1µF 100µF
VM
DRV8823-Q1
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8823-Q1 can be used to drive two bipolar stepper motors.
8.2 Typical Application
Figure 14. Typical Application Schematic
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DRV8823-Q1
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SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
Typical Application (continued)
8.2.1 Design Requirements
Table 5 lists the design requirements for this design example.
Table 5. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Supply voltage VM24 V
Motor winding resistance RL7.4 Ω/phase
Motor full-step angle θstep 1.8°/step
Target microstepping angle nM1/8 step
Target motor speed V 120 rpm
Target full-scale current IFS 1 A
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The appropriate motor voltage will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing a greater average torque. Using a
higher voltage also allows the motor to operate at a faster speed than a lower voltage.
8.2.2.2 Drive Current
The current path running to the motor starts from the supply VM, then goes through the high-side sourcing
NMOS power FET, moves through the inductive winding load of the motor, then through the low-side sinking
NMOS power FET, and finally going through the external sense resistor. Power dissipation losses in both NMOS
power FETs inside of the DRV8823-Q1 are shown in the following equation.
P = I2× (RDS(on) × 2) (2)
The DRV8823-Q1 has been measured to be capable of 1.5-A continuous current with the HTSSOP package at
25°C on standard FR-4 PCBs. The max continuous current will vary based on PCB design and the ambient
temperature.
8.2.3 Application Curves
Figure 15. ½ Step Microstepping With Slow Decay Figure 16. 1/8 Step Microstepping With Slow Decay
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Figure 17. ½ Step Microstepping With Mixed Decay Figure 18. 1/8 Step Microstepping With Mixed Decay
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Product Folder Links: DRV8823-Q1
Local
Bulk Capacitor
Parasitic Wire
Inductance
+
±
Motor
Driver
Power Supply Motor Drive System
VM
GND
+
IC Bypass
Capacitor
DRV8823-Q1
www.ti.com
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
9 Power Supply Recommendations
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance needed depends on a variety of factors, including
• Highest current required by the motor system
• Power supply’s capacitance and ability to source current
• Amount of parasitic inductance between the power supply and motor system
• Acceptable voltage ripple
• Type of motor used (brushed DC, brushless DC, stepper)
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Figure 19. Example Setup of Motor Drive System
With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2× RDS(on) heat that is generated in the device.
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Product Folder Links: DRV8823-Q1
DRV8823-Q1
VM
VM
AOUT2
AOUT1
AISEN
NC
CP2
CP1
VCP
PGND
PGND
PGND
PGND
PGND
PGND
V3P3
ABVREF
TEST
CDVREF
DOUT2
DISEN
DOUT1
VM
VM
BISEN
BOUT1
BOUT2
NC
SCS
RESETn
NC
SLEEPn
NC
PGND
PGND
PGND
PGND
PGND
PGND
SCLK
TEST
SSTB
SDATA
TEST
TEST
COUT1
COUT2
CISEN
+
DRV8823-Q1
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
www.ti.com
10.2 Layout Example
Figure 20. Typical Layout of DRV8823-Q1
10.3 Thermal Considerations
The DRV8823-Q1 device has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
Power dissipation in the DRV8823-Q1 device is dominated by the power dissipated in the output FET resistance,
or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 3.
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Product Folder Links: DRV8823-Q1
20
25
30
35
40
45
50
55
60
65
70
0 10 20 30 40 50 60 70 80 90
Backside Copper Area (cm )
2
Thermal Resistance R ) (°C/W)
(ΘJA
Low-K PCB (2 Layer)
High-K PCB (4 Layer with Ground Plane)
2
TOT DS(ON) OUT(RMS)
P = 4 x R x (I )
DRV8823-Q1
www.ti.com
SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
Thermal Considerations (continued)
(3)
Where: PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current applied to each winding. IOUT(RMS) is equal to approximately 0.7x the full-scale output current setting. The
factor of 4 is derived from the two motor windings, and at any instant two FETs are conducting winding current
for each winding (one high-side and one low-side). The DRV8823-Q1 device has two stepper motor drivers, so
the power dissipation of each must be added together to determine the total device power dissipation.
The maximum amount of power that can be dissipated in the DRV8823-Q1 device is dependent on ambient
temperature and heatsinking. The thermal dissipation ratings table in the datasheet can be used to estimate the
temperature rise for typical PCB constructions.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.2 Heatsinking
The PowerPAD integrated circuit package uses an exposed pad to remove heat from the device. For proper
operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB
with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the
ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate
heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the
heat between top and bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002,PowerPAD™ Thermally
Enhanced Package and TI application brief SLMA004,PowerPAD™ Made Easy, available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated. Figure 21 shows
thermal resistance versus copper plane area for both a single-sided PCB with 2-oz copper heatsink area, and a
4-layer PCB with 1-oz copper and a solid ground plane. Both PCBs are 76 mm x 114 mm, and 1.6 mm thick. The
heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.
Six pins on the center of each side of the package are also connected to the device ground. A copper area can
be used on the PCB that connects to the PowerPAD integrated circuit package as well as to all the ground pins
on each side of the device, which is especially useful for single-layer PCB designs.
Figure 21. Thermal Resistance vs Copper Plane Area
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: DRV8823-Q1
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SLVSBH2C –JUNE 2012–REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•PowerPAD™ Thermally Enhanced Package SLMA002
•PowerPAD™ Made Easy SLMA004
•Current Recirculation and Decay Modes,SLVA321
•Calculating Motor Driver Power Dissipation,SLVA504
•Understanding Motor Driver Current Ratings,SLVA505
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 29-Oct-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DRV8823QDCARQ1 ACTIVE HTSSOP DCA 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV8823Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Oct-2014
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF DRV8823-Q1 :
•Catalog: DRV8823
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DRV8823QDCARQ1 HTSSOP DCA 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Dec-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8823QDCARQ1 HTSSOP DCA 48 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Dec-2017
Pack Materials-Page 2
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